Phase change memory packaging structure

Abstract

The present invention provides a phase change memory and a preparation method thereof, comprising a first peripheral circuit chip formed on a substrate and at least one storage structure formed on the substrate, wherein the storage structure comprises at least two first phase change memory chips stacked in sequence on the substrate; the first phase change memory chips each have a single function, and each of the first phase change memory chips has a first contact that penetrates through; adjacent first phase change memory chips are connected via the first contact. The phase change memory provided by the present invention separates the peripheral circuit from the storage, and stacks the single-function phase change memory chips through the chiplet packaging technology to improve the integration density.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a packaging structure of a phase change memory. Background Art

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, program algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit. Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells.

[0003] 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, phase change memory (PCM) can utilize the difference between the resistivity of the amorphous phase and the crystalline phase in the phase change material based on electrothermal heating and quenching of the phase change material. PCM array cells can be stacked vertically in 3D to form a three-dimensional phase change memory (3D PCM). However, the packaging structure of traditional 3D PCM has the following disadvantages:

[0004] (1) It is difficult to miniaturize PCM chips and the process development cost is high;

[0005] (2) Traditional 3D PCM packaging has difficulty in achieving rapid technological changes due to the problem of layer stacking;

[0006] (3) Traditional 3D PCM chip design is difficult and costly;

[0007] (4) Traditional 3D PCM chips have complex routing, slow data transmission, and small bandwidth. Summary of the invention

[0008] The object of the present invention is to provide a phase change memory and a preparation method thereof, so as to realize the stacking of phase change memory chips with a single function through chiplet packaging technology and improve the integration density.

[0009] To achieve the above object, the present invention provides a phase change memory and a method for preparing the same, comprising:

[0010] a first peripheral circuit chip formed on a substrate, and at least one storage structure formed on the substrate;

[0011] The storage structure includes at least two first phase change memory chips stacked in sequence on a substrate; the first phase change memory chips each have a single function, and each of the first phase change memory chips has a first contact that penetrates through it; adjacent first phase change memory chips are connected via the first contacts.

[0012] In some embodiments, the storage structure further includes a second peripheral circuit chip, the second peripheral circuit chip is formed on the substrate, and the at least two first phase-change memory chips are stacked and packaged on the second peripheral circuit chip in sequence.

[0013] In some embodiments, it further includes at least two second phase-change memory chips stacked and packaged sequentially on the first peripheral circuit chip;

[0014] The second phase-change memory chips all have a single function, and each of the second phase-change memory chips has a penetrating second contact; adjacent second phase-change memory chips are connected via the second contacts.

[0015] In some embodiments, the first peripheral circuit chip and the second peripheral circuit chip both have a third contact extending therethrough, and the first peripheral circuit chip is connected to the substrate and the second contact of the second phase-change memory chip through the third contact;

[0016] The second peripheral circuit chip is connected to the substrate and the first contact of the first phase-change memory chip through the third contact.

[0017] In some embodiments, the structure of the first contact includes: a through hole penetrating the first phase-change memory chip, a barrier layer deposited on a sidewall of the through hole, a conductive layer filling the through hole, and a pad located on the conductive layer.

[0018] In some embodiments, an adhesion layer and a seed layer are further provided on two opposite surfaces of the first phase change memory chip, wherein the seed layer is located on the adhesion layer, the conductive layer penetrates the adhesion layer and connects to the seed layer, and the pad is located on the seed layer and is provided corresponding to the through hole.

[0019] In some embodiments, the first contact, the second contact, and the third contact have the same structure.

[0020] Accordingly, the present invention also provides a method for preparing a phase change memory, comprising:

[0021] forming a first peripheral circuit chip on a substrate, and forming at least one storage structure on the substrate;

[0022] The steps of forming the storage structure include: providing at least two first phase change memory chips, and each of the first phase change memory chips has a single function; forming a penetrating first contact on each of the first phase change memory chips; at least two of the first phase change memory chips are connected through the first contact, and at least two interconnected first phase change memory chips are formed on the substrate.

[0023] In some embodiments, the step of forming the storage structure further includes: forming a second peripheral circuit chip on the substrate, and the at least two first phase-change memory chips are sequentially stacked and packaged on the second peripheral circuit chip; and / or,

[0024] At least two second phase change memory chips are provided, and each of the second phase change memory chips has a single function; a penetrating second contact is formed on each of the second phase change memory chips; at least two of the second phase change memory chips are connected via the second contact, and the interconnected at least two second phase change memory chips are stacked and packaged in sequence on the first peripheral circuit chip.

[0025] In some embodiments, the step of forming the first contact includes:

[0026] forming a through hole penetrating the first phase-change memory chip;

[0027] Depositing a barrier layer on the sidewalls of the through hole and two opposite surfaces of the first phase-change memory chip;

[0028] Filling a conductive layer in the through hole;

[0029] A pad is connected on the conductive layer.

[0030] In summary, the present invention provides a phase change memory and a preparation method thereof, comprising a first peripheral circuit chip formed on a substrate and at least one storage structure formed on the substrate, wherein the storage structure comprises at least two first phase change memory chips stacked in sequence on the substrate; the first phase change memory chips each have a single function, and each of the first phase change memory chips has a first contact that penetrates through; adjacent first phase change memory chips are connected via the first contact. The phase change memory provided by the present invention separates the peripheral circuit from the storage, and stacks the single-function phase change memory chips through chiplet packaging technology to improve the integration density. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A planar layout diagram of a packaging structure of a 3D PCM chip;

[0032] Figure 2 is a schematic cross-sectional structure diagram of a packaging structure of a 3D PCM chip;

[0033] Figure 3 A plan layout diagram of a phase change memory provided by an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of a phase change memory provided by an embodiment of the present invention;

[0035] FIG. 5A to FIG. 5HIt is a schematic structural diagram corresponding to each step in a method for forming a first contact in an embodiment of the present invention;

[0036] Figure 6 A plan layout diagram of a phase change memory provided by another embodiment of the present invention;

[0037] Figure 7 A schematic diagram of a phase change memory provided by another embodiment of the present invention;

[0038] Figure 8 A schematic cross-sectional structure diagram of a phase change memory provided by another embodiment of the present invention;

[0039] Fig. 9 A schematic diagram of the structure of a single storage unit in a two-layer stacked storage array structure.

[0040] Wherein, the accompanying drawings are marked as follows:

[0041] 110 - top bit line; 120 - bottom bit line; 130 - word line; 140 - upper memory cell; 150 - lower memory cell; 101, 103, 105 - electrodes.

[0042] 200 - first phase change memory chip; 210 - through hole; 201 - barrier layer; 202 - conductive layer; 203 - adhesion layer; 204 - seed layer; 205 - pad; 205a - copper layer; 205b - tin layer. DETAILED DESCRIPTION

[0043] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0044] As process nodes continue to shrink, the difficulties encountered in continuing Moore's Law are becoming increasingly arduous, so it is difficult to continue Moore's Law by relying on device size reduction. On the other hand, the design cost of advanced process chips has also increased significantly, making the threshold for chip design higher and higher. In addition, the market has a huge demand for high-performance and diversified chips. These aspects are not conducive to the existing semiconductor development logic. Therefore, finding a new development path has become an important issue facing the continuation of Moore's Law.

[0045] Specifically in the field of phase change memory packaging, the problem also exists. Figure 1 This is a planar layout diagram of the packaging structure of a 3D PCM chip. Figure 2 The cross-sectional structure diagram of the packaging structure of a 3D PCM chip. Figure 1 and Figure 2, the traditional 3D PCM packaging technology requires the design of chips with different functions (such as microprocessor MPU, digital signal processor DSP, microcontroller MCU and phase change memory PCM) together, and the overall packaging together to achieve high-performance chips. This requires the improvement of process technology, circuit design, program algorithm and manufacturing process to scale the planar functional chip to a smaller size, and as the characteristic size of the storage unit approaches the lower limit, the planar process and manufacturing technology become challenging and costly. In addition, when the packaging of 3D PCM chips develops from a 2-layer stack to a 4-layer stack, more layers of stack will continue to be developed in the future to achieve higher capacity and higher storage density. However, stacking upwards will face many problems, such as process alignment problems, stress problems, etc.

[0046] The inventors found that the introduction of chiplet technology will bring new solutions to the current chip technology development problems. Chiplet technology starts from the system end, first decomposing complex functions, and then developing a variety of bare chips with single specific functions that can be modularly assembled with each other, such as realizing data storage, computing, signal processing, data flow management and other functions, and finally building a chip network based on this.

[0047] Based on the above ideas, the present invention provides a phase change memory and a preparation method thereof, including: a first peripheral circuit chip formed on a substrate, and at least one storage structure formed on the substrate; the storage structure includes at least two first phase change memory chips stacked in sequence on the substrate; the first phase change memory chips all have a single function, and each of the first phase change memory chips has a first contact that runs through it; adjacent first phase change memory chips are connected through the first contact. The phase change memory provided by the present invention separates the peripheral circuit from the storage, and stacks the phase change memory chips with a single function through the chiplet packaging technology to improve the integration density. Furthermore, due to the use of chiplet technology packaging, chips with single functions such as storage and logic can be modularized and packaged together to achieve high-performance phase change memory chips, and the phase change memory design is less difficult and has a lower design cost.

[0048] Embodiment 1

[0049] Figure 3 A planar layout diagram of a phase change memory provided in this embodiment, Figure 4 A schematic cross-sectional structure diagram of a phase change memory provided in this embodiment. Figure 3 and Figure 4The phase change memory provided in this embodiment includes: a first peripheral circuit chip (Peri.1) formed on a substrate (Board), and at least one storage structure formed on the substrate; the storage structure includes at least two first phase change memory chips (PCM1, PCM2) stacked in sequence on the substrate; the first phase change memory chips (PCM1, PCM2) each have a single function, and each of the first phase change memory chips has a first contact that runs through it; adjacent first phase change memory chips are connected via the first contacts.

[0050] In the embodiment of the present invention, one storage structure and two first phase-change memory chips are taken as examples for illustration, but this is not intended to limit the protection scope of the present invention.

[0051] Specifically, the substrate (Board) is, for example, a PCB substrate, and may include a first functional module area and a second functional module area, for example, the first functional module area is a peripheral circuit area, and the second functional module area is a storage area. The first peripheral circuit chip (Peri.1) may be located in the first functional module area, and the first two phase change memory chips (PCM1, PCM2) may be bonded to the second functional module area through chiplet technology.

[0052] For example, the first peripheral circuit chip (Peri.) and the phase change memory chip (PCM1) can be formed on the first substrate (Sub1) and the second substrate (Sub2) respectively, and the first substrate (Sub1) and the second substrate (Sub2) are respectively bonded to the first functional module area and the second functional module area of ​​the substrate. Then, the first phase change memory chip (PCM2) is bonded to the first phase change memory chip (PCM1) on the second substrate (Sub2) by chiplet technology to realize the stacking package of the phase change memory chip. In some other embodiments of the present invention, the first substrate (Sub1) and the second substrate (Sub2) corresponding to the first functional module area and the second functional module area are formed on the substrate according to the design, and then the first peripheral circuit chip (Peri.1) and the first phase change memory chip (PCM1) are formed directly on the first substrate (Sub1) and the second substrate (Sub2), respectively, and the stacking of the first phase change memory chip (PCM2) is subsequently completed.

[0053] Preferably, in the present embodiment, the first phase-change memory chip may be a two-layer stacked memory array structure, that is, the phase-change memory chip (PCM1) and the phase-change memory chip (PCM2) may both have a two-layer stacked memory array structure, and the two-layer stacked memory array structure may be implemented using existing process technology. In some other embodiments of the present invention, the phase-change memory chip includes a single-layer memory array structure and a two-layer stacked memory array structure, for example, the first phase-change memory chip (PCM1) is a two-layer stacked memory array structure, and the first phase-change memory chip (PCM2) is a single-layer memory array structure.

[0054] For example, Figure 7 It is a single memory cell segment in a two-layer stacked memory array structure, wherein an upper memory cell 140 is located between a top bit line 110 and a word line 130, and is connected to the top bit line 110 and the word line 130; a lower memory cell 150 is located between a word line 130 and a bottom bit line 120, and is connected to the word line 130 and the bottom bit line 120, and the upper memory cell 140 and the lower memory cell 150 include a stacked phase change memory layer 102, a selection layer 104, and electrode layers 101, 103, 105.

[0055] On the other hand, in some embodiments, the adjacent first phase change memory chips may have the same storage array structure, that is, the storage array structure in the first phase change memory chip (PCM1) and the first phase change memory chip (PCM2) is the same, and the stacking of the first phase change memory chip (PCM1) and the first phase change memory chip (PCM2) is just the stacking of the same storage array structure up and down. In some embodiments, at least two first phase change memory chips may have different storage array structures, that is, the storage array structures in the first phase change memory chip (PCM2) and the first phase change memory chip (PCM1) are different, such as the array arrangement of the storage units in the storage array structure is different, and the stacking of the two is not just a simple repetition of the upper and lower stacking layers. Different storage array structures can be designed for different practical application requirements, and Chiplet technology can be used accordingly to realize the 3D packaging of the first phase change memory chip with different storage array structures.

[0056] In addition, in this embodiment, at least two first phase change memory chips have a single function, that is, the first phase change memory chip (PCM1) and the first phase change memory chip (PCM2) each have an independent single function. For example, the first phase change memory chip (PCM1) is a chip with a single storage function, and the second phase change memory chip (PCM2) is a chip with a single data processing function.

[0057] In this embodiment, each of the first phase-change memory chips has a first contact that penetrates through, and adjacent first phase-change memory chips are connected via the first contacts. Figure 5H As shown, the structure of the first contact includes: a through hole 210 penetrating the first phase change memory chip, a barrier layer 201 deposited on the sidewall of the through hole, a conductive layer 202 filling the through hole, and a pad 205 located on the conductive layer 202 .

[0058] Wherein, an adhesion layer 203 and a seed layer 204 are also arranged on the two opposite surfaces of the first phase change memory chip, wherein the seed layer 204 is located on the adhesion layer 203, the conductive layer 202 penetrates the adhesion layer 203 and connects the seed layer 204, and the pad 205 is located on the seed layer 204 and is arranged corresponding to the through hole 210. The material of the conductive layer 202 is, for example, metallic copper, the material of the barrier layer 201 is, for example, silicon nitride (SiN), and the seed layer 204 is, for example, a Ti / Cu seed layer. The pad 205 includes a copper layer 205a connected to the seed layer 204 and a tin layer 205b located on the copper layer 205a. Adjacent first phase change memory chips are connected via the tin layer 205b on the pad 205.

[0059] Correspondingly, the present invention also provides a method for preparing a phase change memory, comprising: forming a first peripheral circuit chip on a substrate, and forming at least one storage structure on the substrate; the step of forming the storage structure comprises: providing at least two first phase change memory chips, and the first phase change memory chips each have a single function; forming a penetrating first contact on each of the first phase change memory chips; at least two of the first phase change memory chips are connected through the first contact, and at least two interconnected first phase change memory chips are formed on the substrate.

[0060] in, FIG. 5A to FIG. 5H As shown in FIG. 1 , the process of forming a through first contact in each of the first phase change memory chips includes: first, as shown in FIG. Figure 5A and Figure 5B As shown, a first phase change memory chip 200 is provided, and a micro-hole 210 is formed by a deep silicon etching process; then, as shown in FIG. Figure 5C and Figure 5D As shown, a barrier layer 201 is formed on the sidewall of the through hole 210 and the surface of the first phase change memory chip 200, and a conductive layer 202 (such as metal copper) is filled in the through hole 210, and a metal redistribution line (not shown in the figure) is prepared on the surface of the first phase change memory chip 200; then, as shown Figure 5E As shown, chemical polishing and thinning process are performed to form a first contact through hole; then, as shown Fig. 5FAs shown, an adhesion layer 203 and a seed layer 204 are deposited on the surface of the first phase change memory chip 200; then, as shown in Figure 5G and Figure 5H As shown, a pad 205 is made and the excess adhesion layer 203 and seed layer 204 are removed. The pad 205 includes a copper layer 205a and a tin layer 205b located on the surface of the copper layer 205a. Adjacent first phase change memory chips (PCM1, PCM2) are electrically connected via the pads of the first contacts.

[0061] Embodiment 2

[0062] Figure 6 A planar layout diagram of a phase change memory provided in this embodiment, Figure 7 A schematic diagram of a phase change memory provided in this embodiment; Figure 8 A schematic cross-sectional structure diagram of a phase change memory provided in this embodiment. Figures 7 and 8 The phase change memory provided in this embodiment includes: a first peripheral circuit chip (Peri.1) formed on a substrate (Board), and at least one storage structure formed on the substrate; the storage structure includes at least two first phase change memory chips (PCM21, PCM22) stacked in sequence on the substrate; the first phase change memory chips (PCM21, PCM22) each have a single function, and each of the first phase change memory chips has a first contact that runs through it; adjacent first phase change memory chips are connected via the first contacts.

[0063] The storage structure also includes a second peripheral circuit chip (Peri.2), which is formed on the substrate, and the at least two first phase change memory chips (PCM21, PCM22) are stacked and packaged on the second peripheral circuit chip (Peri.2) in sequence.

[0064] The phase change memory also includes at least two second phase change memory chips (PCM11, PCM12) stacked and packaged in sequence on the first peripheral circuit chip (Peri.1), the second phase change memory chips each have a single function, and each of the second phase change memory chips has a second contact that runs through it; adjacent second phase change memory chips are connected via the second contacts.

[0065] Furthermore, the first peripheral circuit chip (Peri.1) and the second peripheral circuit chip (Peri.2) both have a third contact that runs through them, and the first peripheral circuit chip (Peri.1) is connected to the substrate and the second contact of the second phase change memory chip (PCM11) through the third contact; the second peripheral circuit chip (Peri.2) is connected to the substrate and the first contact of the first phase change memory chip (PCM21) through the third contact.

[0066] Specifically, the substrate (Board) is, for example, a PCB substrate. Figure 7 As shown, at least two first phase-change memory chips (PCM21, PCM22) are bonded to the second peripheral circuit chip (Peri.2) through chiplet technology, and at least two second phase-change memory chips (PCM11, PCM12) are bonded to the first peripheral circuit chip (Peri.1) through chiplet technology.

[0067] In this embodiment, two first phase-change memory chips and two second phase-change memory chips are taken as an example for illustration, but this is not intended to limit the protection scope of the present invention.

[0068] The first peripheral circuit chip (Peri.1) and the second peripheral circuit chip (Peri.2) can be first formed on a first substrate (Sub1) and the second substrate (Sub2), respectively, and the first substrate (Sub1) and the second substrate (Sub2) are respectively bonded to the first functional module area and the second functional module area of ​​the substrate. Then, the second phase change memory chip (PCM11, PCM12) and the first phase change memory chip (PCM21, PCM22) are respectively bonded to the first peripheral circuit chip (Peri.1) and the second peripheral circuit chip (Peri.2) through chiplet technology to realize stacked packaging of phase change memory chips. In some other embodiments of the present invention, the required first substrate (Sub1) and second substrate (Sub2) are formed on the substrate according to the design, and then the first peripheral circuit chip (Peri.1) and the second peripheral circuit chip (Peri.2) are formed directly on the first substrate (Sub1) and the second substrate (Sub2), respectively, and subsequently the stacking of the second phase change memory chip (PCM11, PCM12) and the first phase change memory chip (PCM21, PCM22) is completed.

[0069] In some embodiments, the storage array structure of the second phase change memory chip (PCM11, PCM12) located in the first functional module area is the same as the storage array structure of the first phase change memory chip (PCM21, PCM22) located in the second functional module area; in some embodiments, the storage array structure of the second phase change memory chip (PCM11, PCM12) located in the first functional module area is different from the storage array structure of the first phase change memory chip (PCM21, PCM22) located in the second functional module area. Similarly, the storage array structures of the second phase change memory chips located in the first functional module area can be the same or different; the storage array structures of the first phase change memory chips located in the second functional module area can be the same or different.

[0070] In this embodiment, the first phase change memory chip (PCM21, PCM22) and the second phase change memory chip (PCM11, PCM12) each have an independent single function. The first contact, the second contact and the third contact have the same structure. Taking the first contact as an example, Figure 5H As shown, the structure of the first contact includes: a through hole 210 penetrating the first phase-change memory chip, a conductive layer 202 filling the through hole, and a pad 205 located on the conductive layer 202. The first phase-change memory chip is also provided with an adhesion layer 203 and a seed layer 204 on two opposite surfaces, wherein the seed layer 204 is located on the adhesion layer 203, the conductive layer 202 penetrates the adhesion layer 203 and connects the seed layer 204, the pad 205 is located on the seed layer 204, and is arranged corresponding to the through hole 210. Further, a barrier layer 201 is also provided on the side wall of the through hole 210, the material of the conductive layer 202 is, for example, metal copper, and the material of the barrier layer 201 is, for example, silicon nitride (SiN). The pad 205 includes a copper layer 205a connected to the seed layer 204 and a tin layer 205b located on the copper layer 205a. Adjacent first phase-change memory chips are connected via the tin layer 205 b on the pad 205 .

[0071] like Figure 8As shown, the second phase change memory chip (PCM11) and the second phase change memory chip (PCM12) are connected through the first contact, and the first contact of the second phase change memory chip (PCM11) is connected to the third contact of the first peripheral circuit chip (Peri.1); correspondingly, the first phase change memory chip (PCM21) and the first phase change memory chip (PCM22) are connected through the second contact, and the second contact of the first phase change memory chip (PCM21) is connected to the third contact of the second peripheral circuit chip (Peri.2). Preferably, the first substrate (Sub1) and the second substrate (Sub2) also have a fourth contact that penetrates, and the fourth contact of the first substrate (Sub1) is respectively connected to the third contact of the first peripheral circuit chip (Peri.1) and the substrate, and the fourth contact of the second substrate (Sub1) is respectively connected to the third contact of the second peripheral circuit chip (Peri.2) and the substrate.

[0072] In summary, the present invention provides a phase change memory and a preparation method thereof, comprising a first peripheral circuit chip formed on a substrate and at least one storage structure formed on the substrate, wherein the storage structure comprises at least two first phase change memory chips stacked in sequence on the substrate; the first phase change memory chips each have a single function, and each of the first phase change memory chips has a first contact that penetrates through; adjacent first phase change memory chips are connected via the first contact. The phase change memory provided by the present invention separates the peripheral circuit from the storage, and stacks the single-function phase change memory chips through chiplet packaging technology to improve the integration density.

[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0074] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0075] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0076] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

[0077] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A phase change memory, characterized in that: include: a first peripheral circuit chip formed on the substrate, and at least one storage structure formed on the substrate; The storage structure comprises at least two first phase change memory chips sequentially stacked on a substrate; The first phase-change memory chips all have a single function, and each of the first phase-change memory chips has a first contact that penetrates through the first phase-change memory chips; adjacent first phase-change memory chips are connected via the first contacts; The structure of the first contact includes: a through hole penetrating the first phase-change memory chip, a barrier layer deposited on the side wall of the through hole, a conductive layer filling the through hole, and a pad located on the conductive layer.

2. The phase change memory according to claim 1, characterized in that: The storage structure further includes a second peripheral circuit chip, which is formed on the substrate, and the at least two first phase-change memory chips are stacked and packaged on the second peripheral circuit chip in sequence.

3. The phase change memory according to claim 2, characterized in that: It also includes at least two second phase-change memory chips stacked and packaged sequentially on the first peripheral circuit chip; The second phase-change memory chips all have a single function, and each of the second phase-change memory chips has a penetrating second contact; adjacent second phase-change memory chips are connected via the second contacts.

4. The phase change memory according to claim 3, characterized in that: The first peripheral circuit chip and the second peripheral circuit chip both have a third contact extending therethrough, and the first peripheral circuit chip is connected to the substrate and the second contact of the second phase-change memory chip through the third contact; The second peripheral circuit chip is connected to the substrate and the first contact of the first phase-change memory chip through the third contact.

5. The phase change memory according to claim 1, characterized in that: An adhesion layer and a seed layer are also provided on two opposite surfaces of the first phase change memory chip, wherein the seed layer is located on the adhesion layer, the conductive layer penetrates the adhesion layer and connects to the seed layer, and the pad is located on the seed layer and is provided corresponding to the through hole.

6. The phase change memory according to claim 4, characterized in that: The first contact, the second contact and the third contact have the same structure.

7. A method for preparing a phase change memory, characterized in that: include: forming a first peripheral circuit chip on a substrate, and forming at least one storage structure on the substrate; The steps of forming the storage structure include: providing at least two first phase-change memory chips, each of which has a single function; forming a first contact through each of the first phase-change memory chips; at least two of the first phase-change memory chips are connected through the first contact, and the interconnected at least two first phase-change memory chips are formed on the substrate; Wherein, the step of forming the first contact includes: forming a through hole penetrating the first phase-change memory chip; Depositing a barrier layer on the sidewalls of the through hole and two opposite surfaces of the first phase-change memory chip; Filling a conductive layer in the through hole; A pad is connected on the conductive layer.

8. The method for preparing a phase change memory according to claim 7, characterized in that: The step of forming the storage structure further includes: forming a second peripheral circuit chip on the substrate, wherein the at least two first phase-change memory chips are sequentially stacked and packaged on the second peripheral circuit chip; and / or, At least two second phase change memory chips are provided, and each of the second phase change memory chips has a single function; a penetrating second contact is formed on each of the second phase change memory chips; at least two of the second phase change memory chips are connected via the second contact, and the interconnected at least two second phase change memory chips are stacked and packaged in sequence on the first peripheral circuit chip.

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