Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device, comprising: a trench that defines an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. The present disclosure also provides a method for manufacturing a semiconductor device, the method comprising: forming a trench that defines an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing a pre-treatment before forming each semiconductor liner; and performing a post-treatment after forming each semiconductor liner.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0124457, filed on September 25, 2020, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Various embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a plurality of pre - processed and post - processed semiconductor liners and a method of manufacturing the same. Background art

[0004] As the integration degree of semiconductor devices increases, the area occupied by the active region of a transistor decreases. Therefore, the difficulty level of forming the active region increases, and the characteristics of the semiconductor device deteriorate. To solve this problem, a technique of forming a plurality of pre - processed and post - processed semiconductor liners has been proposed. Summary of the invention

[0005] Various embodiments of the present disclosure are directed to a semiconductor device and a method of manufacturing the same, including heat - treated trenches and semiconductor layers, which can improve the characteristics of the semiconductor device.

[0006] According to one embodiment, a semiconductor device may include: a trench that defines an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench.

[0007] According to another embodiment, a method of manufacturing a semiconductor device may include: forming a trench that defines an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing a pre - treatment before forming each of the semiconductor liners; and performing a post - treatment after forming each of the semiconductor liners.

[0008] According to still another embodiment, a method of manufacturing a semiconductor device may include: forming a trench that defines an active region in a substrate; replacing a first natural oxide formed on the trench with a first solid salt; sublimating the first solid salt to expose the surface of the trench; forming a first polysilicon liner over the trench; performing a post - treatment to remove contaminants formed on the first polysilicon liner; replacing a second natural oxide formed on the first polysilicon liner with a second solid salt; sublimating the second solid salt to expose the surface of the first polysilicon liner; forming a second polysilicon liner over the first polysilicon liner; and forming a device isolation layer that fills the trench over the second polysilicon liner. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 11 FIG. 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 12 FIG. 2 is a partial top view of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 13 FIG. 3 is a partial top view of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments described in the present disclosure will be described with reference to cross-sectional views, plan views, and block diagrams that are ideal schematic diagrams of the present disclosure. Therefore, the shapes of the various views may be modified according to manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure are not limited to the specific configurations shown in the respective views, but also include variations in configuration aspects that may result from manufacturing processes. That is, the regions shown in the drawings are general, and the shapes of the regions shown in the drawings illustrate specific shapes of component regions, rather than being intended to limit the scope of the present disclosure. In the drawings, thicknesses and spacings are expressed for ease of description and may be exaggerated compared to actual physical thicknesses. In the following description, detailed descriptions of known configurations irrelevant to the subject matter of the present disclosure may be omitted. It should be understood that in all the drawings, the same components are denoted by the same reference numerals, and will be so even if the components are shown in different drawings, if possible.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. For simplicity of description, the following description will be based on DRAM, but the concept of the present disclosure is not limited thereto and may be applied to other memories or semiconductor devices.

[0014] Figures 1 to 11 FIG. 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] As Figure 1 shown, a substrate 11 is prepared. The substrate 11 may include a semiconductor substrate. The substrate 11 may be made of a silicon-containing material or include a silicon-containing material. The substrate 11 may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multiple layers thereof. The substrate 11 may include other semiconductor materials such as germanium. The substrate 11 may include a group III-V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 11 may also include a silicon-on-insulator (SOI) substrate.

[0016] A trench hard mask 12 can be formed on the substrate 11. The trench hard mask 12 can include a dielectric material. The trench hard mask 12 can include a material having an etching selectivity with respect to the substrate 11. The trench hard mask 12 can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the trench hard mask 12 can include silicon nitride.

[0017] A trench pattern 13 can be formed on the trench hard mask 12. The trench pattern 13 can include a photoresist pattern. The trench pattern 13 can define an area where an active region is to be formed in a subsequent process. Although not shown, the top view of the trench pattern 13 can include a shape in which a pattern inclined in any direction is repeated in parallel. The top view of the trench pattern 13 can include a shape formed by repeating any one of a rectangle, an ellipse, and a rectangle with a curved corner inclined in any direction. The trench pattern 13 can define the active region through a subsequent process. The remaining portion not etched by the trench pattern 13 can include an area where a transistor is formed through a subsequent process.

[0018] As Figure 2 shown, the trench pattern 13 can be used as an etching mask to etch the trench hard mask 12. The trench hard mask 12 can be used as an etching mask to etch the substrate 11. After etching the substrate 11, the trench pattern 13 and the trench hard mask 12 can be removed. When etching the substrate 11, a first trench T1 and a second trench T2 can be formed.

[0019] The first trench T1 and the second trench T2 can define the active region 14. The second trench T2 can be formed to be spaced apart from the first trench T1. The first trench T1 and the second trench T2 can be adjacent to each other. The sidewall profiles of the first trench T1 and the second trench T2 can include inclined profiles. The widths of the first trench T1 and the second trench T2 can gradually decrease from the top to the bottom. In one embodiment (not shown), the first trench T1 and the second trench T2 can include vertical sidewall profiles. The first trench T1 can be formed deeper in the substrate 11 than the second trench T2. The depth of the first trench T1 can be greater than the depth of the second trench T2.

[0020] The first trench T1 can have a first width W1, and the second trench T2 can have a second width W2. Each of the first width W1 and the second width W2 can be measured in a first direction parallel to the upper surface of the substrate 11. The first direction can be the arrangement direction of the first trench T1 and the second trench T2. The first width W1 can be greater than the second width W2. For example, the first width W1 can be twice the second width W2.

[0021] When forming the first trench T1 and the second trench T2, a first contaminant O1 may be formed on the surfaces of the substrate 11 and the active region 14. The first contaminant O1 may be conformally formed along the surfaces of the substrate 11 and the active region 14. The first contaminant O1 may include an oxide. The first contaminant O1 may include a native oxide, such as a thin layer of silicon dioxide (SiO 2 )).

[0022] Figure 3 And Figure 4 FIG. is a diagram illustrating a first pretreatment process for removing the first contaminant O1. The first pretreatment process may include: replacing the first contaminant O1 with a first sacrificial material 15 ( Figure 3 ); and removing the first sacrificial material 15 as shown by reference numeral 15R ( Figure 4 ).

[0023] As Figure 3 shown, the first contaminant O1 may be replaced with the first sacrificial material 15. The first sacrificial material 15 may cover the substrate 11 and the active region 14. The first sacrificial material 15 may fill the first trench T1 and the second trench T2.

[0024] A nitrogen-containing gas, a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof may be used to form the first sacrificial material 15. The first contaminant O1 may be replaced with the first sacrificial material 15 by reacting with a nitrogen-containing gas, a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. For example, ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), and hydrogen (H 2 ) may be used to replace the first contaminant O1 with the first sacrificial material 15. In one embodiment, the amount of each gas may be adjusted according to the thickness of the first contaminant O1 formed on the surfaces of the substrate 11 and the active region 14, the shape of the substrate 11 and the active region 14, the capacity of the equipment used to form the first sacrificial material 15, etc. The ratio between the gases may be changed so as to uniformly remove the first contaminant O1 formed on the substrate 11 and the active region 14. For example, the molar ratio of ammonia (NH 3 ) to nitrogen trifluoride (NF 3 ) may be at least 1:1.

[0025] In another embodiment, a purge gas or a carrier gas may be further included. For a stable reaction, a purge gas or a carrier gas may be used before forming the first sacrificial material 15. The purge gas or the carrier gas may include helium, hydrogen, nitrogen, or a combination thereof. In this embodiment, hydrogen may be used as the purge gas or the carrier gas.

[0026] To replace the first contaminant O1 with the first sacrificial material 15, a nitrogen-containing gas, a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof can be decomposed into reactive species. To replace the first contaminant O1 with the first sacrificial material 15, ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), and hydrogen (H 2 ) can be decomposed into reactive species. Plasma can be used to decompose each gas into reactive species. The decomposed reactive species can recombine to form a reactive gas. The reactive gas can include ammonium fluoride (NH 4 F) and ammonium bifluoride (NH 4 F-HF).

[0027] The reactive gas can be reactive with the first contaminant O1. The reactive gas can react with the first contaminant O1. The reactive gas can react with the first contaminant O1 to form the first sacrificial material 15. The first sacrificial material 15 can be solid. The first sacrificial material 15 can be referred to as a "solid salt". The first sacrificial material 15 can contain hydrogen, nitrogen, fluorine, silicon, or a combination thereof. The first sacrificial material 15 can include, for example, ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ). The reaction mechanism for replacing the first contaminant O1 with the first sacrificial material 15 can be summarized as follows:

[0028] NF 3 (gas) + NH 3 (gas) + 3H 2 → NF 3 F(gas) + NH 4 -HF(gas)

[0029] NF 3 F(gas) + NH 4 -HF(gas) + SiO 2 → (NH 4 ) 2 SiF 6 (solid, salt)

[0030] As Figure 4 shown, a first heat treatment process 16 can be performed on the first sacrificial material 15.

[0031] Through the first heat treatment process 16, the first sacrificial material 15 can be removed as a volatile gas as shown by reference numeral 15R.

[0032] The first sacrificial material 15 can be converted into a volatile gas through the first heat treatment process 16. The first sacrificial material 15 can be sublimated into SiF 4 , NH3 and HF and remove them. The first heat treatment process 16 can be performed at a temperature below 150°C. In one embodiment, the first heat treatment process 16 can be performed at a temperature of 80°C to 150°C.

[0033] When the first sacrificial material 15 is removed as a gas as shown by the reference numeral 15R, the substrate 11 and the active region 14 can be exposed again. When the first sacrificial material 15 is sublimated into a gas as shown by the reference numeral 15R, the surface of the trench can be exposed again.

[0034] The reaction mechanism for sublimating the first sacrificial material 15 can be summarized as follows:

[0035] (NH 4 ) 2 SiF 6 (solid, salt) → SiF 4 (gas) + 2NH 3 (gas) + 2HF (gas) + H 2 O

[0036] By performing the first heat treatment process 16, the first sacrificial material 15 used to displace the first contaminant O1 can be removed while minimizing damage to the substrate 11 and the active region 14. Therefore, the quality of the semiconductor device can be improved.

[0037] As Figure 5 shown, a first semiconductor liner 17 can be formed on the substrate 11 and the active region 14. The first semiconductor liner 17 can be conformally formed on the surfaces of the first trench T1 and the second trench T2.

[0038] The first semiconductor liner 17 can cover the substrate 11 and the active region 14. The first semiconductor liner 17 can be conformally formed on the surfaces of the substrate 11 and the active region 14. The first semiconductor liner 17 can have a thickness greater than 0 nm and less than or equal to 4 nm.

[0039] The first semiconductor liner 17 can be grown from the substrate 11 and the active region 14. The first semiconductor liner 17 can be formed on the surfaces of the substrate 11 and the active region 14, for example, by a selective epitaxial growth (SEG) method or a selective polysilicon growth (SPG) method. Therefore, the first semiconductor liner 17 can include a silicon layer grown from the surfaces of the substrate 11 and the active region 14. The first semiconductor liner 17 can be formed at a temperature of 400°C to 900°C. A gas containing silicon, hydrogen, or a combination thereof can be used to form the first semiconductor liner 17. Disilane (Si 2 H 6) A gas is used to form the first semiconductor liner 17. The first semiconductor liner 17 can be formed of or include polycrystalline silicon (poly-Si). Therefore, the first semiconductor liner 17 can be referred to as the "first polycrystalline silicon liner".

[0040] A single equipment, furnace equipment, or a combination thereof can be used to form the first semiconductor liner 17. The first pretreatment process ( Figure 3 and Figure 4 ) and the formation of the first semiconductor liner ( Figure 5 17 in) can be performed in-situ in a system or non-in-situ in each equipment.

[0041] Even if the active region 14 is formed to have a small area, the width of the active region 14 can be increased by forming the first semiconductor liner 17 in a subsequent process, so the etching difficulty level during etching of the active region 14 can be reduced.

[0042] Subsequently, a second contaminant O2 can be formed on the first semiconductor liner 17. The second contaminant O2 can include the gas remaining in the first semiconductor liner 17. The second contaminant O2 can include the particles formed on the first semiconductor liner 17.

[0043] As Figure 6 shown, a post-treatment process 18 can be performed on the first semiconductor liner 17. The post-treatment process 18 can include a heat treatment process. The post-treatment process 18 can be performed by an annealing process or rapid thermal processing (RTP). The post-treatment process 18 can be performed at a temperature higher than that of the first heat treatment process 16. For the annealing process, the post-treatment process 18 can be performed at a temperature of 500 °C to 900 °C.

[0044] The post-treatment process 18 can be performed in a gas atmosphere. Nitrogen (N 2 ), hydrogen (H 2 ) or other gases can be used to create the gas atmosphere. By forming the gas atmosphere, oxidation of the first semiconductor liner 17, the substrate 11, and the active region 14 can be prevented.

[0045] Before performing the post-treatment process 18, further cleaning of the first semiconductor liner 17 can be included. Cleaning the first semiconductor liner 17 can include wet cleaning or dry cleaning. By further cleaning the first semiconductor liner 17, the second contaminant O2 remaining on the first semiconductor liner 17 can be additionally removed. Therefore, the quality of the semiconductor device can be improved.

[0046] The post-treatment process 18 can be performed in a single device, a furnace device, or a combination thereof. The post-treatment process 18 can be performed in-situ in the same device as the device used to form the first semiconductor liner 17 ( Figure 5 ), or can be performed ex-situ in another device.

[0047] By performing the post-treatment process 18, the second contaminant O2 formed on the first semiconductor liner 17 can be removed. Therefore, defects in the semiconductor device can be reduced. Additionally, even if a second semiconductor liner is formed on the first semiconductor liner 17 in a subsequent process, a high-quality semiconductor device can be obtained.

[0048] As Figure 7 shown, a third contaminant O3 can be formed on the first semiconductor liner 17. The third contaminant O3 can be formed without the need to perform a special process. The third contaminant O3 can be formed conformally along the surface of the first semiconductor liner 17. The third contaminant O3 can include oxides. The third contaminant O3 can include native oxides. The third contaminant O3 can be or include the same material as the first contaminant O1. The third contaminant O3 can be or include silicon dioxide (SiO 2 ).

[0049] Figure 8 And Figure 9 are diagrams depicting a second pre-treatment process for removing the third contaminant O3. The second pre-treatment process can include replacing the third contaminant O3 with a second sacrificial material 19 ( Figure 8 ); and removing the second sacrificial material 19 as shown by reference numeral 19R ( Figure 9 ). The second pre-treatment process can be similar to the first pre-treatment process ( Figure 3 and Figure 4 ).

[0050] As Figure 8 shown, the third contaminant O3 can be replaced with the second sacrificial material 19. The second sacrificial material 19 can cover the first semiconductor liner 17. The second sacrificial material 19 can be formed on the first semiconductor liner 17. In one embodiment, the second sacrificial material 19 can be formed of or include the same material as the first sacrificial material 15.

[0051] To form the second sacrificial material 19, a nitrogen-containing gas, a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof can be used. By reacting with a nitrogen-containing gas, a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof, the third contaminant O3 can be replaced by the second sacrificial material 19. For example, ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), and hydrogen (H 2) Replace the third contaminant O3 with the second sacrificial material 19. In one embodiment, the amount of each gas can be adjusted according to the thickness of the third contaminant O3 formed on the surface of the first semiconductor liner 17, the shape of the first semiconductor liner 17, and the capacity of the equipment used to form the second sacrificial material 19. The ratio between the gases can be changed to uniformly remove the third contaminant O3 formed on the first semiconductor liner 17. For example, the molar ratio of ammonia (NH 3 ) to nitrogen trifluoride (NF 3 ) can be at least 1:1.

[0052] In another embodiment, a purge gas or a carrier gas can be further included. For a stable reaction, a purge gas or a carrier gas can be used before the formation of the second sacrificial material 19. The purge gas or the carrier gas can include helium, hydrogen, nitrogen, or a combination thereof. In this embodiment, hydrogen can be used as the purge gas or the carrier gas.

[0053] To replace the third contaminant O3 with the second sacrificial material 19, a nitrogen-containing gas, a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof can be decomposed into reactive substances. Ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), and hydrogen (H 2 ) can be decomposed into reactive substances to replace the third contaminant O3 with the second sacrificial material 19. Plasma can be used to decompose each gas into reactive substances. The decomposed reactive substances can recombine to form a reaction gas. The reaction gas can include ammonium fluoride (NH 4 F) and ammonium bifluoride (NH 4 F-HF).

[0054] The reaction gas can be reactive with the third contaminant O3. The reaction gas can react with the third contaminant O3. The reaction gas can react with the third contaminant O3 to form the second sacrificial material 19. The second sacrificial material 19 can be solid. Therefore, the second sacrificial material 19 can be referred to as a "solid salt". The second sacrificial material 19 can contain hydrogen, nitrogen, fluorine, silicon, or a combination thereof. The second sacrificial material 19 can include ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ).

[0055] The reaction mechanism for replacing the third contaminant O3 with the second sacrificial material 19 can be summarized as follows:

[0056] NF 3 (gas) + NH 3 (gas) + 3H 2 → NF 3 F(gas) + NH 4 -HF(gas)

[0057] NF 3 F (gas) + NH 4 -HF (gas) + SiO 2 → (NH 4 ) 2 SiF 6 (solid, salt)

[0058] As Figure 9 shown, the second sacrificial material 19 can be removed by the second heat treatment process 20, as shown by reference numeral 19R. The second sacrificial material 19 can be converted into a volatile gas 19R by the second heat treatment process 20. The material 19 can be sublimated into SiF 4 , NH 3 and HF and removed. The second heat treatment process 20 can include a heat treatment process performed at a temperature of 150 °C or lower. In one embodiment, the second heat treatment process 20 can be performed at a temperature of 80 °C to 150 °C. When the second sacrificial material 19 is removed as shown by reference numeral 19R, the surface of the first semiconductor liner 17 can be exposed again.

[0059] The reaction mechanism for sublimating the second sacrificial material 19 can be summarized as follows:

[0060] (NH 4 ) 2 SiF 6 (solid, salt) → SiF 4 (gas) + 2NH 3 (gas) + 2HF (gas) + H 2 O

[0061] By performing the second heat treatment process 20, the second sacrificial material 19 used to displace the third contaminant O3 can be removed while minimizing damage to the first semiconductor liner 17 and the active region 14. Therefore, the quality of the semiconductor device can be improved.

[0062] As Figure 10 shown, a second semiconductor liner 21 can be formed on the first semiconductor liner 17. The second semiconductor liner 21 can cover the first semiconductor liner 17. The second semiconductor liner 21 can be conformally formed on the surface of the first semiconductor liner 17. The second semiconductor liner 21 can have a thickness greater than 0 nm and less than or equal to 4 nm. The second semiconductor liner 21 can have the same thickness as the first semiconductor liner 17.

[0063] The second semiconductor liner 21 can be formed from the first semiconductor liner 17 by a selective epitaxial growth (SEG) method or a selective polysilicon growth (SPG) method. Thus, the second semiconductor liner 21 can include a silicon layer grown from the surface of the first semiconductor liner 17. The second semiconductor liner 21 can be formed at a temperature of 400 °C to 900 °C. A gas containing silicon, hydrogen, or a combination thereof can be used to form the second semiconductor liner 21. Si 2 H 6 gas can be used to form the second semiconductor liner 21. The second semiconductor liner 21 can be formed of or include polysilicon (poly-Si). Thus, the second semiconductor liner 21 can be referred to as the "second polysilicon liner". The substrate 11, the first semiconductor liner 17, and the second semiconductor liner 21 can be formed of or include a silicon-containing material.

[0064] A single device, a furnace device, or a combination thereof can be used to form the second semiconductor liner 21. The second pretreatment process ( Figure 8 and Figure 9 ) and the formation of the second semiconductor liner ( Figure 10 21 in) can be performed in-situ in a single device or non-in-situ in each device.

[0065] Although not shown, a second post-treatment process can be performed on the second semiconductor liner 21 after the second semiconductor liner 21 is formed. The second post-treatment process can be performed in the same manner as the post-treatment process ( Figure 6 18 in) performed on the first semiconductor liner 17. By performing the second post-treatment process, contaminants such as particles or residual gases formed on the second semiconductor liner 21 can be removed. Thus, defects in the semiconductor device can be reduced.

[0066] As Figure 11 shown, a device isolation layer 22 can be formed above the substrate 11.

[0067] The device isolation layer 22 can be formed on the second semiconductor liner 21. The device isolation layer 22 can fill the space between the active regions 14. The upper surface of the device isolation layer 22 can be at the same level as the upper surface of the second semiconductor liner 21. A planarization process can be performed to form the device isolation layer 22. The device isolation layer 22 can include, for example, silicon nitride, silicon oxide, or a combination thereof.

[0068] Figure 12 is a partial top view taken along the line A-A' of Figure 11 .

[0069] As Figure 12As shown, the first semiconductor liner 17 may include a shape surrounding the active region 14. The second semiconductor liner 21 may include a shape surrounding the first semiconductor liner 17. The device isolation layer 22 may be filled between the second semiconductor liners 21 surrounding adjacent active regions 14.

[0070] In the present disclosure, even if the active region 14 is formed to have a small area, the width of the active region 14 can be increased by forming the first semiconductor liner 17 and the second semiconductor liner 21 in subsequent processes. Therefore, the etching difficulty level when etching the active region 14 can be reduced. Since the first semiconductor liner 17 and the second semiconductor liner 21 are formed after etching the active region 14, the width and depth of the active region 14 can be adjusted. Therefore, the characteristics of the semiconductor device can be improved.

[0071] In addition, after forming the first semiconductor liner 17, impurities are removed by performing a post-treatment process 18, and then the second semiconductor liner 21 is formed on the first semiconductor liner 17. Therefore, the active region 14 can grow to a predetermined thickness or greater without degrading the quality of the surface of the active region 14. Therefore, the depth and width of the active region 14 can be ensured.

[0072] Figure 13 is a partial top view of another embodiment. Although only the first semiconductor liner 17 and the second semiconductor liner 21 are described in the above embodiment, the present disclosure is not limited thereto, and thus a plurality of semiconductor liners may be stacked in other embodiments.

[0073] As Figure 13 shown, a third semiconductor liner 23 surrounding the second semiconductor liner 21 may be formed on the second semiconductor liner 21. The third semiconductor liner 23 may be formed by repeating the method of forming the second semiconductor liner 21. Therefore, the second post-treatment process for the second semiconductor liner 21, the third pre-treatment process for the second semiconductor liner 21, and the formation of the third semiconductor liner 23 can be performed sequentially.

[0074] Specifically, a second post-treatment process (not shown) may be performed on the second semiconductor liner 21. The second post-treatment process (not shown) may be performed in the same manner as the first post-treatment process ( Figure 6 18 in). Therefore, the second post-treatment process (not shown) may be performed by an annealing process or rapid thermal processing (RTP).

[0075] Subsequently, a third pre-treatment process may be performed to remove contaminants formed on the second semiconductor liner 21. The third pre-treatment process may be performed in the same manner as the second pre-treatment process ( Figure 8 and Figure 9) be performed in the same manner. Therefore, after replacing the contaminants with the sacrificial material, the sacrificial material can be sublimated and removed by a heat treatment process. The mechanism of removing contaminants can be summarized as follows:

[0076] NF 3 (gas) + NH 3 (gas) + 3H 2 → NF 3 F (gas) + NH 4 -HF (gas)

[0077] NF 3 F (gas) + NH 4 -HF (gas) + SiO 2 → (NH 4 ) 2 SiF 6 (solid, salt)

[0078] (NH 4 ) 2 SiF 6 (solid, salt) → SiF 4 (gas) + 2NH 3 (gas) + 2HF (gas) + H 2 O

[0079] Subsequently, a third semiconductor liner 23 can be formed on the second semiconductor liner 21. The third semiconductor liner 23 can be formed from the second semiconductor liner 21 by a selective epitaxial growth (SEG) method or a selective polysilicon growth (SPG) method. The third semiconductor liner 23 can include a silicon layer grown from the surface of the second semiconductor liner 21. The third semiconductor liner 23 can include polysilicon (poly-Si).

[0080] Although not shown, multiple semiconductor liners can be stacked in the same manner.

[0081] As described above, according to the present technology, contaminants on the substrate can be removed by pre-treating the semiconductor liner. Therefore, the characteristics of the semiconductor device can be improved.

[0082] According to the present technology, contaminants on the semiconductor liner can be removed and defects in the semiconductor device can be reduced by post-treating the semiconductor liner.

[0083] According to the present technology, the difficulty level of etching for forming trenches can be reduced and the width and depth of the active region can be ensured by stacking multiple semiconductor liners.

[0084] Although the present disclosure has been shown and described with respect to particular embodiments, the disclosed embodiments are provided for purposes of description and not of limitation. Additionally, it should be noted that, as will be recognized by those skilled in the art in light of the present disclosure, the present disclosure may be implemented in various ways by substitutions, changes, and modifications that fall within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: a trench defining an active region in a substrate; a first semiconductor liner on the trench; a second semiconductor liner on the first semiconductor liner; and a device isolation layer on the second semiconductor liner and filling the trench; the first semiconductor liner includes a polysilicon layer grown from the surface of the trench, and the second semiconductor liner includes a polysilicon layer grown from the surface of the first semiconductor liner.

2. The semiconductor device according to claim 1, wherein, the first semiconductor liner and the second semiconductor liner are conformally formed on the surface of the trench.

3. The semiconductor device according to claim 1, wherein, the device isolation layer includes silicon nitride, silicon oxide, or a combination thereof.

4. A method for manufacturing a semiconductor device, the method comprising: forming a trench defining an active region in a substrate; growing a plurality of semiconductor liners on the surface of the trench; performing a pre-treatment before forming each of the semiconductor liners; and performing a post-treatment after forming each of the semiconductor liners; wherein, the plurality of semiconductor liners are a polysilicon stack, and the polysilicon stack is stacked to contact each other.

5. The method according to claim 4, wherein, the step of performing the pre-treatment includes: replacing contaminants with a sacrificial material, wherein the contaminants are generated before forming each of the semiconductor liners; and performing a heat treatment to remove the sacrificial material.

6. The method according to claim 5, wherein, the step of replacing the contaminants with the sacrificial material is performed by using a reactive gas reactive with the contaminants.

7. The method as claimed in claim 6, wherein, The reaction gas is formed using ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), and hydrogen gas (H 2 ).

8. The method according to claim 5, wherein, the contaminants include silicon oxide, and The sacrificial material includes ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ).

9. The method according to claim 4, wherein, the post-treatment is performed at a higher temperature than the pre-treatment.

10. The method according to claim 4, wherein, the post-treatment is performed by an annealing process or rapid thermal processing (RTP).

11. The method according to claim 4, wherein, The post-treatment is carried out in a gas atmosphere containing one of nitrogen (N 2 ) and hydrogen (H 2 ).

12. The method according to claim 4, further comprising: cleaning each of the semiconductor liners before performing the post-treatment.

13. The method according to claim 4, wherein, the pre-treatment and the formation of the semiconductor liners are performed in-situ.

14. The method according to claim 4, wherein, the post-treatment is performed in-situ or non-in-situ.

15. A method for manufacturing a semiconductor device, the method comprising: forming a trench defining an active region in a substrate; replacing a first native oxide formed on the trench with a first solid salt; subliming the first solid salt to expose the surface of the trench; growing a first polysilicon liner on the surface of the trench; performing a post-treatment to remove contaminants formed on the first polysilicon liner; replacing a second native oxide formed on the first polysilicon liner with a second solid salt; subliming the second solid salt to expose the surface of the first polysilicon liner; A second polysilicon liner is formed over the first polysilicon liner; and a device isolation layer filling the trench is formed over the second polysilicon liner.

16. The method according to claim 15, wherein the step of replacing the corresponding first native oxide and second native oxide with the first solid salt and the second solid salt is performed by using a reactive gas reactive with the first native oxide and the second native oxide.

17. The method according to claim 16, wherein The reaction gas is formed using ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), and hydrogen gas (H 2 ).

18. The method according to claim 15, wherein The first solid salt and the second solid salt include ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ).

19. The method according to claim 15, wherein the post-treatment is performed at a temperature higher than the sublimation temperature of the first solid salt and the second solid salt.

20. The method according to claim 15, wherein the post-treatment is performed by an annealing process or rapid thermal processing (RTP).

21. The method according to claim 15, wherein The post-treatment is carried out in a gas atmosphere containing one of nitrogen (N 2 ) and hydrogen (H 2 ).

22. The method according to claim 15, further comprising: cleaning the first polysilicon liner before performing the post-treatment.

23. The method according to claim 15, wherein the post-treatment is performed in-situ or ex-situ.

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