A shielded gate structure for improving drain-source leakage

Abstract

The invention discloses a shielding gate structure for improving drain-source leakage, comprising an active region, a terminal region surrounding the active region and a gate lead region; the length of a first cell groove in the active region is greater than that of a second cell groove; the terminal region comprises at least one terminal groove surrounding the cell groove, one side of the terminal groove close to the end of the cell groove has a wave shape, and the other side is a straight line shape or a wave shape, and each wave shape close to the end of the cell groove is located between two adjacent cell grooves, and the vertex of the wave shape is located in the middle; near the corner of the gate lead region, the first cell groove adjacent to the second cell groove is provided with at least one wave shape, and the wave shape is located between the end of the second cell groove and the terminal groove; by arranging a wave structure on one side of the terminal groove close to the active region groove, the depletion layer depletion pinch-off effect of the region is strengthened, the electric field is evenly distributed, thereby alleviating the curvature of the leakage weak area, and improving the drain-source IDSS leakage.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuit chip manufacturing, in particular to a shielding gate structure for improving drain-source leakage, belonging to the field of semiconductor technology. Background Art

[0002] Shielded gate trench (Split-Gate Trench, SGT) semiconductor devices have the advantages of low conduction loss, low gate charge, fast switching speed, low device heat generation and high energy efficiency. The products can be widely used in power supplies or adapters for high-end consumer electronic products such as personal computers, laptops, netbooks or mobile phones, lighting (high-pressure gas discharge lamps) products, and televisions (LCD or plasma TVs) and game consoles.

[0003] For semiconductor devices with shielded gate structure, the withstand voltage is mainly borne by the thick oxygen column of the gate structure under the deep trench structure. When testing the shielded gate structure device, it is very easy to have the problem of excessive drain-source leakage IDSS. Hot spot analysis found that the leakage position is as follows: Figure 1 As shown, the IV curve Figure 2 As shown in the figure, there are three main types of leakage locations:

[0004] 1. A is located between the ends of the cell groove;

[0005] 2. B is located at the corner adjacent to the active area and the terminal area;

[0006] 3. C is located at the corner where the gate lead area meets the active area;

[0007] The curvature of positions A, B, and C is larger than that of other positions. The larger the curvature, the more concentrated the electric field lines are at that position, and the electric field is unbalanced, making that position weaker than other positions, prone to IDSS leakage, and with reduced reliability. Summary of the invention

[0008] The purpose of the present invention is to overcome the drain-source IDSS leakage problem existing in the prior art and to provide a shielded gate structure for improving the drain-source leakage. By setting a waveform structure on one side of the terminal groove close to the active area groove (the waveform structure is set at positions A, B, and C), the depletion layer depletion pinch-off effect in the area can be enhanced, and the electric field can be evenly distributed, thereby alleviating the curvature of the leakage weak area, thereby improving the drain-source IDSS leakage problem and improving the device reliability.

[0009] To achieve the above technical objectives, the present invention provides a shielding gate structure for improving drain-source leakage, comprising an active area, a terminal area surrounding the active area and a gate lead area; characterized in that: the active area comprises a cell groove, the cell groove comprises a first cell groove and a second cell groove arranged parallel to the first cell groove, and the length of the first cell groove is greater than that of the second cell groove; the terminal area comprises at least one terminal groove surrounding the cell groove, one side of the terminal groove near the end of the cell groove has a wavy shape, and the other side is a straight line shape, and each wavy shape is located between two adjacent cell grooves; the vertex of the wavy shape is located in the middle, and near the corner of the gate lead area, the first cell groove adjacent to the second cell groove is provided with at least one wavy shape, and it is located between the end of the second cell groove and the terminal groove.

[0010] Further, the shielded gate device is formed on a first conductive type substrate, the first conductive type substrate includes a first conductive type substrate and a first conductive type epitaxial layer located on the first conductive type substrate, the cell trench is arranged in the first conductive type epitaxial layer, a second conductive type body region is arranged between the cell trenches, and a first conductive type source region is arranged on both sides of the second conductive type body region;

[0011] The cell trench is filled with gate polysilicon and shielding gate polysilicon, the gate polysilicon and shielding gate polysilicon are isolated by a first insulating layer, the shielding gate polysilicon and the first conductive type epitaxial layer are isolated by a second insulating layer, and the gate polysilicon and the second conductive type body are isolated by a gate oxide layer.

[0012] Furthermore, a third insulating layer is disposed on the first conductive type epitaxial layer, a source metal is disposed on the third insulating layer, and the source metal penetrates the third insulating layer to respectively make ohmic contact with the second conductive type body region and the first conductive type source region.

[0013] Furthermore, in the MOSFET with a shielded gate structure for improving drain-source leakage, a gate metal separated from the source metal is also provided on the third insulating layer, the shield gate polysilicon is in ohmic contact with the source metal through a cell trench lead-out end, and the gate polysilicon is in ohmic contact with the gate metal through another lead-out end of the cell trench.

[0014] Furthermore, in the super barrier rectifier (SBR) with a shielded gate structure for improving drain-source leakage, the shielded gate polysilicon is in ohmic contact with the source metal through a cell trench lead-out end, and the source metal penetrates the third insulating layer and is in ohmic contact with the gate polysilicon.

[0015] Furthermore, the wave-shaped portion includes a triangle, a rectangle, or a semicircle.

[0016] Furthermore, the cell grooves are strip-shaped.

[0017] Furthermore, the shape of the end of the cell groove includes a rectangle and a semicircle.

[0018] Furthermore, the distance between the end angle of the second cell groove and the corner of the terminal groove is a, the distance between the end angle of the second cell groove and the crest of the waveform part is c, the distance between the end of the second cell groove and the trough of the waveform part is b, and a=b=c.

[0019] Furthermore, at the corner of the gate lead area, the distance between the end foot of the second-type cell groove and the peak of the waveform part of the first cell groove is d1, the distance between the peak of the waveform part of the first cell groove and the peak of the waveform part is d2, the distance between the first cell groove and the second-type cell groove is e, and d1=d2=e.

[0020] The beneficial technical effects of the present invention are:

[0021] (1) The present invention provides a wave-shaped structure on one side of the terminal groove near the end of the cell groove, and each wave-shaped structure is located between two adjacent cell grooves. This configuration can evenly disperse the electric field line distribution at positions A and B, reduce the drain-source leakage IDSS at this location, and further improve the device reliability.

[0022] (2) In the present invention, at the corner near the gate lead area, the first cell groove adjacent to the second cell groove is provided with at least one wavy shape, and the wavy shape is located between the end of the second cell groove and the terminal groove. Such a setting can evenly disperse the electric field line distribution at the C position, reduce the drain-source leakage IDSS at this location, and further improve the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 The schematic diagram is a structural diagram of the drain-source leakage hotspot of the existing shielded gate structure.

[0025] Figure 2 It is the IV curve of leakage of the existing shielding grid structure.

[0026] Figure 3It is a schematic diagram of the top structure of Example 1 and Example 2 of the present invention.

[0027] Figure 4 For the present invention Figure 3 Schematic diagram of the enlarged structure.

[0028] Figure 5 It is a schematic diagram of the cross-sectional structure of A1-A2 in Example 1 of the present invention.

[0029] Figure 6 It is a schematic diagram of the cross-sectional structure of A1-A2 in Example 2 of the present invention.

[0030] Figure 7 It is a schematic diagram of the top view structure of Example 3 and Example 4 of the present invention.

[0031] Figure 8 For the present invention Figure 7 Schematic diagram of the enlarged structure.

[0032] Fig. 9 It is a schematic diagram of the cross-sectional structure of A1-A2 in Example 3 of the present invention.

[0033] Fig.10 It is a schematic diagram of the cross-sectional structure of A1-A2 in Example 4 of the present invention.

[0034] Fig.11 It is the IV curve of the shielded grid structure of the present invention.

[0035] In the accompanying drawings: 1-first cell trench; 2-second cell trench; 3-terminal trench; 4-first conductive type substrate; 5-first conductive type epitaxial layer; 6-gate polysilicon; 7-shielding gate polysilicon; 8-first insulating layer; 9-second insulating layer; 10-second conductive type body region; 11-gate oxide layer; 12-third insulating layer; 13-source metal; 14-first conductive type source region; 001-active region; 002-terminal region; 003-gate lead region. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0038] Embodiment 1 provides a shielded gate MOSFET with a top-bottom structure that improves drain-source leakage.

[0039] As attached Figure 3 As shown, the shielded gate MOSFET includes an active area 001, a terminal area 002 surrounding the active area 001, and a gate lead area 003; the active area 001 includes a cell groove, the cell groove includes a first cell groove 1 and a second cell groove 2 arranged parallel to the first cell groove 1, and the length of the first cell groove 1 is greater than the second cell groove 2; the terminal area 002 includes at least one terminal groove 3 surrounding the cell groove, and the terminal groove 3 near the end of the cell groove has a wavy shape on one side and a straight line shape on the other side, and each wavy shape is located between two adjacent cell grooves; the vertex of the wavy shape is located in the middle, and near the corner of the gate lead area 003, the first cell groove 1 adjacent to the second cell groove 2 is provided with at least one wavy shape, and it is located between the end of the second cell groove 2 and the terminal groove 3.

[0040] As attached Figure 4 As shown, the distance between the end angle of the second cell groove 2 and the corner of the terminal groove 3 is a, the distance between the end angle of the second cell groove 2 and the crest of the waveform part is c, the distance between the end of the second cell groove 2 and the trough of the waveform part is b, and a=b=c.

[0041] At the corner of the gate lead area 003, the distance between the end foot of the second-type cell groove 2 and the peak of the waveform part of the first cell groove 1 is d1, the distance between the peak of the waveform part of the first cell groove 1 and the peak of the waveform part is d2, the distance between the first cell groove 1 and the second-type cell groove 2 is e, and d1=d2=e.

[0042] like Figure 5 As shown, the shielded gate MOSFET is formed on a first conductive type substrate, the first conductive type substrate includes a first conductive type substrate 4 and a first conductive type epitaxial layer 5 located on the first conductive type substrate 4, the cell trench is arranged in the first conductive type epitaxial layer 5, a second conductive type body region 10 is arranged between the cell trenches, and a first conductive type source region 14 is arranged on both sides of the second conductive type body region 10;

[0043] The cell trench is filled with gate polysilicon 6 and shielding gate polysilicon 7. The gate polysilicon 6 is located above the shielding gate polysilicon 7, and the gate polysilicon 6 and the shielding gate polysilicon 7 are isolated by a first insulating layer 8. The shielding gate polysilicon 7 is isolated from the first conductive type epitaxial layer 5 by a second insulating layer 9. The gate polysilicon 6 is isolated from the second conductive type body region 10 by a gate oxide layer 11.

[0044] A third insulating layer 12 is disposed on the first conductive type epitaxial layer 5 , and a source metal 13 is disposed on the third insulating layer 12 . The source metal 13 penetrates through the third insulating layer 12 and respectively makes ohmic contact with the second conductive type body region 10 and the first conductive type source region 14 .

[0045] The third insulating layer 12 is also provided with a gate metal separated from the source metal 13. The shielding gate polysilicon 7 is in ohmic contact with the source metal 13 through the lead-out end of the cell trench. The gate polysilicon 6 is in ohmic contact with the gate metal through the other lead-out end of the cell trench. The gate metal is not marked in the drawing, which is well known to those skilled in the art and will not be described in detail.

[0046] The waveform portion in Example 1 of the present invention is a triangle, the cell groove includes a strip shape, and the end shape of the cell groove is a rectangle.

[0047] Embodiment 2 provides a shielded gate MOSFET with a left-right structure that improves drain-source leakage.

[0048] Different from the embodiment 1, the cell trench in the embodiment 2 is filled with gate polysilicon 6 and shielding gate polysilicon 7, and the gate polysilicon 6 is located on both sides of the shielding gate polysilicon 7. Figure 6 As shown, except for this, it is the same as Example 1;

[0049] As attached Figure 3 As shown, in Example 2 of the present invention, the waveform portion is a triangle, the cell groove includes a strip shape, and the end shape of the cell groove is a rectangle.

[0050] Embodiment 3 provides a super barrier rectifier (SBR) having a top-bottom structure for improving drain-source leakage.

[0051] As attached Figure 7As shown, the shielded gate MOSFET includes an active area 001, a terminal area 002 surrounding the active area 001, and a gate lead area 003; the active area 001 includes a cell groove, the cell groove includes a first cell groove 1 and a second cell groove 2 arranged parallel to the first cell groove 1, and the length of the first cell groove 1 is greater than the second cell groove 2; the terminal area 002 includes at least one terminal groove 3 surrounding the cell groove, and the terminal groove 3 near the end of the cell groove has a wavy shape on one side and a straight line shape on the other side, and each wavy shape is located between two adjacent cell grooves; the vertex of the wavy shape is located in the middle, and near the corner of the gate lead area 003, the first cell groove 1 adjacent to the second cell groove 2 is provided with at least one wavy shape, and it is located between the end of the second cell groove 2 and the terminal groove 3.

[0052] As attached Figure 8 As shown, the distance between the end angle of the second cell groove 2 and the corner of the terminal groove 3 is a, the distance between the end angle of the second cell groove 2 and the crest of the waveform part is c, the distance between the end of the second cell groove 2 and the trough of the waveform part is b, and a=b=c.

[0053] At the corner of the gate lead area 003, the distance between the end foot of the second-type cell groove 2 and the peak of the waveform part of the first cell groove 1 is d1, the distance between the peak of the waveform part of the first cell groove 1 and the peak of the waveform part is d2, the distance between the first cell groove 1 and the second-type cell groove 2 is e, and d1=d2=e.

[0054] like Fig. 9 As shown, the shielded gate MOSFET is formed on a first conductive type substrate, the first conductive type substrate includes a first conductive type substrate 4 and a first conductive type epitaxial layer 5 located on the first conductive type substrate 4, the cell trench is arranged in the first conductive type epitaxial layer 5, a second conductive type body region 10 is arranged between the cell trenches, and a first conductive type source region 14 is arranged on both sides of the second conductive type body region 10;

[0055] The cell trench is filled with gate polysilicon 6 and shielding gate polysilicon 7. The gate polysilicon 6 is located above the shielding gate polysilicon 7, and the gate polysilicon 6 and the shielding gate polysilicon 7 are isolated by a first insulating layer 8. The shielding gate polysilicon 7 is isolated from the first conductive type epitaxial layer 5 by a second insulating layer 9, and the gate polysilicon 6 is isolated from the second conductive type body region 10 by a gate oxide layer 11.

[0056] A third insulating layer 12 is disposed on the first conductive type epitaxial layer 5 , and a source metal 13 is disposed on the third insulating layer 12 . The source metal 13 penetrates through the third insulating layer 12 and respectively makes ohmic contact with the second conductive type body region 10 and the first conductive type source region 14 .

[0057] The shield gate polysilicon 7 is in ohmic contact with the source metal 13 through the cell trench lead-out end, which is not marked in the figure and is well known to those skilled in the art. The source metal 13 penetrates the third insulating layer 12 and is in ohmic contact with the gate polysilicon 6;

[0058] The waveform part in Example 3 of the present invention is semicircular, the cell groove includes a strip, and the end of the cell groove is in the shape of a semicircular arc, and the semicircular arc at the end of the cell groove corresponds to the semicircular position of the waveform part.

[0059] Embodiment 4 provides a shielded gate SBR with a left-right structure for improving drain-source leakage.

[0060] Different from the third embodiment, the cell trench in the fourth embodiment is filled with gate polysilicon 6 and shielding gate polysilicon 7, and the gate polysilicon 6 is located on both sides of the shielding gate polysilicon 7. Figure 6 As shown, except for this, it is the same as Example 3;

[0061] As attached Figure 7 As shown, the waveform portion of Example 4 of the present invention is semicircular, the cellular groove includes a strip, and the end of the cellular groove is in the shape of a semicircular arc, and the semicircular arc at the end of the cellular groove corresponds to the semicircular position of the waveform portion.

[0062] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a product or system. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the product or system including the elements.

[0063] The above description shows and describes several preferred embodiments of the present invention, but as mentioned above, it should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the invention concept described herein through the above teachings or the technology or knowledge of the relevant field. Changes and variations made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A shielded gate structure for improving drain-source leakage, comprising an active area (001), a terminal area (002) surrounding the active area (001), and a gate lead area (003); characterized in that; The active area (001) comprises a cell groove, wherein the cell groove comprises a first cell groove (1) and a second cell groove (2) arranged parallel to the first cell groove (1). The length of the first cell groove (1) is greater than that of the second cell groove (2); the terminal region (002) comprises at least one terminal groove (3) surrounding the cell groove, the terminal groove (3) close to the end of the cell groove has a wave shape on one side and a straight line shape on the other side, and each wave shape is located between two adjacent cell grooves; the vertex of the wave shape is located in the middle, and near the corner of the gate lead region (003), the first cell groove (1) adjacent to the second cell groove (2) is provided with at least one wave shape, and the wave shape is located between the end of the second cell groove (2) and the terminal groove (3).

2. A shielded gate structure for improving drain-source leakage according to claim 1, characterized in that: A shielding gate structure is formed on a first conductive type substrate, the first conductive type substrate comprising a first conductive type substrate (4) and a first conductive type epitaxial layer (5) located on the first conductive type substrate (4), the unit cell trenches are arranged in the first conductive type epitaxial layer (5), a second conductive type body region (10) is arranged between the unit cell trenches, and a first conductive type source region (14) is arranged on both sides of the second conductive type body region (10); The cell trench is filled with gate polysilicon (6) and shielding gate polysilicon (7); the gate polysilicon (6) and shielding gate polysilicon (7) are isolated by a first insulating layer (8); the shielding gate polysilicon (7) and the first conductive type epitaxial layer (5) are isolated by a second insulating layer (9); the gate polysilicon (6) and the second conductive type body region (10) are isolated by a second insulating layer (9); The two electrodes are isolated by a gate oxide layer (11).

3. A shielded gate structure for improving drain-source leakage according to claim 2, characterized in that: A third insulating layer (12) is provided on the first conductive type epitaxial layer (5), a source metal (13) is provided on the third insulating layer (12), and the source metal (13) penetrates the third insulating layer (12) and is in ohmic contact with the second conductive type body region (10) and the first conductive type source region (14) respectively.

4. The shielded gate structure for improving drain-source leakage according to claim 1, characterized in that: The wave-shaped portion includes a triangle, a rectangle, or a semicircle.

5. The shielded gate structure for improving drain-source leakage according to claim 1, characterized in that: The cell grooves include strip shapes.

6. The shielded gate structure for improving drain-source leakage according to claim 1, characterized in that: The shapes of the end portions of the cell grooves include rectangles and semicircular arcs.

7. The shielded gate structure for improving drain-source leakage according to claim 1, characterized in that: The distance between the end angle of the end of the second cell groove (2) and the corner of the terminal groove (3) is a, the distance between the end angle of the end of the second cell groove (2) and the crest of the waveform part is c, the distance between the end of the second cell groove (2) and the trough of the waveform part is b, and a=b=c.

8. The shielded gate structure for improving drain-source leakage according to claim 1, characterized in that: At the corner of the gate lead area (003), the distance between the end foot of the second cell groove (2) and the peak of the waveform portion of the first cell groove (1) is d1, and the distance between the right end point at the corner of the terminal groove (3) and the waveform portion of the first cell groove (1) is d2. The distance between the peaks of the first and second cellular grooves (1) is d2, the distance between the first cellular groove (1) and the second cellular groove (2) is e, And d1=d2=e.

9. The shielded gate MOSFET with improved drain-source leakage according to claim 3, characterized in that: The third insulating layer (12) is also provided with a gate metal separated from the source metal (13); the shielding gate polysilicon (7) is in ohmic contact with the source metal (13) through a cell trench lead-out end; and the gate polysilicon (6) is in ohmic contact with the gate metal through another lead-out end of the cell trench.

10. The shielded gate structure super barrier rectifier (SBR) with improved drain-source leakage according to claim 3, characterized in that: The shielding gate polysilicon (7) is in ohmic contact with the source metal (13) through a cell trench lead-out end, and the source metal (13) penetrates the third insulating layer (12) and is in ohmic contact with the gate polysilicon (6).

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