Lateral bipolar junction transistor and method of forming the same

Abstract

The application provides a lateral bipolar junction transistor and a forming method thereof. The lateral bipolar junction transistor comprises a substrate, a base region in the substrate, an emitter region in the base region, a collector region in the substrate and connected to one side of the base region, and a pickup region formed in the collector region. A field plate structure is arranged on a part of the surface of the collector region between the base region and the pickup region, and comprises a dielectric layer and a field plate layer which are stacked in sequence. The lateral bipolar junction transistor and the forming method thereof can simultaneously improve the Bvceo value and the beta value of the lateral bipolar junction transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a lateral bipolar junction transistor and a method for forming the same. Background Technology

[0002] Lateral bipolar junction transistors (LBJTs) are power electronic devices that use two anti-polarized PN junctions (NPN or PNP) as their basic structure and achieve their switching effect through base current drive. LBJTs can achieve higher current density at lower bias voltages, exhibit stable high-temperature performance, and do not suffer from the gate oxide stability issues of MOS structures.

[0003] Bvceo and β are two important parameters of LBJTs. Bvceo refers to the collector-emitter reverse breakdown voltage, and β is the current amplification factor, which is the ratio of the collector current to the base current. For LBJTs, the larger the values ​​of Bvceo and β, the better the device performance. However, often increasing the value of Bvceo will decrease the value of β, and vice versa, making it impossible to simultaneously increase the values ​​of Bvceo and β. Summary of the Invention

[0004] The technical problem solved by the present application is to simultaneously improve the Bvceo value and β value of a lateral bipolar transistor.

[0005] To address the aforementioned technical problems, this application provides a lateral bipolar junction transistor, comprising: a substrate; a base region located in the substrate; an emitter region located in the base region; a collector region located in the substrate, situated on one side of the base region and connected to the base region, wherein a pickup region is formed in the collector region; and a field plate structure located on a portion of the surface of the collector region between the base region and the pickup region, comprising a dielectric layer and a field plate layer sequentially stacked.

[0006] In this embodiment of the application, the distance between the field plate structure and the adjacent side of the base region is not greater than one-quarter of the distance between the pickup area and the adjacent side of the base region, and the distance between the field plate structure and the adjacent side of the pickup area is not less than one-quarter of the distance between the pickup area and the adjacent side of the base region.

[0007] In this embodiment of the application, the field plate structure includes a plurality of sub-field plate structures arranged at intervals, and each sub-field plate structure includes a sub-dielectric layer and a sub-field plate layer stacked sequentially.

[0008] In the embodiments of this application, the material of the field plate is metal or polycrystalline silicon.

[0009] In this embodiment, the field plate structure is grounded, floating, or electrically connected to the emission area.

[0010] In the embodiments of this application, the width of the base region is 0.5 micrometers to 10 micrometers.

[0011] In this embodiment, the surface of the base region is coplanar with the top surface of the collector region, and the depth of the base region is the same as the depth of the collector region.

[0012] In this embodiment, the lateral bipolar junction transistor further includes a deep well region located in the substrate below the base region and the collector region.

[0013] This application also provides a method for forming a lateral bipolar junction transistor, comprising: providing a substrate; forming a base region in the substrate; forming a collector region in the substrate, the collector region being located on one side of the base region and connected to the base region; forming an emitter region in the base region; forming a pickup region in the collector region; forming a field plate structure on a portion of the surface of the collector region between the base region and the pickup region, the field plate structure comprising a dielectric layer and a field plate layer stacked sequentially.

[0014] In this embodiment of the application, the distance between the field plate structure and the adjacent side of the base region is not greater than one-quarter of the distance between the pickup area and the adjacent side of the base region, and the distance between the field plate structure and the adjacent side of the pickup area is not less than one-quarter of the distance between the pickup area and the adjacent side of the base region.

[0015] In this embodiment of the application, the field plate structure includes a plurality of sub-field plate structures arranged at intervals, and each sub-field plate structure includes a sub-dielectric layer and a sub-field plate layer stacked sequentially.

[0016] In the embodiments of this application, the material of the field plate is metal or polycrystalline silicon.

[0017] In the embodiments of this application, the width of the base region is 0.5 micrometers to 10 micrometers.

[0018] In this embodiment, the surface of the base region is coplanar with the top surface of the collector region, and the depth of the base region is the same as the depth of the collector region.

[0019] Compared with the prior art, the lateral bipolar junction transistor and its formation method of this application have the following advantages:

[0020] The lateral bipolar junction transistor of this application includes a base region, an emitter region, and a collector region. The emitter region is located in the base region, and the collector region is located on one side of the base region and connected to the base region. A pickup region is formed in the collector region. A field plate structure is formed on a portion of the surface of the collector region between the base region and the pickup region. The field plate structure can significantly improve the electric field distribution and greatly improve the Bvceo and β of the lateral bipolar junction transistor.

[0021] By adjusting the distance between the field plate structure and the base region, and between the field plate structure and the adjacent side of the pickup region, the Bvceo and β of the lateral bipolar junction transistor can be improved, which is simple and effective.

[0022] The width of the base region can be further reduced on the existing basis. On the one hand, this is conducive to the miniaturization of the device, and on the other hand, it ensures that only a small portion of the electrons or holes injected into the base region recombine with the holes or electrons of the base region itself to form the base current, thereby further improving the β value.

[0023] The lateral bipolar junction transistor structure provided by this application can be well integrated with logic devices. It can not only be formed independently, but also serve as a parasitic transistor for CMOS and LDMOS, eliminating unnecessary fabrication processes. Attached Figure Description

[0024] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0025] Figure 1 This is a schematic diagram of the structure of a lateral bipolar junction transistor according to an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of another lateral bipolar junction transistor according to an embodiment of this application;

[0027] Figure 3 The simulation results of TCAD for the embodiments of this application and the prior art lateral bipolar junction transistors are shown in the figure.

[0028] Figure 4 The image shows a test diagram of the Bvceo of a lateral bipolar junction transistor in the embodiments of this application and in the prior art.

[0029] Figure 5 The test diagram shows the β of the lateral bipolar junction transistor in the embodiments of this application and the prior art;

[0030] Figure 6 This is a schematic flowchart illustrating a method for forming a lateral bipolar junction transistor according to an embodiment of this application.

[0031] Figures 7 to 10 This is a schematic diagram of the structure corresponding to each step in the method for forming a lateral bipolar junction transistor according to an embodiment of this application. Detailed Implementation

[0032] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0033] The technical solution of this application will be described in detail below with reference to the embodiments and accompanying drawings.

[0034] refer to Figure 1 This application provides a lateral bipolar junction transistor, including a substrate 100. The substrate 100 can be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator (SiI) or germanium-on-insulator, or it can be a substrate containing other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide. In this embodiment, the substrate 100 is made of silicon.

[0035] A base region 110 is formed in the substrate 100, and the base region 110 is formed by an ion implantation process. The base region 110 is doped with N-type or P-type impurity ions. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions; the P-type impurity ions are one or more of boron ions, indium ions, and gallium ions. The doping concentration of the base region 110 can be controlled at 1 × 10⁻⁶. 16 / cm -3 ~5×10 18 / cm -3 In other embodiments, the specific method can be determined based on the actual situation.

[0036] In this embodiment, the width of the base region 110 can be reduced to half the current base region width of a BJT without affecting device performance. For example, in a 180nm process, the width of the base region 100 can be between 0.5 μm and 10 μm. Reducing the width of the base region 100 is beneficial for device miniaturization, and also ensures that only a small portion of the electrons or holes injected into the base region recombine with the base region's own electrons or holes to form a base current, which helps to improve the β value.

[0037] When the lateral bipolar junction transistor of this application embodiment is integrated with CMOS, the base region 110 can be formed together with the well region; when the lateral bipolar junction transistor is integrated with LDMOS, the base region 110 can be formed together with the body region.

[0038] A current collector region 120 is also formed in the substrate 100. The current collector region 120 is located on one side of the base region 110 and connected to the base region 110. The current collector region 120 is formed by an ion implantation process. The doped ions in the current collector region 120 can be P-type or N-type. The doped ion types of the current collector region 120 and the base region 110 are opposite. When the doped ion type of the base region 110 is N-type, the doped ion type of the current collector region 120 is P-type; when the doped ion type of the base region 110 is P-type, the doped ion type of the current collector region 120 is N-type. The N-type impurity ion is one or more of phosphorus ions, arsenic ions, and antimony ions; the P-type impurity ion is one or more of boron ions, indium ions, and gallium ions.

[0039] The collector region 12 is lightly doped and has a large area, so that the high concentration of electrons in the base region 110 (taking P-type doping as an example) diffuses into the collector region 120 to form a collector current. For example, the doping concentration of the collector region 120 can be 1×10⁻⁶. 17 / cm -3 ~1×10 18 / cm -3 .

[0040] In this embodiment, the top surface of the collector region 120 and the surface of the base region 110 are coplanar, and the depth of the collector region 120 is the same as the depth of the base region 110, which enables better integration with logic devices. The collector region 120 can be formed simultaneously with the well region in CMOS and the drift region in LDMOS.

[0041] An emitter region 130 is formed in the base region 110, and the emitter region 130 can be formed by ion implantation. The emitter region 130 is highly doped, with an ion doping concentration greater than that of the base region 110 and the collector region 120. This ensures that when the emitter junction between the emitter region 130 and the base region 110 is forward biased, electrons injected from the emitter region 130 into the base region 110 (taking a P-type doped base region as an example) will form a considerably high electron concentration gradient in the base region 110. For example, the doping concentration of the emitter region 130 is 1 × 10⁻⁶. 19 / cm -3 ~1×10 21 / cm -3 The doping type of the emitter region 130 is opposite to that of the base region 110. When the doped ion type of the base region 110 is N-type, the doped ion type of the emitter region 130 is P-type; when the doped ion type of the base region 110 is P-type, the doped ion type of the emitter region 130 is N-type. The N-type impurity ion is one or more of phosphorus ions, arsenic ions, and antimony ions; the P-type impurity ion is one or more of boron ions, indium ions, and gallium ions.

[0042] In this embodiment, the emitter region 130 is located on the side of the base region 110 away from the collector region 120, and the depth of the emitter region 130 is less than the depth of the base region 110. The emitter region 130 has the same depth as the source in CMOS and LDMOS, to ensure that the emitter region 130 can be formed simultaneously with the source of CMOS and LDMOS. In other embodiments, the depth of the emitter region 130 can also be determined according to the actual situation.

[0043] A pickup region 140 can also be formed in the collector region 120. The pickup region 140 can be formed by ion implantation. The pickup region 140 has the same doping type as the collector region 120, but the doping concentration is higher than that of the collector region 120. The pickup region 140 is located on the side of the collector region 120 away from the base region 110, and the depth of the pickup region 140 is less than the depth of the collector region 120, but the same as the depth of the emitter region 130, so that the pickup region 140 can be formed simultaneously with the drain of CMOS and LDMOS.

[0044] The base region 110 is also doped with a high concentration of pickup regions. In order to improve the β value, the pickup regions of the base region 110 and the pickup regions 140 of the collector region 120 are not on the same plane, so they are not shown in the figure.

[0045] The lateral bipolar junction transistor of this application embodiment further includes a field plate structure 150, which is located on a portion of the surface of the collector region 120 between the base region 110 and the pickup region 140. The field plate structure 150 includes a dielectric layer 151 and a field plate layer 152 stacked sequentially. The dielectric layer 151 serves as an isolation layer, and the field plate layer 152 can influence the distribution of the electric field, widening the depletion region and improving Bvceo.

[0046] The field plate 152 can be made of polysilicon or metal. When the field plate 152 is made of polysilicon, the field plate structure 150 can be formed simultaneously with the gate structure of CMOS or LDMOS. When the field plate 152 is made of metal, the field plate structure 150 can be formed simultaneously with the metal gate of CMOS or LDMOS, or simultaneously with the metal interconnects of CMOS or LDMOS.

[0047] The field plate structure 150 can be connected to zero potential or a weak potential. For example, the field plate structure 150 can be grounded, floating, or electrically connected to the emitting region 130. When the collector region 120 is connected to a high potential or has a large potential difference with the emitting region 130, the presence of the field plate structure 150 can widen the depletion region on the surface of the collector region 120, thereby optimizing the surface electric field of the collector region 120 and improving Bvceo.

[0048] When the field plate structure 150 is floating, its position is crucial. The field plate structure 150 cannot be too far from the base region 110, especially when it is floating. If the field plate structure 150 is too far from the base region 110 or too close to the pickup area 140 of the collector region 120, it will couple the voltage of the collector region 120, increasing the actual potential of the field plate structure 150 and thus degrading the effect of optimizing the surface electric field. In this embodiment, the distance between the field plate structure 150 and the adjacent side of the base region 110 is no greater than one-quarter of the distance between the pickup area and the adjacent side of the base region, and the distance between the field plate structure 150 and the adjacent side of the pickup area 140 is no less than one-quarter of the distance between the pickup area and the adjacent side of the base region.

[0049] refer to Figure 2 In some embodiments, the field plate structure 150 may include a plurality of spaced sub-field plate structures 150a, each of the sub-field plate structures including a sub-dielectric layer 151a and a sub-field plate layer 152a stacked sequentially. The field plate structure 150 composed of a plurality of sub-field plate structures 150a can achieve the same effect as the whole field plate structure, and can also generate multiple electric field intensity peaks on the surface, thereby further widening the depletion region.

[0050] refer to Figure 1 and Figure 2 In some embodiments, a deep well region 160 is further formed in the substrate 100 below the base region 110 and the collector region 120. The deep well region 160 serves an isolation function to meet the ESD performance requirements of high-voltage devices. The thickness of the deep well region 160 is designed according to the actual situation. In other embodiments, the deep well region 160 may be omitted or may include several layers, depending on the specific needs.

[0051] The deep well region 160 can be formed by ion implantation before the base region 110 and the current collector region 120 are formed. The surface of the deep well region 160 is lightly doped, and its doping concentration increases accordingly with the depth of the deep well region 160. The doping concentration of the deep well region 160 can be achieved using known techniques and is not specifically limited here.

[0052] The deep well region 160 can have the same doping type as the collector region 120. When the doped ions in the base region 110 are P-type, the doped ions in the collector region 120 and the deep well region 160 are N-type; when the doped ions in the base region are N-type, the doped ions in the collector region 120 and the deep well region 160 are P-type. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions; the P-type impurity ions are one or more of boron ions, indium ions, and gallium ions.

[0053] The lateral bipolar junction transistor further includes an interlayer dielectric layer 170, which provides electrical isolation. A metal interconnect layer 180 is formed in the interlayer dielectric layer 170. In some embodiments, the metal interconnect layer 180 is located on a portion of the surfaces of the emitter region 130, the pickup region 140, and the field plate structure 150 to achieve electrical connection between the emitter region 130, the pickup region 140, and the field plate structure 150 and their corresponding metal layers. In this case, the field plate structure 150 is grounded or electrically connected to the emitter region 130. In this embodiment, the metal interconnect layer 180 is located on a portion of the surfaces of the emitter region 130 and the pickup region 140 to achieve electrical connection between the emitter region 130, the pickup region 140, and the metal conductive layer 190. The field plate structure 150 does not have the metal interconnect layer 180 on its surface; therefore, the field plate structure 150 is floating.

[0054] A metal connection layer is also formed on the surface of the pickup area of ​​the base region 110, which connects the pickup area of ​​the base region 110 and the corresponding metal layer. Since the pickup area of ​​the base region 110 and the pickup area 140 of the collector region 120 are not on the same plane, and the metal connection layer of the base region 110 is not on the same plane as the metal connection layer of the emitter region 130 and the metal connection layer of the collector region 120, the specific location of the metal connection layer of the base region 110 is not shown in the figure.

[0055] exist Figure 1 Based on the lateral bipolar junction transistor structure shown, the structure obtained by removing the field plate structure is named BJTa. Figure 1 The lateral bipolar junction transistor structure shown is named BJTb. Both BJTa and BJTb are NPN type. The Bvceo and β values ​​of BJTa and BJTb were measured respectively, and the results are as follows. Figure 3 , Figure 4 and Figure 5 As shown.

[0056] Figure 3 The simulation results are from TCAD, where Figure 3 Figure a in the diagram shows the electric field distribution of BJTa. Figure 3 Figure b in the diagram shows the electric field distribution of BJTb. Figure 3 The area between the dashed lines represents the depletion region. (Compare) Figure 3 As can be seen from the depletion regions in Figures a and b, after adding the field plate structure 150, the depletion region on the surface of the collector region 120 is significantly increased, which means that the higher the voltage that the collector region 120 can withstand, the larger Bvceo is.

[0057] refer to Figure 4 , where is the maximum voltage that the collector regions of BJTa and BJTb can withstand, i.e., the breakdown voltage Bvceo. The Bvceo of BJTa is 20V, while that of BJTb is close to 50V. Therefore, adding a field plate structure can significantly increase Bvceo.

[0058] refer to Figure 5 The curve represents the β values ​​of BJTa and BJTb. (This is from...) Figure 5 It can be seen that the β value of BJTb is much larger than that of BJTa. This is because after adding the field plate structure, the recombination in the collector region of BJTb decreases, resulting in a larger current in the collector region. At the same time, the width of the base region is reduced, which reduces the current in the base region, ultimately leading to a larger β value.

[0059] The lateral bipolar junction transistors of this application embodiment can be well integrated with logic devices. They can not only be formed independently, but also serve as parasitic transistors for CMOS and LDMOS, thus eliminating unnecessary process steps. At the same time, they can also achieve simultaneous improvement of Bvceo and β values.

[0060] refer to Figure 6 This application also provides a method for forming a lateral bipolar junction transistor, comprising:

[0061] Step S1: Provide a substrate;

[0062] Step S2: Form a base region in the substrate;

[0063] Step S3: A current collector region is formed in the substrate, the current collector region being located on one side of the base region and connected to the base region;

[0064] Step S4: A transmit region is formed in the base region, and a pickup region is formed in the collector region;

[0065] Step S5: A field plate structure is formed on a portion of the surface of the collector region between the base region and the pickup region. The field plate structure includes a dielectric layer and a field plate layer stacked sequentially.

[0066] Combination Figure 6 and Figure 7 A substrate 100 is provided. The substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator, or germanium-on-insulator, or it may be a substrate comprising other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide. In this embodiment, the material of the substrate 100 is silicon.

[0067] A deep well region 160 is formed in the substrate 100 using an ion implantation process. The doping type of the deep well region 160 is the same as that of the subsequently formed collector region. A deep well region structure with a low surface doping and a corresponding increase in doping concentration with increasing depth can be formed by a multi-pass ion implantation process.

[0068] Then, a first photoresist layer (not shown) is formed on the surface of the substrate 100, exposing the base region. Using the first photoresist layer as a mask, ion implantation is performed to form the base region 110, after which the first photoresist layer is removed. The doped ions in the base region 110 can be N-type or P-type. When the doped ions in the base region 110 are N-type, a PNP-type BJT is formed; when the doped ions in the base region 110 are P-type, an NPN-type BJT is formed. In this embodiment, the width of the base region 110 is reduced to half the width of the current BJT base region. For example, the width of the base region is 0.5 μm to 10 μm. Reducing the width of the base region 110 is beneficial for device miniaturization and also for improving the β value. When the BJT is integrated with CMOS and / or LDMOS, the base region 110 can be formed simultaneously with the well region of the CMOS and the body region of the LDMOS.

[0069] A collector region 120 is formed on one side of the base region 110, and the collector region 120 is connected to the base region 110. A second photoresist layer (not shown) is formed on the surface of the base region 110. Using the second photoresist layer as a mask, ion implantation is performed into the substrate at the location of the collector region 120. The doping ion types of the collector region 120 and the base region 110 are opposite. In this embodiment, the top surface of the collector region 120 is coplanar with the surface of the base region 110, and the depth of the collector region 120 is the same as the depth of the base region 110.

[0070] refer to Figure 8 An emitter region 130 is formed in the base region 110, and a pickup region 140 is formed in the collector region 120. The emitter region 130 and the pickup region 140 are formed by ion implantation. When the BJT is integrated with a CMOS and / or LDMOS, the emitter region 130 is formed simultaneously with the source of the CMOS and / or LDMOS, and the pickup region 140 is formed simultaneously with the drain of the CMOS and / or LDMOS.

[0071] refer to Figure 9 A field plate structure 150 is formed on a portion of the surface of the collector region 120 between the base region 110 and the pickup region 140. The field plate structure 150 includes a dielectric layer 151 and a field plate layer 152 stacked sequentially. The material of the field plate layer 152 can be polysilicon or metal. When the material of the field plate layer 152 is polysilicon, the field plate structure 150 can be formed simultaneously with the pseudo-gate structure of CMOS or LDMOS. When the material of the field plate layer 152 is metal, the field plate structure 150 can be formed simultaneously with the metal gate or metal interconnect layer of CMOS or LDMOS.

[0072] The following describes the formation process of the field plate structure 150 using polysilicon as an example of the material of the field plate layer 152: a dielectric layer and a polysilicon layer are sequentially deposited on the surfaces of the emitter region 130, the base region 110, the collector region 120, and the pickup region 140 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes; the polysilicon layer and the dielectric layer are etched using a dry etching process to form the field plate layer 152 and the dielectric layer 151.

[0073] In some embodiments, the distance between the field plate layer 152 and the dielectric layer 151 and the adjacent side of the base region 110 shall not exceed one-quarter of the distance between the pickup area and the adjacent side of the base region, and the distance between the field plate layer 152 and the dielectric layer 151 and the adjacent side of the pickup area 140 shall not be less than one-quarter of the distance between the pickup area and the adjacent side of the base region.

[0074] The field plate structure 150 can be a single piece or it can include several spaced sub-field plate structures 150a. Each sub-field plate structure 150a includes a sub-dielectric layer 151a and a sub-field plate layer 152a stacked sequentially. Figure 10 .

[0075] After forming the field plate structure 150, conventional processes may also be included: forming an interlayer dielectric layer and a metal bonding layer.

[0076] Combination Figure 1 and Figure 9 An interlayer dielectric layer 170 is deposited on the surfaces of the emitter region 130, base region 110, collector region 120, and field plate structure 150, with the top surface of the interlayer dielectric layer 170 higher than the surface of the field plate structure 150. The interlayer dielectric layer 170 is etched to expose a portion of the surfaces of the emitter region 130 and the pickup region 140, forming contact holes. Metal material is filled into the contact holes to form a metal connection layer 180, and a metal conductive layer 190 is formed on the surfaces of the metal connection layer 180 and a portion of the interlayer dielectric layer 170.

[0077] It should be noted that a pickup area is also formed in the base region 110, and a metal connection layer is also formed on the surface of the pickup area of ​​the base region 110. A metal conductive layer is also formed on the surface of the metal connection layer. The pickup area, metal connection layer, and metal conductive layer of the base region 110 are located in relation to... Figure 10 On a plane perpendicular to each other, therefore not shown.

[0078] This application provides only one implementation method for forming the BJT structure of this application embodiment. In other embodiments, adjustments can be made according to the fabrication process of the CMOS or LDMOS integrated with the BJT.

[0079] The method for forming a lateral bipolar junction transistor provided in this application is compatible with CMOS and LDMOS fabrication processes, avoiding unnecessary process steps and improving device fabrication efficiency.

[0080] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0081] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0082] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0083] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0084] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A lateral bipolar junction transistor, characterized by, The application relates to a semiconductor device, comprising: a substrate; a base region in the substrate; an emitter region in the base region; a collector region in the substrate, on one side of the base region and connected to the base region, and a pickup region formed in the collector region; a field plate structure on a part of the surface of the collector region between the base region and the pickup region, comprising a dielectric layer and a field plate layer arranged in sequence, the distance between the field plate structure and the adjacent side of the base region being not more than one fourth of the distance between the pickup region and the adjacent side of the base region, and the distance between the field plate structure and the adjacent side of the pickup region being not less than one fourth of the distance between the pickup region and the adjacent side of the base region.

2. The lateral bipolar junction transistor of claim 1, wherein, The field plate structure comprises a plurality of sub-field plate structures arranged at intervals, and each of the sub-field plate structures comprises a sub-dielectric layer and a sub-field plate layer arranged in sequence.

3. The lateral bipolar junction transistor of claim 1, wherein, The material of the field plate is metal or polysilicon.

4. The lateral bipolar junction transistor of claim 1, wherein, The field plate structure is grounded, floating or electrically connected to the emitter region.

5. The lateral bipolar junction transistor of claim 1, wherein, The width of the base region is 0.5-10 microns.

6. The lateral bipolar junction transistor of claim 1, wherein, The surface of the base region is coplanar with the top surface of the collector region, and the depth of the base region is the same as the depth of the collector region.

7. The lateral bipolar junction transistor of claim 1, wherein, A deep well region is further provided, and the deep well region is in the substrate below the base region and the collector region.

8. A method of forming a lateral bipolar junction transistor, characterized by, The application further relates to a manufacturing method of the semiconductor device, comprising: providing a substrate; forming a base region in the substrate; forming a collector region in the substrate, on one side of the base region and connected to the base region; forming an emitter region in the base region and a pickup region in the collector region; forming a field plate structure on a part of the surface of the collector region between the base region and the pickup region, the field plate structure comprising a dielectric layer and a field plate layer arranged in sequence, the distance between the field plate structure and the adjacent side of the base region being not more than one fourth of the distance between the pickup region and the adjacent side of the base region, and the distance between the field plate structure and the adjacent side of the pickup region being not less than one fourth of the distance between the pickup region and the adjacent side of the base region.

9. The method of forming a lateral bipolar junction transistor of claim 8, wherein, The field plate structure comprises a plurality of sub-field plate structures arranged at intervals, and each of the sub-field plate structures comprises a sub-dielectric layer and a sub-field plate layer arranged in sequence.

10. The method of forming a lateral bipolar junction transistor of claim 8, wherein, The material of the field plate is metal or polysilicon.

11. The method of forming a lateral bipolar junction transistor of claim 8, wherein, The width of the base region is 0.5-10 microns.

12. The method of forming a lateral bipolar junction transistor of claim 8, wherein, The surface of the base region is coplanar with the top surface of the collector region, and the depth of the base region is the same as the depth of the collector region.

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