A semiconductor device and a manufacturing method thereof

Abstract

The embodiment of the present application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first electrode layer, a semiconductor layer and a second electrode layer which are sequentially formed on a substrate, and a channel layer which is formed on the side wall of the first electrode layer and the second electrode layer after etching part of the semiconductor layer from the side wall of the semiconductor layer to form an opening, wherein the channel layer comprises a first channel part in the opening and a second channel part except the opening, the first channel part is filled with a pseudo gate layer, part of the pseudo gate layer is etched from the side wall of the pseudo gate layer with the second channel part as a mask, and then the second channel part and the first channel part which is in contact with the upper and lower surfaces of the pseudo gate layer are removed to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the pseudo gate layer, the recess is filled with a dielectric material, and an isolation side wall is formed. The formed isolation side wall can reduce the parasitic capacitance of the semiconductor device and optimize the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the rapid development of semiconductor technology, vertically oriented semiconductor devices have attracted widespread attention. The channel current in vertically oriented semiconductor devices flows perpendicular to the plane of the substrate, offering advantages such as low power consumption and enabling the reduction of device size or the increase of integrated circuit density.

[0003] However, with the rapid development of computer technology and other technologies, the demand for high-performance vertically structured semiconductor devices is increasing. Therefore, high-performance semiconductor devices are now urgently needed. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, thereby improving the performance of a vertically structured semiconductor device.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] This application provides a method for manufacturing a semiconductor device, including:

[0007] A first electrode layer, a semiconductor layer comprising at least germanium, and a second electrode layer are sequentially formed on one side of a substrate; the first electrode layer is either a source layer or a drain layer, and the second electrode layer is either a source layer or a drain layer.

[0008] A portion of the semiconductor layer is etched from the sidewall of the semiconductor layer to form an opening, the opening including an arc shape with the arc-shaped notch facing outward;

[0009] A channel layer is formed on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer, wherein the channel layer includes a first channel portion located within the opening and a second channel portion excluding the opening, and the first channel portion is conformal to the opening;

[0010] A dummy gate layer is filled in the first channel portion, and the sidewalls of the dummy gate layer are flush with the sidewalls of the second channel portion.

[0011] Etch a portion of the dummy gate layer from its sidewall so that the sidewall of the etched dummy gate layer is flush with the sidewall of the first electrode layer.

[0012] Remove the second channel portion and the first channel portion that contacts the upper and lower surfaces of the dummy gate layer to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the dummy gate layer;

[0013] The recess is filled with a medium material to form an isolation sidewall.

[0014] Optionally, the opening includes a first opening and a second opening, the first opening being located outside the second opening, and the channel layer includes a first sub-channel layer and a second sub-channel layer, the first sub-channel layer being located outside the second sub-channel layer.

[0015] The etching of a portion of the semiconductor layer from its sidewalls to form an opening, the opening comprising an arcuate notch facing outwards, includes:

[0016] A portion of the semiconductor layer is etched from the outer sidewall of the semiconductor layer using atomic layer etching to form an arc-shaped first opening, the first opening including an arc-shaped notch facing outward;

[0017] The formation of a channel layer on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer includes:

[0018] A first sub-channel layer is epitaxially grown on the first opening, the outer sidewall of the first electrode layer, and the outer sidewall of the second electrode layer.

[0019] The etching of a portion of the semiconductor layer from its sidewalls to form an opening, the opening comprising an arcuate notch facing outwards, includes:

[0020] The remaining semiconductor layer is etched from the inner sidewall of the semiconductor layer using atomic layer etching to form a second opening including an arc shape, wherein the arc shape of the second opening is conformal to the arc shape of the first opening;

[0021] The formation of a channel layer on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer includes:

[0022] A second sub-channel layer is epitaxially grown on the second opening, the inner sidewall of the first electrode layer, and the inner sidewall of the second electrode layer.

[0023] Optionally, the dummy gate layer includes a first dummy gate layer and a second dummy gate layer, with the first dummy gate layer located outside the second dummy gate layer; the recess includes a first recess and a second recess, with the first recess located outside the second recess.

[0024] The step of filling the first channel portion with a dummy gate layer includes:

[0025] The first dummy gate layer is filled in the first channel portion of the first opening, and the second dummy gate layer is filled in the first channel portion of the second opening;

[0026] The dummy gate layer, etched from the sidewall of the dummy gate layer, includes:

[0027] The first dummy gate layer and the second dummy gate layer are partially etched from the sidewalls of the first dummy gate layer and the sidewalls of the second dummy gate layer using isotropic etching.

[0028] The step of removing the second channel portion and the first channel portion that contacts the upper and lower surfaces of the dummy gate layer to form a recess formed by the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer includes:

[0029] Atomic layer etching is used to remove the second channel portion of the first sub-channel layer and the first channel portion that contacts the upper and lower surfaces of the first dummy gate layer, forming a first recess formed by the first electrode layer or the second electrode layer, the first sub-channel layer and the first dummy gate layer;

[0030] Atomic layer etching is used to remove the second channel portion of the second sub-channel layer and the first channel portion that contacts the upper and lower surfaces of the second dummy gate layer, forming a second recess formed by the first electrode layer or the second electrode layer, the second sub-channel layer and the second dummy gate layer;

[0031] The step of filling the recess with a medium material to form an isolation sidewall includes:

[0032] Medium material is deposited in the first and second recesses to form isolation sidewalls.

[0033] Optionally, before etching the remaining semiconductor layer from the inner sidewall of the semiconductor layer using atomic layer etching, the method further includes:

[0034] A trench is formed that penetrates the first electrode layer, the semiconductor layer, and the second electrode layer, and the trench is surrounded by a wall structure composed of the first electrode layer, the semiconductor layer, and the second electrode layer.

[0035] Optionally, before etching a portion of the semiconductor layer from its sidewalls, the method further includes:

[0036] An etch barrier layer, a silicon layer, and a dielectric layer are sequentially formed on the second electrode layer;

[0037] The crystalline silicon layer and the dielectric layer are processed to form a top-level structure, the top-level structure including a crystalline silicon core region and a dielectric barrier surrounding the crystalline silicon core region, wherein the crystalline silicon core region corresponds to the trench;

[0038] The formation of a trench penetrating the first electrode layer, the semiconductor layer, and the second electrode layer, wherein the trench is surrounded by a wall structure composed of the first electrode layer, the semiconductor layer, and the second electrode layer, includes:

[0039] A trench is formed that penetrates the dielectric barrier, the crystalline silicon core region, the etch barrier layer, the first electrode layer, the semiconductor layer, and the second electrode layer. The trench is surrounded by a wall structure composed of the dielectric barrier, the etch barrier layer, the first electrode layer, the semiconductor layer, and the second electrode layer.

[0040] Optionally, after filling the recess with a medium material to form an isolation sidewall, the method further includes:

[0041] Remove the dummy gate layer and form a gate in the first channel portion.

[0042] Optionally, before the gate is formed in the first channel portion, the method further includes:

[0043] An interface layer and a high-K material layer are sequentially conformally formed in the first channel portion.

[0044] Optionally, the material of the semiconductor layer comprising at least germanium is germanium or silicon-germanium.

[0045] Optionally, the medium material is a low-K material.

[0046] This application provides a semiconductor device, including: a substrate, a first electrode layer, a functional layer, and a second electrode layer stacked sequentially; a trench penetrating the first electrode layer, the functional layer, and the second electrode layer to the substrate, wherein the trench has a surrounding wall structure formed by the first electrode layer, the functional layer, and the second electrode layer;

[0047] The first electrode layer is located on one side of the substrate;

[0048] The functional layer is located on the side of the first electrode layer away from the substrate. The functional layer includes a channel region, a gate region, and an isolation sidewall region. The channel region includes an arc-shaped region with an arc-shaped notch facing outward. The gate regions are located on both sides of the arc-shaped region. The isolation sidewall region is located above and below the gate region.

[0049] The second electrode layer is located on the side of the functional layer away from the substrate, and the first electrode layer is either a source layer or a drain layer, and the second electrode layer is either a source layer or a drain layer.

[0050] This application provides a method for manufacturing a semiconductor device. A first electrode layer, a semiconductor layer comprising at least germanium, and a second electrode layer are sequentially formed on a substrate. The first electrode layer is either a source layer or a drain layer, and the second electrode layer is either a source layer or a drain layer. Then, a portion of the semiconductor layer is etched from its sidewall to form an opening. The opening is arc-shaped, with the arc-shaped notch facing outwards. Subsequently, a channel layer is formed on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer. The channel layer includes a first channel portion located within the opening and a second channel portion excluding the opening. The first channel portion is conformal to the opening. The channel portion also includes an arc shape. A dummy gate layer is filled in the first channel portion including the arc shape. The sidewall of the resulting dummy gate layer is flush with the sidewall of the second channel portion. Then, using the second channel portion as a mask, a portion of the dummy gate layer is etched from the sidewall of the dummy gate layer so that the sidewall of the etched dummy gate layer is flush with the sidewall of the first electrode layer. Then, the second channel portion and the first channel portion that contacts the upper and lower surfaces of the dummy gate layer are removed to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the dummy gate layer. The recess is filled with dielectric material to form an isolation sidewall. The formed isolation sidewall can reduce the parasitic capacitance of the semiconductor device and optimize the performance of the semiconductor device. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown;

[0053] Figures 2-20 A schematic diagram of the structure of a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the embodiments of this application is shown. Detailed Implementation

[0054] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0055] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0056] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0057] Currently, there is an increasing demand for high-performance vertical-structure semiconductor devices. For example, the high parasitic capacitance of current vertical-structure semiconductor devices affects their performance. Therefore, there is an urgent need for high-performance semiconductor devices.

[0058] Based on this, embodiments of this application provide a method for manufacturing a semiconductor device. A first electrode layer, a semiconductor layer comprising at least germanium, and a second electrode layer are sequentially formed on a substrate. The first electrode layer is either a source layer or a drain layer, and the second electrode layer is either a source layer or a drain layer. Then, a portion of the semiconductor layer is etched from its sidewall to form an opening. The opening is arc-shaped, with the arc-shaped notch facing outwards. Subsequently, a channel layer is formed on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer. The channel layer includes a first channel portion located within the opening and a second channel portion excluding the opening. The first channel portion is conformal to the opening. The first channel portion also includes an arc shape. A dummy gate layer is filled in the arc-shaped first channel portion, and the sidewall of the resulting dummy gate layer is flush with the sidewall of the second channel portion. Then, using the second channel portion as a mask, a portion of the dummy gate layer is etched from the sidewall of the dummy gate layer so that the sidewall of the etched dummy gate layer is flush with the sidewall of the first electrode layer. Then, the second channel portion and the first channel portion that contacts the upper and lower surfaces of the dummy gate layer are removed to form a recess formed by the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer. The recess is filled with dielectric material to form an isolation sidewall. The formed isolation sidewall can reduce the parasitic capacitance of the semiconductor device and optimize the performance of the semiconductor device.

[0059] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0060] The semiconductor device provided in this application embodiment can be a memory device or a logic device. The semiconductor device provided in this application embodiment can be a vertical structure transistor device, such as a vertical structure field-effect transistor (FET), specifically a metal-oxide-semiconductor field-effect transistor (MOSFET) or a tunneling field-effect transistor (TFET).

[0061] refer to Figure 1 The diagram shown is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application. The method includes the following steps:

[0062] S101, a first electrode layer 120, a semiconductor layer 130 comprising at least germanium, and a second electrode layer 140 are sequentially formed on one side of the substrate 110, reference. Figure 2 As shown.

[0063] In embodiments of this application, a first electrode layer 120, a semiconductor layer 130 comprising at least germanium, and a second electrode layer 140 may be sequentially formed on one side surface of the substrate 110. Specifically, the first electrode layer 120, the semiconductor layer 130 comprising at least germanium, and the second electrode layer 140 may be formed by epitaxial growth.

[0064] Substrate 110 may be a semiconductor substrate, such as a silicon substrate. Before forming the first electrode layer 120 on one side surface of substrate 110, substrate 110 may be doped to form a well layer, see reference. Figure 2 As shown, the well layer is formed by doping the substrate 110. Compared to the substrate 110, the doped well layer has higher conductivity and can form good electrical contact with the first electrode layer 120. The doping can be N-type doping, with the doping element being As or P, and the doping concentration being 1e17-2e19 / cm³. 3 Doping can also be p-type doping, with the doping element being B or In, and the doping concentration being 1e17-2e19 / cm³. 3 Specifically, a well layer can be formed on a silicon substrate by implanting dopant ions and then performing an annealing process.

[0065] As an example, an N-type field-effect transistor (FET) is implanted with P-type impurities to form a well layer, and a P-type field-effect transistor (FET) is implanted with N-type impurities to form a well layer.

[0066] In the embodiments of this application, after the epitaxial growth of the first electrode layer 120 and the second electrode layer 140, the thickness of the first electrode layer 120 and the second electrode layer 140 is approximately 10-50 nanometers (nm). The first electrode layer 120 and the second electrode layer 140 are doped semiconductor layers, and the doping type of the first electrode layer 120 and the second electrode layer 140 is the same, which can be either N-type doping or P-type doping. Since the first electrode layer 120 is either a source layer or a drain layer, and the second electrode layer 140 is either a source layer or a drain layer, the conductivity of the first electrode layer 120 and the second electrode layer 140 can be improved by doping. Specifically, in-situ doping can be used for doping.

[0067] As an example, for a P-type FET device, the first electrode layer 120 is a P-type doped silicon layer, with the doping element being B or In, and the doping concentration being 1e18-1e21 / cm³. 3 The second electrode layer 120 is a p-type doped silicon layer, with the doping element being B or In, and the doping concentration being 1e18-1e21 / cm³. 3 .

[0068] As another example, for an N-type FET device, the first electrode layer 120 is an N-type doped silicon layer, with the doping element being As or P, and the doping concentration being 1e18-1e21 / cm³. 3 The second electrode layer 120 is an N-type doped silicon layer, with the doping element being As or P, and the doping concentration being 1e18-1e21 / cm³. 3 .

[0069] In embodiments of this application, after the first electrode layer 120 is epitaxially grown, a semiconductor layer 130 comprising at least germanium can be epitaxially grown on the first electrode layer 120. The material of the semiconductor layer 130 comprises at least germanium, for example, germanium or silicon-germanium. The thickness of the semiconductor layer 130 can range from 10 to 100 nanometers.

[0070] As one possible implementation, if the material of semiconductor layer 130 is silicon-germanium (SiGe), the doping ratio of germanium is in the range of 10%-50%. If the doping ratio is too small, the opening of the C-type structure cannot be formed. If the doping ratio is too large, there will be more lattice defects, which may reduce the performance of the memory device.

[0071] As an example, the germanium doping ratio remains constant in the direction perpendicular to the substrate 110.

[0072] As another example, in the direction perpendicular to the substrate 110, the germanium doping ratio first increases and then decreases, meaning the Ge composition in the central region is greater than that in the upper and lower regions. Because the Ge composition is high in the central region and low in the upper and lower regions, the etching rate for the region with high Ge composition is greater than that for the region with low Ge composition, thus making it easier to form arc-shaped openings through subsequent etching.

[0073] In the embodiments of this application, after the semiconductor layer 130 is epitaxially formed, a second electrode layer 140 is formed on the semiconductor layer 130, and then an etch stop layer 101, a silicon layer 102, and a dielectric layer 103 are sequentially formed on the second electrode layer 140. (Refer to...) Figure 3 As shown. Specifically, an etch barrier layer 101, a silicon layer 102, and a dielectric layer 103 can be formed using a deposition process.

[0074] The etch barrier layer 101 covers the second electrode layer 140, protecting the underlying second electrode layer 140 and also serving as an etch barrier to prevent etching damage to the second electrode layer 140 during the formation of the second contact. The etch barrier layer 101 can be made of silicon oxide, specifically high-quality silicon oxide formed using a high-temperature process, to improve the performance of the semiconductor device. The thickness of the etch barrier layer 101 can be 1-10 nanometers.

[0075] A crystalline silicon layer 102 is also covered on the etch barrier layer 101. The material of the crystalline silicon layer 102 can be polycrystalline silicon or amorphous silicon, and the thickness can be 50-150 nanometers.

[0076] A dielectric layer 103 is also deposited on the crystalline silicon layer 102. The dielectric layer 103 serves to isolate other film layers and the second electrode layer 140 during device fabrication. It also isolates the second contact after the formation of the second contact of the second electrode layer 140, ensuring that the second contact only forms an electrical connection with the second electrode layer 140 in the semiconductor device. The material of the dielectric layer 103 can be a nitride, such as silicon nitride, and the thickness of the dielectric layer 103 can be 30-100 nanometers.

[0077] In the embodiments of this application, after the first electrode layer 120, semiconductor layer 130, second electrode layer 140, etch stop layer 101, silicon layer 102, and dielectric layer 103 are sequentially formed on the substrate 110, a patterned photoresist layer 104 may be formed on the dielectric layer 103. The patterned photoresist layer 104 defines the silicon core region 1021 of the semiconductor device. (Refer to...) Figure 4 , Figure 4 This is a top-view structural diagram of a semiconductor device during the manufacturing process.

[0078] Then, the dielectric layer 103 and the silicon layer 102 are etched using a patterned photoresist layer 104, as referenced. Figure 5 As shown. Figure 5 This is a schematic diagram of a semiconductor structure obtained by cross-sectioning along the AA' direction of a semiconductor device. After etching, the photoresist layer 104 is removed, leaving the etched dielectric layer 103 and the silicon core region 1021. Dielectric layer material is then deposited, followed by etching to form a dielectric barrier 105 surrounding the silicon core region 1021. (Refer to...) Figure 6 As shown. That is, by processing the crystalline silicon layer 102 and the dielectric layer 103, a top-level structure including a crystalline silicon core region 1021 and a dielectric barrier 105 surrounding the crystalline silicon core region 1021 is formed.

[0079] When etching to form the medium barrier 105, it is also necessary to select an etchant with a selectivity for the etching barrier layer 101 so as not to damage the etching barrier layer 101 during etching.

[0080] Then, using the dielectric barrier 105 as a mask, the etch stop layer 101, the second electrode layer 140, the semiconductor layer 130, the first electrode layer 120, and a portion of the substrate 110 are etched, as shown in the reference. Figure 7 As shown. After etching, dielectric material is deposited until it covers the entire semiconductor device, and then a shallow trench isolation (STI) layer 106 is formed using chemical mechanical polishing (CMP) and etching processes, as shown in the reference. Figure 8 As shown. The shallow trench isolation (STI) layer 106 is used to isolate the semiconductor device from other semiconductor devices manufactured simultaneously during the unified manufacturing of integrated circuits. The dielectric material can be silicon oxide. The etching process can be wet etching or dry etching.

[0081] S102, etching a portion of the semiconductor layer 130 from its sidewalls to form an opening, referenced. Figure 8 and Figure 13 As shown.

[0082] In the embodiments of this application, after etching the barrier layer 101, the second electrode layer 140, the semiconductor layer 130, the first electrode layer 120 and a portion of the substrate 110 are completed, a portion of the semiconductor layer 130 is etched from the sidewall of the semiconductor layer 130 to form an opening, wherein the opening includes an arc shape and the arc-shaped notch faces outward.

[0083] In embodiments of this application, the opening includes a first opening 1071 and a second opening 1072, with the first opening 1071 located outside the second opening 1072.

[0084] refer to Figure 8 As shown, a portion of the semiconductor layer 130 is etched from its outer sidewall to form an arc-shaped first opening 1071, the arc-shaped notch of which faces outward. The arc-shaped first opening 1071 resembles the letter C. The arc-shaped opening facilitates the subsequent formation of an arc-shaped channel layer within the opening, which has lower leakage current and a longer channel length, thereby improving the performance of the semiconductor device.

[0085] In the direction perpendicular to the substrate 110, the width of the remaining semiconductor layer 130 gradually decreases and then increases, that is, it presents a structure in which the width at the top and bottom is greater than the width in the middle, similar to the letter X.

[0086] When the semiconductor layer 130 is made of silicon or germanium, atomic layer etching is used to etch the semiconductor layer 130 from its sidewalls, etching 10-40 nm to form a C-shaped opening 1071. During the etching process, an etchant with a selectivity ratio to the first electrode layer 120 and the second electrode layer 140 is selected so that the first electrode layer 120 and the second electrode layer 140 are not damaged during the etching process to form the opening 1071.

[0087] In the embodiments of this application, reference is made to Figure 13 As shown, the remaining semiconductor layer 130 is etched from the inner sidewall of the semiconductor layer 130 to form a second arc-shaped opening 1072. The arc shape of the second opening 1072 is conformal to the arc shape of the first opening 1071, meaning the arc-shaped notch of the second opening 1072 also faces outwards, and the arc-shaped second opening 1072 also resembles the letter C. The process for forming the second opening 1072, after filling the channel layer and dummy gate layer in the first opening 1071, will be described in detail later.

[0088] S103, a channel layer is formed on the opening, the sidewall of the first electrode layer 120, and the sidewall of the second electrode layer 140, with reference to... Figure 9 and Figure 14 As shown.

[0089] In embodiments of this application, after etching to form an opening, a channel layer can be formed on the opening, the sidewall of the first electrode layer 120, and the sidewall of the second electrode layer 140. The channel layer includes a first sub-channel layer 1081 and a second sub-channel layer 1082, with the first sub-channel layer 1081 located outside the second sub-channel layer 1082. The channel layer includes a first channel portion located within the opening and a second channel portion excluding the opening, with the first channel portion conforming to the opening.

[0090] refer to Figure 9 As shown, a first sub-channel layer 1081 is epitaxially grown on the outer sidewall of the first opening 1071, the outer sidewall of the first electrode layer 120, and the outer sidewall of the second electrode layer 140. The first sub-channel layer 1081 includes a first channel portion 1081-1 located within the first opening 1071 and a second channel portion 1081-2 excluding the first opening 1071. The first channel portion 1081-1 is conformal to the first opening 1071, that is, the first channel portion 1081-1 also includes an arc shape, and the arc-shaped notch faces outward.

[0091] The thickness of the channel layer can be 3-30nm, and the channel layer material can be silicon or silicon-germanium. When the channel layer material is silicon-germanium, the doping ratio of germanium can range from 10% to 50%.

[0092] refer to Figure 14As shown, a second sub-channel layer 1082 is epitaxially grown on the inner sidewall of the second opening 1072, the inner sidewall of the first electrode layer 120, and the inner sidewall of the second electrode layer 140. The second sub-channel layer 1082 includes a first channel portion 1082-1 ​​located within the second opening 1072 and a second channel portion 1082-2 excluding the second opening 1072. The first channel portion 1082-1 ​​is conformal to the second opening 1072, meaning it also includes an arc shape, with the arc-shaped notch facing outwards.

[0093] S104, fill the first channel portion with a dummy gate layer, reference Figure 10 and Figure 15 As shown.

[0094] In embodiments of this application, after filling the first channel portion of the channel layer within the opening, if the first channel portion does not completely fill the opening, a dummy gate layer can continue to be filled in the first channel portion. The sidewalls of the dummy gate layer are flush with the sidewalls of the second channel portion. The dummy gate layer includes a first dummy gate layer 1091 and a second dummy gate layer 1092, with the first dummy gate layer 1091 located outside the second dummy gate layer 1092.

[0095] refer to Figure 10 As shown, a first dummy gate layer 1091 is filled in the first channel portion 1081-1 of the first opening 1071. (Reference) Figure 15 As shown, the first dummy gate layer 1092 is filled in the first channel portion 1082-1 ​​of the second opening 1072.

[0096] Specifically, when filling the dummy gate layer, the dummy gate layer material can be deposited first, followed by etching to make the sidewalls of the dummy gate layer flush with the sidewalls of the second channel portion. During etching, an etchant with a selectivity for the channel layer should be selected to avoid damaging the channel layer. The dummy gate layer material can be oxide nitride.

[0097] In the embodiments of this application, a first opening 1071 is etched from the outer sidewall of the channel layer. A first sub-channel layer 1081 is epitaxially grown on the first opening 1071, the outer sidewall of the first electrode layer 120, and the outer sidewall of the second electrode layer 140. After filling the first channel portion 1081-1 of the first sub-channel layer 1081 with a first dummy gate layer 1091, the dielectric barrier 105, the silicon core region 1021, the etch barrier layer 101, the first electrode layer 120, the semiconductor layer 130, and the second electrode layer 140 are etched. 40 and a portion of the substrate 110 form a trench 201 that penetrates the dielectric barrier 105, the silicon core region 1021, the etch stop layer 101, the first electrode layer 120, the semiconductor layer 130, and the second electrode layer 140. The silicon core region 1021 corresponds to the trench 201, that is, the silicon core region 1021 defines the position of the trench 201. The trench 201 is surrounded by a wall structure 202 composed of the dielectric barrier 105, the etch stop layer 101, the first electrode layer 120, the semiconductor layer 130, and the second electrode layer 140. (Refer to...) Figure 11 and Figure 12 As shown. Figure 11 This is a top-view structural diagram of a semiconductor device during the manufacturing process. Figure 12 This is a schematic diagram of a semiconductor structure obtained by taking a cross-section along the AA' direction of the semiconductor device.

[0098] In the embodiments of this application, after etching to obtain trench 201 and forming a wall structure 202, trench 201 is the inner side of the wall structure 202, and the wall structure 202 has an outer side. A first opening 1071 has been formed on the outer side of the wall structure 202, and a first sub-channel layer 1081 and a first dummy gate layer 1091 are formed on the outer side of the wall structure 202 and in the first opening 1071.

[0099] refer to Figure 13 As shown, on the inner side of the enclosure structure 202, the remaining semiconductor layer 130 is etched from the inner sidewall of the semiconductor layer 130 to form a second arc-shaped opening 1072. The arc shape of the second opening 1072 is conformal to the arc shape of the first opening 1071, that is, the arc-shaped notch of the second opening 1072 also faces outward, and the arc-shaped second opening 1072 is also similar to the letter C. The process of forming the second opening 1072 is after filling the channel layer and the dummy gate layer in the first opening 1071 and etching to obtain the trench 201.

[0100] refer to Figure 14As shown, similar to the process of epitaxially growing the first sub-channel layer 1081, the second sub-channel layer 1082 is epitaxially grown on the inner side of the enclosure structure 202, on the inner sidewall of the second opening 1072, the inner sidewall of the first electrode layer 120, and the inner sidewall of the second electrode layer 140. The second sub-channel layer 1082 includes a first channel portion 1082-1 ​​located within the second opening 1072 and a second channel portion 1082-2 excluding the second opening 1072. The first channel portion 1082-1 ​​is conformal to the second opening 1072, meaning it also includes an arc shape, and the arc-shaped notch faces outwards.

[0101] The thickness of the first sub-channel layer 1081 and the second sub-channel layer 1082 can be 3-15nm, and the material can be silicon or silicon-germanium. When the material is silicon-germanium, the doping ratio of germanium can be 10%-30%.

[0102] refer to Figure 15 As shown, on the inner side of the enclosure structure 202, the first channel portion 1082-1 ​​of the second opening 1072 is filled with a first dummy gate layer 1092. The material of the dummy gate layer can be oxynitride.

[0103] After forming the first dummy gate layer 1092, dielectric material is deposited until it covers the entire semiconductor device. Then, a shallow trench isolation (STI) layer 106 is formed within the trench 201 using chemical mechanical polishing (CMP) and etching processes. (Refer to...) Figure 16 As shown. The dielectric material can be silicon oxide. The etching process can be wet etching or dry etching.

[0104] S105, etch a portion of the dummy gate layer from the sidewall of the dummy gate layer, referencing... Figure 16 As shown.

[0105] In the embodiments of this application, the second channel portion of the inner and outer channel layers of the enclosure structure 202 is used as a mask to etch a portion of the dummy gate layer from the sidewall of the dummy gate layer so that the sidewall of the etched dummy gate layer is flush with the sidewall of the first electrode layer.

[0106] refer to Figure 16 As shown, the sidewalls of the first dummy gate layer 1091 located outside the enclosure structure 202 and the sidewalls of the second dummy gate layer 1092 located inside the enclosure structure 202 are isotropically etched, such that the sidewall of the first dummy gate layer 1091 after etching is flush with the outer sidewall of the first electrode layer 120, and the sidewall of the second dummy gate layer 1092 after etching is flush with the inner sidewall of the first electrode layer 120.

[0107] S106, remove the second channel portion and the first channel portion that contacts the upper and lower surfaces of the dummy gate layer, refer to Figure 17 As shown.

[0108] In the embodiments of this application, a dummy gate layer is used as a mask to remove the second channel portion of the channel layer and the first channel portion of the channel layer that contacts the upper and lower surfaces of the dummy gate layer, while retaining a portion of the channel layer, forming a recess formed by the first electrode layer 120 or the second electrode layer 140, the remaining portion of the channel layer, and the dummy gate layer.

[0109] The recess includes a first recess 2031 and a second recess 2032. The first recess 2031 is located outside the second recess 2032, that is, the first recess 2031 is located outside the wall structure 202, and the second recess 2032 is located inside the wall structure 202. (Refer to...) Figure 17 As shown.

[0110] Specifically, atomic layer etching can be used to remove the second channel portion 1081-2 of the first sub-channel layer 1081 located outside the wall structure 202 and the first channel portion 1081-1 in contact with the upper and lower surfaces of the first dummy gate layer 1091, forming a first recess 2031 formed by the first electrode layer 120 or the second electrode layer 140, the first sub-channel layer 1081 and the first dummy gate layer 1091. At the same time, atomic layer etching can be used to remove the second channel portion 1082-2 of the second sub-channel layer 1082 located inside the wall structure 202 and the first channel portion 1082-1 ​​in contact with the upper and lower surfaces of the second dummy gate layer 1092, forming a second recess 2032 formed by the first electrode layer 120 or the second electrode layer 140, the second sub-channel layer 1082 and the second dummy gate layer 1091.

[0111] When etching is performed, an etchant with a selectivity ratio for the first electrode layer 120 and the second electrode layer 140 is selected so that the first electrode layer 120 and the second electrode layer 140 are not damaged when etching away part of the channel layer.

[0112] S107, the recess is filled with a medium material to form an isolation sidewall 150, reference. Figure 18 As shown.

[0113] In embodiments of this application, after forming the recesses, dielectric material is filled within the recesses to form isolation sidewalls 150. Specifically, dielectric material can be deposited and etched within the first recess 2031 and the second recess 2032 to form the isolation sidewalls 150. The formed isolation sidewalls 150 can reduce the parasitic capacitance of the semiconductor device and optimize its performance. The dielectric material can be a low-k material.

[0114] When etching is performed, an etchant with a selectivity ratio for the first electrode layer 120, the second electrode layer 140 and other film layers is selected so that the first electrode layer 120, the second electrode layer 140 and other film layers will not be damaged when etching to form the isolation sidewall 150.

[0115] Therefore, the method for forming the isolation sidewall in this application embodiment has a relatively simple process flow, and the formed sidewall structure is controllable, providing a strong foundation for improving the performance of semiconductor devices.

[0116] In embodiments of this application, after forming the isolation sidewall 150, the dummy gate layer is removed, and then an interface layer (not shown) and a high-k material layer 160 are conformally formed sequentially in the first channel portion. The interface layer is used to improve interface quality and further improve the performance of the semiconductor device; the material of the interface layer can be silicon oxide. After forming the high-k material layer 160, the gate 170 is formed in the first channel portion, as shown in the reference. Figure 19 As shown. The material of gate 170 can be a material with good conductivity, such as TiN, TaN, and W.

[0117] In the embodiments of this application, an isolation layer 180 is finally formed. The isolation layer 180 is located on the substrate 110 and surrounds the first electrode layer 120, the channel layer, the gate 170, the second electrode layer 140, the etch stop layer 101, and the dielectric barrier 105, etc., to isolate and protect the device. The material of the isolation layer 180 can be a dielectric material with good insulating properties, such as silicon oxide. Then, a first contact 191, a second contact 192, and a gate contact 193 are formed through the isolation layer 180 using a via process and are electrically connected to the first electrode layer 120, the second electrode layer 140, and the gate 170, respectively. (Refer to...) Figure 20 As shown.

[0118] In summary, the semiconductor device manufacturing method provided in this application involves sequentially forming a first electrode layer, a semiconductor layer comprising at least germanium, and a second electrode layer on a substrate. The first electrode layer is either a source layer or a drain layer, and the second electrode layer is either a source layer or a drain layer. Then, a portion of the semiconductor layer is etched from its sidewall to form an opening. The opening is arc-shaped, with the arc-shaped notch facing outwards. Subsequently, a channel layer is formed on the opening, the sidewalls of the first electrode layer, and the sidewalls of the second electrode layer. The channel layer includes a first channel portion located within the opening and a second channel portion excluding the opening. The first channel portion is conformal to the opening. The first channel portion also includes an arc shape. A dummy gate layer is filled in the arc-shaped first channel portion, and the sidewall of the resulting dummy gate layer is flush with the sidewall of the second channel portion. Then, using the second channel portion as a mask, a portion of the dummy gate layer is etched from the sidewall of the dummy gate layer so that the sidewall of the etched dummy gate layer is flush with the sidewall of the first electrode layer. Then, the second channel portion and the first channel portion that contacts the upper and lower surfaces of the dummy gate layer are removed to form a recess formed by the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer. The recess is filled with dielectric material to form an isolation sidewall. The formed isolation sidewall can reduce the parasitic capacitance of the semiconductor device and optimize the performance of the semiconductor device.

[0119] Based on the semiconductor device manufacturing method provided in the above embodiments, this application also provides a semiconductor device. (See reference...) Figure 20 The diagram shown is a schematic representation of the structure of a semiconductor device provided in an embodiment of this application.

[0120] The semiconductor device provided in this application embodiment includes a substrate 110, a first electrode layer 120, a functional layer, and a second electrode layer 140 stacked sequentially, and a trench penetrating the first electrode layer 120, the functional layer, and the second electrode layer 140 to the substrate 110. The trench has a surrounding wall structure formed by the first electrode layer 120, the functional layer, and the second electrode layer 140.

[0121] The first electrode layer 120 is located on one side of the substrate 110;

[0122] The functional layer is located on the side of the first electrode layer 120 away from the substrate 110. The functional layer includes a channel region 108, a gate region 170 and an isolation sidewall region 150. The channel region 108 includes an arc-shaped region with an arc-shaped notch facing outward. The gate region 170 is located on both sides of the arc-shaped region. The isolation sidewall region 150 is located above and below the gate region 170.

[0123] The second electrode layer 140 is located on the side of the functional layer away from the substrate 110. The first electrode layer 120 is either a source layer or a drain layer, and the second electrode layer 140 is either a source layer or a drain layer.

[0124] In embodiments of this application, the semiconductor device further includes an isolation layer 180, a first contact 191, a second contact 192, and a gate contact 193, as shown in the reference. Figure 20 As shown.

[0125] An isolation layer 180 is located on a substrate 110 and surrounds a first electrode layer 120, a channel layer, a gate layer 170, a second electrode layer 140, an etch barrier layer 101, and a dielectric barrier 105, etc., to isolate and protect the device.

[0126] The first contact 191, the second contact 192, and the gate contact 193 penetrate the isolation layer 180 and are electrically connected to the first electrode layer 120, the second electrode layer 140, and the gate 170, respectively, so as to allow for the electrical outgoing of the first electrode layer 120, the second electrode layer 140, and the gate 170.

[0127] In the embodiments of this application, the second electrode layer 140 is covered with an etching barrier layer 101 and a dielectric barrier 105.

[0128] In embodiments of this application, an interface layer (not shown) and a high-K material layer 160 are further included between the gate region 170 and the channel region 108.

[0129] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so they are described more simply; relevant parts can be referred to the descriptions of the structural embodiments.

[0130] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0131] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

[0132] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming, on one side of a substrate, a first electrode layer, a semiconductor layer comprising at least germanium, and a second electrode layer in sequence; the first electrode layer is one of a source electrode layer or a drain electrode layer, and the second electrode layer is the other of the source electrode layer or the drain electrode layer; etching part of the semiconductor layer from the sidewall of the semiconductor layer to form an opening, the opening comprising an arc shape, and a gap of the arc shape facing outward; forming a channel layer on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer, wherein the channel layer comprises a first channel portion located in the opening and a second channel portion other than the opening, and the first channel portion is conformal to the opening; filling a dummy gate layer in the first channel portion, and a sidewall of the dummy gate layer is flush with a sidewall of the second channel portion; etching part of the dummy gate layer from the sidewall of the dummy gate layer to make the sidewall of the etched dummy gate layer flush with the sidewall of the first electrode layer; removing the second channel portion and the first channel portion in contact with the upper and lower surfaces of the dummy gate layer to form a recess formed by the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer; filling a dielectric material in the recess to form an isolation sidewall; the opening comprises a first opening and a second opening, the first opening is located outward of the second opening, and the channel layer comprises a first sub-channel layer and a second sub-channel layer, the first sub-channel layer is located outward of the second sub-channel layer; the etching part of the semiconductor layer from the sidewall of the semiconductor layer to form an opening, the opening comprising an arc shape, and a gap of the arc shape facing outward comprises: etching part of the semiconductor layer from the outer sidewall of the semiconductor layer by atomic layer etching to form a first opening comprising an arc shape, and a gap of the arc shape of the first opening facing outward; the forming a channel layer on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer comprises: epitaxially growing a first sub-channel layer on the first opening, the outer sidewall of the first electrode layer, and the outer sidewall of the second electrode layer; the etching part of the semiconductor layer from the sidewall of the semiconductor layer to form an opening, the opening comprising an arc shape, and a gap of the arc shape facing outward comprises: etching the remaining semiconductor layer from the inner sidewall of the semiconductor layer by atomic layer etching to form a second opening comprising an arc shape, and the arc shape of the second opening is conformal to the arc shape of the first opening; the forming a channel layer on the opening, the sidewall of the first electrode layer, and the sidewall of the second electrode layer comprises: epitaxially growing a second sub-channel layer on the second opening, the inner sidewall of the first electrode layer, and the inner sidewall of the second electrode layer.

2. The production method according to claim 1, characterized by the dummy gate layer comprises a first dummy gate layer and a second dummy gate layer, the first dummy gate layer is located outward of the second dummy gate layer; and the recess comprises a first recess and a second recess, the first recess is located outward of the second recess; the filling a dummy gate layer in the first channel portion comprises: filling the first pseudo gate layer in the first channel portion of the first opening, and filling the second pseudo gate layer in the first channel portion of the second opening; the etching part of the pseudo gate layer from the sidewall of the pseudo gate layer comprises: etching part of the first pseudo gate layer and the second pseudo gate layer from the sidewall of the first pseudo gate layer and the sidewall of the second pseudo gate layer by isotropic etching; the removing the second channel portion and the first channel portion in contact with the upper and lower surfaces of the pseudo gate layer to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the pseudo gate layer comprises: removing the second channel portion of the first sub-channel layer and the first channel portion in contact with the upper and lower surfaces of the first pseudo gate layer by atomic layer etching to form a first recess formed by the first electrode layer or the second electrode layer, the first sub-channel layer and the first pseudo gate layer; removing the second channel portion of the second sub-channel layer and the first channel portion in contact with the upper and lower surfaces of the second pseudo gate layer by atomic layer etching to form a second recess formed by the first electrode layer or the second electrode layer, the second sub-channel layer and the second pseudo gate layer; the filling the medium material in the recess to form the isolation side wall comprises: depositing the medium material in the first recess and the second recess to form the isolation side wall.

3. The production method according to claim 2, characterized by Before the remaining semiconductor layer is etched from the inner sidewall of the semiconductor layer by atomic layer etching, the method further comprises: forming a trench penetrating through the first electrode layer, the semiconductor layer and the second electrode layer, and the trench has a surrounding wall structure formed by the first electrode layer, the semiconductor layer and the second electrode layer.

4. The production method according to claim 3, characterized by Before etching part of the semiconductor layer from the sidewall of the semiconductor layer, the method further comprises: forming an etching stop layer, a crystalline silicon layer and a medium layer in sequence on the second electrode layer; processing the crystalline silicon layer and the medium layer to form a top layer structure, the top layer structure comprises a crystalline silicon core area and a medium barrier wall surrounding the crystalline silicon core area, wherein the crystalline silicon core area corresponds to the trench; the forming a trench penetrating through the first electrode layer, the semiconductor layer and the second electrode layer, and the trench has a surrounding wall structure formed by the first electrode layer, the semiconductor layer and the second electrode layer comprises: forming a trench penetrating through the medium barrier wall, the crystalline silicon core area, the etching stop layer, the first electrode layer, the semiconductor layer and the second electrode layer, and the trench has a surrounding wall structure formed by the medium barrier wall, the etching stop layer, the first electrode layer, the semiconductor layer and the second electrode layer.

5. The production method according to claim 1, characterized by After filling the medium material in the recess to form the isolation side wall, the method further comprises: removing the pseudo gate layer to form a gate in the first channel portion.

6. The production method according to claim 5, wherein Before forming a gate in the first channel portion, the method further comprises: conformally forming an interface layer and a high-K material layer in sequence in the first channel portion.

7. The production method according to any one of claims 1 to 6, characterized by, The material of the semiconductor layer at least comprising germanium is germanium or silicon germanium.

8. The production method according to any one of claims 1 to 6, characterized by, The medium material is a low-K material.

Images