A semiconductor device and a method of manufacturing the same

Abstract

An embodiment of the present application provides a semiconductor device and a method for manufacturing the same, comprising a substrate, a first electrode layer, a functional layer, and a second electrode layer, wherein the functional layer is located between the first and second electrode layers, the functional layer comprising a first region and a second region with a U-shaped structure surrounding the first region, the U-shaped opening of the second region being oriented parallel to the substrate and away from the first region, i.e., the U-shaped opening is oriented outward, the material of the first region comprises at least germanium, and the second region comprises a U-shaped ferroelectric layer and a U-shaped gate stacked in sequence. In an embodiment of the present application, a ferroelectric layer with a U-shaped structure is used as the storage layer of a memory device. While maintaining a constant gate voltage, the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the storage window of the entire semiconductor device. Furthermore, while maintaining a constant storage window of the entire semiconductor device, the gate voltage can be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the memory device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the rapid development of semiconductor technology, memory devices have attracted widespread attention. For example, non-volatile memory devices and dynamic random access memory (DRAM) devices are among the most popular memory devices.

[0003] However, with the rapid development of computer technology and other technologies, the demand for high-performance memory devices is also increasing. Therefore, high-performance memory devices are urgently needed. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a semiconductor device and a manufacturing method thereof to improve the performance of the memory device.

[0005] To achieve the above objectives, this application has the following technical solutions:

[0006] An embodiment of the present application provides a semiconductor device, including:

[0007] substrate;

[0008] a first electrode layer, located on one side of the substrate;

[0009] a functional layer located on a side of the first electrode layer away from the substrate, the functional layer comprising a first region and a second region with a U-shaped structure surrounding the first region, the U-shaped opening of the second region being oriented parallel to the substrate and away from the first region, the material of the first region comprising at least germanium, and the second region comprising a U-shaped ferroelectric layer and a U-shaped gate layer stacked in sequence;

[0010] The second electrode layer is located on a side of the functional layer away from the substrate. The first electrode layer is a source electrode layer or a drain electrode layer, and the second electrode layer is the other of the source electrode layer and the drain electrode layer.

[0011] Optionally, the second region of the U-shaped structure is arc-shaped, and a radial length of the U-shaped opening gradually increases along a direction parallel to the substrate and away from the first region.

[0012] Optionally, the material of the first region is germanium or silicon germanium.

[0013] Optionally, when the material of the first region is silicon germanium, in a direction perpendicular to the substrate, the doping ratio of the germanium first increases and then decreases.

[0014] Optionally, the doping ratio of germanium is in the range of 10%-70%.

[0015] Optionally, the material of the ferroelectric layer is HfZrO, and the thickness of the ferroelectric layer is in the range of 3-30 nanometers.

[0016] Optionally, the substrate has an isolation layer surrounding the first electrode layer, the functional layer and the second electrode layer, and the first contact, the second contact and the gate contact penetrate the isolation layer and are electrically connected to the first electrode layer, the second electrode layer and the gate respectively.

[0017] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0018] A first electrode layer, a semiconductor layer including at least germanium, and a second electrode layer are sequentially formed on one side of a substrate; the first electrode layer is one of a source electrode layer and a drain electrode layer, and the second electrode layer is the other of the source electrode layer and the drain electrode layer;

[0019] Etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening, with the remaining semiconductor layer serving as the first region, wherein the U-shaped opening is parallel to the substrate and away from the first region;

[0020] A ferroelectric layer and a gate are sequentially formed in the U-shaped opening. The ferroelectric layer and the gate constitute a second region, and the second region surrounds the first region.

[0021] Optionally, the material of the semiconductor layer comprising at least germanium is silicon germanium, and in a direction perpendicular to the substrate, the doping ratio of the germanium first increases and then decreases;

[0022] Etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening includes:

[0023] The semiconductor layer is etched from the sidewall of the semiconductor layer by atomic layer etching to form a U-shaped opening.

[0024] Optionally, the material of the semiconductor layer including at least germanium is germanium;

[0025] Etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening includes:

[0026] The semiconductor layer is etched from the sidewall of the semiconductor layer by using atomic layer etching and an etchant having crystal plane selectivity to the germanium to form a U-shaped opening.

[0027] An embodiment of the present application provides a semiconductor device comprising a substrate, a first electrode layer, a functional layer, and a second electrode layer, wherein the first electrode layer is a source electrode layer or a drain electrode layer, and the second electrode layer is the other source electrode layer or the drain electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and the functional layer comprises a first region and a second region with a U-shaped structure surrounding the first region. The U-shaped opening of the second region is oriented parallel to the substrate and away from the first region, i.e., the U-shaped opening faces outward. The material of the first region comprises at least germanium, and the second region comprises a U-shaped ferroelectric layer and a U-shaped gate stacked in sequence. The embodiment of the present application utilizes a ferroelectric layer with a U-shaped structure as the storage layer of a storage device. While maintaining a constant gate voltage, the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the storage window of the entire semiconductor device. While maintaining a constant storage window of the entire semiconductor device, the gate voltage can also be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application is shown;

[0030] Figure 2 A schematic structural diagram of another semiconductor device provided in an embodiment of the present application is shown;

[0031] Figure 3 for Figure 2 A schematic top view of the semiconductor device shown;

[0032] Figure 4 To follow Figure 3 A schematic structural diagram of a semiconductor device taken along the AA' direction is shown;

[0033] Figure 5 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0034] Figures 6-18 A schematic structural diagram of a semiconductor device manufactured according to a method for manufacturing a semiconductor device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0036] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0037] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0038] Currently, the demand for high-performance memory devices is increasing, and therefore, high-performance memory devices are urgently needed.

[0039] Based on the above technical problems, an embodiment of the present application provides a semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer, wherein the first electrode layer is one of a source layer and a drain layer, and the second electrode layer is the other of the source layer and the drain layer, the functional layer is located between the first electrode layer and the second electrode layer, the functional layer includes a first region and a second region of a U-shaped structure surrounding the first region, the U-shaped opening of the second region is oriented parallel to the substrate and away from the first region, that is, the U-shaped opening faces outward, the material of the first region includes at least germanium, and the second region includes a U-shaped ferroelectric layer and a U-shaped gate stacked in sequence. The embodiment of the present application utilizes a ferroelectric layer of a U-shaped structure as a storage layer of a storage device. While keeping the gate voltage unchanged, the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the storage window of the entire semiconductor device, and while keeping the storage window of the entire semiconductor device unchanged, the gate voltage can also be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the storage device.

[0040] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0041] refer to Figure 1, which is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application. The semiconductor device provided in an embodiment of the present application is a memory device, which may be, for example, a non-volatile memory device and a dynamic random access memory (DRAM) device. The semiconductor device provided in an embodiment of the present application may be a vertical transistor device, such as a vertical field effect transistor (FET).

[0042] The semiconductor device provided in the embodiment of the present application includes a substrate 110, a first electrode layer 120, a functional layer 130 and a second electrode layer 140, Figure 1 shown.

[0043] The substrate 110 may be a semiconductor substrate, such as a silicon substrate. The first electrode layer 120 is located on one side of the substrate 110, the functional layer 130 is located on the side of the first electrode layer 120 away from the substrate 110, and the second electrode layer 140 is located on the side of the functional layer 130 away from the substrate 110. In other words, the first electrode layer 120, the functional layer 130, and the second electrode layer 140 are stacked in sequence, wherein the first electrode layer 110 is either a source layer or a drain layer, and the second electrode layer 140 is the other of the source layer and the drain layer.

[0044] The thickness of the first electrode layer 120 and the second electrode layer 140 is about 10-50 nanometers (nm). The first electrode layer 120 and the second electrode layer 140 are doped semiconductor layers. The first electrode layer 120 and the second electrode layer 140 have the same doping type, which can be N-type doping or P-type doping.

[0045] As an example, the first electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20 / cm 3 The second electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20 / cm 3 .

[0046] As another example, the first electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20 / cm 3 The second electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20 / cm 3 .

[0047] In the embodiment of the present application, the functional layer 130 is located between the first electrode layer 120 and the second electrode layer 140. The functional layer 130 includes a first region 131 and a U-shaped second region 132 surrounding the first region 131. The U-shaped opening of the second region 132 is oriented parallel to the substrate 110 and away from the first region 131, that is, the U-shaped opening of the second region 132 faces outward. The U-shaped opening of the second region 132 includes a U-shaped ferroelectric layer 1321 and a U-shaped gate 1322 stacked in sequence.

[0048] The first region 131 has a width that gradually decreases and then increases in a direction perpendicular to the substrate 110 , that is, it presents a structure in which the widths at the top and bottom are greater than the width at the middle, similar to the letter X structure.

[0049] As one possible implementation, the U-shaped structure of the second region 132 is arc-shaped, with the radial length of the U-shaped opening gradually increasing along a direction parallel to the substrate 110 and away from the first region 131. In other words, the U-shaped opening of the second region 132 has a curvature, and the curvature slowly changes in a direction approaching the first region 131. The curved U-shaped structure enables the subsequent formation of a U-shaped ferroelectric layer 1321 within the U-shaped opening, so that the U-shaped ferroelectric layer 1321 can improve the performance of the memory device.

[0050] The material of the first region 131 includes at least germanium, such as germanium or silicon germanium. A U-shaped opening can be formed using the material including germanium, so as to form a U-shaped ferroelectric layer 1321 in the U-shaped opening.

[0051] Specifically, if the material of the first region 131 is silicon germanium, the germanium doping ratio first increases and then decreases in the direction perpendicular to the substrate 110. That is, in the direction perpendicular to the substrate 110, the germanium doping ratio in the middle region is greater than the germanium doping ratios in the upper and lower regions, thereby forming a U-shaped opening.

[0052] In a direction perpendicular to the substrate 110 , the doping ratio of germanium may vary gradually and slowly, which helps to form a U-shaped opening with a uniform curvature.

[0053] The doping ratio of germanium ranges from 10% to 70%. If the doping ratio is too low, the opening of the U-shaped structure cannot be formed. If the doping ratio is too high, the lattice defects increase, which may reduce the performance of the memory device.

[0054] In an embodiment of the present application, in a direction perpendicular to the substrate 110, the arc shape of the opening of the U-shaped structure finally formed can be controlled by controlling the doping ratio of germanium. The greater the change in the doping ratio of germanium from the middle area to the upper and lower areas, the deeper the depth of the opening of the U-shaped structure formed in the direction parallel to the substrate 110.

[0055] The material of the ferroelectric layer 1321 can be a ferroelectric material, such as HfZrO, that is, Hf x Zr 1-x O2, that is, the memory device of the present application utilizes ferroelectric materials to achieve data storage.

[0056] The thickness of the ferroelectric layer 1321 is in the range of 3-30 nanometers. If the ferroelectric layer 1321 is too thick, the ferroelectric properties will be lost. Therefore, selecting an appropriate thickness range can improve the performance of the memory device.

[0057] The gate 1322 may be made of a material with good conductivity, such as TiN, TaN, and W.

[0058] In the embodiments of the present application, a U-shaped ferroelectric layer is used as the storage layer of the memory device. While maintaining the gate voltage unchanged, the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the memory window of the entire semiconductor device. Furthermore, while maintaining the memory window of the entire semiconductor device unchanged, the gate voltage can be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the memory device. Furthermore, in the present application, the source, functional layer, and drain are stacked sequentially to form a channel structure perpendicular to the substrate surface, forming a vertical memory device that can be applied to 3D integration scenarios, further increasing the integration density and reducing device power consumption.

[0059] In the embodiment of the present application, the semiconductor device further includes an isolation layer 150, a first contact 161, a second contact 162 and a gate contact 163. Figure 2 shown.

[0060] The isolation layer 150 is located on the substrate 110 and surrounds the first electrode layer 120, the functional layer 130, and the second electrode layer 140 to isolate and protect the device. The isolation layer 150 can be made of a dielectric material with good insulation properties, such as silicon oxide.

[0061] The first contact 161 , the second contact 162 and the gate contact 163 penetrate the isolation layer 150 and are electrically connected to the first electrode layer 120 , the second electrode layer 140 and the gate 1322 , respectively, so as to electrically lead out the first electrode layer 120 , the second electrode layer 140 and the gate 1322 .

[0062] In the embodiment of the present application, a well layer 170 is provided between the first electrode layer 120 and the substrate 110. Figure 2 As shown, the well layer 170 is formed by doping a portion of the substrate 110. Compared with the substrate 110, the doped well layer 170 has a higher conductivity and can form a good electrical contact with the first electrode layer 120. The doping can be N-type doping, with the doping element being As or P, and the doping concentration being 1e17-2e19 / cm 3The doping can also be P-type doping, with the doping element being B or In, and the doping concentration being 1e17-2e19 / cm 3 .

[0063] In the embodiment of the present application, the second electrode layer 140 is covered with an etch stop layer 180 and a dielectric layer 190 .

[0064] The etch stop layer 180 covers the second electrode layer 140 to protect the second electrode layer 140 thereunder. It also serves as an etch stop to prevent damage to the second electrode layer 140 during the formation of the second contact 162 on the second electrode layer 140. The etch stop layer 180 may be made of silicon oxide and may have a thickness of 2-5 nanometers.

[0065] A dielectric layer 190 is also provided over the etch stop layer 180. Dielectric layer 190 is used to isolate the hard mask layer from the second electrode layer 140 during device fabrication. It is also used to isolate the second contacts 162 after they are formed on the second electrode layer 140, ensuring that the second contacts 162 are electrically connected only to the second electrode layer 140 in the semiconductor device. Dielectric layer 190 can be made of silicon nitride or a low-K material, and can have a thickness of 10 to 100 nanometers.

[0066] In an embodiment of the present application, the second region 132 also includes an interface layer (not shown in the figure), which is located between the first region 131 and the second region 132. The interface layer is used to improve the interface quality and further improve the performance of the semiconductor device. The material of the interface layer can be silicon oxide.

[0067] In the embodiments of the present application, Figure 1 and Figure 2 The schematic diagram of the semiconductor device structure provided is along the Figure 3 A cross section of the provided semiconductor device is obtained along the BB' direction.

[0068] refer to Figure 4 As shown, along Figure 3 A schematic diagram of a semiconductor structure obtained by taking a cross section of the semiconductor device in the AA' direction is provided. Figure 4 It can be seen that the opening of the U-shaped structure exists on each sidewall of the semiconductor device.

[0069] In summary, the semiconductor device provided by the embodiment of the present application includes a substrate, a first electrode layer, a functional layer, and a second electrode layer, the first electrode layer is one of a source layer or a drain layer, the second electrode layer is the other of the source layer or the drain layer, the functional layer is located between the first electrode layer and the second electrode layer, the functional layer includes a first region and a second region of a U-shaped structure surrounding the first region, the U-shaped opening of the second region is oriented parallel to the substrate and away from the first region, that is, the U-shaped opening faces outward, the material of the first region includes at least germanium, and the second region includes a U-shaped ferroelectric layer and a U-shaped gate stacked in sequence. The embodiment of the present application utilizes a ferroelectric layer of a U-shaped structure as the storage layer of the memory device. While keeping the gate voltage unchanged, the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the storage window of the entire semiconductor device, and while keeping the storage window of the entire semiconductor device unchanged, the gate voltage can also be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the memory device.

[0070] Based on the semiconductor device provided in the above embodiments, the present application also provides a method for manufacturing a semiconductor device. Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application, the method comprising the following steps:

[0071] S101, forming a first electrode layer 120, a semiconductor layer 101 including at least germanium, and a second electrode layer 140 in sequence on one side of a substrate 110, referring to Figure 6 shown.

[0072] In an embodiment of the present application, a first electrode layer 120, a semiconductor layer 101 including at least germanium, and a second electrode layer 140 may be sequentially formed on a side surface of a substrate 110. Specifically, the first electrode layer 120, the semiconductor layer 101 including at least germanium, and the second electrode layer 140 may be formed by epitaxial growth.

[0073] The substrate 110 may be a semiconductor substrate, such as a silicon substrate. Before forming the first electrode layer 120 on one side surface of the substrate 110, a well layer 170 may be formed in the substrate 110. Figure 6 As shown, the well layer 170 is formed by doping a portion of the substrate 110. Compared with the substrate 110, the doped well layer 170 has a higher conductivity and can form a good electrical contact with the first electrode layer 120. The doping can be N-type doping, with the doping element being As or P, and the doping concentration being 1e17-2e19 / cm 3 The doping can also be P-type doping, with the doping element being B or In, and the doping concentration being 1e17-2e19 / cm 3 Specifically, the well layer 170 may be formed on the silicon substrate by implanting dopant ions and performing an annealing process.

[0074] As an example, an N-type field effect transistor (FET) is implanted with P-type impurities to form a well layer 170 , and a P-type field effect transistor (FET) is implanted with N-type impurities to form a well layer 170 .

[0075] In the embodiment of the present application, after the first electrode layer 120 and the second electrode layer 140 are formed by epitaxial growth, the thickness of the first electrode layer 120 and the second electrode layer 140 is approximately 10-50 nanometers. The first electrode layer 120 and the second electrode layer 140 are doped semiconductor layers. The first electrode layer 120 and the second electrode layer 140 have the same doping type, which can be N-type doping or P-type doping. Because the first electrode layer 110 is one of the source layer and the drain layer, and the second electrode layer 140 is the other of the source layer and the drain layer, the conductivity of the first electrode layer 120 and the second electrode layer 140 can be improved by doping, and specifically, the doping can be performed by in-situ doping.

[0076] As an example, for a P-type FET device, the first electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20 / cm 3 The second electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20 / cm 3 .

[0077] As another example, for an N-type FET device, the first electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20 / cm 3 The second electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20 / cm 3 .

[0078] In an embodiment of the present application, after the first electrode layer 120 is formed by epitaxial growth, a semiconductor layer 101 comprising at least germanium may be epitaxially grown on the first electrode layer 120. The material of the semiconductor layer 101 comprises at least germanium, and may be, for example, germanium or silicon germanium. The thickness of the semiconductor layer 101 may range from 5 to 500 nanometers.

[0079] As a possible implementation method, if the material of the semiconductor layer 101 is germanium Ge, then refer to Figure 6 shown.

[0080] As another possible implementation, if the material of semiconductor layer 101 is silicon germanium (SiGe), the germanium doping ratio first increases and then decreases in the direction perpendicular to substrate 110, that is, the Ge component in the central region is greater than the Ge component in the upper and lower regions. Because the Ge component in the central region is high and the Ge component in the upper and lower regions is low, the etching rate of the high Ge component is greater than the etching rate of the low Ge component, thus forming a U-shaped opening through subsequent etching.

[0081] The doping ratio of germanium ranges from 10% to 70%. If the doping ratio is too low, the opening of the U-shaped structure cannot be formed. If the doping ratio is too high, the lattice defects increase, which may reduce the performance of the memory device.

[0082] As an example, see Figure 7 As shown, the doping ratio of germanium increases from 10% in the upper and lower regions to 30% in the middle region, so that the doping ratio of germanium gradually changes in the direction perpendicular to the substrate 110 .

[0083] When forming a semiconductor layer 101 with a varying germanium composition, multiple layers of SiGe can be epitaxially grown, approximately 5-100 layers, with each layer having a thickness of 1-5 nm. In the direction perpendicular to the substrate 110, the arc of the opening of the U-shaped structure formed can be controlled by controlling the doping ratio of germanium. The greater the change in the doping ratio of germanium from the middle region to the upper and lower regions, the deeper the depth of the opening of the U-shaped structure formed in the direction parallel to the substrate 110. The doping ratio of germanium can be gradually and slowly changed, which helps to form a U-shaped opening with a uniform curvature. Therefore, in the actual manufacturing process, the range of change of the germanium composition, the number of layers of epitaxial SiGe, and the trend of change of the Ge composition can be controlled as needed.

[0084] In the embodiment of the present application, after the semiconductor layer 101 is epitaxially formed, the second electrode layer 140 is epitaxially formed on the semiconductor layer 101, and then the etch stop layer 180 and the dielectric layer 190 are sequentially formed on the second electrode layer 140. Specifically, the etch stop layer 180 and the dielectric layer 190 can be formed by a deposition process.

[0085] The etch stop layer 180 covers the second electrode layer 140, protecting the second electrode layer 140 thereunder. It also serves as an etch stop to prevent damage to the second electrode layer 140 during the formation of the second contact 162 thereon. The etch stop layer 180 can be made of silicon oxide, which can be high-quality silicon oxide formed using a high-temperature process to improve the performance of the semiconductor device. The thickness of the etch stop layer 180 can be 2-5 nanometers.

[0086] A dielectric layer 190 is also provided over the etch stop layer 180. Dielectric layer 190 is used to isolate the hard mask layer from the second electrode layer 140 during device fabrication. It is also used to isolate the second contacts 162 after they are formed on the second electrode layer 140, ensuring that the second contacts 162 are electrically connected only to the second electrode layer 140 in the semiconductor device. Dielectric layer 190 can be made of silicon nitride or a low-K material, and can have a thickness of 10 to 100 nanometers.

[0087] In the embodiment of the present application, after the well layer 170, the first electrode layer 120, the semiconductor layer 101, the second electrode layer 140, the etch stop layer 180 and the dielectric layer 190 are sequentially formed, a patterned photoresist layer 102 may be further formed on the dielectric layer 190. The patterned photoresist layer 102 defines the active area of the semiconductor device. The projection of the active area of the semiconductor device on the substrate 110 is within the well layer 170. Figure 8 or Figure 9 As shown, Figure 8 This is a schematic diagram of the top view of the semiconductor device during the manufacturing process. Figure 9 To follow Figure 8 A schematic diagram of a semiconductor structure obtained by taking a cross section of a semiconductor device along the AA' direction is provided.

[0088] Then, the dielectric layer 190, the etching stop layer 180, the second electrode layer 140, the semiconductor layer 101, the first electrode layer 120 and a portion of the well layer 170 are etched using the patterned photoresist layer 102. Figure 10 After etching, the photoresist layer 102 is removed, and the dielectric material is deposited until all semiconductor devices are covered. Then, a chemical mechanical polishing (CMP) process and an etching process are used to form a shallow trench isolation (STI) layer 103. Figure 11 、 Figure 12 and Figure 13 shown. Figure 11 This is a schematic diagram of the 3D structure of a semiconductor device during the manufacturing process. Figure 12 To follow Figure 11 A schematic diagram of a semiconductor structure obtained by taking a cross section of the semiconductor device in the AA' direction is provided. Figure 13 To follow Figure 11 A schematic diagram of a semiconductor structure obtained by taking a cross-section along the BB' direction of a semiconductor device is provided. Shallow trench isolation (STI) layer 103 is used to isolate this semiconductor device from other semiconductor devices fabricated simultaneously during integrated circuit manufacturing. The dielectric material can be silicon oxide. The etching process can be either wet or dry etching.

[0089] S102, etching the semiconductor layer 101 from the sidewall of the semiconductor layer 101 to form a U-shaped opening 104, referring to Figure 14 、 Figure 15 and Figure 16 shown.

[0090] In the embodiment of the present application, after etching the dielectric layer 190, the etch stop layer 180, the second electrode layer 140, the semiconductor layer 101, the first electrode layer 120 and a portion of the well layer 170, the semiconductor layer 101 is etched from the sidewall of the semiconductor layer 101 to form a U-shaped opening 104, and the remaining semiconductor layer 101 is etched into the first region 131. The direction of the U-shaped opening 104 is parallel to the substrate 110 and away from the first region 131, that is, the U-shaped opening 104 faces outward, with reference to FIG. Figure 14 、 Figure 15 and Figure 16 shown. Figure 14 and Figure 15 Schematic diagram of the semiconductor structure obtained by taking a cross section along the AA' direction of the semiconductor device. Figure 16 Schematic diagram of a semiconductor structure obtained by taking a cross section along the BB' direction of the semiconductor device. It can be seen that in the embodiment of the present application, etching is performed on all four sidewalls of the semiconductor device to form a U-shaped opening 104.

[0091] refer to Figure 14 、 Figure 15 and Figure 16 As shown, the width of the first region 131 gradually decreases and then increases in the direction perpendicular to the substrate 110 , that is, the width of the upper and lower parts is greater than the width of the middle part, which is similar to the letter X structure.

[0092] As one possible implementation, the U-shaped opening 104 is arcuate, with the radial length of the U-shaped opening 104 gradually increasing along a direction parallel to the substrate 110 and away from the first region 131. In other words, the U-shaped opening 104 has a curvature, and the curvature slowly changes in a direction approaching the first region 131. The arcuate U-shaped opening 104 enables the subsequent formation of a U-shaped ferroelectric layer 1321 within the U-shaped opening 104, thereby improving the performance of the memory device.

[0093] When etching the semiconductor layer 101 from the sidewall of the semiconductor layer 101 to form the U-shaped opening 104, different etching processes are used for different materials of the semiconductor layer 101:

[0094] When the material of the semiconductor layer 101 is silicon germanium, and the doping ratio of germanium increases first and then decreases in the direction perpendicular to the substrate 110, the semiconductor layer 101 is etched from the sidewall of the semiconductor layer 101 by atomic layer etching. Since the Ge component in the middle area is high and the Ge component in the upper and lower areas is low, the etching rate of the high Ge component is greater than the etching rate of the low Ge component. Therefore, the etching process can be accurately controlled by atomic layer etching to form a U-shaped opening 104. Figure 14 and Figure 16 When etching is performed, an etchant having a selectivity ratio to the first electrode layer 120 and the second electrode layer 140 is selected so that the first electrode layer 120 and the second electrode layer 140 will not be damaged when etching to form the U-shaped opening 104 .

[0095] When the material of the semiconductor layer 101 is germanium, the semiconductor layer 101 is etched from the sidewall of the semiconductor layer 101 by atomic layer etching, and an etchant with crystal plane selectivity to germanium is selected during etching. For example, compared with the (111) crystal plane, the etching rate of the (100) and (110) crystal planes is faster, and the angle difference between the (111) crystal plane and the (110) crystal plane is 54.7 degrees. Therefore, the etching process can be precisely controlled by atomic layer etching to form a U-shaped opening 104, referring to Figure 15 and Figure 16 When etching, it is also necessary to select an etchant that has a selectivity ratio for the first electrode layer 120 and the second electrode layer 140 so that the first electrode layer 120 and the second electrode layer 140 will not be damaged when etching to form the U-shaped opening 104 .

[0096] S103, forming a ferroelectric layer 1321 and a gate 1322 in the U-shaped opening 104 in sequence, Figure 17 and Figure 18 shown.

[0097] In the embodiment of the present application, after etching to obtain the U-shaped opening 104, a ferroelectric layer 1321 and a gate 1322 are sequentially formed in the U-shaped opening 104. Figure 17 and Figure 18 As shown, the ferroelectric layer 1321 and the gate 1322 constitute the second region 132 , which surrounds the first region 131 . The second region 132 has a U-shaped structure. Correspondingly, the ferroelectric layer 1321 and the gate 1322 also have a U-shape. The first region 131 and the second region 132 constitute the functional layer 130 . Figure 17 Schematic diagram of the semiconductor structure obtained by taking a cross section along the AA' direction of the semiconductor device. Figure 18 Schematic diagram of a semiconductor structure obtained by taking a cross section along the BB' direction of the semiconductor device.

[0098] The ferroelectric layer 1321 and the gate 1322 can be formed by deposition and etching. The material of the ferroelectric layer 1321 can be a ferroelectric material, such as HfZrO, that is, Hf x Zr 1-x O2, that is, the memory device of the present application utilizes ferroelectric materials to store data. The thickness of the ferroelectric layer 1321 ranges from 3 to 30 nanometers. If the ferroelectric layer 1321 is too thick, it will lose its ferroelectric properties. Therefore, selecting an appropriate thickness range can improve the performance of the memory device. The gate 1322 can be made of a highly conductive material, such as TiN, TaN, and W.

[0099] In an embodiment of the present application, before forming the ferroelectric layer 1321 and the gate 1322 in the U-shaped opening 104, an interface layer (not shown) may be formed within the U-shaped opening. The interface layer is located between the first region 131 and the second region 132. The interface layer is used to improve the interface quality and further enhance the performance of the semiconductor device. The material of the interface layer may be silicon oxide. The process for forming the interface layer may be to oxidize the remaining first region 131 of the semiconductor layer 101 using ozone.

[0100] In the embodiment of the present application, an isolation layer 150 is finally formed. The isolation layer 150 is located on the substrate 110 and surrounds the first electrode layer 120, the functional layer 130, and the second electrode layer 140 to isolate and protect the device. The material of the isolation layer 150 can be a dielectric material with good insulation properties, such as silicon oxide. Then, a first contact 161, a second contact 162, and a gate contact 163 are formed by a through-hole process to penetrate the isolation layer 150 and electrically connect to the first electrode layer 120, the second electrode layer 140, and the gate 1322, respectively. Figure 2 and Figure 4 shown.

[0101] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the structural embodiments. For relevant parts, refer to the description of the structural embodiments.

[0102] The descriptions of the processes or structures corresponding to the above figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0103] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

[0104] Based on the implementation methods provided in the above aspects, this application can also be further combined to provide more implementation methods.

Claims

1. A semiconductor device, characterized in that: include: substrate; a first electrode layer, located on one side of the substrate; a functional layer located on a side of the first electrode layer away from the substrate, the functional layer comprising a first region and a second region with a U-shaped structure surrounding the first region, the U-shaped opening of the second region being oriented parallel to the substrate and away from the first region, the material of the first region comprising at least germanium, and the second region comprising a U-shaped ferroelectric layer and a U-shaped gate layer stacked in sequence; a second electrode layer, located on a side of the functional layer away from the substrate, the first electrode layer being one of a source electrode layer and a drain electrode layer, and the second electrode layer being the other of the source electrode layer and the drain electrode layer; The material of the first region is silicon germanium; When the material of the first region is silicon germanium, in a direction perpendicular to the substrate, the doping ratio of the germanium first increases and then decreases.

2. The semiconductor device according to claim 1, wherein The second region of the U-shaped structure is arc-shaped, and a radial length of the U-shaped opening gradually increases along a direction parallel to the substrate and away from the first region.

3. The semiconductor device according to claim 2, wherein The doping ratio of germanium is in the range of 10%-70%.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The material of the ferroelectric layer is HfZrO, and the thickness of the ferroelectric layer is in the range of 3-30 nanometers.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The substrate has an isolation layer surrounding the first electrode layer, the functional layer and the second electrode layer. The first contact, the second contact and the gate contact penetrate the isolation layer and are electrically connected to the first electrode layer, the second electrode layer and the gate respectively.

6. A method for manufacturing a semiconductor device, characterized in that: include: A first electrode layer, a semiconductor layer including at least germanium, and a second electrode layer are sequentially formed on one side of a substrate; the first electrode layer is one of a source electrode layer and a drain electrode layer, and the second electrode layer is the other of the source electrode layer and the drain electrode layer; Etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening, with the remaining semiconductor layer serving as the first region, wherein the U-shaped opening is parallel to the substrate and away from the first region; forming a ferroelectric layer and a gate in sequence in the U-shaped opening, wherein the ferroelectric layer and the gate constitute a second region, and the second region surrounds the first region; The material of the semiconductor layer comprising at least germanium is silicon germanium, and in a direction perpendicular to the substrate, the doping ratio of the germanium first increases and then decreases; Etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening includes: The semiconductor layer is etched from the sidewall of the semiconductor layer by atomic layer etching to form a U-shaped opening.

7. The manufacturing method according to claim 6, characterized in that The material of the semiconductor layer including at least germanium is germanium; Etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening includes: The semiconductor layer is etched from the sidewall of the semiconductor layer by using atomic layer etching and an etchant having crystal plane selectivity to the germanium to form a U-shaped opening.

Images