Switching Circuit

Abstract

An embodiment of the present invention relates to a switching circuit comprising a high-frequency switch, a first charge pump circuit, a boost signal generating circuit, and a second charge pump circuit. The high-frequency switch switches between transmission and reception of a high-frequency signal. The first charge pump circuit generates a first voltage and a second voltage to be supplied to the high-frequency switch. The boost signal generating circuit, upon detecting an edge of an input signal, generates a first boost signal for temporarily increasing the driving capability of the first charge pump circuit. The second charge pump circuit, upon receiving the first boost signal, operates to temporarily increase the driving capability of the first charge pump circuit.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-159604 (filing date: September 24, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a switching circuit. Background Art

[0004] High-frequency switches (hereinafter referred to as RF switches) are used in mobile phone base stations and the like to switch on and off (for switching between transmission and reception), adjust impedance, and change frequency bands when transmitting and receiving wireless signals.

[0005] RF switches are used in mobile phone base stations and the like, and are therefore required to have higher withstand voltages and faster switching times. However, achieving both these requirements is difficult. Summary of the Invention

[0006] The embodiment provides a switch circuit capable of achieving higher withstand voltage and faster switching of an RF switch.

[0007] A switching circuit according to an embodiment includes a high-frequency switch, a first charge pump circuit, a boost signal generating circuit, and a second charge pump circuit. The high-frequency switch switches between transmission and reception of the high-frequency signal. The first charge pump circuit generates a first voltage and a second voltage, which are supplied to the high-frequency switch. Upon detecting an edge in an input signal, the boost signal generating circuit generates a first boost signal for temporarily increasing the driving capability of the first charge pump circuit. Upon receiving the first boost signal, the second charge pump circuit operates to temporarily increase the driving capability of the first charge pump circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a configuration diagram showing an example of the configuration of a switching device including a switching circuit according to one embodiment.

[0009] Figure 2 This is a configuration diagram showing an example of the configuration of a switching circuit.

[0010] Figure 3 This is a configuration diagram showing an example of the configuration of a filter circuit and an RF switch in a switch circuit.

[0011] Figure 4 This is a circuit diagram showing an example of the circuit configuration of OSC.

[0012] Figure 5This is a configuration diagram showing an example of the configuration of a charge pump unit.

[0013] Figure 6 : is a circuit diagram showing an example of the circuit configuration of a charge pump circuit.

[0014] Figure 7 This is a circuit diagram showing an example of the circuit configuration of a boost signal generating circuit.

[0015] Figure 8 This is a waveform diagram showing an example of the waveforms of the input and output signals of the boost signal generating circuit.

[0016] Figure 9 2 is a circuit diagram showing an example of the circuit configuration of a level shift circuit.

[0017] Figure 10 3 is a waveform diagram showing simulation results of the output voltage of the charge pump unit, the boost signal, and the output signal of the OSC.

[0018] Figure 11 It is a waveform diagram showing simulation results when no boost signal generating circuit is provided.

[0019] Figure 12 It is a waveform diagram showing simulation results in the case of having a boost signal generating circuit. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments will be described with reference to the drawings.

[0021] Figure 1 This is a configuration diagram showing an example of the configuration of a switching device including a switching circuit according to one embodiment.

[0022] The switch device 1 includes a switch circuit 10, a transceiver circuit 11, and a control circuit 12. Furthermore, the switch device 1 is connected to an antenna ANT. The control circuit 12 is connected to the switch circuit 10 and the transceiver circuit 11. The control circuit 12 controls the switch circuit 10 and the transceiver circuit 11, thereby controlling the transmission and reception of high-frequency signals (hereinafter referred to as RF signals). This enables the switch device 1 to transmit and receive RF signals, among other functions.

[0023] The control circuit 12 outputs a control signal CTRL, which will be described later, to the switch circuit 10 . The switch circuit 10 is switched based on the control signal CTRL from the control circuit 12 .

[0024] Figure 2 This is a configuration diagram showing an example of the configuration of a switching circuit.

[0025] The switching circuit 10 includes a boost signal generating circuit 20, an OR circuit 21, an oscillator (hereinafter referred to as OSC) 22, a charge pump unit 23 having charge pump circuits 24 and 25, a level shift circuit 26, a filter circuit 27, an RF switch 28, and comparators 29 and 30.

[0026] The boost signal generating circuit 20 receives input of the control signal CTRL from the control circuit 12. The control signal CTRL is a signal with an L level of 0 V and an H level of 1.8 V. Upon detecting either a rising edge transitioning from the L level to the H level or a falling edge transitioning from the H level to the L level of the control signal CTRL, the boost signal generating circuit 20 outputs an H-level boost signal (a first boost signal) to the OR circuit 21.

[0027] In addition to the boost signal from the boost signal generating circuit 20, the OR circuit 21 receives an H-level boost signal (second and third boost signals) from the comparators 29 and 30, as will be described later. When any one of the boost signals from the boost signal generating circuit 20 or the comparators 29 and 30 is H-level, the OR circuit 21 outputs the H-level boost signal to the OSC 22, the charge pump circuit 25, and the filter circuit 27.

[0028] The OSC 22 generates a clock signal (pulse signal) CLK at a predetermined frequency. The OSC 22 outputs the generated clock signal CLK at the predetermined frequency to the charge pump circuits 24 and 25. When a boost signal (described later) is input, the OSC 22 generates a clock signal CLK temporarily increased in frequency above the predetermined frequency and outputs it to the charge pump circuits 24 and 25.

[0029] The charge pump circuit 24, which constitutes the first charge pump circuit, receives, for example, a 3V power supply VDD or a 0V ground GND as input. The charge pump circuit 24 steps up or steps down the power supply VDD or the ground GND in response to the clock signal CLK, and outputs +4.3V (a first voltage) or -3V (a second voltage). The +4.3V output is input to the level shift circuit 26 and the comparator 29. The -3V output is input to the level shift circuit 26 and the comparator 30.

[0030] The charge pump circuit 25 constituting the second charge pump circuit operates only when a boost signal is input. In other words, if the drive capability of the charge pump circuit 24 decreases and cannot provide outputs of +4.3V and -3V, the charge pump circuit 25 increases the current supply capability to improve the drive capability.

[0031] The level shift circuit 26 receives a control signal CTRL having an L level of 0 V and an H level of 1.8 V from the control circuit 12. When 1.8 V is input as the control signal CTRL, the level shift circuit 26 shifts the level to +4.3 V and outputs the signal to the filter circuit 27. When 0 V is input as the control signal CTRL, the level shift circuit 26 shifts the level to -3 V and outputs the signal to the filter circuit 27.

[0032] The filter circuit 27 isolates noise and the like from the input signal and outputs it to the RF switch 28. When an H-level boost signal is input, the filter circuit 27 outputs the input signal to the RF switch 28 without isolation, as will be described in detail later.

[0033] The RF switch 28 switches based on the input signal. One end of the RF switch 28 is connected to the antenna ANT, and the other end is connected to the transceiver circuit 11. With this configuration, the switch circuit 10 can output the RF signal received via the antenna ANT to the transceiver circuit 11, or transmit the RF signal input from the transceiver circuit 11 via the antenna ANT.

[0034] The comparator 29 compares the +4.3V output voltage of the charge pump circuit 24 with the reference voltage ref1 , and outputs a boost signal (H-level signal) to the OR circuit 21 when the output voltage is lower than the reference voltage ref1 .

[0035] The comparator 30 compares the −3 V output voltage of the charge pump circuit 24 with the reference voltage ref2 , and outputs a boost signal (H-level signal) to the OR circuit 21 when the output voltage is higher than the reference voltage ref2 .

[0036] The switch circuit 10 can also be formed on SOI (Silicon on Insulator). Forming the switch circuit 10 on SOI allows for a higher withstand voltage. Furthermore, forming the switch circuit 10 on SOI reduces parasitic capacitance compared to high-capacity CMOS, and enables faster RF switching compared to silicon substrates.

[0037] Figure 3 This is a configuration diagram showing an example of the configuration of a filter circuit and an RF switch in a switch circuit.

[0038] The filter circuit 27 is composed of a resistor R for isolation and a switch SW connected in parallel with the resistor R. The resistor R for isolation prevents noise and the like from being input to the RF switch 28 from the filter circuit 27 side.

[0039] The switch SW switches on / off according to the boost signal. When the boost signal at an H level is input, the switch SW turns on and directly inputs the output of the level shift circuit 26 to the RF switch 28.

[0040] That is, when an H-level boost signal is input, the isolation resistor R is temporarily short-circuited. This reduces the RC time constant determined by the product of the resistance value of the filter circuit 27 and the capacitance of the RF switch 28, thereby speeding up the switching time of the RF switch 28.

[0041] The RF switch 28 includes a plurality of transistors Tr1 with their sources and drains connected in series. One end of a withstand voltage resistor R1 is connected to the gate of each transistor Tr1 to prevent leakage of the RF signal toward the filter circuit 27. The other ends of the plurality of resistors R1 are connected to a separating resistor R.

[0042] RF signals are input from or output to the antenna ANT. As described above, one end of the RF switch 28 is connected to the antenna ANT, and the other end is connected to the transceiver circuit 11. When the switch circuit 10 is used for switching during impedance adjustment, an adjustment element such as a capacitor or inductor is connected to the other end of the RF switch 28.

[0043] Figure 4 This is a circuit diagram showing an example of the circuit configuration of OSC.

[0044] The OSC 22 is configured by connecting a plurality of variable delay inverters INV in a ring shape. When a boost signal is input, the OSC 22 is configured to increase the current supplied to each inverter INV via the plurality of transistors Tr2 to increase the frequency of the clock signal CLK.

[0045] The OSC 22 is not limited to a ring oscillator in which a plurality of inverters INV are connected in a ring shape, and may be another type of oscillator as long as it is capable of generating a clock signal CLK of a desired frequency.

[0046] Figure 5 This is a configuration diagram showing an example of the configuration of a charge pump unit. Figure 6 : is a circuit diagram showing an example of the circuit configuration of a charge pump circuit.

[0047] The charge pump circuit 24 steps up or steps down the power supply VDD or ground GND to output +4.3V or -3V. If a single charge pump circuit 24 cannot step up or down the voltage to +4.3V or -3V, the charge pump circuit 24 may be configured by connecting multiple charge pump circuits 24a in series. The charge pump circuit 25 may also be configured by connecting multiple charge pump circuits 25a in series.

[0048] The charge pump circuits 24 and 25 receive the clock signal CLK(+) from the OSC 22 and the inverted clock signal CLK(-) inverted by, for example, an inverter circuit. In the charge pump circuit 25, a switching circuit 25b is provided on the signal lines of the clock signal CLK(+) and the inverted clock signal CLK(-).

[0049] Switching circuit 25b switches so that the clock signal CLK and the inverted clock signal CLK(-) are input to charge pump circuit 25 (or 25a) when a boost signal at an H level is input. Thus, charge pump circuit 25 (or 25a) operates only when a boost signal is input, thereby enhancing the driving capability of charge pump circuit 24.

[0050] like Figure 6 As shown, the charge pump circuit 24 includes p-type transistors Tr3 and Tr4, n-type transistors Tr5 and Tr6, and capacitors C1 and C2. The on / off states of transistors Tr3 to Tr6 are controlled by a clock signal CLK(+) and an inverted clock signal CLK(-), thereby storing charge in capacitors C1 and C2 or discharging charge from capacitors C1 and C2. As a result, the charge pump circuit 24 outputs an output signal that is a step-up or step-down of the input signal.

[0051] The charge pump circuit 25 is configured as follows: Figure 6 The configuration of the charge pump circuit 24 shown in FIG. 2 is the same as that of the charge pump circuit 24. Figure 6 The configuration including p-type transistors Tr3 and Tr4, n-type transistors Tr5 and Tr6, and capacitors C1 and C2 may also be another configuration.

[0052] Figure 7 This is a circuit diagram showing an example of the circuit configuration of a boost signal generating circuit. Figure 8 This is a waveform diagram showing an example of the waveforms of the input and output signals of the boost signal generating circuit.

[0053] like Figure 7 As shown, the boost signal generating circuit 20 includes a delay circuit 31 and an XOR circuit 32 .

[0054] The input signal (control signal CTRL) input to the boost signal generating circuit 20 is input to one terminal of the delay circuit 31 and the XOR circuit 32. The delay circuit 31 delays the input signal by a predetermined time and outputs the signal to the XOR circuit 32. The delayed input signal, delayed by the predetermined time by the delay circuit 31, is input to the other terminal of the XOR circuit 32.

[0055] Thus, the XOR circuit 32 is input Figure 8 The input signal and the delayed input signal are shown. The input signal switches from the low level to the high level at time t1, and switches from the high level to the low level at time t3. In addition, the delayed input signal is delayed by the delay circuit 31, switches from the low level to the high level at time t2, and switches from the high level to the low level at time t4.

[0056] When the input signal levels are different, the XOR circuit 32 outputs an H-level signal. Therefore, the XOR circuit 32 outputs an H-level output signal (boosted signal) to the OR circuit 21 during the period from time t1 to time t2 and the period from time t3 to time t4.

[0057] Thus, the boost signal generating circuit 20 is such that when the control signal CTRL switches from the L level to the H level or from the H level to the L level, it immediately outputs the output signal (boost signal) to the OR circuit 21. In other words, when the rising edge or the falling edge of the control signal CTRL is detected, the boost signal generating circuit 20 immediately outputs the H level output signal (boost signal) to the OR circuit 21. The pulse width of the output signal can be arbitrarily determined according to the time (delay amount) by which the delay circuit 31 delays the input signal. In addition, the configuration of the boost signal generating circuit 20 is not limited to any configuration as long as it can detect the edge of the control signal CTRL. Figure 7 It can also be other compositions.

[0058] Figure 9 : is a circuit diagram showing an example of the circuit configuration of a level shift circuit.

[0059] The level shift circuit 26 includes a plurality of transistors. The control signal CTRL is input to the level shift circuit 26, and the inverted control signal CTRL is input to the inverted input.

[0060] When the control signal CTRL of the H level (1.8V) is inputted to the level shift circuit 26, the p-type transistors Tr7 and Tr8 are turned on, and the output signal whose level is shifted to +4.3V is outputted.

[0061] On the other hand, when the control signal CTRL of the L level (0V) is inputted to the level shift circuit 26, the n-type transistors Tr9 and Tr10 are turned on, and the output signal whose level is shifted to -3V is outputted.

[0062] The configuration of the level shift circuit 26 is not limited to any other configuration as long as it shifts the H-level and L-level control signals CTRL to +4.3V and -3V. Figure 9 It can also be other compositions.

[0063] Figure 10 3 is a waveform diagram showing simulation results of the output voltage of the charge pump unit, the boost signal, and the output signal of the OSC.

[0064] When the control signal CTRL changes from H level to L level (from off to on) or from L level to H level (from on to off), a through current flows in the level shift circuit 26, and the output voltage of the charge pump circuit 24 of the charge pump section 23 decreases.

[0065] When detecting a change in the signal level of the control signal CTRL (a rising or falling edge), the boost signal generating circuit 20 outputs the boost signal to the OR circuit 21 , whereby the boost signal immediately becomes an H level.

[0066] Furthermore, comparators 29 and 30 compare the output voltage of the charge pump unit 23 with reference voltages ref1 and ref2, and when they detect that the output voltage of the charge pump unit 23 has decreased (or increased), they output a boost signal to the OR circuit 21. Consequently, the boost signal becomes H level even immediately after the signal level of the control signal CTRL changes.

[0067] The boost signal is input to the OSC 22 and the charge pump circuit 25 of the charge pump unit 23. The input of the boost signal to the OSC 22 increases the frequency of the output signal (clock signal CLK) of the OSC 22, thereby increasing the output voltage of the charge pump unit 23. Furthermore, the input of the boost signal to the charge pump circuit 25 activates the charge pump circuit 25, thereby increasing the output voltage of the charge pump unit 23.

[0068] Furthermore, the boost signal is input to both the OSC 22 and the charge pump unit 23. However, the boost signal may be input to either the OSC 22 or the charge pump unit 23. Even with the configuration where the boost signal is input to either the OSC 22 or the charge pump unit 23, the output voltage of the charge pump unit 23 can be increased.

[0069] When the boost signal generating circuit 20 detects a rising or falling edge of the control signal CTRL, it outputs a boost signal to the OR circuit 21. This in turn inputs the boost signal from the OR circuit 21 to the OSC 22 and the charge pump unit 23. This improves the driving capability of the charge pump unit 23, which generates the gate voltage of the RF switch 28, and speeds up the switching time of the RF switch 28.

[0070] Here, use Figure 11 as well as Figure 12 Simulation results will be described for a case where the switching circuit 10 does not include the boost signal generating circuit 20 and a case where the switching circuit 10 includes the boost signal generating circuit 20 .

[0071] Figure 11 It is a waveform diagram showing simulation results when no boost signal generating circuit is provided. Figure 12 This is a waveform diagram of a simulation result in the case of having a boost signal generating circuit.

[0072] If the switching circuit 10 does not include the boost signal generating circuit 20, the boost signal is input from the comparator 29 or 30 after the output voltage of the charge pump circuit 24 decreases (or increases). Therefore, if the switching circuit 10 does not include the boost signal generating circuit 20, the boost signal is generated T1 (nsec) after the signal level of the control signal CTRL is switched.

[0073] In contrast, when the switching circuit 10 includes the boost signal generating circuit 20, the boost signal is immediately generated upon detecting an edge in the control signal CTRL. Therefore, when the switching circuit 10 includes the boost signal generating circuit 20, the boost signal is generated T2 (nsec) after the signal level of the control signal CTRL is switched.

[0074] Furthermore, assuming that the gate voltage at which switch switching is completed is -V1 (V), if the switch circuit 10 does not include the boost signal generating circuit 20, switch switching is completed at T3 (usec). In contrast, if the switch circuit 10 includes the boost signal generating circuit 20, switch switching is completed at T4 (usec).

[0075] When the switch circuit 10 includes the boost signal generating circuit 20 , the switching time of the switch becomes faster by a predetermined time compared to the case where the switch circuit 10 does not include the boost signal generating circuit 20 , and the RF switch 28 can be switched at high speed.

[0076] Conventionally, RF switches are used in mobile phone base stations and other applications, requiring both high withstand voltage and faster switching times. While higher withstand voltage can be achieved by connecting RF switches in series, switching time is determined by the RC time constant, which is the product of the filter circuit's resistance and the RF switch's capacitance. Therefore, achieving faster switching times has its limits.

[0077] Conventionally, to achieve faster switching speeds, a boost signal is output to the charge pump circuit to increase or decrease the output voltage of the charge pump circuit, which determines the gate voltage of the RF switch, when a decrease or increase in the output voltage of the charge pump circuit is detected. The charge pump circuit then performs a voltage boost operation based on the boost signal, temporarily increasing its current supply capacity, thereby achieving faster switching speeds.

[0078] However, since the boost signal is output after a decrease or increase in the output voltage of the charge pump circuit is detected, time is required until the detection, and the switching speed of the RF switch cannot be increased.

[0079] In contrast, the switch circuit 10 of this embodiment is configured to include a boost signal generating circuit 20 that detects the edge of the control signal CTLR. Upon detecting the edge of the control signal CTLR, the boost signal is immediately output to the OSC 22 and the charge pump circuit 25. This improves the current supply capability of the charge pump circuits 24 and 25, thereby accelerating the switching speed of the RF switch 28.

[0080] Therefore, according to the switch circuit 10 of the present embodiment, it is possible to achieve a higher withstand voltage and higher switching speed for the RF switch 28 .

[0081] Furthermore, in this embodiment, a switch SW is provided in parallel with the isolation resistor R of the filter circuit 27 to temporarily short-circuit the isolation resistor R when a boost signal is input. This reduces the RC time constant determined by the product of the resistance value of the filter circuit 27 and the capacitance of the RF switch 28, thereby accelerating the switching time of the RF switch 28.

[0082] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are encompassed by the invention set forth in the claims and their equivalents.

Claims

1. A switching circuit comprising: High-frequency switch, which switches the transmission and reception of high-frequency signals; a first charge pump circuit generating a first voltage and a second voltage to be supplied to the high-frequency switch; The second charge pump circuit operates only when the first boost signal is input; a level shift circuit that shifts the level of the control signal output from the control circuit to the first voltage or the second voltage, and outputs the level of the control signal to the high-frequency switch via the filter circuit; a boost signal generating circuit, which, upon detecting an edge of the control signal, generates the first boost signal for temporarily increasing the current supply capacity of the first charge pump circuit and the second charge pump circuit combined; a first comparator, configured to compare the first voltage with a first reference voltage and generate a second boost signal when the first voltage is lower than the first reference voltage; a second comparator that compares the second voltage with a second reference voltage and generates a third boost signal when the second voltage is higher than the second reference voltage; and The OR circuit calculates a logical OR of the first boost signal, the second boost signal, and the third boost signal.

2. The switching circuit according to claim 1, wherein: have: a resistor for separating noise from a signal input to the high-frequency switch; and The switch is connected in parallel with the resistor and temporarily short-circuits the resistor according to the first boost signal.

3. The switching circuit according to claim 1, wherein: The boost signal generating circuit has the following features: a delay circuit for delaying the control signal for a predetermined time; and The XOR circuit calculates a logical XOR between the control signal and the delayed control signal after being delayed by the delay circuit.

4. The switching circuit according to claim 1, wherein: have: The oscillator generates a clock signal of a predetermined frequency, and when the first boosted signal is inputted, generates a clock signal of a frequency higher than the predetermined frequency.

5. The switching circuit according to claim 1, wherein: The switching circuit is formed on SOI (Silicon on Insulator).

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