A control method for a high-precision two-phase three-order ring oscillator circuit

Abstract

The application provides a control method of a two-phase three-order ring oscillator circuit, which comprises the following steps: a two-phase three-order ring oscillator circuit generates a square wave signal, wherein the square wave signal is determined by two voltages corresponding to first and second nodes on a gain stage circuit; and a clock signal CLK is obtained after the square wave signal is shaped, which is beneficial to generate a clock signal with higher precision, smaller temperature variation and higher frequency, and each gain stage adopts a differential structure input to provide good common mode rejection.

Description

Technical Field

[0001] This application relates to the field of oscillator circuit technology, and in particular to a two-phase third-order ring oscillator circuit, control method, chip and electronic device. Background Technology

[0002] Oscillator circuits are commonly used in analog integrated circuits to provide a stable clock signal for the system. In the field of fast charging technology, fast charging chips can also use oscillator circuits to provide clock signals. Existing clock generation circuits often use relaxation oscillator structures or ring oscillator structures cascaded with inverters.

[0003] However, existing technologies generally suffer from drawbacks such as low clock signal accuracy, low frequency, large temperature variations, and susceptibility to noise interference, which affect the performance of fast charging chips. Summary of the Invention

[0004] The main objective of this application is to provide a two-phase third-order ring oscillator circuit that eliminates common-mode noise interference by introducing a differential input structure and can generate a high-frequency clock signal for use in charging chips.

[0005] Another objective of this application is to provide a control method for a two-phase third-order ring oscillator circuit of a charging chip that eliminates common-mode noise interference by introducing a differential input structure and can generate a high-frequency clock signal.

[0006] Firstly, to achieve the aforementioned main objective, this application provides a two-phase third-order ring oscillator circuit, comprising: a ring oscillator auxiliary circuit and a ring oscillator circuit; wherein,

[0007] The ring oscillator auxiliary circuit is used to provide the ring oscillator circuit with a reference voltage signal Vreg and an initial state signal PD before the ring oscillator circuit starts.

[0008] The ring oscillator circuit includes: a first-stage gain stage circuit, a second-stage gain stage circuit, and a third-stage gain stage circuit, a voltage comparator, and an inverter; the first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit are interconnected; one end of the voltage comparator is connected to the third-stage gain stage circuit, and the other end of the voltage comparator is connected to the inverter.

[0009] The first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit constitute a differential input structure to reduce the influence of common-mode noise;

[0010] The voltage comparator P1 is used to compare the two voltages corresponding to the first node A and the second node B on the third-stage gain stage circuit to obtain a square wave signal.

[0011] The inverter L1 is used to shape the square wave signal to obtain the clock signal CLK.

[0012] Optionally, the first gain stage circuit includes: a first current source I1, a first field-effect transistor M1, a second field-effect transistor M2, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2; the first field-effect transistor M1 and the second field-effect transistor M2 are connected as a differential input pair, with the tail current source provided by the first current source I1; the first resistor R1 and the first capacitor C1 are connected as a passive load; and the second resistor R2 and the second capacitor C2 are connected as a passive load.

[0013] The second-stage gain stage circuit includes a second current source I2, a third field-effect transistor M3, a fourth field-effect transistor M4, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4; the third field-effect transistor M3 and the fourth field-effect transistor M4 are connected as a differential input pair, with the tail current source provided by the second current source I2; the third resistor R3 and the third capacitor C3 are connected as a passive load; and the fourth resistor R4 and the fourth capacitor C4 are connected as a passive load.

[0014] The third-stage gain stage circuit includes a third current source I3, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5, and a sixth resistor R6. The fifth field-effect transistor M5 and the sixth field-effect transistor M6 are connected as a differential input pair, with the tail current source provided by the third current source I3. The fifth resistor R5 and the fifth capacitor C5 are connected as a passive load, and the sixth resistor R6 and the sixth capacitor C6 are connected as a passive load.

[0015] Optionally, the transfer functions of the first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit are respectively expressed as:

[0016] H(s1)=H(s2)=H(s3)=-A0 / (1+s / ω0)

[0017] The loop gain of the ring oscillator circuit is:

[0018] H(s)=-A0 3 / (1+s / ω0) 3

[0019] Where s1 represents the first-stage gain stage circuit, s2 represents the second-stage gain stage circuit, s3 represents the third-stage gain stage circuit, A0 is the low-frequency gain, s is the complex frequency, and ω0 is the bandwidth.

[0020] Optionally, the range of the reference voltage signal Vreg is:

[0021] Vreg≥V P，min +V THN +{I1 / [μ n ·C OX (W / L) 1，2 ]} 1 / 2 +I1·R 1，2 / 2

[0022] Where, μ n For the electron mobility of each field-effect transistor, C OX The capacitance of the gate oxide layer per unit area (W / L) 1，2 R is the aspect ratio of the first field-effect transistor M1 or the second field-effect transistor M2. 1，2 I1 is the resistance value of the first resistor or the resistance value of the second resistor, and V is the current value of the first current source. THN V is the threshold voltage of the N-type field-effect transistor. P，min This is the minimum voltage required across the first current source;

[0023] After the ring oscillator circuit is started, oscillation signals with a 180° phase difference are generated at the first node A and the second node B. The output voltage ranges corresponding to the first node A and the second node B are as follows:

[0024] Vreg-(4 / 5)·I3·R 5，6 ≤V A，B ≤Vreg-(1 / 5)·I3·R 5，6

[0025] Among them, V A，B I3 is the output voltage corresponding to the first node A and the second node B, I3 is the current value of the third current source, and R... 5，6 This refers to the resistance value of the fifth resistor or the resistance value of the sixth resistor.

[0026] Optionally, the ring oscillator auxiliary circuit includes a linear regulator, the linear regulator comprising:

[0027] The seventeenth field-effect transistor M17, the twelfth field-effect transistor M12, the thirteenth field-effect transistor M13, the fourteenth field-effect transistor M14, the fifteenth field-effect transistor M15, the sixteenth field-effect transistor M16, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the seventh capacitor C7, and the fourth current source I4.

[0028] The gate of the seventeenth field-effect transistor M17 is connected to the gate of the twelfth field-effect transistor M12. The source of the seventeenth field-effect transistor M17 is connected to the power supply VDD. The drain of the twelfth field-effect transistor M12 is connected to the fourth current source I4 through the third node C. The gate of the thirteenth field-effect transistor M13 is connected to the first signal EN. The drain of the thirteenth field-effect transistor M13 is connected to the gate of the fourteenth field-effect transistor M14. The drain of the thirteenth field-effect transistor M13 is also connected to the fourth current source I4 and the twelfth field-effect transistor M12 through the third node C. The drain of the fourteenth field-effect transistor M14, the second terminal of the seventh resistor R7, and the first terminal of the eighth resistor R8 are connected and output parameters. The voltage signal Vreg is sent to the ring oscillator circuit; the first end of the seventh capacitor C7 is connected to the fourth current source I4 through the third node C, and the first end of the seventh capacitor C7 is also connected to the drain of the twelfth field-effect transistor M12; the first end of the seventh resistor R7 is connected to the second end of the seventh capacitor C7, the second end of the ninth resistor R9 is connected to the first end of the tenth resistor R10, the gate of the fifteenth field-effect transistor M15, and the gate of the sixteenth field-effect transistor M16, the second end of the tenth resistor R10 is grounded, the drain of the fifteenth field-effect transistor M15 is connected to the drain of the seventeenth field-effect transistor M17, and the source and drain of the sixteenth field-effect transistor M16 are grounded.

[0029] Optionally, the seventeenth field-effect transistor M17 and the twelfth field-effect transistor M12 are current source loads, and the width-to-length ratio of the seventeenth field-effect transistor M17 is the same as that of the twelfth field-effect transistor M12.

[0030] The thirteenth field-effect transistor M13 is a linear regulator switch; the fourteenth field-effect transistor M14 is a linear regulator power transistor; and the fifteenth field-effect transistor M15 is a feedback signal input transistor.

[0031] The sixteenth field-effect transistor M16 is a Zener MOS capacitor; the fourth current source I4 is a PTAT current source.

[0032] The seventh capacitor C7 and the seventh resistor R7 form a Miller compensation network; the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 form a linear regulator feedback network.

[0033] Optionally, the seventeenth field-effect transistor M17, the twelfth field-effect transistor M12, the fifteenth field-effect transistor M15, and the fourth current source I4 constitute a pseudo-differential input operational amplifier; the seventh resistor R7, the ninth resistor R9, and the tenth resistor R10 form a resistive feedback network; the reference voltage signal Vreg is:

[0034] Vreg={[2·I4 / (μ n ·C OX (W / L) 15 )] 1 / 2 +V THN}·(R8+R9+R10) / R10

[0035] Where, μ n For the electron mobility of each field-effect transistor, C OX The capacitance of the gate oxide layer per unit area (W / L) 15 V is the aspect ratio of the fifteenth field-effect transistor M15. THN I0 is the threshold voltage of the N-type field-effect transistor, and I4 is the current value of the fourth current source.

[0036] As temperature increases, the threshold voltage of the N-type field-effect transistor decreases. The fourth current source I4 uses a temperature-proportional-to-absolute-temperature (PTAT) current to reduce the threshold voltage V. THN Voltage compensation is performed to reduce the temperature-dependent deviation of the reference voltage signal Vreg;

[0037] When the voltage difference V between the gate and source of the fifteenth field-effect transistor M15 GS15 <V THN When the linear regulator fails to function properly, the reference voltage signal Vreg is:

[0038] Vreg = VDD - V DSAT14

[0039] Where VDD is the power supply voltage, V DSAT14 This is the overdrive voltage of the fourteenth field-effect transistor M14.

[0040] Optionally, the ring oscillator auxiliary circuit further includes: a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, and a fifth current source I5; the source of the seventh field-effect transistor M7, the source of the eighth field-effect transistor M8, and the source of the ninth field-effect transistor M9 are connected to the power supply VDD; the gate of the seventh field-effect transistor M7 is connected in series with the gate of the eighth field-effect transistor M8 and then connected to the fifth current source I5. The drain of transistor M7 is connected to the fifth current source I5. The drain of the eighth field-effect transistor M8 is connected to the fifth node E. The drain of the tenth field-effect transistor M10 is connected to the fifth node E. The gate of the tenth field-effect transistor M10 is connected to the fourth node D. The gate of the ninth field-effect transistor M9 is connected to the first signal EN. The drain of the ninth field-effect transistor M9 is connected to the gate of the eleventh field-effect transistor M11. The drain of the eleventh field-effect transistor M11 outputs the initial state signal PD to the ring oscillator circuit.

[0041] Optionally, the seventh field-effect transistor M7 and the eighth field-effect transistor M8 are current mirror structures, and the width-to-length ratio of the seventh field-effect transistor M7 is the same as that of the eighth field-effect transistor M8.

[0042] The ninth field-effect transistor M9 is an auxiliary circuit switch, which ensures that the output initial state signal PD is low when the first signal EN is low.

[0043] The fifth current source I5 is a PTAT current source;

[0044] The tenth field-effect transistor M10 and the eleventh field-effect transistor M11 are used to determine the reference voltage signal Vreg. During the establishment of the reference voltage signal Vreg, the voltage at the fourth node D rises with the reference voltage signal Vreg, the tenth field-effect transistor M10 turns on and the voltage at the fifth node E decreases, and the eleventh field-effect transistor M11 turns off, so that the initial state signal PD output by the ring oscillator auxiliary circuit does not affect the ring oscillator circuit.

[0045] Secondly, to achieve the aforementioned objective, this application provides a control method for a two-phase third-order ring oscillator circuit. The two-phase third-order ring oscillator circuit employs the aforementioned two-phase third-order ring oscillator circuit, which includes: a ring oscillator auxiliary circuit and a ring oscillator circuit; the ring oscillator circuit includes: a first-stage gain stage circuit, a second-stage gain stage circuit, and a third-stage gain stage circuit, a voltage comparator, and an inverter; the first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit are interconnected; one end of the voltage comparator is connected to the third-stage gain stage circuit, and the other end of the voltage comparator is connected to the inverter; the method includes:

[0046] The ring oscillator auxiliary circuit provides the ring oscillator circuit with a reference voltage signal Vreg and an initial state signal PD before the ring oscillator circuit starts.

[0047] The first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit constitute a differential input structure to reduce the influence of common-mode noise; the voltage comparator compares the two voltages corresponding to the first node A and the second node B on the third-stage gain stage circuit to obtain a square wave signal; the inverter shapes the square wave signal to obtain the clock signal CLK.

[0048] Thirdly, this application provides a chip comprising a two-phase third-order ring oscillator circuit as described in the first aspect.

[0049] Fourthly, this application provides an electronic device comprising a two-phase third-order ring oscillator circuit as described in the first aspect. The method includes the following steps: a ring oscillator auxiliary circuit provides a reference voltage and an initial circuit state before the ring oscillator starts. The ring oscillator circuit consists of three gain stage circuits, each with differential input to eliminate common-mode noise interference. The generated oscillation signal is compared by a voltage comparator and then shaped by an inverter before being output, thus obtaining a low-temperature drift, high-precision clock signal CLK.

[0050] Therefore, the two-phase third-order ring oscillator circuit proposed in this application includes: a ring oscillator auxiliary circuit and a ring oscillator circuit; the ring oscillator auxiliary circuit provides a reference voltage signal Vreg and an initial state signal PD before the ring oscillator circuit starts; the ring oscillator circuit includes: a first-stage gain stage circuit, a second-stage gain stage circuit, and a third-stage gain stage circuit, a voltage comparator, and an inverter; the first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit are interconnected, and the voltage comparator... One end of the voltage comparator is connected to the third-stage gain stage circuit, and the other end of the voltage comparator is connected to the inverter. The first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit form a differential input structure to reduce the influence of common-mode noise. The voltage comparator compares the two voltages corresponding to the first and second nodes on the third-stage gain stage circuit to obtain a square wave signal. The inverter is used to shape the square wave signal to obtain the clock signal CLK, thereby generating a clock signal with high precision, low temperature variation, and high frequency. The differential input structure of each gain stage can provide good common-mode rejection. Attached Figure Description

[0051] Figure 1 This is a circuit diagram of a ring oscillator circuit in an embodiment of a two-phase third-order ring oscillator circuit according to this application.

[0052] Figure 2 This is a circuit diagram of the auxiliary circuit of the ring oscillator in an embodiment of a two-phase third-order ring oscillator circuit according to this application.

[0053] The present application will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0054] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0055] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects have an "or" relationship.

[0056] In this application's embodiments, "multiple" refers to two or more. The use of terms like "first," "second," etc., in this application's embodiments is merely illustrative and for distinguishing the described objects; it has no order and does not indicate a specific limitation on the number of devices in this application's embodiments, nor does it constitute any limitation on the embodiments of this application. The term "connection" in this application's embodiments refers to various connection methods, such as direct or indirect connections, to achieve communication between devices; this application's embodiments do not impose any limitations on this.

[0057] An embodiment of a two-phase third-order ring oscillator circuit:

[0058] See Figures 1-2 This application discloses a two-phase third-order ring oscillator circuit, comprising a ring oscillator auxiliary circuit and a ring oscillator circuit; wherein, Figure 1 A circuit schematic diagram of a ring oscillator circuit provided in an embodiment of this application. Figure 2 A circuit schematic diagram of a ring oscillator auxiliary circuit provided in this application embodiment, wherein,

[0059] The ring oscillator auxiliary circuit is used to provide the ring oscillator circuit with a reference voltage signal Vreg and an initial state signal PD before the ring oscillator circuit starts.

[0060] The ring oscillator circuit includes: a first-stage gain stage circuit 10, a second-stage gain stage circuit 20, and a third-stage gain stage circuit 30, a voltage comparator P1, and an inverter L1; the first-stage gain stage circuit 10 and the second-stage gain stage circuit 20 are interconnected with the third-stage gain stage circuit 30, one end of the voltage comparator P1 is connected to the third-stage gain stage circuit, and the other end of the voltage comparator P1 is connected to the inverter L1;

[0061] The first-stage gain stage circuit 10, the second-stage gain stage circuit 20, and the third-stage gain stage circuit 30 constitute a differential input structure to reduce the influence of common-mode noise.

[0062] The voltage comparator P1 is used to compare the two voltages corresponding to the first node A and the second node B on the third-stage gain stage circuit 30 to obtain a square wave signal.

[0063] The inverter L1 is used to shape the square wave signal to obtain the clock signal CLK.

[0064] Among them, voltage comparator P1 is a high-speed comparator.

[0065] In specific implementation, the ring oscillator circuit includes three gain stage circuits, a voltage comparator P1, and an inverter L1. The first-stage gain stage circuit 10, the second-stage gain stage circuit 20, and the third-stage gain stage circuit 30 form a differential input structure. The voltage comparator P1 compares the voltages at the first node A and the second node B on the third-stage gain stage circuit 30 to obtain a square wave signal. The inverter L1 shapes the square wave signal to obtain the clock signal CLK. In this way, by introducing a differential input structure to eliminate common-mode noise interference, a high-precision clock signal with low temperature variation and a high frequency can be obtained. The differential input structure of each gain stage can provide good common-mode rejection.

[0066] Optionally, the first gain stage circuit 10 includes: a first current source I1, a first field-effect transistor M1, a second field-effect transistor M2, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2; the first field-effect transistor M1 and the second field-effect transistor M2 are connected as a differential input pair, with the tail current source provided by the first current source I1; the first resistor R1 and the first capacitor C1 are connected as a passive load; and the second resistor R2 and the second capacitor C2 are connected as a passive load.

[0067] The second-stage gain stage circuit 20 includes a second current source I2, a third field-effect transistor M3, a fourth field-effect transistor M4, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4; the third field-effect transistor M3 and the fourth field-effect transistor M4 are connected as a differential input pair, with the tail current source provided by the second current source I2; the third resistor R3 and the third capacitor C3 are connected as a passive load; and the fourth resistor R4 and the fourth capacitor C4 are connected as a passive load.

[0068] The third-stage gain stage circuit 30 includes a third current source I3, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5, and a sixth resistor R6. The fifth field-effect transistor M5 and the sixth field-effect transistor M6 are connected as a differential input pair, with the tail current source provided by the third current source I3. The fifth resistor R5 and the fifth capacitor C5 are connected as a passive load, and the sixth resistor R6 and the sixth capacitor C6 are connected as a passive load.

[0069] Among them, the width-to-length ratio (W / L)1 of the first field-effect transistor M1 is the same as the width-to-length ratio (W / L)2 of the second field-effect transistor M2. The first resistor R1 and the first capacitor C1 form an RC network, and the second resistor R2 and the second capacitor C2 form an RC network.

[0070] Among them, the width-to-length ratio (W / L)3 of the third field-effect transistor M3 is the same as that of the fourth field-effect transistor M4 (W / L)4. The third resistor R3 and the third capacitor C3 form an RC network, and the fourth resistor R4 and the fourth capacitor C4 form an RC network.

[0071] Among them, the width-to-length ratio (W / L) 5 of the fifth field-effect transistor M5 is the same as that of the sixth field-effect transistor M6 (W / L) 6. The fifth resistor R5 and the fifth capacitor C5 form an RC network, and the sixth resistor R6 and the sixth capacitor C6 form an RC network.

[0072] Optionally, the transfer functions of the first gain stage circuit 10, the second gain stage circuit 20, and the third gain stage circuit 30 are respectively expressed as:

[0073] H(s1)=H(s2)=H(s3)=-A0 / (1+s / ω0) (1)

[0074] The loop gain of the ring oscillator circuit is:

[0075] H(s)=-A0 3 / (1+s / ω0) 3 (2)

[0076] Where A0 is the low-frequency gain, s is the complex frequency, and ω0 is the bandwidth.

[0077] Optionally, the range of the reference voltage signal Vreg is:

[0078] Vreg≥V P，min +V THN +{I1 / [μ n ·C OX (W / L) 1，2 ]} 1 / 2 +I1·R 1，2 / twenty three)

[0079] Where, μ n For the electron mobility of each field-effect transistor, C OX The capacitance of the gate oxide layer per unit area (W / L) 1，2 R is the aspect ratio of the first field-effect transistor M1 or the second field-effect transistor M2. 1，2 For the first resistor R1 or the second resistor R2, V THN V is the threshold voltage of the N-type field-effect transistor. P，min This is the minimum voltage required across the first current source I1;

[0080] After the ring oscillator circuit is started, oscillation signals with a 180° phase difference are generated at the first node A and the second node B. The output voltage ranges corresponding to the first node A and the second node B are as follows:

[0081] Vreg-(4 / 5)·I3·R 5，6 ≤V A，B ≤Vreg-(1 / 5)·I3·R 5，6 (4)

[0082] Among them, V A，B R represents the output voltage corresponding to the first node A and the second node B. 5，6 It is the fifth or sixth resistor.

[0083] In practice Figure 1 The ring oscillator circuit shown has three gain stages. Each gain stage uses differential input and has the same structure. The transfer function of each stage is as follows:

[0084] H(s1)=H(s2)=H(s3)=-A0 / (1+s / ω0) (1)

[0085] Where A0 is the low-frequency gain, s is the complex frequency, and ω0 is the bandwidth, for example, a 3dB bandwidth;

[0086] The loop gain of the ring oscillator circuit is shown below:

[0087] H(s)=-A0 3 / (1+s / ω0) 3 (2)

[0088] Therefore, since the three poles of the ring oscillator circuit are at the same frequency, according to the Barkhausen criterion, oscillation can only occur when the frequency-dependent phase shift is equal to 180° and the loop gain is greater than or equal to 1. The relationship between the oscillation frequency and the frequency at the poles is as follows:

[0089] arctan(ω osc / ω0)=60° (5)

[0090] Where, ω osc ω is the oscillation angular frequency, and ω0 is the pole angular frequency.

[0091] Therefore, the oscillation frequency and the minimum gain of each gain stage are as follows:

[0092] f osc =3 1 / 2 ·[1 / (2·π·R·C)] (6)

[0093] Among them, f oscR is the oscillation frequency, R is the resistance value in the RC network, and C is the capacitance in the RC network.

[0094] A0≥[1+(ω osc / ω0) 2 ] 1 / 2 =2 (7)

[0095] In the first gain stage, the gate voltages of the first field-effect transistor M1 and the second field-effect transistor M2 are V, respectively. A V B ,but:

[0096] (1 / 2)·μ n ·C OX (W / L) 1，2 ·(V A -V P -V THN ) 2 +(1 / 2)·μ n ·C OX (W / L) 1，2 ·(V B -V P -V THN ) 2 =I1 (8)

[0097] Where, μ n C represents the electron mobility of the field-effect transistor. OX V is the gate oxide capacitance per unit area. P For the voltage corresponding to the sixth node P, simplifying equation (8) yields:

[0098] V P =(1 / 2)·{V A +V B -2V THN ±[-(V A -V B ) 2 +4I1 / (μ n C OX (W / L) 1，2 )] 1 / 2} (9)

[0099] Since the voltages at points A and B change differentially, they can be expressed by the following formula:

[0100] V A =V CM +ΔV (10)

[0101] V B =V CM -ΔV (11)

[0102] V CM＝ Vreg-(1 / 2)·I1·R 1，2 (12)

[0103] Among them, V CM ΔV is the common-mode voltage, and ΔV is the differential-mode voltage.

[0104] Substituting equations (10), (11), and (12) into equation (9), we get:

[0105] V P =V CM -V THN ±(1 / 2)·{-(2ΔV) 2 +4I1 / [μ n ·C OX (W / L) 1，2 ]} 1 / 2 (13)

[0106] According to Equation 15, the minimum voltage of the sixth node P can be obtained, and thus the voltage range of Vreg can be determined:

[0107] Vreg≥V P，min +V THN +{I1 / [μ n ·C OX (W / L) 1，2 ]} 1 / 2 +I1·R 1，2 / twenty three)

[0108] In the above formula, V P，min This represents the minimum voltage required across the first current source I1.

[0109] In this two-phase third-order ring oscillator circuit, the single-phase loop consists of three single-pole common-source amplifiers. The gain-bandwidth product of the single-pole system is as follows:

[0110] GBW = A0·f d (14)

[0111] Where GBW is the gain-bandwidth product, f d The frequency of the dominant pole.

[0112] As temperature rises, the threshold voltage of the input pair transistors decreases. The use of PTAT current in the tail current source can reduce the deviation of the transconductance of the input pair transistors caused by temperature changes, that is, reduce the error caused by the overall loop bandwidth changing with temperature. Ensuring the bandwidth stability of the signal processing loop helps to stabilize the frequency of the oscillation signal and generate an oscillation signal that changes less with temperature.

[0113] After the ring oscillator circuit starts, oscillation signals with a 180° phase difference will be generated at points A and B. Due to the RC network at the load, the output voltage at each stage will increase or decrease exponentially. Based on the RC network time constant and oscillation frequency, the output voltage ranges at points A and B are as follows:

[0114] Vreg-(4 / 5)·I3·R 5，6 ≤V A，B ≤Vreg-(1 / 5)·I3·R 5，6 (4)

[0115] The oscillation signals with a 180° phase difference between the first node A and the second node B are compared by a high-speed comparator, and after being shaped by an inverter, the output is a low-temperature drift, high-precision CLK signal.

[0116] See Figure 2 In this embodiment of the application, the ring oscillator auxiliary circuit includes a linear regulator, and the linear regulator includes:

[0117] The seventeenth field-effect transistor M17, the twelfth field-effect transistor M12, the thirteenth field-effect transistor M13, the fourteenth field-effect transistor M14, the fifteenth field-effect transistor M15, the sixteenth field-effect transistor M16, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the seventh capacitor C7, and the fourth current source I4.

[0118] The gate of the seventeenth field-effect transistor M17 is connected to the gate of the twelfth field-effect transistor M12. The source of the seventeenth field-effect transistor M17 is connected to the power supply VDD. The drain of the twelfth field-effect transistor M12 is connected to the fourth current source I4 through the third node C. The gate of the thirteenth field-effect transistor M13 is connected to the first signal EN. The drain of the thirteenth field-effect transistor M13 is connected to the gate of the fourteenth field-effect transistor M14. The drain of the thirteenth field-effect transistor M13 is also connected to the fourth current source I4 and the twelfth field-effect transistor M12 through the third node C. The drain of the fourteenth field-effect transistor M14, the second terminal of the seventh resistor R7, and the first terminal of the eighth resistor R8 are connected and output parameters. The voltage signal Vreg is sent to the ring oscillator circuit; the first end of the seventh capacitor C7 is connected to the fourth current source I4 through the third node C, and the first end of the seventh capacitor C7 is also connected to the drain of the twelfth field-effect transistor M12; the first end of the seventh resistor R7 is connected to the second end of the seventh capacitor C7, the second end of the ninth resistor R9 is connected to the first end of the tenth resistor R10, the gate of the fifteenth field-effect transistor M15, and the gate of the sixteenth field-effect transistor M16, the second end of the tenth resistor R10 is grounded, the drain of the fifteenth field-effect transistor M15 is connected to the drain of the seventeenth field-effect transistor M17, and the source and drain of the sixteenth field-effect transistor M16 are grounded.

[0119] Optionally, the seventeenth field-effect transistor M17 and the twelfth field-effect transistor M12 are current source loads, and the width-to-length ratio of the seventeenth field-effect transistor M17 is the same as that of the twelfth field-effect transistor M12.

[0120] The thirteenth field-effect transistor M13 is a linear regulator switch; the fourteenth field-effect transistor M14 is a linear regulator power transistor; and the fifteenth field-effect transistor M15 is a feedback signal input transistor.

[0121] The sixteenth field-effect transistor M16 is a Zener MOS capacitor; the fourth current source I4 is a PTAT current source.

[0122] The seventh capacitor C7 and the seventh resistor R7 form a Miller compensation network; the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 form a linear regulator feedback network.

[0123] The seventh capacitor C7 and the seventh resistor R7 form a Miller compensation network to ensure loop stability.

[0124] Optionally, the seventeenth field-effect transistor M17, the twelfth field-effect transistor M12, the fifteenth field-effect transistor M15, and the fourth current source I4 constitute a pseudo-differential input operational amplifier; the seventh resistor R7, the ninth resistor R9, and the tenth resistor R10 form a resistive feedback network; the reference voltage signal Vreg is:

[0125] Vreg={[2 I4 / (μ n ·C OX (W / L) 15 )] 1 / 2 +V THN}·(R8+R9+R10) / R10 (15)

[0126] Where, μ n C represents the electron mobility of the field-effect transistor. OX The capacitance of the gate oxide layer per unit area (W / L) 15 V is the aspect ratio of the fifteenth field-effect transistor M15. THN This is the threshold voltage of the N-type field-effect transistor.

[0127] As temperature increases, the threshold voltage of the N-type field-effect transistor decreases. The fourth current source I4 uses PTAT current to control the threshold voltage V. THN Voltage compensation is performed to reduce the temperature-dependent deviation of the reference voltage signal Vreg;

[0128] When the voltage difference V between the gate and source of the fifteenth field-effect transistor M15 GS15 <V THN When the linear regulator fails to function properly, the reference voltage signal Vreg is:

[0129] Vreg = VDD - V DSAT14 (16)

[0130] Where VDD is the power supply voltage, V DSAT14 This is the overdrive voltage of the fourteenth field-effect transistor M14.

[0131] In specific implementation, the seventeenth field-effect transistor M17, the twelfth field-effect transistor M12, the fifteenth field-effect transistor M15, and the fourth current source I4 constitute a pseudo-differential input operational amplifier. Therefore, the fourth current source I4 can be expressed as:

[0132] I4=(1 / 2)·μ n ·C OX (W / L) 15 (V GS15 -V THN ) 2 (17)

[0133] The eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 form a resistance feedback network. Therefore:

[0134] V GS15 / Vreg=R10 / (R8+R9+R10) (18)

[0135] Therefore, we can conclude that:

[0136] Vreg={[2 I4 / (μ n ·C OX (W / L) 15 )] 1 / 2 +V THN}·(R8+R9+R10) / R10 (15)

[0137] As can be seen from equation (15), the threshold voltage of the field-effect transistor will decrease as the temperature rises. Here, the fourth current source I4 uses PTAT current to compensate for the decrease in threshold voltage and reduce the deviation of Vreg with temperature.

[0138] When V GS15 <V THN When the linear regulator loop fails to function properly, it can be concluded that:

[0139] Vreg = VDD - V DSAT14 (16)

[0140] Optionally, the ring oscillator auxiliary circuit further includes: a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, and a fifth current source I5; the source of the seventh field-effect transistor M7, the source of the eighth field-effect transistor M8, and the source of the ninth field-effect transistor M9 are connected to the power supply VDD; the gate of the seventh field-effect transistor M7 is connected in series with the gate of the eighth field-effect transistor M8 and then connected to the fifth current source I5. The drain of transistor M7 is connected to the fifth current source I5. The drain of the eighth field-effect transistor M8 is connected to the fifth node E. The drain of the tenth field-effect transistor M10 is connected to the fifth node E. The gate of the tenth field-effect transistor M10 is connected to the fourth node D. The gate of the ninth field-effect transistor M9 is connected to the first signal EN. The drain of the ninth field-effect transistor M9 is connected to the gate of the eleventh field-effect transistor M11. The drain of the eleventh field-effect transistor M11 outputs the initial state signal PD to the ring oscillator circuit.

[0141] Optionally, the seventh field-effect transistor M7 and the eighth field-effect transistor M8 are current mirror structures, and the width-to-length ratio of the seventh field-effect transistor M7 is the same as that of the eighth field-effect transistor M8.

[0142] The ninth field-effect transistor M9 is an auxiliary circuit switch. When the first signal EN is low, it ensures that the output initial state signal PD is low, providing an initial state signal to the ring oscillator circuit.

[0143] The fifth current source I5 is a PTAT current source;

[0144] The tenth field-effect transistor M10 and the eleventh field-effect transistor M11 are used to determine the reference voltage signal Vreg. During the establishment of the reference voltage signal Vreg, the voltage at the fourth node D rises with the reference voltage signal Vreg, the tenth field-effect transistor M10 turns on and the voltage at the fifth node E decreases, and the eleventh field-effect transistor M11 turns off, so that the initial state signal PD output by the ring oscillator auxiliary circuit will not affect the ring oscillator circuit.

[0145] An embodiment of a control method for a two-phase third-order ring oscillator circuit:

[0146] This application provides a control method for a two-phase third-order ring oscillator circuit, wherein the two-phase third-order ring oscillator circuit adopts the above-mentioned... Figure 1 and Figure 2 A two-phase third-order ring oscillator circuit is constructed, comprising: a ring oscillator auxiliary circuit and a ring oscillator circuit; the ring oscillator circuit includes: a first-stage gain stage circuit, a second-stage gain stage circuit, and a third-stage gain stage circuit, a voltage comparator, and an inverter; the first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit are interconnected; one end of the voltage comparator is connected to the third-stage gain stage circuit, and the other end of the voltage comparator is connected to the inverter; the method includes the following steps:

[0147] The ring oscillator auxiliary circuit provides the ring oscillator circuit with a reference voltage signal Vreg and an initial state signal PD before the ring oscillator circuit starts.

[0148] The first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit constitute a differential input structure to reduce the influence of common-mode noise; the voltage comparator compares the two voltages corresponding to the first node A and the second node B on the third-stage gain stage circuit to obtain a square wave signal; the inverter shapes the square wave signal to obtain the clock signal CLK.

[0149] The ring oscillator auxiliary circuit provides the ring oscillator circuit with a reference voltage signal Vreg and an initial state signal PD before the ring oscillator circuit starts. The first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit are interconnected. One end of the voltage comparator is connected to the third-stage gain stage circuit, and the other end of the voltage comparator is connected to the inverter. The first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit form a differential input structure to reduce the influence of common-mode noise. The voltage comparator P1 compares the two voltages corresponding to the first node A and the second node B on the third-stage gain stage circuit to obtain a square wave signal. The inverter L1 is used to shape the square wave signal to obtain the clock signal CLK, thereby generating a clock signal with high precision, low temperature variation, and high frequency. The differential input structure of each gain stage can provide good common-mode rejection.

[0150] In specific implementation, in the linear regulator, the gate of the thirteenth field-effect transistor M13 is connected to the first signal EN; the seventeenth field-effect transistor M17 and the twelfth field-effect transistor M12 are current source loads; the aspect ratio of the seventeenth field-effect transistor M17 is the same as that of the twelfth field-effect transistor M12; the thirteenth field-effect transistor M13 is the linear regulator switch; the fourteenth field-effect transistor M14 is the linear regulator power transistor; the fifteenth field-effect transistor M15 is the feedback signal input transistor; the sixteenth field-effect transistor M16 is the voltage-regulating MOS capacitor; the fourth current source I4 is the PTAT current source; the seventh capacitor C7 and the seventh resistor R7 form a Miller compensation network to ensure loop stability; the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 form the linear regulator feedback network.

[0151] Among them, such as Figure 2 As shown, the seventeenth field-effect transistor M17, the twelfth field-effect transistor M12, the fifteenth field-effect transistor M15, and the fourth current source I4 constitute a pseudo-differential input operational amplifier;

[0152] Therefore, the fourth current source can be represented as:

[0153] I4=(1 / 2)·μ n ·C OX (W / L) 15 (V GS15 -V THN ) 2 (17)

[0154] Where, μ n For electron mobility, C OX The capacitance of the gate oxide layer per unit area (W / L) 15 V represents the aspect ratio of the fifteenth field-effect transistor, M15. GS15 V represents the gate-source voltage difference of the fifteenth field-effect transistor M15.THN This is the threshold voltage of the N-type field-effect transistor.

[0155] The eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 form a resistance feedback network. Therefore:

[0156] V GS15 / Vreg=R10 / (R8+R9+R10) (18)

[0157] Therefore, we can conclude that:

[0158] Vreg={[2 I4 / (μ n C OX (W / L) 15 )] 1 / 2 +V THN}·(R8+R9+R10) / R10 (15)

[0159] As can be seen from equation (15), the threshold voltage of the N-type field-effect transistor will decrease as the temperature rises. Here, the fourth current source I4 uses PTAT current to compensate for the decrease in threshold voltage and reduce the deviation of Vreg with temperature.

[0160] When V GS15 <V THN When the linear regulator loop fails to function properly, it can be concluded that:

[0161] Vreg = VDD - V DSAT14 (16)

[0162] Among them, V DSAT14 This is the overdrive voltage of the fourteenth field-effect transistor, M14.

[0163] Optionally, in this embodiment, the seventh field-effect transistor M7 and the eighth field-effect transistor M8 are current mirror structures, and the width-to-length ratio of the seventh field-effect transistor M7 is the same as that of the eighth field-effect transistor M8; the ninth field-effect transistor M9 is an auxiliary circuit switch, which ensures that the output initial state signal PD is low when the first signal EN is low, providing an initial state signal to the ring oscillator circuit; the fifth current source I5 is a PTAT current source; the tenth field-effect transistor M10 and the eleventh field-effect transistor M11 are used to determine the reference voltage signal Vreg. When the reference voltage signal Vreg is established, the voltage of the fourth node D rises with the reference voltage signal Vreg, the tenth field-effect transistor M10 turns on and the voltage of the fifth node E decreases, and the eleventh field-effect transistor M11 turns off, so that the initial state signal PD output by the ring oscillator auxiliary circuit will not affect the ring oscillator circuit.

[0164] Among them, such as Figure 1As shown, in the first gain stage circuit, the first field-effect transistor M1 and the second field-effect transistor M2 are connected as a differential input pair, and the tail current source is provided by the first current source I1. The first resistor R1 and the first capacitor C1 are connected as a passive load, and the second resistor R2 and the second capacitor C2 are connected as a passive load. The width-to-length ratio (W / L)1 of the first field-effect transistor M1 is the same as the width-to-length ratio (W / L)2 of the second field-effect transistor M2. The first resistor R1 and the first capacitor C1 form an RC network, and the second resistor R2 and the second capacitor C2 form an RC network.

[0165] In the second-stage gain stage circuit, the third field-effect transistor M3 and the fourth field-effect transistor M4 are connected as a differential input pair, with the tail current source provided by the second current source I2. The third resistor R3 and the third capacitor C3 are connected as a passive load, and the fourth resistor R4 and the fourth capacitor C4 are connected as a passive load. The width-to-length ratio (W / L) 3 of the third field-effect transistor M3 is the same as that of the fourth field-effect transistor M4. The third resistor R3 and the third capacitor C3 form an RC network, and the fourth resistor R4 and the fourth capacitor C4 form an RC network.

[0166] The third-stage gain stage circuit includes a fifth field-effect transistor M5 and a sixth field-effect transistor M6 connected as a differential input pair, with the tail current source provided by the third current source I3. The fifth resistor R5 and the fifth capacitor C5 are connected as a passive load, and the sixth resistor R6 and the sixth capacitor C6 are connected as a passive load. The width-to-length ratio (W / L) 5 of the fifth field-effect transistor M5 is the same as that of the sixth field-effect transistor M6. The fifth resistor R5 and the fifth capacitor C5 form an RC network, and the sixth resistor R6 and the sixth capacitor C6 form an RC network.

[0167] In practical implementation, in the three-stage gain stage circuit, each stage uses differential input and has the same structure. The transfer function of each stage is as follows:

[0168] H(s1)=H(s2)=H(s3)=-A0 / (1+s / ω0) (1)

[0169] Where A0 is the low-frequency gain, s is the complex frequency, and ω0 is the bandwidth, for example, a 3dB bandwidth;

[0170] The loop gain of the ring oscillator circuit is shown below:

[0171] H(s)=-A0 3 / (1+s / ω0) 3 (2)

[0172] Therefore, since the three poles of the ring oscillator circuit are at the same frequency, according to the Barkhausen criterion, oscillation can only occur when the frequency-dependent phase shift is equal to 180° and the loop gain is greater than or equal to 1. The relationship between the oscillation frequency and the frequency at the poles is as follows:

[0173] arctan(ω osc / ω0)=60° (5)

[0174] Where, ω osc ω is the oscillation angular frequency, and ω0 is the pole angular frequency.

[0175] Therefore, the oscillation frequency and the minimum gain of each gain stage are as follows:

[0176] f osc =3 1 / 2 ·(1 / 2πRC) (6)

[0177] Among them, f osc R is the oscillation frequency, R is the resistance value in the RC network, and C is the capacitance in the RC network.

[0178] A0≥[1+(ω osc / ω0) 2 ] 1 / 2 =2 (7)

[0179] In the first gain stage, the gate voltages of the first field-effect transistor M1 and the second field-effect transistor M2 are V, respectively. A V B ,but:

[0180] (1 / 2)·μ n ·C OX (W / L) 1，2 ·(V A -V P -V THN ) 2 +(1 / 2)·μ n ·C OX (W / L) 1，2 ·(V B -V P -V THN ) 2 =I1 (8)

[0181] Where, μ n C represents the electron mobility of the field-effect transistor. OX V is the gate oxide capacitance per unit area. P For the voltage corresponding to the sixth node P, simplifying equation (8) yields:

[0182] V P=(1 / 2)·{V A +V B -2 V THN ±[-(V A -V B ) 2 +4 I1 / (μ n C OX (W / L) 1，2 )] 1 / 2} (9)

[0183] Since the voltages at points A and B change differentially, they can be expressed by the following formula:

[0184] V A =V CM +ΔV (10)

[0185] V B =V CM -ΔV (11)

[0186] V CM＝ Vreg-(1 / 2)·I1·R 1，2 (12)

[0187] Among them, V CM ΔV is the common-mode voltage, and ΔV is the differential-mode voltage.

[0188] Substituting equations (10), (11), and (12) into equation (9), we get:

[0189] V P =V CM -V THN ±(1 / 2)·{-(2ΔV) 2 +4 I1 / [μ n ·C OX (W / L) 1，2 ]} 1 / 2 (13)

[0190] According to Equation 15, the minimum voltage of the sixth node P can be obtained, and thus the voltage range of Vreg can be determined:

[0191] Vreg≥V P，min +V THN +{I1 / [μ n ·C OX (W / L) 1，2 ]} 1 / 2 +I1·R 1，2 / twenty three)

[0192] In the above formula, V P，min This represents the minimum voltage required across the first current source I1.

[0193] In this two-phase third-order ring oscillator circuit, the single-phase loop consists of three single-pole common-source amplifiers. The gain-bandwidth product of the single-pole system is as follows:

[0194] GBW = A0·f d (14)

[0195] Where GBW is the gain-bandwidth product, f d The frequency of the dominant pole.

[0196] As temperature rises, the threshold voltage of the input pair transistors decreases. The use of PTAT current in the tail current source can reduce the deviation of the transconductance of the input pair transistors caused by temperature changes, that is, reduce the error caused by the overall loop bandwidth changing with temperature. Ensuring the bandwidth stability of the signal processing loop helps to stabilize the frequency of the oscillation signal and generate an oscillation signal that changes less with temperature.

[0197] After the ring oscillator circuit starts, oscillation signals with a 180° phase difference will be generated at points A and B. Due to the RC network at the load, the output voltage at each stage will increase or decrease exponentially. Based on the RC network time constant and oscillation frequency, the output voltage ranges at points A and B are as follows:

[0198] Vreg-(4 / 5)·I3·R 5，6 ≤V A，B ≤Vreg-(1 / 5)·I3·R 5，6 (4)

[0199] The oscillation signals with a 180° phase difference between the first node A and the second node B are compared by a high-speed comparator, and after being shaped by an inverter, the output is a low-temperature drift, high-precision CLK signal.

[0200] Therefore, the two-phase third-order ring oscillator circuit proposed in this application can generate a clock signal with high precision, low temperature variation, and high frequency. The differential input structure of each gain stage can provide good common-mode rejection.

[0201] This application also provides a chip that includes the aforementioned two-phase third-order ring oscillator circuit. Optionally, the chip can be a fast-charging chip.

[0202] This application also provides an electronic device, wherein the electronic device includes the aforementioned two-phase third-order ring oscillator circuit.

[0203] The electronic device may be a mobile phone, tablet computer, or other terminal, or it may be a charging adapter. Optionally, the electronic device may also include other components, which are not limited in this embodiment.

[0204] It should be noted that the above are only preferred embodiments of this application, but the design concept of the invention is not limited thereto. Any non-substantial modifications made to this application using this concept also fall within the protection scope of this application.

Claims

1. A control method for a two-phase third-order ring oscillator circuit, characterized in that, A two-phase third-order ring oscillator circuit generates a square wave signal, which depends on two voltages corresponding to the first and second nodes on the gain stage circuit. The square wave signal is shaped to obtain the clock signal CLK; The two-phase third-order ring oscillator circuit includes: a ring oscillator auxiliary circuit and a ring oscillator circuit; wherein, The ring oscillator auxiliary circuit is used to provide the ring oscillator circuit with a reference voltage signal Vreg and an initial state signal PD before the ring oscillator circuit starts. The ring oscillator circuit includes: a first-stage gain stage circuit, a second-stage gain stage circuit, and a third-stage gain stage circuit, a voltage comparator, and an inverter; the first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit are interconnected; one end of the voltage comparator is connected to the third-stage gain stage circuit, and the other end of the voltage comparator is connected to the inverter. The voltage comparator is used to compare the two voltages corresponding to the first node and the second node on the third-stage gain stage circuit to obtain a square wave signal. The inverter is used to shape the square wave signal to obtain the clock signal CLK; The first-stage gain stage circuit, the second-stage gain stage circuit, and the third-stage gain stage circuit constitute a differential input structure.

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