Logic simulation verification system, logic simulation verification method, and program

Abstract

The present invention relates to a logic simulation verification system, method, and program. The same logic simulation results are provided to each logic simulator in a short time. The logic simulation verification system verifies the change of signals described in a library, a circuit description, and a test bench for a reference signal that is a basis for the change of signals, and includes: a change timing specifying unit that specifies a reference signal and change information of the reference signal; a change possibility time calculation unit that obtains a first time when there is a possibility that a first signal substituted for a variable changes; a reference possibility time calculation unit that obtains a second time when there is a possibility that a second signal to which the variable is referred is referred; a change possibility time determination unit that compares the first times when the first signals are the same between different circuits to determine whether the first times are consistent; and a change and reference possibility time determination unit that determines whether the first signal of one party and the second signal of the other party are the same between different circuits and the first time and the second time are consistent.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-155694 filed on September 16, 2020, and incorporates the entire content thereof by reference. Technical Field

[0002] Embodiments of the present invention relate to a logic simulation verification system, a logic simulation verification method, and a program. Background Art

[0003] In logic simulation, a logic simulator is executed using a library described in the Verilog-HDL language, a circuit description, and input information data described in a test bench file. In addition, in order to avoid a race condition of each signal, the logic simulator sometimes analyzes whether a race condition of each signal occurs. Summary of the Invention

[0004] One embodiment provides the same logic simulation result to each logic simulator in a short time.

[0005] The logic simulation verification system according to the embodiment verifies changes in signals described in a library, a circuit description, and a test bench with respect to a reference signal that is a basis for signal changes. The logic simulation verification system includes: a change timing specifying unit that specifies a reference signal and change information of the reference signal; a change possibility time calculation unit that calculates a first time at which there is a possibility that a first signal substituted into a variable described in the library, the circuit description, and the test bench changes with respect to the reference signal and the change of the reference signal; a reference possibility time calculation unit that obtains a second time at which there is a possibility that a second signal described in the library, the circuit description, and the test bench is referenced with respect to the reference signal and the change of the reference signal; a change possibility time determination unit that compares the first times at which the first signals are the same between different circuits to determine whether the first times are consistent; and a change and reference possibility time determination unit that determines whether the first signal of one of different circuits is the same as the second signal of the other circuit and the first time is consistent with the second time.

[0006] According to the above configuration, the same logic simulation result can be provided to each logic simulator in a short time. Brief Description of the Drawings

[0007] Figure 1 It is a schematic diagram showing the configuration of the logic simulation verification system according to the embodiment.

[0008] Figure 2 It is a detailed functional module configuration diagram of a server and a storage medium of the logic simulation verification system according to the embodiment.

[0009] Figure 3It is a description example of signals and signal change information stored in the timing information storage unit related to the embodiment, represented in SDC (Synopsys Design Constraint Format).

[0010] Figure 4 It is a unit description example of a library described in Verilog-HDL language.

[0011] Figure 5 It is a specific unit description example of a library where there is a possibility of signal change substituted by multiple circuits.

[0012] Figure 6 It is a block diagram of a system using the logic simulation verification system related to the embodiment.

[0013] Figure 7 It is an operation flowchart of the logic simulation verification system related to the embodiment.

[0014] Figure 8 It is Figure 4 a correction example of the unit description of the library.

[0015] Figure 9 It is a description example of a reference signal of frequency represented in SDC.

[0016] Figure 10 It is a description example of the change timing of a reference signal without a period represented in SDC for an example of a library unit.

[0017] Figure 11 It is a description example of a test bench representing the change timing of a reference signal in SDC for a description example.

[0018] Figure 12 It is a description example of a test bench where the time of change possibility and the time of reference possibility change in a begin - end circuit module.

[0019] Figure 13 It is a description example of a test bench representing the change timing of a reference signal in SDC for a description example.

[0020] Figure 14 It is a block diagram when verifying whether the constraint conditions given by SDC are complied with in logic simulation. Detailed Embodiment

[0021] Next, each embodiment will be described with reference to the accompanying drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. The drawings are schematic drawings.

[0022] In addition, the following-described embodiments illustrate apparatuses and methods for embodying a technical idea. The embodiments can be subjected to various modifications.

[0023] In the following description, for the sake of simplification, SDC (Synopsys Design Constraint Format), 1 (1‘b1), and 0 (1‘b0) may sometimes be shown as SDC, 1, and 0. SDC is a reference format for describing timing constraints publicly disclosed by Synopsys, Inc. For 1‘b1, for example, 1‘ indicates a 1-bit width, b indicates binary (base 2), and 1 indicates the value itself.

[0024]

First Embodiment

[0025] The logic simulation verification system 1 connects the computer device 10 operated by a user, the server 20 that stores programs for the computers used in the logic simulation verification system 1, and the storage medium 40 via the network 30. The storage medium 40 stores input information data required to execute programs for the computers used in logic simulation, and messages of verification results.

[0026] The computer device 10 can be, for example, a personal computer (PC), a thin client terminal, a mobile terminal, or a PDA (Personal Digital Assistant). The server 20 can be, for example, an engineering workstation, a mainframe, or a supercomputer. The network 30 can be, for example, the Internet, an intranet, a LAN, a telephone communication network, or a dedicated line. The storage medium 40 can be, for example, an external storage device of a hard disk, a semiconductor storage device of a memory, or a storage medium (medium). However, in reality, it is not limited to these examples.

[0027] Figure 2 is a block diagram showing a detailed configuration example of the server 20 and the storage medium 40 of the logic simulation verification system 1 according to an embodiment. As Figure 2 shown, the server 20 includes a logic simulation verification unit 21 that executes programs for the computers used in the logic simulation verification system 1, and a logic simulator 22 that executes programs for the computers used in logic simulation.

[0028] Among them, the logic simulation verification unit 21 can be, for example, a processing device such as a CPU (Central Processing Unit) or a microprocessor, or a semiconductor integrated circuit (Integrated Circuit (IC)) that performs the same function. However, in reality, it is not limited to these examples.

[0029] In addition, the logic simulation verification unit 21 includes a change timing specification unit 211, a change possibility time calculation unit 212, a reference possibility time calculation unit 213, a change possibility time determination unit 214, a write-write hazard message output unit 215, a change and reference possibility time determination unit 216, and a read-write hazard message output unit 217. In the following description, write-write hazard and read-write hazard are referred to as WW hazard and RW hazard.

[0030] The storage medium 40 includes a timing information storage unit 41, an input information data storage unit 42, and a message storage unit 43.

[0031] The timing information storage unit 41 stores, for example, a file that represents a reference signal serving as a reference for signal changes and change information of the reference signal in SDC. In the following description, the file that represents the reference signal and the change information of the reference signal in SDC is referred to as the SDC file 41A. In addition, the reference signal serving as a reference for signal changes and the change information of the reference signal are also referred to as the timing reference signal and its change timing.

[0032] The SDC file 41A is input information data required to execute a program of a computer used for the logic simulation verification system 1. In addition, the SDC file 41A can also be input information data required to execute the logic simulator 22.

[0033] Figure 3 It is a description example that represents the specific reference signal and the change information of the reference signal stored in the timing information storage unit 41 according to the embodiment in SDC.

[0034] As Figure 3 shown, the timing information storage unit 41 stores information using a library, circuit description, signal names of signals input to a testbench file, clock periods of signals, and node names of the input signals described in the Verilog-HDL (Hardware Description Language) language as reference signals.

[0035] The input information data storage unit 42 stores, for example, a library, a circuit description, and a test bench file described in Verilog-HDL language. In the following description, the library, the circuit description, and the test bench file described in Verilog-HDL language are referred to as the input information data 42A of "first data".

[0036] The input information data 42A is the input information data required to execute the program of the computer used by the logic simulation verification system 1. In addition, the input information data 42A can also be the input information data required to execute the logic simulator 22.

[0037] The message storage unit 43 stores the messages output from the write write hazard message output unit 215 or the read write hazard message output unit 217 in the logic simulation verification unit 21. The WW hazard and the RW hazard will be described later.

[0038] When the library, the circuit description, and the test bench are included in the input information data, the logic simulation generates a signal competition state due to two reasons, namely the RW hazard and the WW hazard, and there is a possibility that each simulator of the logic simulator 22 has a different simulation result. The signal competition state refers to a signal state in which there is a possibility of malfunction (an action not desired by the designer) due to multiple signals changing simultaneously in the logic circuit.

[0039] Next, the RW hazard, which is the reason for the different results of the logic simulation, will be described.

[0040] Figure 4 It is an example of the cell description of the specific library stored in the input information data storage unit 42 according to the embodiment.

[0041] Figure 4 The circuit B1 of the always module from LineB to LineE and the circuit B2 of the always module from LineF to LineK are described in the figure. In the following description, Figure 4 the circuit B1 of the always module and the circuit B2 of the always module in the figure are referred to as the circuit B1 and the circuit B2.

[0042] The circuit B1 is started by the rising edge of CLK1, and when the variable COND is 1, 1 is substituted into the variable A (LineC). In addition, when the variable COND is 0, 0 is substituted into the variable A (LineD).

[0043] The circuit B2 is started by the rising edge of CLK2, and when the variable A is 1, 1 is substituted into the variable COND (LineG). In addition, when the variable A is 0, 0 is substituted into the variable COND (LineH).

[0044] Here, in the following description, for the reference signal and the change of the reference signal, the signal substituted into the variable is referred to as the first signal.

[0045] That is, in the above description, 1 or 0 substituted into the variable A of circuit B1 is the output signal of circuit B1 and is an example of the first signal. Similarly, 1 or 0 substituted into the variable COND of circuit B2 is the output signal of circuit B2 and is an example of the first signal.

[0046] And, in the following description, for the reference signal and the change of the reference signal, the signal referred to by the reference variable is referred to as the second signal.

[0047] That is, 1 or 0 referred to by the variable COND of circuit B1 is the input signal of circuit B1 and is an example of the second signal. Similarly, 1 or 0 referred to by the variable A of circuit B2 is the input signal of circuit B2 and is an example of the second signal.

[0048] Circuits B1 and B2 are as Figure 3 shown, and the clock periods of CLK1 and CLK2 as the reference signals are the same. For such a reference signal and the change of the reference signal, the variable A of circuit B1 and the variable COND of circuit B2, which are the first signals of circuits B1 and B2, may change at the rising edges of CLK1 and CLK2.

[0049] And, the variable A as the first signal of circuit B1 is the same as the variable A of the second signal of circuit B2. Similarly, the variable COND as the first signal of circuit B2 is the same as the variable COND of the second signal of circuit B1. Therefore, between circuits B1 and B2, the results of the variable A and the variable COND are different when circuit B1 is evaluated first and when circuit B2 is evaluated first.

[0050] Specifically, when circuit B1 is evaluated first, circuit B1 starts at the rising edge of CLK1 as the reference signal, and there is a possibility that the variable COND as the second signal is referred to. Since the variable COND as the second signal is 1, circuit B1 substitutes 1 into the variable A as the first signal.

[0051] Next, circuit B2 starts at the rising edge of CLK2 as the reference signal, and there is a possibility that the variable A as the second signal is referred to. Since the variable A as the second signal is 1, circuit B2 substitutes 1 into the variable COND of the first signal. As a result, the variable A is 1 and the variable COND is 1.

[0052] In the case of evaluating circuit B2 first, circuit B2 starts at the rising edge of CLK2 which serves as the reference signal, and there is a possibility that the variable COND as the second signal is referred to. Since the variable A as the second signal is 0, circuit B2 substitutes 0 into the variable COND as the first signal.

[0053] Next, circuit B1 starts at the rising edge of CLK1 which serves as the reference signal, and there is a possibility that the variable COND as the second signal is referred to. Since the variable COND as the second signal is 0, circuit B1 substitutes 0 into the variable A of the first signal. As a result, the variable A is 0 and the variable COND is 0.

[0054] As described above, if logical simulation is performed using the SDC file 41A described by Figure 3 and the input information data 42A including the library described by Figure 4 , the simulation result changes depending on which of circuit B1 and circuit B2 is evaluated first. The situation where it is possible to refer to (read) the second signal and change (write) the first signal at the same timing of the reference signal is called the RW hazard.

[0055] Next, the WW hazard which is the reason for the different results of the logical simulation will be described.

[0056] Figure 5 This is a specific example of the unit description of a library where there is a possibility that the signal substituted into the variable changes among multiple circuits in the embodiment.

[0057] Figure 5 In the figure of Figure 5 , the circuit B3 of the always module from LineA to LineD and the circuit B4 of the always module from LineE to LineH are described. In the following description, the circuit B3 of the always module and the circuit B4 of the always module in the figure of Figure 5 are referred to as circuit B3 and circuit B4.

[0058] Circuit B3 starts due to the rising of CLK1 as the reference signal. When the variable COND1 is 1, 1 is substituted into the variable A (LineB). In addition, when the variable COND1 is 0, 0 is substituted into the variable A (LineC).

[0059] Circuit B4 starts due to the rising of CLK2 as the reference signal. When the variable COND2 is 1, 0 is substituted into the variable A (LineF). In addition, when the variable COND2 is 0, 1 is substituted into the variable A (LineG).

[0060] This circuit B3 and circuit B4 are as Figure 3As shown, the clock cycles of CLK1 and CLK2, which are reference signals, are the same. And, as Figure 5 shown, the first signals of circuit B3 and circuit B4 are the same variable A.

[0061] For such reference signals, the variable A, which is the first signal of circuit B3 and circuit B4, may change at the rising edges of CLK1 and CLK2. Therefore, between circuit B3 and circuit B4, the result of the variable A of the first signal is different when circuit B3 is evaluated first and when circuit B4 is evaluated first.

[0062] Specifically, when circuit B3 is evaluated first, circuit B3 starts at the rising edge of CLK1, which is a reference signal, and there is a possibility that the variable COND1, which is the second signal, is referred to. When the variable COND1, which is the second signal, is 1, circuit B3 substitutes 1 for the variable A, which is the first signal.

[0063] Next, circuit B4 starts at the rising edge of CLK2, which is a reference signal, and there is a possibility that the variable COND2, which is the second signal, is referred to. When the variable COND2, which is the second signal, is 1, circuit B4 substitutes 0 for the variable A of the first signal. As a result, the variable A, which is the first signal, is 0.

[0064] When circuit B4 is evaluated first, circuit B4 starts at the rising edge of CLK2, which is a reference signal, and there is a possibility that the variable COND2, which is the second signal, is referred to. When the variable COND2, which is the second signal, is 1, circuit B4 substitutes 0 for the variable A, which is the first signal.

[0065] Next, circuit B3 starts at the rising edge of CLK1, which is a reference signal, and there is a possibility that the variable COND1, which is the second signal, is referred to. When the variable COND1, which is the second signal, is 1, circuit B3 substitutes 1 for the variable A of the first signal. As a result, the variable A, which is the first signal, is 1.

[0066] As described above, if the logic simulation is performed using the SDC file 41A described by Figure 3 and the input information data 42A including the library described by Figure 5 the simulation result changes depending on which of circuit B3 and circuit B4 is evaluated first. The situation where the first signal may change (be written) at the same timing of the reference signal is called the WW hazard.

[0067] The logic simulation verification unit 21 according to the embodiment will be described.

[0068] Figure 6It is a block diagram of a system using the logic simulation verification system 1 involved in the embodiment.

[0069] The logic simulation verification unit 21, as Figure 6 shown, performs static analysis using the SDC 41A as input information data and the input information data 42A including a library, a circuit description, and a test bench.

[0070] This static analysis means verifying the possibility that a first signal changes and a second signal is referenced in response to a reference signal and a change in the reference signal without using the logic simulator 22.

[0071] The change timing specifying unit 211 specifies the signal information of the reference signal and the change in the reference signal stored in the timing information storage unit 41 of the storage medium 40. That is, the change timing specifying unit 211, as Figure 3 shown in the description example, specifies, for example, CLK1 and CLK2 as reference signals.

[0072] The change possibility time calculation unit 212 reads the input information data including the input information data 42A of the library, the circuit description, and the test bench stored in the input information data storage unit 42 of the storage medium 40.

[0073] The change possibility time calculation unit 212 calculates the change possibility time of the signal substituted into the variable for the possibility that a first signal changes in response to a change in the reference signal based on the input information data 42A of the input information data. Hereinafter, the change possibility time of the signal substituted into the variable is referred to as the first time.

[0074] Specifically, as Figure 5 shown, for the rising edges of CLK1 and CLK2 as reference signals, the first time of circuit B3 is the time when there is a possibility of substituting into variable A as the output signal of the first signal. Similarly, the first time of circuit B4 is the time when there is a possibility of substituting into variable A as the output signal of the first signal.

[0075] The reference possibility time calculation unit 213 reads the input information data including the input information data 42A of the library, the circuit description, and the test bench stored in the input information data storage unit 42 of the storage medium 40.

[0076] The reference possibility time calculation unit 213 calculates the reference possibility time of the signal referenced by the variable for the second signal to be referenced in response to a change in the reference signal based on the input information data 42A of the input information data. Hereinafter, the reference possibility time of the signal referenced by the variable is referred to as the second time.

[0077] Specifically, as Figure 4As shown, for the rising edges of CLK1 and CLK2 serving as reference signals, the second moment of circuit B1 is the moment when there is a possibility that the variable COND of the input signal as the second signal is referred to and substituted into the variable A of the output signal as the first signal. Similarly, the second moment of circuit B2 is the moment when there is a possibility that the variable A of the input signal as the second signal is referred to and substituted into the variable COND of the output signal as the first signal.

[0078] When the first signal is the same for the change of the reference signal between different circuits, the change possibility time determination unit 214 compares each first moment when there is a possibility of change in the first signal to determine whether the first moments are consistent.

[0079] Between these different circuits, for example, Figure 5 the circuit B3 of the always module from LineA to LineD and the circuit B4 of the always module from LineE to LineH as shown.

[0080] When it is determined by the change possibility time determination unit 214 that the first moments between different circuits are consistent, the write write hazard message output unit 215 outputs the content that there is a possibility of a WW hazard to the message storage unit 43 of the storage medium 40. Additionally, when it is determined by the change possibility time determination unit 214 that the first moments between different circuits are inconsistent, the content that there is no problem is output to the message storage unit 43 of the storage medium 40.

[0081] When one first signal is the same as the other second signal between different circuits, the change and reference possibility time determination unit 216 determines whether there is a possibility that the first moment and the second moment are the same. The first moment is the moment when there is a possibility of change in the first signal for the change of the reference signal, and the second moment is the moment when there is a possibility that the second signal is referred to for the change of the reference signal.

[0082] When it is determined by the change and reference possibility time determination unit 216 that the first moment and the second moment between different circuits are the same moment, the read write hazard message output unit 217RW outputs the content that there is a possibility of a hazard to the message storage unit 43 of the storage medium 40. Additionally, when it is determined by the change and reference possibility time determination unit 216 that the first moment and the second moment between different circuits are different, the content that there is no problem is output to the message storage unit 43 of the storage medium 40.

[0083] The logic simulator 22 performs dynamic analysis using, for example, the input information data stored in the timing information storage unit 41 and the input information data storage unit 42. This dynamic analysis refers to performing analysis using the logic simulator 22. In addition, the signal race state can be verified by the logic simulation verification unit 21, and dynamic analysis can be performed using the input information data including the corrected library, circuit description, and input information data 42B of the test bench. Since the internal configuration of the logic simulator 22 is well-known, the description of the internal configuration is omitted.

[0084] Figure 7 It is a flowchart of the operation of the logic simulation verification system 1 according to the embodiment.

[0085] Refer to Figure 2 、 Figure 6 、 Figure 7 to describe the logic simulation verification method of the logic simulation verification system 1 according to the embodiment.

[0086] In step S11, the change timing specifying unit 211 reads the SDC file 41A. Moreover, the change timing specifying unit 211 specifies the reference signal and the change information of the reference signal from the SDC file 41A.

[0087] In step S12, the change possibility time calculation unit 212 reads the input information data 42A including the library, circuit description, and test bench. Moreover, the change possibility time calculation unit 212 calculates, based on the input information data 42A, the first time at which there is a possibility that a first signal changes with respect to the reference signal specified in step S11 and the change of the reference signal.

[0088] In step S13, the reference possibility time calculation unit 213 reads the input information data 42A including the library, circuit description, and test bench. Moreover, the reference possibility time calculation unit 213 calculates, based on the input information data 42A, the second time at which there is a possibility that a second signal is referenced with respect to the reference signal specified in step S11 and the change of the reference signal.

[0089] In step S14, when the change possibility time calculation unit 212 and the reference possibility time calculation unit 213 have obtained all the first times and second times, it proceeds to step S15. When the change possibility time calculation unit 212 and the reference possibility time calculation unit 213 have not obtained all the first times and second times, it proceeds to step 12.

[0090] In step S15, when the first signal is the same among different circuits with respect to the reference signal and the change of the reference signal, the change possibility time determination unit 214 compares each first moment at which there is a possibility of the first signal changing to determine whether the first moments are the same. Moreover, when the change possibility time determination unit 214 determines that the first moments are the same, the process proceeds to step S16. When the first moments are not the same, the process proceeds to step S17.

[0091] In step S16, when it is determined by the change possibility time determination unit 214 that the first moments are the same, the write write hazard message output unit 215 outputs to the message storage unit 43 of the storage medium 40 the content that there is a possibility of a WW hazard. Moreover, after the output, the process proceeds to step S18.

[0092] In step S17, when it is determined by the change possibility time determination unit 214 that the first moments are not the same, the write write hazard message output unit 215 outputs to the message storage unit 43 of the storage medium 40 the content that there is no problem. Moreover, after the output, the process proceeds to step S18.

[0093] In step S18, when the first signal on one side is the same as the second signal on the other side among different circuits, the change and reference possibility time determination unit 216 determines whether there is a possibility that the first moment at which there is a possibility of the first signal changing with respect to the reference signal and the change of the reference signal, and the second moment at which there is a possibility of the second signal being referenced with respect to the reference signal and the change of the reference signal are simultaneous.

[0094] Moreover, when the change and reference possibility time determination unit 216 determines that there is a possibility that the first moment and the second moment are simultaneous, the process proceeds to step S19. When there is no possibility that the first moment and the second moment are simultaneous, the process proceeds to step S20.

[0095] In step S19, when it is determined by the change and reference possibility time determination unit 216 that there is a possibility that the first moment and the second moment among different circuits are simultaneous, the read write hazard message output unit 217 outputs to the message storage unit 43 of the storage medium 40 the content that there is a possibility of an RW hazard. Moreover, after the output, the process ends.

[0096] In step S20, when it is determined by the change and reference possibility time determination unit 216 that the first moment and the second moment among different circuits are different, the read write hazard message output unit 217 outputs to the message storage unit 43 of the storage medium 40 the content that there is no problem. Moreover, after the output, the process ends.

[0097] In addition, the user refers to the warning message stored in the message storage unit 43 regarding the possibility of WW adventures and RW adventures, and corrects the input information data 42A. The corrected file becomes the input information data 42B including the corrected library, circuit description, and test bench.

[0098] Figure 8 is a specific example Figure 4 of the correction of the RW adventure in the cell description of the library involved in the embodiment. For example, the user Figure 3 uses the reference signal of the SDC file 41A with the possibility of RW adventure Figure 4 to execute the logic simulation verification system 1 with the cell description example of the library. Moreover, the user refers to the analysis result of this execution, that is, the message regarding the possibility of RW adventure.

[0099] Specifically, the analysis result of this logic simulation verification system 1 Figure 4 warns the library that for Figure 3 the reference signal shown and the change of the reference signal, there is a possibility that the first signal of circuit B1 in the library shown by Figure 4 that is, variable A changes at the first moment (here, the first moment is the group of moments when the moment is divided by 10 and the remainder is 0). Similarly, the analysis result Figure 4 warns the library that for Figure 3 the reference signal shown and the change of the reference signal, there is a possibility that the first signal of circuit B2 in the library shown by Figure 4 that is, variable COND changes at the first moment (here, the first moment is the group of moments when the moment is divided by 10 and the remainder is 0).

[0100] Moreover, the analysis result Figure 4 warns the library that for Figure 3 the reference signal shown and the change of the reference signal, there is a possibility that the second signal of circuit B1 in the library shown by Figure 4 that is, variable COND is referenced at the second moment (here, the second moment is the group of moments when the moment is divided by 10 and the remainder is 0). Similarly, the analysis result Figure 4 warns the library that for Figure 3 the reference signal shown and the change of the reference signal, there is a possibility that the second signal of circuit B2 in the library shown by Figure 4 that is, variable A is referenced at the second moment (here, the second moment is the group of moments when the moment is divided by 10 and the remainder is 0).

[0101] As described above, since there is a possibility that the reference signal refers to (reads) the second signal and changes (writes) the first signal between different circuits at the same timing (the same time as the first time and the second time), the parsing result sends a message that a signal competition state has occurred.

[0102] The user refers to the message related to the parsing result where there is a possibility of RW hazard. As Figure 8 shown, since there is a possibility of RW hazard in circuit B1 and circuit B2, the description substituting LineC, that is, "A = 1'b1;" is corrected to "A <= #1 1'b1;". Similarly, the user corrects the description substituting LineG, that is, "COND = 1'b1;" to "COND <= #1 1'b1;". "A <= #1 1'b1;" is a sentence that delays the time when substituting 1 into A by 1. For example, # is a symbol representing the delayed time.

[0103] That is, when substituting into a variable as the first signal, by delaying the time by 1, the first time when the first signal changes is the group of times where the remainder when dividing the time by 10 is 1. In addition, the second time when the second signal is referred to is the group of times where the remainder when dividing the time by 10 is 0. Therefore, since the first time and the second time do not match, it is determined that there is no possibility of a signal competition state between different circuits.

[0104] As described above, the logic simulation verification system 1 can avoid the signal competition state for the reference signal and the change of the reference signal through the logic simulation verification system method. In addition, the logic simulation verification system 1 can reduce the execution of the memory in a short time by statically parsing without using the logic simulator 22. And by manipulating the time when substituting into a variable and the time when the variable is referred to for the reference signal and the change of the reference signal, the delay time can be manipulated.

[0105] By the logic simulation verification system 1 performing logic simulation using the input information data 42B including the corrected library, circuit description, and test bench, the logic simulator 22 can obtain the simulation result 44 without a signal competition state.

[0106]

Second Embodiment

[0107] Figure 9 This is a description example expressing the reference signals of specific multiple frequencies stored in the timing information storage unit 41 related to the second embodiment in SDC. The logic simulation verification system 1 related to the second embodiment is an example of verifying the library for reference signals of multiple frequencies.

[0108] The logic simulation verification system 1 according to the second embodiment stores a description example of reference signals of multiple frequencies shown in Figure 9 in the timing information storage unit 41.

[0109] That is, for example, in the case where the reference signals of multiple frequencies shown in Figure 4 are the description examples of the library shown in Figure 9 the change possibility time calculation unit 212 of the logic simulation verification system 1 according to the second embodiment calculates, in Figure 7 step S12 shown in Figure 9 the first moment when there is a possibility that the first signal changes until the moment of the least common multiple for the reference signals of multiple frequencies. Specifically,

[0110] the clock period of the signal of one reference signal CLK1 shown in is 15 ns, and the clock period of the signal of the other reference signal CLK2 is 20 ns.

[0110] That is, the least common multiple of CLK1 and CLK2 is 60. At the moments until this least common multiple 60, there may be a signal competition state at 0, 15, 20, 30, 40, 45.

[0111] In Figure 4 the case of the library shown in Figure 4 for the first moment of the variable A for circuit B1, the remainders when the moments of the reference signal CLK1 are divided by 60 are 0, 15, 30, 45. In addition, for the reference moment of the variable COND for circuit B2, the remainders when the moments of the first signal CLK2 are divided by 60 are 0, 20, 40. In step S13, the reference possibility time calculation unit 213 is referred to calculate the second moment when there is a possibility that the second signal is referred to until the moment of the least common multiple for the reference signal.

[0112] That is, for the second moment of the variable COND for circuit B1, the remainders when the moments of the reference signal CLK1 are divided by 60 are 0, 15, 30, 45. In addition, for the second moment of the variable A for circuit B2, the remainders when the moments of the reference signal CLK2 are divided by 60 are 0, 20, 40.

[0113] In step S18, when the remainder is 0 when the moment of the reference signal is divided by 60 between different circuits B1 and B2, since there is a possibility that the first signal changes simultaneously, and there is a possibility that the second signal is referred to simultaneously, it is determined that a signal competition state occurs for the change of the reference signal.

[0114] Other configurations, the logic simulation verification system verification method, and the effects are the same as those of the Figures 1 to 8 first embodiment shown in

[0115]

Third Embodiment

[0116] Figure 10 This is a description example in SDC that the change timing of the reference signal having no period is not present in the example of the unit of the library to be specifically checked stored in the timing information storage unit 41 according to the third embodiment. As Figure 10 shown, in the logic simulation verification system 1 according to the third embodiment, the power supply is turned on at time 100 for the reference signals CLK1 and CLK2.

[0117] The logic simulation verification system 1 according to the third embodiment stores the description example in SDC that Figure 10 shows the change timing of the reference signal having no period in the timing information storage unit 41.

[0118] That is, for example, in the change possibility time calculation unit 212 of the logic simulation verification system 1 according to the third embodiment, for Figure 4 the description example of the library shown, when it is Figure 10 the reference signal having no period shown, in Figure 7 step S12 shown, when the reference signal CLK1 is at time 100, the first time when there is a possibility that the variable A, which is the first signal of the circuit B1, changes is calculated. Similarly, when the reference signal CLK2 is at time 100, the first time when there is a possibility that the variable COND, which is the first signal of the circuit B2, changes is calculated.

[0119] In step S13, when the reference signal CLK1 is at time 100, the second time when there is a possibility that the variable COND, which is the second signal of the circuit B1, is referred to is calculated with reference to the possibility time calculation unit 213. Similarly, when the reference signal CLK2 is at time 100, the second time when there is a possibility that the variable A, which is the second signal of the circuit B2, is referred to is calculated.

[0120] In step S18, since there is a possibility that the first signals change simultaneously and there is a possibility that the second signals are referred to simultaneously between different circuits B1 and B2 when the reference signal is at time 100, it is determined that a signal competition state occurs for the change of the reference signal. Other configurations, the logic simulation verification system verification method, and the effects are the same as those of the Figures 1 to 8 first embodiment shown.

[0121]

Fourth Embodiment

[0122] Figure 11This is a description example that represents the change timing of the reference signal using SDC for the specific test bench to be checked stored in the timing information storage unit 41 related to the fourth embodiment.

[0123] Figure 12 This is a description example of a test bench in which the time of change possibility and the time of reference possibility change due to "@" and "wait" in the specific begin - end circuit module stored in the input information data storage unit 42 related to the fourth embodiment.

[0124] As Figure 11 and Figure 12 show, the object of the logic simulation verification system 1 related to the fourth embodiment is an example where the first moment and the second moment change when "@" and "wait" are included in the description of the test bench for the axm.CLK as the reference signal.

[0125] The logic simulation verification system 1 related to the fourth embodiment stores the SDC file 41A of the description example that represents the change timing of the reference signal using SDC in the timing information storage unit 41. In addition, it stores the input information data 42A of the test bench shown in Figure 11 in the input information data storage unit 42. Figure 12 shown in

[0126] Figure 11 This is information on the change timing of the reference signal, that is, the clock period of the signal, the node name of the signal to be input, and the input delay information of the input pin for the clock. The following line specifies that the change timing of axm.Ready is delayed by 2 (for example, when the remainder of dividing the time of the reference signal by 100 is 2).

[0127] As Figure 12 shown, axm.CLK as the reference signal rises when the remainder of dividing the time of axm.CLK by 100 is 0 (LineC). Next, the signal is delayed by the substitution statement (LineD). When the remainder of dividing the time of axm.CLK by 100 is 1, Axm.ADDR is substituted with addr (LineE). If axm.READY is 1 at the same moment, it proceeds to the next line. Wait until Axm.READY changes from 0 to 1, and proceed to the next line at the moment when the remainder of dividing by 100 is 2 (LineG). Next, the signal is delayed by the substitution statement (LineH). Axm.DATA is substituted with data when the remainder of dividing the time of axm.CLK by 100 is 2 or 3 (LineK).

[0128] When using Figure 11 and Figure 12When the input information data is subjected to logical simulation verification by the system and parsed, in Figure 7 In step S12 shown in FIG., the change possibility time calculation unit 212 calculates the first time when there is a possibility that axm.ADDR, which is the first signal, changes with respect to the change of axm.CLK as the reference signal. In addition, the change possibility time calculation unit 212 calculates the first time when there is a possibility that axm.DATA, which is the first signal, changes.

[0129] That is, when the remainder obtained by dividing the time of axm.CLK by 100 is 1, there is a possibility that axm.ADDR, which is the first signal, changes. In addition, when the remainder obtained by dividing the time of axm.CLK by 100 is 2 or 3, there is a possibility that axm.DATA, which is the first signal, changes.

[0130] In step S13, the reference possibility time calculation unit 213 calculates the second time when there is a possibility that axm.READY, which is the second signal, is referenced with respect to the change of axm.CLK as the reference signal.

[0131] That is, when the remainder obtained by dividing the time of axm.CLK by 100 is 1, if the value of axm.READY is 1, axm.READY, which is the second signal, advances to the next line at the same time. In addition, when the remainder obtained by dividing the time of axm.CLK by 100 is 1, if the value of axm.READY is 0, axm.READY, which is the second signal, stops. When the remainder obtained by dividing the time of CLK by 100 is 2, there is a possibility that the value of axm.READY becomes 1, and at this time, it advances to the next line.

[0132] In step S18, when the remainder obtained by dividing the time of the reference signal by 100 is 2, there is a possibility that axm.READY changes. When the remainder obtained by dividing the time of the reference signal by 100 is 1, there is a possibility that axm.READY is referenced as the second signal. Therefore, it is determined that there is no signal competition state for axm.READY. Other configurations, the logical simulation verification system verification method, and the effects are the same as those of the Figures 1 to 8 first embodiment shown in FIG.

[0133]

Fifth Embodiment

[0134] Figure 13This is a description example that expresses the change timing of the reference signal for the test platform to be specifically checked stored in the timing information storage unit 41 according to the fifth embodiment using SDC. The following line designates the timing delay of 1 for the change of axm.Ready (for example, when the remainder obtained by dividing the time of the reference signal by 100 is 1).

[0135] As Figure 11 and Figure 13 such, the object of the logic simulation verification system 1 according to the fifth embodiment is an example where the first and second moments change when “@” and “wait” are included in the description of the test platform for axm.CLK as the reference signal.

[0136] The logic simulation verification system 1 according to the fifth embodiment stores the SDC file 41A with the description example expressing the change timing of the reference signal shown in Figure 13 in the timing information storage unit 41. In addition, the input information data 42A of the test platform including that shown in Figure 12 is stored in the input information data storage unit 42.

[0137] The logic simulation verification system 1 according to the fifth embodiment, as shown in Figure 13 changes the input delay information of the input pin of the clock for the description example expressed by SDC of the information as the reference signal from 2 to 1.

[0138] When performing the logic simulation verification system using the input information data of Figure 13 and Figure 12 and performing analysis, in step S12 shown in Figure 7 the change possibility time calculation unit 212 calculates the first moment when there is a possibility of change of axm.ADDR as the first signal for the change of axm.CLK as the reference signal. In addition, the change possibility time calculation unit 212 calculates the first moment when there is a possibility of change of axm.DATA as the second signal. And the change possibility time calculation unit 212 calculates the first moment when there is a possibility of change of axm.READY as the second signal.

[0139] That is, when the remainder obtained by dividing the time of axm.CLK by 100 is 1, there is a possibility of change of axm.ADDR as the first signal. In addition, when the remainder obtained by dividing the time of axm.CLK by 100 is 2, there is a possibility of change of axm.DATA as the first signal. And for axm.READY, when the remainder obtained by dividing the time of axm.CLK by 100 is 1, there is a possibility of change of axm.READY as the second signal.

[0140] In step S13, the reference possibility time calculation unit 213 calculates a second time at which there is a possibility that axm.READY as a second signal is referenced in response to a change in axm.CLK as a reference signal.

[0141] That is, for axm.READY as a second signal, when the remainder obtained by dividing the time of axm.CLK by 100 is 1, there is a possibility that the value of axm.READY is referenced.

[0142] In step S18, when the remainder obtained by dividing the time of the reference signal by 100 is 1, since there is a possibility that the first signal changes and there is a possibility that the second signal is referenced, it is determined that a signal competition state occurs in response to the change in the reference signal. Other configurations, the logic simulation verification system verification method, and the effects are the same as those of the Figures 1 to 8 first embodiment shown.

[0143]

Sixth Embodiment

[0144] Figure 14 is a block diagram when verifying whether the constraint conditions given by SDC are complied with by logic simulation by the logic simulation verification system 1 according to the sixth embodiment.

[0145] As Figure 14 shown, the SDC file 41B can give timing constraints of a reference signal by SDC. In view of this, the logic simulation verification unit 21 of the logic simulation verification system 1 according to the sixth embodiment may include a transformation program 21A that reads the SDC file 41B given the timing restrictions expressed in SDC and outputs a Verilog description for outputting a VCD (Value Change Dump) file of the signals described in SDC.

[0146] The Verilog description for outputting the VCD file 45 of the signals described in SDC is referred to as 41C. Among them, the VCD file 45 is a file in the standard waveform format of Verilog-HDL. This VCD file is a text file that describes the changes in the waveforms specified by the language.

[0147] The logic simulator 22 uses the Verilog description 41C for sending the signals of the SDC file to the VCD, the input information data 42A including the library, the circuit description, and the test bench as input information data, and executes it to output the VCD file 45.

[0148] The logic simulation verification unit 21 of the logic simulation verification system 1 according to the sixth embodiment may include a program 21B that compares an SDC file 41B given timing constraints expressed in SDC with a VCD file 45 to check whether the timing constraints of the SDC are complied with.

[0149] In addition, the program 21B for checking whether the timing constraints of the SDC are complied with may also output the comparison result, for example, as OK or NG to an output file 46. Other configurations, the logic simulation verification system verification method, and the effects are the same as those of the Figures 1 to 8 first embodiment shown.

[0150] (Other embodiments)

[0151] In addition to the data described by Verilog-HDL, the above embodiments may also be performed by data described in other hardware description languages.

[0152] The format of the timing constraints in the above embodiments is based on SDC (Synopsys Design Constraint Format), but it may also be performed in other formats.

[0153] Although several embodiments of the present invention have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and their equivalents.

[0154] For example, in other embodiments, the circuit description of the circuit description file may also be described in units of logic cones.

Claims

1. A logic simulation verification system verifies, within a first data described in HDL language, the change of a first signal in response to the change of a reference signal and the possibility of a second signal being referenced. It is characterized in that Comprising: A change timing specifying unit that specifies the reference signal and the change information of the reference signal; A change possibility time calculation unit that obtains a first time at which there is a possibility that the first signal changes with respect to the change of the reference signal and the reference signal; A reference possibility time calculation unit that obtains a second time at which there is a possibility that the second signal is referenced with respect to the change of the reference signal and the reference signal; A change possibility time determination unit that determines whether the first signals between different circuits are the same, and compares and determines whether the first times between different circuits are consistent; And A change and reference possibility time determination unit that determines whether the first signal on one side and the second signal on the other side between different circuits are the same, and whether the first time and the second time are consistent.

2. The logic simulation verification system according to claim 1, wherein When the first signals between different circuits are the same and the first times are consistent, the change possibility time determination unit records the possibility of occurrence of a hazard in the first data.

3. The logic simulation verification system according to claim 1, wherein When the first signal on one side and the second signal on the other side between different circuits are the same and the first time and the second time are consistent, the reference possibility time determination unit records the possibility of occurrence of a hazard in the first data.

4. The logic simulation verification system according to claim 1, wherein In the case where there are a plurality of cycles of change of the reference signal, the change possibility time calculation unit obtains the least common multiple of the plurality of cycles of change of the reference signal, and calculates the first time for the time from the initial value of the reference signal to the least common multiple, The reference possibility time calculation unit calculates the second time for the time from the initial value of the reference signal to the least common multiple.

5. The logic simulation verification system according to claim 1, wherein In the case where the reference signal does not have a cycle, the change timing specifying unit can assume a state in which the first signal and the second signal change simultaneously based on the reference signal, thereby confirming the competition state of the signals in the powered-on state.

6. The logic simulation verification system according to claim 1, wherein The change timing specifying unit confirms whether the reference signal and the change information of the reference signal specified by the specified timing constraint conditions and the result information obtained by performing logic simulation according to the reference signal and the change information of the reference signal specified by the specified conditions are correct in the logic simulation.

7. A logic simulation verification method for verifying the possibility of change of a first signal and reference of a second signal with respect to a reference signal and a change of the reference signal in a first data described in HDL language, characterized in that Specify the reference signal and the change information of the reference signal based on the information stored in the timing information storage unit of the storage medium. Based on the information stored in the input information data storage unit of the storage medium, find the first time when there is a possibility that the first signal changes with respect to the reference signal and the change of the reference signal. Based on the information stored in the input information data storage unit of the storage medium, find the second time when there is a possibility that the second signal is referenced with respect to the reference signal that becomes the change reference and the change of the reference signal. Judge whether the first signals between different circuits are the same and whether the first times are the same, and output the judgment result to the message storage unit. Judge whether the first signal of one of the different circuits is the same as the second signal of the other, and whether the first time is consistent with the second time, and output the judgment result to the message storage unit.

8. A recording medium that records a program, which is a program for a computer used in a logic simulation verification system, characterized in that The program is used to verify the possibility that the first signal changes and the second signal is referenced with respect to the reference signal and the change of the reference signal by causing the computer to execute the following processing: Specify the reference signal and the change information of the reference signal based on the information stored in the timing information storage unit of the storage medium. Based on the information stored in the input information data storage unit storing the first data described in HDL language, find the first time when there is a possibility that the first signal changes with respect to the reference signal and the change of the reference signal. Based on the information of the input information data storage unit, find the second time when there is a possibility that the second signal is referenced with respect to the reference signal and the change of the reference signal. Judge whether the first signals between different circuits are the same, compare the first times and judge whether the first times are consistent, and output the judgment result to the message storage unit through a message. Judge whether the first signal of one of the different circuits is the same as the second signal of the other, and whether the first time is consistent with the second time, and output the judgment result to the message storage unit through a message.

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