A method, system, and readable storage medium for generating a connectivity test file

Abstract

The application discloses a method, system and readable storage medium for generating a connectivity test file, and the method comprises the following steps: creating a hierarchical configuration file, a special interface description file and a special signal relationship description file; obtaining a configuration file of a chip to be verified, parsing input and output interface information of each test module and associated modules in the configuration file based on the hierarchical configuration file to generate input and output interface files of the test module and input and output interface files of the associated modules respectively; obtaining the input interface file of the test module, and searching for output signals matched with input signals in the input interface file in the output interface files of the associated modules in sequence; forming a connection relationship group by matching the output signals with the input signals, and outputting the connection relationship group to the connectivity test file; and updating the connection relationship group of the connectivity test file based on the special signal relationship description file to obtain a final connectivity test file. The application shortens the chip verification time.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a method, system and readable storage medium for generating a connectivity test file. BACKGROUND

[0002] With the rapid development of large-scale integrated circuit system design, the integrated circuit scale is larger and larger, the chip complexity is increasingly complex, and the project progress pressure always exists, so how to quickly find and solve problems in the early stage of the project is crucial to eliminate problems in the middle and later stages of the project execution.

[0003] At present, a large-scale chip design includes multiple modules, multiple subsystems and multiple systems, and there is a coupling of functions and connections between each module and system. For such a large-scale chip with multiple modules and multiple systems, the following problems exist in the early stage of design and verification: 1. The interface definition and interface timing of the design personnel of each module, subsystem and system are not completely aligned; 2. In higher level integration, the integration personnel may not have a good understanding of the width, properties and connectivity of all interface signals; 3. Finally, for the verification personnel, a large amount of manpower and time is consumed to solve the connection and related problems in the early stage of the project, and even some interface connectivity and functionality are not completely verified when collecting code coverage in the later stage of the project.

[0004] In the face of increasingly updated verification technology, as the first firewall for chip function verification, the verification personnel must ensure the correctness of the internal connection of the module, the connection between the modules, and the integration connection of the subsystem and the system, so as to lay a foundation for subsequent verification work. At present, the problems encountered in the connectivity test verification are as follows: in the early stage of verification, firstly, for a complex SoC (System on a Chip) chip, there are thousands of interface signals, and the design personnel cannot provide correct input and output and interface signal connection and timing document; the development of connectivity test cases requires a large amount of time, and the multi-bit or timing required signals cannot be traversed; the connectivity test needs to be redefined at a higher level, and if the verification does not follow up with the subsequent design update, it will cause the omission of the verification point. SUMMARY

[0005] Therefore, the present application provides a method, system and readable storage medium for generating a connectivity test file, which automatically generates a connectivity test file based on a hierarchical structure configuration file, a special interface specification file and a special signal relationship specification file, solves the connectivity error problem caused by non-standard design coding resulting in non-uniform interfaces, and solves the problems of long development time of traditional test cases and long positioning time of chip connectivity errors.

[0006] To achieve the above objectives, one aspect of the present invention provides a method for generating a connectivity test file, specifically including the following steps:

[0007] Create hierarchical configuration files, special interface specification files, and special signal relationship specification files;

[0008] Obtain the configuration file of the chip to be verified, and parse the input and output interface information of each module to be tested and related modules in the configuration file based on the hierarchical configuration file to generate the input and output interface files of the module to be tested and the input and output interface files of the related modules respectively.

[0009] Obtain the input interface file of the module to be tested, and sequentially search the output interface files of the associated modules for output signals that match the input signals in the input interface file;

[0010] The output signals in the matching output interface file and the input signals in the input interface file are combined to form a connection relationship group, which is then output to the connectivity test file.

[0011] The connection relationship group of the connectivity test file is updated based on the special signal relationship description document to obtain the final connectivity test file.

[0012] In some implementations, the method further includes:

[0013] If no output signal matching the input signal in the input interface file is found in the output interface file, then based on the special interface specification file and the mismatched input signal, an output signal that is connected to the mismatched input signal is searched in the output interface file.

[0014] The steps are as follows: output the mismatched input signal and the connected output signal to the connectivity test file, and return to the step of updating the connectivity test file based on the special interface specification file.

[0015] In some implementations, the method further includes:

[0016] If no output signal connected to the mismatched input signal is found in the output interface file, the mismatched input signal and the module containing the mismatched input signal are output to the error file.

[0017] In some implementations, updating the connectivity test file's connectivity relationship group based on the specific signal relationship specification document to obtain the final connectivity test file includes:

[0018] Based on the connectivity test function in the special signal relationship specification file, each connectivity group in the connectivity test file is updated to obtain the final connectivity test file.

[0019] In some implementations, updating the various connection relationship groups in the connectivity test file to obtain the final connectivity test file according to the connectivity test function in the specific signal relationship specification file includes:

[0020] Obtain the parameter length and special characters of the connection relationship group, and based on the parameter length and special characters, call the corresponding connectivity test function to update the connection relationship group.

[0021] In some implementations, parsing the input and output interface information of each module to be tested and associated modules in the hierarchical configuration file to generate input and output interface files for the module to be tested and the associated modules respectively includes:

[0022] Based on the hierarchical configuration file, the path information of each module to be tested and the associated module of the chip to be verified is extracted from the configuration file;

[0023] Based on the path information, extract the interface information of the module to be tested and the interface information of the associated module;

[0024] The interface information of the module under test and the interface information of the associated modules are analyzed to generate input and output interface files for each module under test and the associated modules of the chip to be verified.

[0025] In some implementations, the hierarchical configuration file includes: information about the module to be tested, information about associated modules, and information about the output file;

[0026] The special interface specification document includes: interface information of the mismatched module under test and interface information of related modules that are connected to the interface information of the mismatched module under test.

[0027] In some implementations, after outputting the connection group to a connectivity test file, the method further includes:

[0028] Obtain the output interface file of the module to be tested, and sequentially search the input interface files of the associated modules for associated input signals that match the output signal to be tested in the output interface file;

[0029] The matched associated input signal and the output signal under test are combined to form a connection relationship group, which is then output to the connectivity test file.

[0030] Another aspect of this invention provides a system for generating connectivity test files, comprising:

[0031] A creation module is configured to create a hierarchical structure configuration file, a special interface specification file, and a special signal relationship specification file.

[0032] The parsing module is configured to obtain the configuration file of the chip to be verified, and based on the hierarchical configuration file, parse the input and output interface information of each module to be tested and related modules in the configuration file to generate input and output interface files of the module to be tested and the input and output interface files of the related modules respectively.

[0033] The search module is configured to obtain the input interface file of the module to be tested, and sequentially search the output interface file of the associated module for an output signal that matches the input signal in the input interface file;

[0034] The search module is also configured to form a connection relationship group by matching the output signals in the output interface file and the input signals in the input interface file, and output it to the connectivity test file;

[0035] An update module is configured to update the connection relationship group of the connectivity test file based on the special signal relationship description file to obtain the final connectivity test file.

[0036] In another aspect, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method steps.

[0037] The present invention has at least the following beneficial technical effects: it automatically generates connectivity test files based on hierarchical configuration files, special interface description files, and special signal relationship description files, which shortens the time for chip verification development and design of test cases, shortens the chip verification time, and improves chip verification efficiency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0039] Figure 1 A block diagram illustrating an embodiment of the method for generating connectivity test files provided by the present invention;

[0040] Figure 2 A schematic diagram of an embodiment of the system for generating connectivity test files provided by the present invention;

[0041] Figure 3 This is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0043] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0044] Based on the above objectives, a first aspect of the present invention provides an embodiment of a method for generating connectivity test files. For example... Figure 1 As shown, it includes the following steps:

[0045] Step S101: Create a hierarchical configuration file, a special interface specification file, and a special signal relationship specification file;

[0046] Step S103: Obtain the configuration file of the chip to be verified, and parse the input and output interface information of each module to be tested and related modules in the configuration file based on the hierarchical configuration file to generate the input and output interface files of the module to be tested and the input and output interface files of the related modules respectively.

[0047] Step S105: Obtain the input interface file of the module to be tested, and sequentially search the output interface files of the associated modules for output signals that match the input signals in the input interface file;

[0048] Step S107: Combine the output signals in the matching output interface file with the input signals in the input interface file to form a connection relationship group, and output it to the connectivity test file;

[0049] Step S109: Update the connection relationship group of the connectivity test file based on the special signal relationship description file to obtain the final connectivity test file.

[0050] The hierarchical configuration file specifies the module to be tested, its hierarchical structure, and the associated modules and their hierarchical structures within the system or subsystem. The special interface specification file specifies interfaces not defined according to code naming rules or interfaces with special input / output requirements. Parsing this file reveals the connection relationships of incompletely matching interfaces and generates a connectivity test file. The special signal relationship specification file provides special explanations for interfaces with inversion, timing relationships, or delay relationships between signals. Updating the corresponding interface signal relationship groups in the connectivity test file using this file yields the final connectivity test file.

[0051] The path information of the module to be tested and related modules is extracted from the configuration file of the chip to be verified, and the interfaces of these modules are analyzed to generate input and output interface files for each module, which facilitates subsequent connectivity matching.

[0052] Since the input signal of the module under test is the output signal of the associated module, and the output signal of the module under test is the input signal of the associated module, in order to verify the connectivity of the input and output signals of the module under test, it is necessary to generate separate connectivity test files for the input interface and the output interface of the module under test. The generation methods for the connectivity test files of the two interfaces are the same. This embodiment describes the generation of connectivity test files for the input interface of the module under test.

[0053] Import the input file of the module under test, and search for output signals in the output files of related modules in turn. If the signal name of the output signal exactly matches the signal name of the input signal, output the connection relationship to the connectivity test file or the review file; if no matching output signal is found in any of the output interface files of all related modules, parse the input signal of the module under test for which no matching output signal is found according to the special interface specification file, that is, search the special interface specification file for whether there is an output signal connected to the input signal.

[0054] According to the special signal relationship specification document, the connection relationship groups in the current connectivity test file are replaced accordingly. That is, the signals described in the document are replaced with tasks or functions with special requirements. For example, if the signal sig_a of module A (the module under test) and the signal sig_b of module B (the associated module of the module under test) are directly connected and inverted, then according to the special signal relationship specification document, the following replacement is made: replace cc_check(hier_a.sig_a, hier_b.sig_b) with cc_check(hier_a.sig_a, hier_b.sig_b, reversal).

[0055] In this embodiment, basic signal mismatches and connection problems can be directly detected during the generation of connectivity test files. When the design document is complete, the design document can be automatically extracted from the design document. When the design document is incomplete, signals with connection relationships can be automatically matched and output to the connectivity test file.

[0056] This embodiment enables the automatic generation of connectivity test files based on hierarchical configuration files, special interface description files, and special signal relationship description files. This reduces the time spent developing test cases in traditional chip verification processes, reduces the time spent locating signal connection errors, and minimizes the risk of verification vulnerabilities caused by interface changes during later stages of chip design updates. This shortens chip verification time and improves the reliability of chip verification.

[0057] In some implementations, the method further includes:

[0058] If no output signal matching the input signal in the input interface file is found in the output interface file, then based on the special interface specification file and the mismatched input signal, an output signal that is connected to the mismatched input signal is searched in the output interface file.

[0059] The steps are as follows: output the mismatched input signal and the connected output signal to the connectivity test file, and return to the step of updating the connectivity test file based on the special interface specification file.

[0060] Specifically, the input file of the module under test is imported, and the output signal is searched sequentially in the output files of the associated modules. If no matching output signal is found in any of the output interface files of all associated modules, the input signal of the module under test for which no matching output signal is found is parsed according to the special interface specification file, that is, the special interface specification file is searched for whether there is an output signal that is connected to the input signal.

[0061] If the special interface specification document contains an output signal that is connected to the input signal, then the input signal and the output signal that is connected to it will be combined into a connection relationship group and output to the connectivity test document.

[0062] In some implementations, the method further includes:

[0063] If no output signal connected to the mismatched input signal is found in the output interface file, the mismatched input signal and the module containing the mismatched input signal are output to the error file.

[0064] Specifically, the special interface specification file is searched for an output signal that is connected to the input signal. If no output signal is found in the special interface specification file, the signal is output to an error file for later verification and design self-checking.

[0065] The definition and format of error files are as follows:

[0066]

[0067] Error files are used to store information about issues such as unconnected signals and mismatched signal widths in the module under test.

[0068] For example, if module A contains 100 input signals, then theoretically there should be 100 output signals associated with these 100 input signals. After parsing module A's configuration file through a hierarchical configuration file to obtain module A's input and output interface files and the input and output interface files of each associated module, 90 output signals matching module A's input signals are found in all the associated module's output interface files. These 90 matching input and output signals are then grouped into a connection relationship group and output to the connectivity test file. However, 10 input signals of module A still lack matching output signals. The special interface specification file is then searched for output signals connected to these 10 input signals. If 8 input signals find a connected output signal, and 2 input signals do not find a corresponding output signal, the connection relationship group consisting of the 8 input signals and the connected output signal is output to the connectivity test file, and the 2 input signals are output to the error file. At this point, the connectivity test file contains 98 input signals. The special signal relationship specification file is used to update the corresponding input signals in the connectivity test file, resulting in the final connectivity test file.

[0069] In some implementations, updating the connectivity test file's connectivity relationship group based on the specific signal relationship specification document to obtain the final connectivity test file includes:

[0070] Based on the connectivity test function in the special signal relationship specification file, each connectivity group in the connectivity test file is updated to obtain the final connectivity test file.

[0071] In some implementations, updating the various connection relationship groups in the connectivity test file to obtain the final connectivity test file according to the connectivity test function in the specific signal relationship specification file includes:

[0072] Obtain the parameter length and special characters of the connection relationship group, and based on the parameter length and special characters, call the corresponding connectivity test function to update the connection relationship group.

[0073] According to various embodiments of the present invention, the special signal relationship specification document contains multiple connectivity test functions, and the connectivity test functions are encapsulated.

[0074] Below are some predefined basic connectivity test functions. Some indicate direct connection between input and output signals; some indicate inverted input and output signals; some indicate clock synchronization between input and output signals; some indicate clock synchronization and inversion between input and output signals; some indicate a delay between input and output signals; and some indicate a delay and inversion between input and output signals, etc. The interface signals of the connectivity functions are all single-bit. Each function checks the 0 and 1 values. These functions are extensible and can be extended to the detection of some combinational logic, such as performing AND, OR, and NOT operations on two signals and then outputting the result to a certain module.

[0075] cc_direct(src,dst);

[0076] cc_reversal_chk(src,dst,cmd);

[0077] cc_with_clock(src,dst,clock,cnt);

[0078] cc_reversal_with_clok(src,dst,clock,cnt,cmd);

[0079] cc_with_delay(src,dst,scale,cnt);

[0080] cc_reversal_with_delay(src,dst,scale,cnt,cmd).

[0081] The predefined connectivity test function is encapsulated in the following format:

[0082]

[0083] The special signal relationship description file determines the corresponding connectivity test function by judging the number of parameters and special characters. Specifically, it obtains the parameter length and special characters of the connection relationship group in the connectivity test file, and based on the parameter length and special characters, calls the corresponding connectivity test function to update the connection relationship group to obtain the final connectivity test file.

[0084] The connectivity test file can be implemented using the Tcl language. The basic functions and wrapper functions mentioned in the above embodiments can be stored in agent_tcl.do, and the connectivity test file can be stored in user_tcl.do. The .do file to be executed in the test cases is specified, and then executed by another automated software. During the test case execution phase, connection errors between signals and basic logical errors can be checked. When there are logical or timing relationships between multiple signals, SVA can be used for further checks.

[0085] The definition and format of the connectivity test file are as follows:

[0086]

[0087] Furthermore, the method further includes generating a signal connection text (CSV) file based on the final connectivity test file, as shown in Table 1. In Table 1, the first row contains labels, which are the module name of the module containing the source signal, the signal name of the source signal, the module name of the module containing the target signal, the signal name of the target signal, and the connection relationship, respectively. Each column contains the content corresponding to the label.

[0088] Table 1

[0089]

[0090] In this embodiment of the invention, during the script execution phase, by parsing and filtering multiple input files, mismatches and connection problems of some signals can be detected based on the generated error file. During the test case execution phase, based on the generated connectivity test file and error file, connectivity testing is performed. The connectivity test file can be updated according to changes in the extracted files without recompiling. After execution, post-processing can be performed to output the connectivity test file to a CSV file.

[0091] The embodiments of this invention can extract interfaces from the script files of various modules, subsystems, and systems of the chip to be verified. Connectivity test files can be automatically generated for verification at different levels of the chip. When the verification environment is incomplete, connectivity test files and error files can be automatically generated by extracting configuration files. Based on the error files, interfaces with connection errors are automatically output, revealing connectivity issues from the early design stages. When the verification environment is complete, logical connection problems are discovered through the automatically generated connectivity test files and error files, significantly reducing time and manpower consumption. In the later stages, when the design documents are complete, the connection files can be directly extracted from the design documents, ensuring consistency between design and verification. The connectivity test files can serve as test cases for chip verification. When running test cases, the connectivity test files can be automatically updated based on the latest chip design documents, avoiding asynchrony between design and verification and reducing the risk of verification vulnerabilities caused by interface changes during later-stage chip design updates.

[0092] In some implementations, parsing the input and output interface information of each module to be tested and associated modules in the hierarchical configuration file to generate input and output interface files for the module to be tested and the associated modules respectively includes:

[0093] Based on the hierarchical configuration file, the path information of each module to be tested and the associated module of the chip to be verified is extracted from the configuration file;

[0094] Based on the path information, extract the interface information of the module to be tested and the interface information of the associated module;

[0095] The interface information of the module under test and the interface information of the associated modules are analyzed to generate input and output interface files for each module under test and the associated modules of the chip to be verified.

[0096] In some implementations, the hierarchical configuration file includes: information about the module to be tested, information about associated modules, and information about the output file;

[0097] The special interface specification document includes: interface information of the mismatched module under test and interface information of related modules that are connected to the interface information of the mismatched module under test.

[0098] The hierarchical configuration file includes: the name of the module to be tested or the name of the associated module, for example, 'name'; the hierarchical structure of the module to be tested and associated modules, for example, 'hier'; the file names and paths of the module to be tested and related modules, for example, 'path'; and the location and format of the output file, for example, 'output'.

[0099] The definition and format of the hierarchical configuration file are as follows:

[0100]

[0101] The special interface specification document includes: the signal name of the mismatched signal (source signal) and the module name of the module under test;

[0102] The signal name of the connection signal (target signal) and the module name of the associated module. The definition and format of the special interface specification document are as follows:

[0103]

[0104] Special signal relationship documentation is mainly for input / output interfaces that are not directly connected, have a certain logical relationship, or have been processed in the external logic, such as input and output signals being inverted, signals having a delay between them, or signals that directly require clock signal synchronization.

[0105] The special signal relationship specification document is also extensible. When multiple signals have logical or timing relationships, they can be checked using the SVA method.

[0106] The definition and format of the special signal relationship specification document are as follows:

[0107]

[0108] In some implementations, after outputting the connection group to a connectivity test file, the method further includes:

[0109] Obtain the output interface file of the module to be tested, and sequentially search the input interface files of the associated modules for associated input signals that match the output signal to be tested in the output interface file;

[0110] The matched associated input signal and the output signal under test are combined to form a connection relationship group, which is then output to the connectivity test file.

[0111] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 2 As shown, embodiments of the present invention also provide a system for generating connectivity test files, comprising:

[0112] A creation module 110 is configured to create a hierarchical structure configuration file, a special interface specification file, and a special signal relationship specification file.

[0113] The parsing module 120 is configured to obtain the configuration file of the chip to be verified, and parse the input and output interface information of each module to be tested and associated modules in the configuration file based on the hierarchical configuration file to generate input and output interface files of the module to be tested and the input and output interface files of the associated modules respectively.

[0114] Search module 130 is configured to acquire the input interface file of the module to be tested, and sequentially search the output interface file of the associated module for an output signal that matches the input signal in the input interface file;

[0115] The search module 130 is further configured to form a connection relationship group by matching the output signals in the output interface file and the input signals in the input interface file, and output it to the connectivity test file;

[0116] Update module 140 is configured to update the connection relationship group of the connectivity test file based on the special signal relationship description file to obtain the final connectivity test file.

[0117] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 3 As shown, embodiments of the present invention also provide a computer-readable storage medium 40, which stores a computer program 410 that, when executed by a processor, performs the methods described above.

[0118] Embodiments of the present invention may also include a corresponding computer device. The computer device includes a memory, at least one processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes any of the methods described above when executing the program.

[0119] The memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for generating connectivity test files described in the embodiments of this application. The processor executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in the memory, thereby implementing the method for generating connectivity test files as described in the above embodiments.

[0120] The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the device, etc. Furthermore, the memory may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0121] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium for the program can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The above computer program embodiments can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0122] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0123] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for generating connectivity test files, characterized in that, include: Create hierarchical configuration files, special interface specification files, and special signal relationship specification files; Obtain the configuration file of the chip to be verified, and parse the input and output interface information of each module to be tested and related modules in the configuration file based on the hierarchical configuration file to generate the input and output interface files of the module to be tested and the input and output interface files of the related modules respectively. Obtain the input interface file of the module to be tested, and sequentially search the output interface files of the associated modules for output signals that match the input signals in the input interface file; form a connection relationship group with the matching output signals in the output interface file and output it to the connectivity test file; If no output signal matching the input signal in the input interface file is found in the output interface file, then based on the special interface specification file and the mismatched input signal, an output signal with a connection relationship to the mismatched input signal is searched in the special interface specification file; the mismatched input signal and the output signal with a connection relationship are output to the connectivity test file; wherein, the special signal relationship specification file contains multiple connectivity test functions and encapsulates the connectivity test functions; the connectivity test functions include: a connectivity test function indicating that the input and output signals are directly connected, a connectivity test function indicating that the input and output signals are inverted, a connectivity test function indicating that the input and output signals need to be synchronized with a clock signal, a connectivity test function indicating that the input and output signals need to be synchronized with a clock signal and inverted, a connectivity test function indicating that there is a delay between the input and output signals, and a connectivity test function indicating that the input and output signals need to be delayed and inverted; wherein, the special signal relationship specification file implements the calling of the corresponding connectivity test functions by judging the number of parameters and special characters; Based on the connectivity test function in the special signal relationship specification file, each connectivity group in the connectivity test file is updated to obtain the final connectivity test file.

2. The method according to claim 1, characterized in that, Further includes: If no output signal connected to the mismatched input signal is found in the output interface file, the mismatched input signal and the module containing the mismatched input signal are output to the error file.

3. The method according to claim 1, characterized in that, The connection test function in the connection test file, based on the specific signal relationship specification file, updates each connection relationship group in the connection test file to obtain the final connection test file, including: Obtain the parameter length and special characters of the connection relationship group, and based on the parameter length and special characters, call the corresponding connectivity test function to update the connection relationship group.

4. The method according to claim 1, characterized in that, Based on the hierarchical configuration file, the input and output interface information of each module to be tested and its associated modules in the configuration file is parsed to generate input and output interface files for the modules to be tested and the associated modules, respectively, including: Based on the hierarchical configuration file, the path information of each module to be tested and the associated module of the chip to be verified is extracted from the configuration file; Based on the path information, extract the interface information of the module to be tested and the interface information of the associated module; The interface information of the module under test and the interface information of the associated modules are analyzed to generate input and output interface files for each module under test and the associated modules of the chip to be verified.

5. The method according to claim 1, characterized in that, The hierarchical configuration file includes: information about the module to be tested, information about associated modules, and information about the output file; The special interface specification document includes: interface information of the mismatched module under test and interface information of related modules that are connected to the interface information of the mismatched module under test.

6. The method according to claim 1, characterized in that, After outputting the connection group to the connectivity test file, the method further includes: Obtain the output interface file of the module to be tested, and sequentially search the input interface files of the associated modules for associated input signals that match the output signal to be tested in the output interface file; The matched associated input signal and the output signal under test are combined to form a connection relationship group, which is then output to the connectivity test file.

7. A system for generating connectivity test files, characterized in that, include: A creation module is configured to create a hierarchical structure configuration file, a special interface specification file, and a special signal relationship specification file. The parsing module is configured to obtain the configuration file of the chip to be verified, and based on the hierarchical configuration file, parse the input and output interface information of each module to be tested and related modules in the configuration file to generate input and output interface files of the module to be tested and the input and output interface files of the related modules respectively. The search module is configured to obtain the input interface file of the module to be tested, sequentially search the output interface file of the associated module for output signals that match the input signals in the input interface file, form a connection relationship group with the matching output signals in the output interface file, and output it to the connectivity test file. The search module is further configured to, if no output signal matching the input signal in the input interface file is found in the output interface file, then, based on the special interface description file and the mismatched input signal, search for an output signal connected to the mismatched input signal in the output interface file; output the mismatched input signal and the connected output signal to the connectivity test file; wherein, the special signal relationship description file contains multiple connectivity test functions and encapsulates the connectivity test functions; the connectivity test functions include: a connectivity test function indicating that the input and output signals are directly connected, a connectivity test function indicating that the input and output signals are inverted, a connectivity test function indicating that the input and output signals need to be synchronized by a clock signal, a connectivity test function indicating that the input and output signals need to be synchronized by a clock signal and inverted, a connectivity test function indicating that there is a delay between the input and output signals, and a connectivity test function indicating that the input and output signals need to be delayed and inverted; wherein, the special signal relationship description file implements the calling of the corresponding connectivity test functions by judging the number of parameters and special characters; An update module is configured to update each connection relationship group in the connection test file according to the connection test function in the special signal relationship specification file to obtain the final connection test file.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-6.

Images