Method, device and electronic device for realizing data classification based on machine learning model

Abstract

The present disclosure relates to a method and device for implementing data classification based on a machine learning model, and an electronic device. The method is implemented through a field programmable logic gate array device, and includes: obtaining feature parameters to be input into the machine learning model, wherein the machine learning model is used to classify the feature parameters through reasoning, and the machine learning model is divided into multiple levels of reasoning units, and the multiple levels of reasoning units are stored in a random access memory of the field programmable logic gate array device, and each level of reasoning unit includes node information of the machine learning model; according to the multiple levels of reasoning units, the feature parameters are cached in multiple levels on the random access memory, wherein the number of levels for caching the feature parameters is the same as the number of reasoning units, and the feature parameters cached at each level are the same; sequentially using each level of reasoning unit in the multi-level reasoning unit to obtain the feature parameters corresponding to the reasoning unit from the random access memory, and performing reasoning processing on the feature parameters.

Description

Technical Field

[0001] The present disclosure relates to the field of machine learning, and in particular to a method and device for implementing data classification based on a machine learning model, and an electronic device. Background Art

[0002] Among the related technologies, the random forest algorithm is one of the many machine learning algorithms. It has a wide range of application prospects due to its strong interpretability, high flexibility, excellent accuracy, and ability to run effectively on large data sets. The random forest is composed of decision trees, which use a tree structure and use layer-by-layer reasoning to achieve the final classification.

[0003] At present, the general technical solution is to use Field Programmable Gate Array (FPGA) instead of Central Processing Unit (CPU) to implement the random forest model. For the CPU, for random forests with more levels or larger models, due to the constraints of computing delay and thread resources, the throughput and delay of the CPU directly performing random forest model calculations are not ideal. As a programmable logic device, FPGA can realize certain specific functions through programming, and has the characteristics of high efficiency, ease of use, and programmability. Therefore, it is a common method to accelerate random forest reasoning based on FPGA instead of CPU, and the common FPGA acceleration random forest reasoning solutions are all based on multi-level reasoning.

[0004] For the above method, when the dimension of the feature parameter input to the random forest model is relatively large, the reasoning performance of the random forest model will be reduced. Summary of the invention

[0005] The present disclosure provides a method and device for implementing data classification based on a machine learning model, so as to at least solve the problem in the related art that when the dimension of the feature parameter input into the random forest model is relatively large, the reasoning performance of the random forest model will be reduced. The technical solution of the present disclosure is as follows:

[0006] According to a first aspect of an embodiment of the present disclosure, a method for implementing data classification based on a machine learning model is provided, and the method is implemented by a field programmable logic gate array device, comprising: obtaining feature parameters to be input into the machine learning model, wherein the machine learning model is used to classify the feature parameters by reasoning, and the machine learning model is divided into multiple levels of reasoning units, and the multiple levels of reasoning units are stored in a random access memory of the field programmable logic gate array device, and each level of reasoning unit includes node information of the machine learning model; according to the multiple levels of reasoning units, the feature parameters are cached in multiple levels on the random access memory, wherein the number of levels for caching the feature parameters is the same as the number of reasoning units, and the feature parameters cached at each level are the same; sequentially using each level of reasoning unit in the multi-level reasoning unit to obtain the feature parameters corresponding to the reasoning unit from the random access memory, and perform reasoning processing on the feature parameters.

[0007] Optionally, each level of reasoning unit includes multiple threads, wherein the multiple threads are used to perform classification processing on feature parameters in parallel.

[0008] Optionally, the inference units at each level in the multi-level inference unit are used in turn to obtain feature parameters corresponding to the inference unit from the random access memory, and perform inference processing on the feature parameters, including: using each thread in the multiple threads to execute the following process: reading the node information of the machine learning model corresponding to the inference unit where the current thread is located from the random access memory, and obtaining the feature number and the corresponding threshold value required for comparison operation during the inference processing; obtaining the feature parameters corresponding to the inference processing from the hierarchical cache corresponding to the current inference unit, wherein obtaining the feature parameters includes: feature request and feature return; using the obtained feature parameters and the threshold value to perform comparison operation according to the feature number.

[0009] Optionally, the cycle of each thread execution process includes multiple clock cycles, wherein the clock cycle is a clock cycle of a field programmable logic gate array device.

[0010] Optionally, the above method also includes: controlling each thread to execute the feature request step in different clock cycles of the cycle, and controlling each thread to execute the feature return step in different clock cycles of the cycle, wherein the clock cycles of the same thread executing the feature request step and the feature return step are different.

[0011] Optionally, feature parameters are cached in a random access memory at multiple levels, including: using two random access memories to cache feature parameters in each level of cache, respectively, wherein the two random access memories include a first random access memory and a second random access memory, and when the inference unit obtains feature parameters from the first random access memory of the corresponding level cache, the second random access memory of the level cache receives and caches the feature parameters of the new inference request.

[0012] Optionally, the machine learning model is a random forest model, and the node information of the machine learning model includes the number of decision tree node layers constituting the random forest model; the number of decision tree node layers of the random forest model obtained by each thread included in each inference unit is within a preset range.

[0013] According to a second aspect of an embodiment of the present disclosure, there is provided a device for implementing data classification based on a machine learning model, comprising: an acquisition module, configured to execute acquisition of feature parameters to be input into the machine learning model, wherein the machine learning model is used to classify the feature parameters by reasoning, and the machine learning model is divided into multiple levels of reasoning units, and the multiple levels of reasoning units are stored in a random access memory of a field programmable logic gate array device, and each level of reasoning unit includes node information of the machine learning model; a storage module, configured to execute multi-level caching of the feature parameters on the random access memory according to the multiple levels of reasoning units, wherein the feature parameters of each level of cache are the same; a processing module, configured to execute sequentially using the multiple levels of reasoning units in the multiple levels of reasoning units to obtain the feature parameters corresponding to the reasoning unit from the random access memory, and perform reasoning processing on the feature parameters.

[0014] Optionally, each level of reasoning unit includes multiple threads, wherein the multiple threads are used to perform classification processing on feature parameters in parallel.

[0015] Optionally, the processing module is configured to execute the following process using each thread of the multiple threads respectively: reading the node information of the machine learning model corresponding to the inference unit where the current thread is located from the random access memory, and obtaining the feature number and the corresponding threshold value required for comparison operation during the inference processing; obtaining the feature parameters corresponding to the reasoning processing from the hierarchical cache corresponding to the current inference unit, wherein obtaining the feature parameters includes: feature request and feature return; using the obtained feature parameters and the threshold value to perform comparison operation according to the feature number.

[0016] Optionally, the cycle of each thread execution process includes multiple clock cycles, wherein the clock cycle is a clock cycle of a field programmable logic gate array device.

[0017] Optionally, the above-mentioned device also includes: a control module, configured to execute the steps of respectively controlling each thread to execute feature request in different clock cycles of the cycle, and respectively controlling each thread to execute feature return in different clock cycles of the cycle, wherein the clock cycles of the same thread executing the feature request step and the feature return step are different.

[0018] Optionally, the storage module is configured to execute caching feature parameters in each level of cache using two random access memories respectively, wherein the two random access memories include a first random access memory and a second random access memory, and when the inference unit obtains the feature parameters from the first random access memory of the corresponding level cache, the second random access memory of the level cache receives and caches the feature parameters of the new inference request.

[0019] Optionally, the machine learning model is a random forest model, and the node information of the machine learning model includes the number of decision tree node layers constituting the random forest model; the number of decision tree node layers of the random forest model obtained by each thread included in each inference unit is within a preset range.

[0020] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to execute instructions to implement a method for data classification based on a machine learning model as described above.

[0021] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided. When instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the above method for implementing data classification based on a machine learning model.

[0022] According to a fifth aspect of an embodiment of the present disclosure, there is provided a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above method for data classification based on a machine learning model.

[0023] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects: using the more abundant random access memory (RAM) on the FPGA to perform multi-level caching of feature parameters, and using a special step-by-step multi-path acceleration method to solve the resource bottleneck while further improving the FPGA's reasoning performance for the random forest algorithm, which can not only meet some scenarios with high requirements for reasoning performance, but also realize reasoning acceleration of some models with relatively large input feature dimensions.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0026] Figure 1 It is a schematic diagram of the existing random forest acceleration method using FPGA;

[0027] Figure 2 is to use Figure 1 The method shown is a schematic diagram of an inference data flow for implementing a random forest acceleration method;

[0028] Figure 3 is a structural block diagram of a method for implementing data classification based on a machine learning model according to an exemplary embodiment;

[0029] Figure 4 is a flow chart of a method for implementing data classification based on a machine learning model according to an exemplary embodiment;

[0030] Figure 5 is a schematic diagram showing a method for implementing a random forest acceleration method using FPGA according to an exemplary embodiment;

[0031] Figure 6 is a schematic diagram showing an inference data flow of a pipeline where each thread is located according to an exemplary embodiment;

[0032] Figure 7 is a flow chart of a step-by-step multi-path acceleration method according to an exemplary embodiment;

[0033] Figure 8 is a schematic diagram showing a feature parameter multi-level cache module feature request data flow according to an exemplary embodiment;

[0034] Fig. 9 is a schematic diagram showing a characteristic return data flow of a characteristic parameter multi-level cache module according to an exemplary embodiment;

[0035] Fig.10 is a structural block diagram of a device for implementing data classification based on a machine learning model according to an exemplary embodiment;

[0036] Fig.11 The present invention is a structural block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0037] In order to enable ordinary persons in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0039] Figure 1 This is a schematic diagram of the existing random forest acceleration method using FPGA, such as Figure 1 As shown in the figure, when implementing FPGA, the random forest needs to be divided into N inference units to realize the inference pipeline. The node information of the model is stored in each level of inference unit. On the basis of pursuing inference performance, in order to realize the pipeline calculation of each inference unit, the feature parameters of the input end also need to be cached at N levels, so as to achieve the consistency of inference and feature parameters. Among the existing solutions, a typical implementation is to store the model node information in the inference unit in the random access memory (RAM) of the FPGA, and the multi-level cache of the feature parameters is often realized by the register of the FPGA.

[0040] Figure 2 is to use Figure 1 The method shown in the figure implements a reasoning data flow diagram of the random forest acceleration method, as shown in Figure 2 As shown, in the "read model" step, the inference unit reads the node information of the current inference from the model stored in RAM, and obtains the feature number and corresponding threshold value that need to be compared. The "get feature" step is to obtain the corresponding feature from the feature parameter multi-level cache module. The "comparison operation" is to perform the corresponding comparison operation on the obtained feature and the threshold value to obtain the next node information address or leaf node to be calculated.

[0041] In this scheme, the unit with the lowest inference performance among all inference units determines the performance of the entire pipeline. It can be seen that, generally speaking, it takes 3 FPGA clocks to complete the inference operation of a node. For a random forest, when the number and depth of its decision trees remain unchanged, the model information in the inference unit can be evenly distributed, and the number of pipeline stages can be increased as much as possible, or the inference scale of each pipeline can be reduced to achieve the optimal performance. However, when the number of pipeline stages increases, the cache of the corresponding feature parameters must also be increased accordingly. When the dimension of the feature parameters is relatively small, it is feasible to increase the number of pipeline stages, but when the dimension of the feature parameters is larger, the resources consumed in the multi-level cache part of the feature parameters are greater. In the case of limited on-chip resources on the FPGA, a model with a large dimension of feature parameters is often constrained by resources and cannot achieve more levels of pipelines, thus failing to achieve a better acceleration effect.

[0042] In view of the current technical status, this application proposes a new design solution: using the more abundant RAM on the FPGA to cache the feature parameters at multiple levels, and using a special step-by-step multi-path acceleration method to solve the resource bottleneck and further improve the reasoning performance. The following is a detailed description of the solution proposed in this application:

[0043] Figure 3 is a structural block diagram of a method for implementing data classification based on a machine learning model according to an exemplary embodiment. Figure 3 As shown, the CPU downloads the random forest model to the FPGA through the PCIe port. The network port on the FPGA board receives the message from the network, parses and extracts the calculation-related feature parameters, and performs reasoning based on the feature parameters and the updated random forest model. After the reasoning is completed, the reasoning result is sent out through the network port.

[0044] In an optional embodiment of the present application, Figure 3 The FPGA selected in the illustrated embodiment is Intel's Stratix10GX FPGA acceleration card D5005, which has 229 Mbit embedded memory.

[0045] Figure 4 is a flow chart of a method for implementing data classification based on a machine learning model according to an exemplary embodiment. Figure 4 As shown, the method comprises the following steps:

[0046] In step S41, characteristic parameters to be input into a machine learning model are obtained, wherein the machine learning model is used to classify the characteristic parameters by reasoning, the machine learning model is divided into a multi-level reasoning unit, the multi-level reasoning unit is stored in a random access memory of a field programmable logic gate array device, and each level of reasoning unit includes node information of the machine learning model;

[0047] It should be noted that the machine learning model in step S41 includes a random forest model.

[0048] See also Figure 1 When executing step S41, the random forest model is divided into N levels of reasoning units to implement the reasoning pipeline, and each level of reasoning unit stores the node information of the model.

[0049] It should be noted that the node information of the model includes the feature numbers and corresponding thresholds that need to be compared during the inference process.

[0050] In step S42, according to the multi-level reasoning unit, the feature parameters are cached in multiple levels on the random access memory, wherein the feature parameters of each level of cache are the same;

[0051] In this solution, the random forest model and feature parameters are stored in the RAM of the FPGA, and the random forest model storage is the node information in the model.

[0052] In order to realize the pipeline calculation of each inference unit, it is also necessary to cache the feature parameters of the input end at N levels, so as to achieve the consistency of inference and feature parameters. Figure 1 As shown, the number of levels of feature parameter cache is the same as the number of inference units obtained by splitting the random forest model.

[0053] In step S43, each level of the multi-level reasoning unit is used in turn to obtain the feature parameters corresponding to the reasoning unit from the random access memory, and the feature parameters are inferred.

[0054] Through the above method, the more abundant RAM on the FPGA is used to perform multi-level caching of feature parameters, which not only solves the resource bottleneck, but also further improves the FPGA's reasoning performance for the random forest algorithm. It can not only meet some scenarios with high requirements for reasoning performance, but also realize the reasoning acceleration of some models with relatively large input feature dimensions.

[0055] According to an optional embodiment of the present application, each level of reasoning unit includes multiple threads, wherein the multiple threads are used to perform classification processing on feature parameters in parallel.

[0056] Figure 5is a schematic diagram showing a method for implementing a random forest acceleration method using FPGA according to an exemplary embodiment, Figure 5 The method shown and Figure 1 The difference from the existing method shown is that each reasoning unit contains multiple threads that can perform parallel computing.

[0057] According to an optional embodiment of the present application, step S43 is executed to sequentially use each level of inference unit in the multi-level inference unit to obtain feature parameters corresponding to the inference unit from the random access memory, and perform inference processing on the feature parameters, which is achieved by the following method: using each thread in the multiple threads to execute the following process respectively: reading the node information of the machine learning model corresponding to the inference unit where the current thread is located from the random access memory, and obtaining the feature number and the corresponding threshold value that need to be compared during the inference processing; obtaining the feature parameters corresponding to the inference processing from the hierarchical cache corresponding to the current inference unit, wherein obtaining the feature parameters includes: feature request and feature return; using the obtained feature parameters and the threshold value to perform comparison operations according to the feature number.

[0058] For example, each inference unit contains 4 threads. The inference data flow of each thread pipeline is as follows: Figure 6 As shown, the scheme infers the data flow and Figure 2 The scheme shown is basically the same, except that the inference operation for each node requires 4 FPGA clocks. This is because the feature acquisition process uses RAM and also cooperates with the step-by-step multi-path acceleration method of the scheme, which takes up two FPGA clock cycles to execute the "feature request" and "feature return" steps respectively.

[0059] In some optional embodiments of the present application, the cycle of each thread execution process includes multiple clock cycles, wherein the clock cycle is a clock cycle of a field programmable logic gate array device.

[0060] According to an optional embodiment of the present application, the above method also includes: respectively controlling each thread to execute the step of feature request in different clock cycles of the cycle, and respectively controlling each thread to execute the step of feature return in different clock cycles of the cycle, wherein the clock cycles of the same thread executing the step of feature request and the step of executing feature return are different.

[0061] exist Figure 2 In the existing scheme shown, it can be seen that the feature parameter multi-level cache module is in an idle state in the "read model" and "comparison operation" stages. By starting the thread in a step-by-step manner, the feature parameter multi-level cache module can be in a "full load" state.

[0062] Figure 7This is a flowchart of a step-by-step multi-path acceleration method according to an exemplary embodiment. The feature parameter multi-level cache module accessed by the four threads in reasoning is common, and the inference data flow is started in a step-by-step manner according to the FPGA clock cycle. It can be seen that although the single-node reasoning cycle of each thread uses four FPGA clocks, by performing step-by-step reasoning data flow on the four threads, the feature parameter multi-level cache module can be accessed in a time-sharing manner, thereby making full use of the multi-level cache module to perform as many node reasonings as possible. Of course, if a leaf node appears in the thread's reasoning process, the thread will output the leaf node in the next "read model" stage and pass it to the calculation module for accumulation and other voting rule operations. The step-by-step multi-path acceleration method determines that the leaf node output of each thread must be misaligned and will not generate "competition".

[0063] Figure 8 is a schematic diagram showing a feature parameter multi-level cache module feature request data flow according to an exemplary embodiment, Fig. 9 is a schematic diagram of a characteristic parameter multi-level cache module characteristic return data flow according to an exemplary embodiment, Figure 8 and Fig. 9 It can be seen that in each FPGA clock cycle, the module is cyclically accessed by 4 threads, and the feature loop is returned to the 4 threads in each cycle. In other words, the feature parameter multi-level cache module is working at "full load".

[0064] The above-mentioned step-by-step multi-path acceleration method proposed in this application can greatly save the use resources of FPGA while accelerating the random forest algorithm through FPGA, and solve the problem of decreased reasoning performance due to excessive input dimensions.

[0065] In some other optional embodiments of the present application, feature parameters are cached in multiple levels on a random access memory, including: using two random access memories to cache feature parameters in each level of cache, respectively, wherein the two random access memories include a first random access memory and a second random access memory, and when the inference unit obtains the feature parameters from the first random access memory of the corresponding level cache, the second random access memory of the level cache receives and caches the feature parameters of the new inference request.

[0066] The feature parameters are stored on RAM, and two pieces of RAM are used for ping-pong storage in each pipeline level. When one piece of RAM serves the feature parameter acquisition of the inference unit, the other piece of RAM is used to receive the feature parameters of the new inference request, which can achieve the technical effect of ensuring that the reception of feature parameters does not affect the performance of inference.

[0067] In other optional embodiments of the present application, the machine learning model is a random forest model, and the node information of the machine learning model includes the number of decision tree node layers that constitute the random forest model; the number of decision tree node layers of the random forest model obtained by each thread included in each inference unit is within a preset range.

[0068] In this scheme, four threads in each pipeline share one feature parameter multi-level cache module. The total number of decision tree node layers Li stored in each thread determines the inference efficiency of the thread, which is Li*4. The thread with the largest total number of decision tree node layers among the four threads is the inference bottleneck of the entire pipeline. In this scheme, when the CPU updates the model to the FPGA, it should try to ensure that the number of decision tree node layers of the model in each thread of each pipeline is balanced, so as to achieve optimal performance.

[0069] From the inference data flow of this scheme and the existing scheme, it can be seen that for the same model, assuming that the two schemes use the same number of pipelines Kn, the number of decision tree layers that need to be calculated for each layer of the existing scheme is the total number of model layers Lsum / Kn, and the inference time of each node layer is 3 FPGA clocks, so the final inference performance is approximately:

[0070] Through_now=Freq / (3*Lsum / Kn)

[0071] Assuming that the number of decision tree node layers of the new solution is basically balanced, the reasoning performance of the new solution is approximately:

[0072] Through_new=Freq / (Lsum / Kn)

[0073] It can be seen that when the on-chip resources are sufficient, if the same number of pipeline stages is implemented, the inference performance of the new solution is three times that of the existing solution.

[0074] When the input feature dimension is large, since the existing technical solution stores the input feature parameters in the register and caches the feature parameters for each stage of the pipeline, the existing solution is almost unable to design a multi-stage pipeline due to the limitation of register resources during implementation. However, since this solution stores the feature parameters in RAM, the RAM resource usage is relatively more abundant, and a certain number of pipelines can be implemented within the scope of reasonable resource usage to accelerate reasoning.

[0075] In this solution, the random forest model and feature parameters are stored in the RAM of the FPGA. The FPGA clock is 250MHz. The model is loaded for 500 decision trees with a depth of 3. The input dimensions of the model are single-precision floating-point data of 500, 1000, 5000, and 10000 respectively. A multi-stage pipeline is opened to load the model, and there are 4 threads in each pipeline. Table 1 shows the resource usage and inference performance of this solution under various models (without considering the network input bandwidth).

[0076] Table 1 FPGA resource usage and reasoning performance in different dimensions

[0077]

[0078] It can be seen from Table 1 that for different feature input dimensions, a larger number of pipeline stages can be achieved, thereby achieving better inference performance.

[0079] Fig.10 is a structural block diagram of a device for implementing data classification based on a machine learning model according to an exemplary embodiment, referring to Fig.10 The device includes an acquisition module 101, a storage module 102 and a processing module 103.

[0080] The acquisition module 101 is configured to execute acquisition of feature parameters to be input into a machine learning model, wherein the machine learning model is used to classify the feature parameters through reasoning, and the machine learning model is divided into multiple levels of reasoning units, which are stored in a random access memory of a field programmable logic gate array device, and each level of reasoning unit includes node information of the machine learning model.

[0081] See also Figure 1 , the random forest model is divided into N levels of inference units to implement the inference pipeline, and each level of inference unit stores the node information of the model.

[0082] In the solution provided in the embodiment of the present application, the random forest model and feature parameters are stored in the RAM of the FPGA, and the random forest model storage is the node information in the model.

[0083] The storage module 102 is configured to perform multi-level caching of feature parameters on a random access memory according to multi-level reasoning units, wherein the number of levels at which the feature parameters are cached is the same as the number of reasoning units, and wherein the feature parameters cached at each level are the same.

[0084] In order to realize the pipeline calculation of each inference unit, it is also necessary to cache the feature parameters of the input end at N levels, so as to achieve the consistency of inference and feature parameters. Figure 1As shown, the number of levels of feature parameter cache is the same as the number of inference units obtained by splitting the random forest model.

[0085] The processing module 103 is configured to sequentially use each level of the multi-level reasoning unit to obtain the feature parameters corresponding to the reasoning unit from the random access memory, and perform reasoning processing on the feature parameters.

[0086] Through the above device, the more abundant RAM on the FPGA is used to perform multi-level caching of feature parameters, which not only solves the resource bottleneck but also further improves the FPGA's reasoning performance for the random forest algorithm. It can not only meet some scenarios with high requirements for reasoning performance, but also realize the reasoning acceleration of some models with relatively large input feature dimensions.

[0087] According to an optional embodiment of the present application, each level of reasoning unit includes multiple threads, wherein the multiple threads are used to perform classification processing on feature parameters in parallel.

[0088] Figure 5 is a schematic diagram showing a method for implementing a random forest acceleration method using FPGA according to an exemplary embodiment, Figure 5 The method shown and Figure 1 The difference from the existing method shown is that each reasoning unit contains multiple threads that can perform parallel computing.

[0089] According to another optional embodiment of the present application, the processing module 103 is configured to execute the following process using each thread in the multiple threads respectively: read the node information of the machine learning model corresponding to the inference unit where the current thread is located from the random access memory, and obtain the feature number and the corresponding threshold value that need to be compared during the inference processing; obtain the feature parameters corresponding to the inference processing from the hierarchical cache corresponding to the current inference unit, wherein obtaining the feature parameters includes: feature request and feature return; use the obtained feature parameters and the threshold value to perform comparison operations according to the feature number.

[0090] For example, each inference unit contains 4 threads. The inference data flow of each thread pipeline is as follows: Figure 6 As shown, the scheme infers the data flow and Figure 2 The scheme shown is basically the same, except that the inference operation for each node requires 4 FPGA clocks. This is because the feature acquisition process uses RAM and also cooperates with the step-by-step multi-path acceleration method of the scheme, which takes up two FPGA clock cycles to execute the "feature request" and "feature return" steps respectively.

[0091] In some optional embodiments of the present application, the cycle of each thread execution process includes multiple clock cycles, wherein the clock cycle is a clock cycle of a field programmable logic gate array device.

[0092] In some other optional embodiments of the present application, the above-mentioned device also includes: a control module, which is configured to execute the steps of respectively controlling each thread to execute feature requests in different clock cycles of the cycle, and respectively controlling each thread to execute feature returns in different clock cycles of the cycle, wherein the clock cycles of the same thread executing the feature request step and the feature return step are different.

[0093] exist Figure 2 In the existing scheme shown, it can be seen that the feature parameter multi-level cache module is in an idle state in the "read model" and "comparison operation" stages. By starting the thread in a step-by-step manner, the feature parameter multi-level cache module can be in a "full load" state.

[0094] Figure 7 This is a flowchart of a step-by-step multi-path acceleration method according to an exemplary embodiment. The feature parameter multi-level cache module accessed by the four threads in reasoning is common, and the inference data flow is started in a step-by-step manner according to the FPGA clock cycle. It can be seen that although the single-node reasoning cycle of each thread uses four FPGA clocks, by performing step-by-step reasoning data flow on the four threads, the feature parameter multi-level cache module can be accessed in a time-sharing manner, thereby making full use of the multi-level cache module to perform as many node reasonings as possible. Of course, if a leaf node appears in the thread's reasoning process, the thread will output the leaf node in the next "read model" stage and pass it to the calculation module for accumulation and other voting rule operations. The step-by-step multi-path acceleration method determines that the leaf node output of each thread must be misaligned and will not generate "competition".

[0095] Figure 8 is a schematic diagram showing a feature parameter multi-level cache module feature request data flow according to an exemplary embodiment, Fig. 9 is a schematic diagram of a characteristic parameter multi-level cache module characteristic return data flow according to an exemplary embodiment, Figure 8 and Fig. 9 It can be seen that in each FPGA clock cycle, the module is cyclically accessed by 4 threads, and the feature loop is returned to the 4 threads in each cycle. In other words, the feature parameter multi-level cache module is working at "full load".

[0096] The above-mentioned step-by-step multi-path acceleration method proposed in this application can greatly save the use resources of FPGA while accelerating the random forest algorithm through FPGA, and solve the problem of decreased reasoning performance due to excessive input dimensions.

[0097] In an optional embodiment, the storage module 102 is configured to execute caching feature parameters in each level of cache using two random access memories respectively, wherein the two random access memories include a first random access memory and a second random access memory, and when the inference unit obtains the feature parameters from the first random access memory of the corresponding level cache, the second random access memory of the level cache receives and caches the feature parameters of the new inference request.

[0098] The feature parameters are stored on RAM, and two pieces of RAM are used for ping-pong storage in each pipeline level. When one piece of RAM serves the feature parameter acquisition of the inference unit, the other piece of RAM is used to receive the feature parameters of the new inference request, which can achieve the technical effect of ensuring that the reception of feature parameters does not affect the performance of inference.

[0099] According to an optional embodiment of the present application, the machine learning model is a random forest model, and the node information of the machine learning model includes the number of decision tree node layers that constitute the random forest model; the number of decision tree node layers of the random forest model obtained by each thread included in each inference unit is within a preset range.

[0100] In this scheme, four threads in each pipeline share one feature parameter multi-level cache module. The total number of decision tree node layers Li stored in each thread determines the inference efficiency of the thread, which is Li*4. The thread with the largest total number of decision tree node layers among the four threads is the inference bottleneck of the entire pipeline. In this scheme, when the CPU updates the model to the FPGA, it should try to ensure that the number of decision tree node layers of the model in each thread of each pipeline is balanced, so as to achieve optimal performance.

[0101] From the inference data flow of this scheme and the existing scheme, it can be seen that for the same model, assuming that the two schemes use the same number of pipelines Kn, the number of decision tree layers that need to be calculated for each layer of the existing scheme is the total number of model layers Lsum / Kn, and the inference time of each node layer is 3 FPGA clocks, so the final inference performance is approximately:

[0102] Through_now=Freq / (3*Lsum / Kn)

[0103] Assuming that the number of decision tree node layers of the new solution is basically balanced, the reasoning performance of the new solution is approximately:

[0104] Through_new=Freq / (Lsum / Kn)

[0105] It can be seen that when the on-chip resources are sufficient, if the same number of pipeline stages is implemented, the inference performance of the new solution is three times that of the existing solution.

[0106] When the input feature dimension is large, since the existing technical solution stores the input feature parameters in the register and caches the feature parameters for each stage of the pipeline, the existing solution is almost unable to design a multi-stage pipeline due to the limitation of register resources during implementation. However, since this solution stores the feature parameters in RAM, the RAM resource usage is relatively more abundant, and a certain number of pipelines can be implemented within the scope of reasonable resource usage to accelerate reasoning.

[0107] In this solution, the random forest model and feature parameters are stored in the RAM of the FPGA. The FPGA clock is 250MHz. The model is loaded for 500 decision trees with a depth of 3. The input dimensions of the model are single-precision floating-point data of 500, 1000, 5000, and 10000 respectively. A multi-stage pipeline is opened to load the model, and there are 4 threads in each pipeline. As can be seen from Table 1, for different feature input dimensions, a large number of pipeline stages can be achieved, thereby achieving better inference performance.

[0108] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0109] Fig.11 is a structural block diagram of an electronic device according to an exemplary embodiment. Fig.11 The electronic device may be a terminal 1100, for example, the terminal 1100 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0110] Terminal 1100 may include one or more of the following components: a processing component 1102 , a memory 1104 , a power component 1106 , a multimedia component 1108 , an audio component 1110 , an input / output (I / O) interface 1112 , a sensor component 1114 , and a communication component 1116 .

[0111] The processing component 1102 generally controls the overall operation of the terminal 1100, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1102 may include one or more processors 1120 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1102 may include one or more modules to facilitate the interaction between the processing component 1102 and other components. For example, the processing component 1102 may include a multimedia module to facilitate the interaction between the multimedia component 1108 and the processing component 1102.

[0112] The memory 1104 is configured to store various types of data to support operations on the device 1100. Examples of such data include instructions for any application or method operating on the terminal 1100, contact data, phone book data, messages, pictures, videos, etc. The memory 1104 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0113] The power component 1106 provides power to various components of the terminal 1100. The power component 1106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the terminal 1100.

[0114] The multimedia component 1108 includes a screen that provides an output interface between the terminal 1100 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1108 includes a front camera and / or a rear camera. When the device 1100 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0115] The audio component 1110 is configured to output and / or input audio signals. For example, the audio group 1110 includes a microphone (MIC), and when the terminal 1100 is in an operation mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 1104 or sent via the communication component 1116. In some embodiments, the audio component 1110 also includes a speaker for outputting audio signals.

[0116] I / O interface 1112 provides an interface between processing component 1102 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0117] The sensor assembly 1114 includes one or more sensors for providing various aspects of status assessment for the terminal 1100. For example, the sensor assembly 1114 can detect the open / closed state of the device 1100, the relative positioning of the components, such as the display and keypad of the terminal 1100, and the sensor assembly 1114 can also detect the position change of the terminal 1100 or a component of the terminal 1100, the presence or absence of contact between the user and the terminal 1100, the orientation or acceleration / deceleration of the terminal 1100, and the temperature change of the terminal 1100. The sensor assembly 1114 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 1114 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1114 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0118] The communication component 1116 is configured to facilitate wired or wireless communication between the terminal 1100 and other devices. The terminal 1100 can access a wireless network based on a communication standard, such as WiFi, an operator network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 1116 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1116 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0119] In an exemplary embodiment, terminal 1100 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above method.

[0120] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as a memory 1104 including instructions, and the above instructions can be executed by a processor 1120 of an electronic device to perform the above method. The computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0121] In an exemplary embodiment, a computer program product is also provided, including a computer program / instruction, which, when executed by a processor, implements the above method for data classification based on a machine learning model.

[0122] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0123] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for data classification based on a machine learning model, characterized in that: The method is implemented by a field programmable logic gate array device, comprising: Acquire feature parameters to be input into a machine learning model, wherein the machine learning model is used to classify the feature parameters by reasoning, the machine learning model is divided into multiple levels of reasoning units, the multiple levels of reasoning units are stored in a random access memory of the field programmable logic gate array device, and each level of the reasoning unit includes node information of the machine learning model; According to the multi-level reasoning unit, the feature parameters are cached in multiple levels on the random access memory, wherein the feature parameters of each level of cache are the same; sequentially using each level of the multi-level reasoning unit to obtain the feature parameter corresponding to the reasoning unit from the random access memory, and perform reasoning processing on the feature parameter; The characteristic parameters are cached in multiple levels on the random access memory, including: The feature parameters are cached in each level of cache using two pieces of random access memories respectively, wherein the two pieces of random access memories include a first random access memory and a second random access memory, and when the inference unit obtains the feature parameters from the first random access memory of the corresponding level cache, the second random access memory of the level cache receives and caches the feature parameters of the new inference request.

2. The method according to claim 1, characterized in that Each level of the reasoning unit includes multiple threads, wherein the multiple threads are used to perform classification processing on the feature parameters in parallel.

3. The method according to claim 2, characterized in that Sequentially using each level of the multi-level reasoning unit to obtain the feature parameter corresponding to the reasoning unit from the random access memory, and performing reasoning processing on the feature parameter, including: The following process is performed using each of the multiple threads respectively: Reading node information of the machine learning model corresponding to the inference unit where the current thread is located from the random access memory, and obtaining a feature number and a corresponding threshold value required for comparison operation in the inference processing process; Acquire feature parameters corresponding to the reasoning process from the hierarchical cache corresponding to the current reasoning unit, wherein acquiring the feature parameters includes: feature request and feature return; The acquired characteristic parameter is compared with the threshold value according to the characteristic number.

4. The method according to claim 3, characterized in that The cycle of each thread executing the process includes multiple clock cycles, wherein the clock cycle is the clock cycle of the field programmable logic gate array device.

5. The method according to claim 4, characterized in that The method further comprises: Respectively control each of the threads to execute the step of requesting the feature in different clock cycles of the cycle, and respectively control each of the threads to execute the step of returning the feature in different clock cycles of the cycle, wherein the clock cycles for the same thread to execute the step of requesting the feature and the step of returning the feature are different.

6. The method according to claim 2, characterized in that The machine learning model is a random forest model, and the node information of the machine learning model includes the number of decision tree node layers constituting the random forest model; The number of decision tree node layers of the random forest model obtained by each thread included in each of the inference units is within a preset range.

7. A device for implementing data classification based on a machine learning model, characterized in that: include: an acquisition module, configured to execute acquisition of feature parameters to be input into a machine learning model, wherein the machine learning model is used to classify the feature parameters by reasoning, the machine learning model is divided into multiple levels of reasoning units, the multiple levels of reasoning units are stored in a random access memory of a field programmable logic gate array device, and each level of the reasoning unit includes node information of the machine learning model; A storage module, configured to perform multi-level caching of the feature parameters on the random access memory according to the multi-level reasoning unit, wherein the feature parameters of each level of cache are the same; A processing module is configured to sequentially use the inference units of each level in the multi-level inference unit to obtain the feature parameters corresponding to the inference unit from the random access memory, and perform inference processing on the feature parameters; The storage module is configured to execute caching the feature parameters in each level of cache using two pieces of the random access memory respectively, wherein the two pieces of the random access memory include a first random access memory and a second random access memory, and when the inference unit obtains the feature parameters from the first random access memory of the corresponding level cache, the second random access memory of the level cache receives and caches the feature parameters of the new inference request.

8. The device according to claim 7, characterized in that Each level of the reasoning unit includes multiple threads, wherein the multiple threads are used to perform classification processing on the feature parameters in parallel.

9. The device according to claim 8, characterized in that The processing module is configured to execute the following process using each thread of the multiple threads respectively: Reading node information of the machine learning model corresponding to the inference unit where the current thread is located from the random access memory, and obtaining a feature number and a corresponding threshold value required for comparison operation in the inference processing process; Acquire feature parameters corresponding to the reasoning process from the hierarchical cache corresponding to the current reasoning unit, wherein acquiring the feature parameters includes: feature request and feature return; The acquired characteristic parameter is compared with the threshold value according to the characteristic number.

10. The device according to claim 9, characterized in that The cycle of each thread executing the process includes multiple clock cycles, wherein the clock cycle is the clock cycle of the field programmable logic gate array device.

11. The device according to claim 10, characterized in that The above device also includes: a control module, The method is configured to respectively control each thread to execute the step of executing the feature request in different clock cycles of the cycle, and to respectively control each thread to execute the step of returning the feature in different clock cycles of the cycle, wherein the clock cycles for the same thread to execute the step of requesting the feature and the step of returning the feature are different.

12. The device according to claim 8, characterized in that The machine learning model is a random forest model, and the node information of the machine learning model includes the number of decision tree node layers constituting the random forest model; The number of decision tree node layers of the random forest model obtained by each thread included in each of the inference units is within a preset range.

13. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; Wherein, the processor is configured to execute the instructions to implement the method for data classification based on a machine learning model as described in any one of claims 1 to 6.

14. A computer-readable storage medium, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method for implementing data classification based on a machine learning model as described in any one of claims 1 to 6.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method for data classification based on a machine learning model described in any one of claims 1 to 6 is implemented.

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