A global configuration programming method, device and system

Abstract

The present invention relates to the technical field of semiconductor integrated circuits, and specifically discloses a global configuration programming method, apparatus and system. Among them, the programming method includes the following steps: obtaining all configuration bit address information; generating read instruction information according to the configuration bit address information; reading the configuration bit information in all the cfg latches according to the read instruction information, and writing all the configuration bit information into the sram, so that the controller generates programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash memory chip; compared with the traditional one-read-one-write programming process, this programming method integrates multiple read commands into one-time read instruction information, simplifies the writing logic of the configuration bit information, and effectively improves the reading and writing efficiency of the configuration bit information.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuits, and more particularly, to a global configuration programming method, apparatus, and system. Background Art

[0002] After the configuration bit information of the nor flash memory is updated, it is necessary to solidify the updated cfg latch (config latch, that is, cfg latch, configuration bit latch) data configuration bit information into the cfg register (config register, global configuration register) of the flash through programming, that is, non-volatile programming of the cfg register. The general method of this programming is to read each cfg latch data (volatile data recorded in the latch) at the corresponding address in the cfg latch one by one through the controller, that is, the configuration bit information, and then generate corresponding page program instructions according to the configuration bit information to program the flash chip, that is, to solidify the configuration bit information, so as to achieve non-volatile programming of the global configuration.

[0003] In this programming process, it is necessary to read each cfg latch data one by one and program according to the read data. For N config bits, N read instructions and N page program instructions need to be sent, and the programming process is very cumbersome and inefficient.

[0004] In view of the above problems, there is currently no effective technical solution. Summary of the Invention

[0005] The purpose of the present application is to provide a global configuration programming method, apparatus, and system to simplify the reading and writing process of configuration bit information and improve the programming efficiency of configuration bit information in the flash chip.

[0006] In a first aspect, the present application provides a global configuration programming method for programming a flash chip according to the configuration bit information of a cfg latch. The programming method includes the following steps:

[0007] Obtain all configuration bit address information;

[0008] Generate read instruction information according to the configuration bit address information;

[0009] Read the configuration bit information in all the cfg latches according to the read instruction information, and write all the configuration bit information into the sram, so that the controller generates programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash chip.

[0010] A global configuration programming method of the present application generates read instruction information based on all obtained configuration bit address information, so as to read and write the configuration bit information in all cfg latches into the sram at one time, enabling the controller to configure the programming information according to the configuration bit information written in the sram at one time to program the flash chip. Compared with the traditional one-read-one-write programming process, multiple read commands are integrated into one-time read instruction information, simplifying the writing logic of the configuration bit information and effectively improving the reading and writing efficiency of the configuration bit information.

[0011] The described global configuration programming method, wherein the configuration bit address information includes cfg latch configuration bit address information, or includes cfg latch configuration bit address information and cfg register configuration bit address information.

[0012] The described global configuration programming method, wherein the step of reading the configuration bit information in all the cfg latches according to the read instruction information includes: reading the configuration bit information in all the cfg latches simultaneously according to the read instruction information, or reading the configuration bit information in all the cfg latches sequentially according to the read instruction information.

[0013] In a global configuration programming method of this example, during the process of simultaneously reading the configuration bit information in all cfg latches according to the read instruction information, the latch data in all cfg latches containing configuration bit information is read out simultaneously, thereby ensuring the data transmission efficiency and improving the programming efficiency of the programming method of the present application; during the process of sequentially reading the configuration bit information in all cfg latches according to the read instruction information, according to the flag bit (N in configN) or latch number of the configuration bit information, the latch data in all cfg latches containing configuration bit information is read out sequentially in an increasing or decreasing manner, so that the process of reading and writing the configuration bit information into the sram has orderliness, ensuring that the configuration bit information can be accurately written into the cfg register of the flash chip in sequence.

[0014] The described global configuration programming method, wherein the programming method further includes a step executed before the step of obtaining all the configuration bit address information: obtaining flag bit information, and the flag bit information is used to determine whether it is necessary to program the flash chip according to the configuration bit information of the cfg latch.

[0015] In a global configuration programming method of this example, the programming method of the present application is started according to the flag bit information, that is, when the flag bit information is generated, the programming method of the present application starts to execute to program the flash chip.

[0016] In a second aspect, the present application provides a global configuration programming device for programming a flash memory chip according to configuration bit information of a cfg latch, including a configuration register, and the configuration register includes:

[0017] An acquisition module for acquiring all configuration bit address information;

[0018] A configuration module for generating read instruction information according to the configuration bit address information;

[0019] A read / write module for reading the configuration bit information in all the cfg latches according to the read instruction information and writing all the configuration bit information into the sram, so that a controller generates programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash memory chip.

[0020] The global configuration programming device of the present application uses the configuration module to generate read instruction information based on all the configuration bit address information acquired by the acquisition module, so that the read / write module reads and writes the configuration bit information in all the cfg latches into the sram at one time, enabling the controller to configure programming information according to the configuration bit information written in the sram at one time to program the flash memory chip. Compared with the traditional one-read-one-write programming process, multiple read commands are integrated into one-time read instruction information, simplifying the writing logic of the configuration bit information and effectively improving the read / write efficiency of the configuration bit information.

[0021] In a third aspect, the present application provides a global configuration programming method for programming a flash memory chip according to configuration bit information of a cfg latch, and the programming method includes:

[0022] Sending all the configuration bit address information to the configuration register, so that the configuration register generates read instruction information according to the configuration bit address information, and the configuration register reads the configuration bit information in all the cfg latches according to the read instruction information to write all the configuration bit information into the sram;

[0023] Generating programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash memory chip.

[0024] The global configuration programming method of the present application sends the configuration bit address information to the configuration register, and hands over the process of reading and transferring the configuration bit information in the cfg latch to the sram to the configuration register. Compared with the traditional one-read-one-write programming process, the configuration register integrates multiple read commands into one-time read instruction information, simplifying the writing logic of the configuration bit information and effectively improving the read / write efficiency of the configuration bit information.

[0025] The described global configuration programming method, wherein the step of generating programming information according to the configuration bit information in the SRAM includes: generating programming information according to the configuration bit address information and each configuration bit information in the SRAM.

[0026] The described global configuration programming method, wherein the programming information includes programming instruction information, cfg register configuration bit address information, and programming time information.

[0027] In a fourth aspect, the present application provides a global configuration programming device for programming a flash memory chip according to the configuration bit information of a cfg latch, including a controller, and the controller includes:

[0028] A sending module, configured to send all configuration bit address information to a configuration register, so that the configuration register generates read instruction information according to the configuration bit address information, and the configuration register reads the configuration bit information in all the cfg latches according to the read instruction information, so as to write all the configuration bit information into the SRAM;

[0029] A programming module, configured to generate programming information according to the configuration bit information in the SRAM, and the programming information is used to program the cfg register in the flash memory chip.

[0030] In the global configuration programming device of the present application, the sending module is used to send all configuration bit address information to the configuration register, and the process of reading and rewriting the configuration bit information in the cfg latch to the SRAM is executed by the configuration register. Compared with the traditional one-read-one-write programming process, in the programming method of the present application, the process of the controller sending read instructions one by one is changed to that the configuration register integrates multiple read commands into one-time read instruction information, that is, by setting the configuration register as the read-write information interaction layer between the controller and the flash memory chip, the writing logic of the configuration bit information is simplified, and the read-write efficiency of the configuration bit information is effectively improved.

[0031] In a fifth aspect, the present application provides a global configuration programming system for programming a flash memory chip according to the configuration bit information of a cfg latch, and the programming system includes:

[0032] The cfg latch, which stores the configuration bit information therein;

[0033] A controller, which stores configuration bit address information therein;

[0034] A configuration register, electrically connected to the controller, the cfg latch, and the SRAM, and configured to generate read instruction information;

[0035] The SRAM, used to temporarily store the configuration bit information;

[0036] The controller is used to send the configuration bit address information to the configuration register, so that the configuration register generates the read instruction information according to the configuration bit information;

[0037] The configuration register is used to read the configuration bit information in all the cfg latches according to the read instruction information, and write all the configuration bit information into the sram;

[0038] The controller is also used to generate programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash chip.

[0039] A global configuration programming system of the present application, compared with the traditional one-read-one-write programming process, in the programming system of the present application, the process of the controller sending read instructions one by one is changed to that the configuration register integrates multiple read commands into a one-time read instruction information, that is, by setting the configuration register as the read-write information interaction layer between the controller and the flash chip, the writing logic of the configuration bit information is simplified, the read-write efficiency of the configuration bit information is effectively improved, and the operation load of the controller is effectively reduced.

[0040] As can be seen from the above, the present application provides a global configuration programming method, device and system. Among them, the programming method generates read instruction information based on all the obtained configuration bit address information, so as to read and write the configuration bit information in all the cfg latches into the sram at one time, so that the controller can configure the programming information according to the configuration bit information written in the sram at one time to program the flash chip. Compared with the traditional one-read-one-write programming process, multiple read commands are integrated into a one-time read instruction information, the writing logic of the configuration bit information is simplified, and the read-write efficiency of the configuration bit information is effectively improved. Description of the Drawings

[0041] Figure 1 It is a flowchart of a global configuration programming method provided in the first aspect of the embodiment of the present application.

[0042] Figure 2 It is a schematic structural diagram of a global configuration programming device provided in the second aspect of the embodiment of the present application.

[0043] Figure 3 It is a flowchart of a global configuration programming method provided in the third aspect of the embodiment of the present application.

[0044] Figure 4 It is a schematic structural diagram of a global configuration programming device provided in the fourth aspect of the embodiment of the present application.

[0045] Figure 5A schematic structural diagram of a global configuration programming system provided in the fifth aspect of the embodiments of the present application.

[0046] Label description: 201, acquisition module; 202, configuration module; 203, read-write module; 401, sending module; 402, programming module; 501, cfg latch; 502, controller; 503, configuration register; 504, sram; 505, flash chip. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the protection scope of the present application.

[0048] It should be noted that: similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0049] The manufacturing process of the flash chip requires wafer testing (Circuit Probing). During the wafer testing process, non-volatile programming testing of the cfg register (global configuration register of the flash chip, which is composed of some storage units in the flash chip, and the addresses of these storage units are generally not continuous) of the flash chip is required. This testing process generally includes: generating new configuration bit information (stored in the latch of the cfg latch), reading the configuration bit information from the cfg latch and programming it into the corresponding address of the flash chip to solidify the configuration bit information, and then testing whether the flash chip operates normally.

[0050] In this test, the reading and programming processes need to read and program each cfg one by one. For N cfgs, N read instructions and N page program instructions need to be sent. The programming process is very cumbersome and inefficient. The specific process is as follows:

[0051] Send an 8-bit read instruction + 24-bit address (config0) + 1 byte of data, and the sram is required to temporarily store this data;

[0052] Send an 8-bit page program instruction + 24-bit address (config0) + 1-byte data + program time (1 - 4 ms), and query until the algorithm ends;

[0053] Send an 8-bit read instruction + 24-bit address (config1) + 1-byte data, and the data needs to be temporarily stored in SRAM;

[0054] Send an 8-bit page program instruction + 24-bit address (config1) + 1-byte data + program time (1 - 4 ms), and query until the algorithm ends;

[0055] ………

[0056] Send an 8-bit read instruction + 24-bit address (configN) + 1-byte data, and the data needs to be temporarily stored in SRAM;

[0057] Send an 8-bit page program instruction + 24-bit address (configN) + 1-byte data + program time (1 - 4 ms), and query until the algorithm ends.

[0058] Among them, N is determined by the number of bits of the flash memory chip config (configuration bits).

[0059] In the above programming process, a dedicated read and program command needs to be generated for each configuration bit, and the read and program processes alternate, resulting in a very cumbersome and inefficient overall programming process, which seriously restricts the programming efficiency of the global configuration of the flash memory chip.

[0060] In a first aspect, please refer to Figure 1 , Figure 1 which is a global configuration programming method in some embodiments of the present application, used to program a flash memory chip according to the configuration bit information of a cfg latch. The programming method includes the following steps:

[0061] S101. Obtain all configuration bit address information;

[0062] Specifically, the storage address of the configuration bit information (config information, generally denoted as config0, config1... configN in sequence) in the cfg latch and the write address of the configuration bit information in the flash memory chip (cfg register address) are generally discontinuous, but the two have a pairing relationship, that is, config0 is stored in a specific cfg latch, and config0 must be written into a storage unit at a specific address in the flash memory chip (the cfg register is specifically used to record the position of config0).

[0063] More specifically, since each configuration bit has a corresponding address, step S101 is to obtain all configuration bit address information sequentially or simultaneously, that is, the read and write addresses corresponding to all configuration bit information are obtained at once.

[0064] S102. Generate read instruction information according to the configuration bit address information;

[0065] Specifically, the configuration bit address information reflects the address position where the configuration bit information is stored in the cfg latch, that is, the corresponding cfg latch position. Therefore, step S102 can generate read instruction information for reading the configuration bit information at the corresponding address position in the cfg latch according to each configuration bit address information.

[0066] More specifically, step S102 generates read instruction information for obtaining all configuration bit information in the cfg latch at once according to all the configuration bit address information obtained in step S101.

[0067] S103. Read the configuration bit information in all cfg latches according to the read instruction information, and write all the configuration bit information into the sram, so that the controller generates programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash chip.

[0068] Specifically, since the read instruction information is generated according to the configuration bit address information, step S103 can read the configuration bit information in all cfg latches at once and write all the configuration bit information into the sram (static random access memory) as temporary data for storage, that is, all the configuration bit information is stored in the sram at the same time.

[0069] More specifically, after all the configuration bit information is written into the sram, the controller generates programming information according to the configuration bit information stored in the sram, so as to write the configuration bit information into the corresponding address of the flash chip, so as to solidify the configuration bit information in the flash chip.

[0070] A global configuration programming method according to an embodiment of the present application generates read instruction information based on all the obtained configuration bit address information, so as to read and write the configuration bit information in all cfg latches into the sram at once, so that the controller can configure programming information according to the configuration bit information written in the sram at once to program the flash chip. Compared with the traditional one-read-one-write programming process, multiple read commands are integrated into one read instruction information at once, which simplifies the writing logic of the configuration bit information and effectively improves the reading and writing efficiency of the configuration bit information.

[0071] Specifically, in the programming method of the embodiments of the present application, multiple read commands are integrated into a single read instruction message, effectively reducing the number of times of sending and receiving read commands, thereby reducing the transmission time of command data and improving the global configuration programming efficiency.

[0072] In some preferred embodiments, the configuration bit address information includes cfg latch configuration bit address information, or includes cfg latch configuration bit address information and cfg register configuration bit address information.

[0073] Specifically, when the configuration bit address information includes cfg latch configuration bit address information, step S102 is to generate a read instruction message according to the cfg latch configuration bit address information (i.e., the latch position), that is, the read instruction message is used to read the configuration bit information in the cfg latch; after the configuration bit information is written into the sram, the controller generates programming information according to the cfg register configuration bit address information that is not included in the pre-stored configuration bit address information in combination with the configuration bit information in the sram.

[0074] More specifically, when all the configuration bit information is written into the sram in step S103, the flag bit of the configuration bit information is also written into the sram, that is, N in configN and the corresponding configuration bit information are written into the sram together, so that the controller can call the configuration bit address information according to the flag bit N to pair with the configuration bit information in the sram, thereby generating programming information that can write the configuration bit information into the corresponding cfg register configuration bit address information. This generation method of programming information can reduce the amount of data reading and writing.

[0075] Specifically, when the configuration bit address information includes cfg latch configuration bit address information and cfg register configuration bit address information, when all the configuration bit information is written into the sram in step S103, the corresponding cfg register configuration bit address information is also written into the sram, that is, the address position in the flash chip where configN should be written is written into the sram, so that the controller can directly generate programming information according to the configuration bit information and cfg register configuration bit address information in the sram without having to call the configuration bit address information stored in the controller again. This generation method of programming information can ensure the accurate pairing of the configuration bit information and the cfg register configuration bit address information, and based on the cache characteristics of the sram, the controller can directly obtain the configuration bit information and cfg register configuration bit address information from the sram at high speed to generate programming information.

[0076] In some preferred embodiments, the step of reading the configuration bit information in all cfg latches according to the read instruction message includes: reading the configuration bit information in all cfg latches simultaneously according to the read instruction message, or reading the configuration bit information in all cfg latches sequentially according to the read instruction message.

[0077] Specifically, the read instruction information includes a read command and a read address. The read address is determined according to the configuration bit address information. The programming method of the embodiment of the present application reads out the configuration bit information in the cfg latch by sending the read command and the read address to the cfg latch.

[0078] More specifically, the configuration bit information is represented as latch data in the cfg latch, and each cfg latch is used to record at most one configuration bit information. The read address in the read instruction information matches the cfg latch position. When the cfg latch receives the read instruction information, all the latch data is read out.

[0079] More specifically, during the process of simultaneously reading the configuration bit information in all cfg latches according to the read instruction information, the latch data in all cfg latches containing the configuration bit information is read out simultaneously, so as to ensure the data transmission efficiency and improve the programming efficiency of the programming method of the embodiment of the present application.

[0080] More specifically, during the process of sequentially reading the configuration bit information in all cfg latches according to the read instruction information, according to the flag bit (N in configN) or the latch number of the configuration bit information, the latch data in all cfg latches containing the configuration bit information is sequentially read out incrementally or decrementally, so that the process of reading and writing the configuration bit information to the sram has orderliness, and it is ensured that the configuration bit information can be accurately written into the cfg register of the flash chip in sequence.

[0081] In some preferred embodiments, the programming method further includes steps performed before the step of obtaining all configuration bit address information:

[0082] S100. Obtain flag bit information, which is used to determine whether to program the flash chip according to the configuration bit information of the cfg latch.

[0083] Specifically, the programming method of the embodiment of the present application is started according to the flag bit information, that is, when the flag bit information is generated, the programming method of the embodiment of the present application is started to program the flash chip.

[0084] More specifically, step S101 is started only after step S100 successfully obtains the effective flag bit information. For example, if the flag bit information is a high and low level signal, step S101 is started only when the flag bit information is high.

[0085] More specifically, the programming method of the embodiment of the present application is mainly used for testing whether the configuration bit information of the cfg latch can be correctly solidified in the flash chip during the CP test. Therefore, the flag bit information is generated by the CP test device according to the user's operation behavior.

[0086] For a second aspect, please refer to Figure 2 , Figure 2 which is a global configuration programming device provided in some embodiments of the present application, and is used to program a flash memory chip according to the configuration bit information of a cfg latch. The device includes a configuration register, and the configuration register includes:

[0087] An acquisition module 201, configured to acquire all configuration bit address information;

[0088] A configuration module 202, configured to generate read instruction information according to the configuration bit address information;

[0089] A read / write module 203, configured to read the configuration bit information in all cfg latches according to the read instruction information, and write all the configuration bit information into the sram, so that the controller generates programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash memory chip.

[0090] For a global configuration programming device according to an embodiment of the present application, the configuration module 202 generates read instruction information based on all the configuration bit address information acquired by the acquisition module 201, so that all the configuration bit information in all cfg latches is read and written into the sram at one time through the read / write module 203, enabling the controller to configure programming information according to the configuration bit information written in the sram at one time to program the flash memory chip. Compared with the traditional one-read-one-write programming process, multiple read commands are integrated into one-time read instruction information, simplifying the logic of writing configuration bit information and effectively improving the read / write efficiency of the configuration bit information.

[0091] For a global configuration programming device according to an embodiment of the present application, by setting the configuration register as the read / write information interaction layer between the controller and the flash memory chip, multiple read commands originally issued by the controller can be integrated into one-time read instruction information, and the configuration bit information in the cfg latch is read and written into the sram at one time for the controller to generate programming information according to the configuration bit information temporarily stored in the sram to program the flash memory chip.

[0092] In some preferred embodiments, a global configuration programming device according to the second aspect is used to execute a global configuration programming method according to the first aspect.

[0093] In some preferred embodiments, the configuration register further includes:

[0094] A first flag bit acquisition module, configured to acquire flag bit information, and the flag bit information is used to determine whether it is necessary to program the flash memory chip according to the configuration bit information of the cfg latch.

[0095] Specifically, the programming device according to the embodiments of the present application is started according to the flag bit information, that is, when the flag bit information is generated, the programming method according to the embodiments of the present application is started to program the flash memory chip. In some preferred embodiments, the configuration register is a volatile register.

[0096] In a third aspect, please refer to Figure 3 , Figure 3 which is a global configuration programming method provided in some embodiments of the present application for programming a flash memory chip according to the configuration bit information of a cfg latch. The programming method includes:

[0097] S301. Send all configuration bit address information to the configuration register, so that the configuration register generates read instruction information according to the configuration bit address information, and the configuration register reads the configuration bit information in all cfg latches according to the read instruction information to write all configuration bit information into the sram;

[0098] Specifically, compared with the traditional configuration bit information programming process, the programming method according to the embodiments of the present application hands over the process of reading and temporarily storing the configuration bit information in the cfg latch to the configuration register, and the configuration register can read and write all configuration bit information into the sram simultaneously according to all configuration bit address information, changing the originally multiple alternately issued read and programming commands into a centralized read and centralized programming command, where the centralized read command is an integrated read instruction information, which is generated and executed by the configuration register to read and write all configuration bit information into the sram at one time.

[0099] More specifically, the configuration register reads the configuration bit information in the cfg latch sequentially or simultaneously, where the configuration register reads the configuration bit information in the cfg latch simultaneously by means of parallel reading.

[0100] S302. Generate programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash memory chip.

[0101] A global configuration programming method according to the embodiments of the present application sends the configuration bit address information to the configuration register, and hands over the process of reading the configuration bit information in the cfg latch and transferring it to the sram to the configuration register. Compared with the traditional one-read-one-write programming process, the configuration register is used to integrate multiple read commands into a one-time read instruction information, simplifying the configuration bit information writing logic and effectively improving the reading and writing efficiency of the configuration bit information.

[0102] In some preferred embodiments, the step of generating programming information according to the configuration bit information in the SRAM includes: generating programming information according to the configuration bit address information and each configuration bit information in the SRAM, so that the programming information is paired with the configuration bit address information, ensuring that the corresponding configuration bit information can be successfully written into the corresponding CFG register address in the flash chip.

[0103] In some preferred embodiments, the programming information includes programming instruction information, CFG register configuration bit address information, and programming time information.

[0104] Specifically, the programming time information can be a detection time interval or a preset programming time; when the programming time information is a detection time interval, during the programming process of the flash chip, according to the programming time information, periodically detect whether the CFG register currently undergoing the programming operation has been programmed. If so, proceed with the programming of the next configuration bit information; when the programming time information is a preset programming time, during the programming process of the flash chip, program the flash chip to write a configuration bit information. After the programming time information has passed, start writing the next configuration bit information.

[0105] More specifically, the programming instruction information is a programming command. In the CP test, generally the page program command is used. Therefore, the programming method of the embodiments of the present application issues a page program command according to the programming information to write the configuration bit information into the CFG register of the flash chip.

[0106] More specifically, the programming information is generated according to the configuration bit information and the CFG register configuration bit address information, where the CFG register configuration bit address information can be obtained from the SRAM or the controller can obtain it from the programming task of the CP tester. Among them, when the configuration bit address information includes the CFG latch configuration bit address information and the CFG register configuration bit address information, the CFG register configuration bit address information is obtained from the SRAM (the CFG register configuration bit address information is written into the SRAM by step S103 or step S301).

[0107] More specifically, the generation process of the programming instruction information includes the process of packing the programming instruction information, the CFG register configuration bit address information, and the programming time information. The CFG register configuration bit address information is used for positioning the address location information that needs to be programmed in the CFG register.

[0108] In some preferred embodiments, the programming method further includes steps performed before step S301:

[0109] S300. Obtain flag bit information, and the flag bit information is used to determine whether it is necessary to program the flash chip according to the configuration bit information of the CFG latch.

[0110] Specifically, the programming method of the embodiments of the present application is started according to the flag bit information, that is, when the flag bit information is generated, the programming method of the embodiments of the present application is started to program the flash memory chip.

[0111] In a fourth aspect, please refer to Figure 4 , Figure 4 which is a global configuration programming device provided in some embodiments of the present application, used to program the flash memory chip according to the configuration bit information of the cfg latch, including a controller, and the controller includes:

[0112] A sending module 401, configured to send all configuration bit address information to a configuration register, so that the configuration register generates read instruction information according to the configuration bit address information, and the configuration register reads the configuration bit information in all cfg latches according to the read instruction information to write all configuration bit information into the sram;

[0113] A programming module 402, configured to generate programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash memory chip.

[0114] For a global configuration programming device of the embodiments of the present application, the sending module 401 is used to send all configuration bit address information to the configuration register, and the process of reading and transferring the configuration bit information in the cfg latch to the sram is executed by the configuration register. Compared with the traditional one-read-one-write programming process, the programming method of the embodiments of the present application changes the process of the controller sending read instructions one by one into a process where the configuration register integrates multiple read commands into a single read instruction information, that is, by setting the configuration register as the read-write information interaction layer between the controller and the flash memory chip, simplifies the writing logic of the configuration bit information, and effectively improves the read-write efficiency of the configuration bit information.

[0115] Specifically, the method of the embodiments of the present application executes the process of reading and transferring the configuration bit information in the cfg latch to the sram by the configuration register, and can also effectively reduce the operation load of the controller, so that the controller only needs to be responsible for generating programming information for the configuration bit information temporarily stored in the sram, and then can program the cfg register in the flash memory chip.

[0116] In some preferred embodiments, the configuration register further includes:

[0117] A second flag bit acquisition module, configured to acquire flag bit information, and the flag bit information is used to determine whether it is necessary to program the flash memory chip according to the configuration bit information of the cfg latch. In some preferred embodiments, a global configuration programming device of the fourth aspect described above is used to execute a global configuration programming method of the third aspect.

[0118] For a fifth aspect, please refer to Figure 5 , Figure 5 which is a global configuration programming system provided in some embodiments of the present application for programming a flash memory chip 505 according to the configuration bit information of a cfg latch 501. The programming system includes:

[0119] A cfg latch 501 that stores configuration bit information therein;

[0120] A controller 502 that stores configuration bit address information therein;

[0121] A configuration register 503 electrically connected to the controller 502, the cfg latch 501, and the sram 504, for generating read instruction information;

[0122] An sram 504 for temporarily storing configuration bit information;

[0123] The controller 502 is configured to send the configuration bit address information to the configuration register 503, so that the configuration register 503 generates read instruction information according to the configuration bit information;

[0124] The configuration register 503 is configured to read the configuration bit information in all cfg latches 501 according to the read instruction information and write all the configuration bit information into the sram 504;

[0125] The controller 502 is further configured to generate programming information according to the configuration bit information in the sram 504, and the programming information is used to program the cfg register in the flash memory chip 505.

[0126] Specifically, the configuration bit information in the cfg latch 501 is volatile data.

[0127] In a global configuration programming system according to an embodiment of the present application, the controller 502 is used to send all the configuration bit address information to the configuration register 503, and the process of reading and rewriting the configuration bit information in the cfg latch 501 to the sram 504 is executed by the configuration register 503. Compared with the traditional one-read-one-write programming process, in the programming system according to the embodiment of the present application, the process of the controller 502 sending read instructions one by one is changed to the configuration register 503 integrating multiple read commands into a single read instruction information, that is, by setting the configuration register 503 as the read-write information interaction layer between the controller 502 and the flash memory chip 505, the writing logic of the configuration bit information is simplified, the read-write efficiency of the configuration bit information is effectively improved, and the operating load of the controller 502 is effectively reduced.

[0128] In some preferred embodiments, both the configuration register 503 and the controller 502 are connected to the host computer, which is the control terminal of the cp test machine; when it is necessary to test the cfg latch 501, the host computer generates a programming task and generates flag bit information according to the programming task. The configuration register 503 obtains the flag bit information and changes one of its own flag bits to the flag bit information (such as data 1). When the controller 502 obtains the flag bit information in the configuration register 503, it sends the configuration bit address information to the configuration register 503 to start the global configuration programming process.

[0129] In summary, the embodiments of the present application provide a global configuration programming method, device and system. Among them, the programming method generates read instruction information based on all the obtained configuration bit address information, so as to read and write all the configuration bit information in the cfg latch into the sram at one time, so that the controller can configure the programming information according to the configuration bit information written in the sram at one time to program the flash chip. Compared with the traditional one-read-one-write programming process, multiple read commands are integrated into one-time read instruction information, which simplifies the writing logic of the configuration bit information and effectively improves the reading and writing efficiency of the configuration bit information.

[0130] In the embodiments provided by the present application, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces, and the indirect coupling or communication connection of the device or unit may be in an electrical, mechanical or other form.

[0131] In addition, the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0132] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0133] In this document, relational terms such as first and second are used solely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0134] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A global configuration programming method for programming a flash memory chip according to the configuration bit information of a cfg latch, characterized in that Applied in the configuration register, the programming method includes the following steps: Obtain all configuration bit address information; Generate read instruction information according to the configuration bit address information; Read the configuration bit information in all the cfg latches according to the read instruction information, and write all the configuration bit information into the sram, so that the controller generates programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash chip; The step of generating read instruction information according to the configuration bit address information includes: Generate read instruction information for obtaining all the configuration bit information in the cfg latch at one time according to all the obtained configuration bit address information.

2. The global configuration programming method according to claim 1, wherein The configuration bit address information includes cfg latch configuration bit address information, or includes cfg latch configuration bit address information and cfg register configuration bit address information.

3. A global configuration programming method according to claim 1, characterized in that The step of reading the configuration bit information in all the cfg latches according to the read instruction information includes: reading the configuration bit information in all the cfg latches simultaneously according to the read instruction information, or reading the configuration bit information in all the cfg latches sequentially according to the read instruction information.

4. A global configuration programming method according to claim 1, characterized in that The programming method further includes a step executed before the step of obtaining all the configuration bit address information: obtain flag bit information, and the flag bit information is used to judge whether it is necessary to program the flash chip according to the configuration bit information in the cfg latch.

5. A global configuration programming device for programming a flash memory chip according to the configuration bit information of a cfg latch, characterized in that, Including a configuration register, the configuration register includes: An acquisition module for obtaining all configuration bit address information; A configuration module for generating read instruction information according to the configuration bit address information; A read / write module for reading the configuration bit information in all the cfg latches according to the read instruction information, and writing all the configuration bit information into the sram, so that the controller generates programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash chip; The step of generating read instruction information according to the configuration bit address information includes: Generate read instruction information for obtaining all the configuration bit information in the cfg latch at one time according to all the obtained configuration bit address information.

6. A global configuration programming method for programming a flash memory chip according to the configuration bit information of a cfg latch, characterized in that, The programming method includes: Send all the configuration bit address information to the configuration register, so that the configuration register generates read instruction information according to the configuration bit address information, and the configuration register reads the configuration bit information in all the cfg latches according to the read instruction information, so as to write all the configuration bit information into the sram; Generate programming information according to the configuration bit information in the sram, and the programming information is used to program the cfg register in the flash chip; The step of generating read instruction information according to the configuration bit address information includes: Generate read instruction information for obtaining all the configuration bit information in the cfg latch at one time according to all the obtained configuration bit address information.

7. A global configuration programming method according to claim 6, characterized in that, The step of generating programming information according to the configuration bit information in the SRAM includes: generating programming information according to the configuration bit address information and each configuration bit information in the SRAM.

8. A global configuration programming method according to claim 7, wherein The programming information includes programming instruction information, cfg register configuration bit address information, and programming time information.

9. A global configuration programming device for programming a flash memory chip according to the configuration bit information of a cfg latch, characterized in that, It includes a controller, and the controller includes: A sending module, configured to send all the configuration bit address information to the configuration register, so that the configuration register generates read instruction information according to the configuration bit address information, and the configuration register reads the configuration bit information in all the cfg latches according to the read instruction information, so as to write all the configuration bit information into the SRAM; A programming module, configured to generate programming information according to the configuration bit information in the SRAM, and the programming information is used to program the cfg register in the flash chip; The step of generating read instruction information according to the configuration bit address information includes: Generating, at one time, read instruction information for obtaining all the configuration bit information in the cfg latch according to all the obtained configuration bit address information.

10. A global configuration programming system for programming a flash memory chip according to configuration bit information of a cfg latch, characterized in that, The programming system includes: The cfg latch, which stores the configuration bit information therein; A controller, which stores the configuration bit address information therein; A configuration register, electrically connected to the controller, the cfg latch, and the SRAM, and configured to generate read instruction information; The SRAM, which is used to temporarily store the configuration bit information; The controller is configured to send the configuration bit address information to the configuration register, so that the configuration register generates the read instruction information according to the configuration bit address information; The configuration register is configured to read the configuration bit information in all the cfg latches according to the read instruction information, and write all the configuration bit information into the SRAM; The controller is further configured to generate programming information according to the configuration bit information in the SRAM, and the programming information is used to program the cfg register in the flash chip; The step of generating the read instruction information according to the configuration bit address information includes: Generating, at one time, read instruction information for obtaining all the configuration bit information in the cfg latch according to all the obtained configuration bit address information.

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