A silicon wafer carrier and a preparation process for improving the damaged layer of a heavily doped double-polished wafer

Abstract

The present application belongs to the field of silicon wafer (wafer) manufacturing technology in integrated circuits, and specifically relates to a silicon wafer carrier and a preparation process for improving the damaged layer of heavily doped double-polished wafers using the carrier. Compared with the existing carrier structure, the silicon wafer carrier adds a circular groove design in the center of the existing circular slot. The specific carrier structure includes: a rectangular carrier base that bears the weight of the entire structure, and a circular slot for placing silicon wafers provided in the middle of the rectangular carrier base; a circular groove is provided on the carrier base inside the circular slot; at the same time, a positioning groove (also called a positioning pin groove) and a heat conduction groove that pass through the carrier base are provided on the carrier base inside the circular slot. The present application makes relevant improvements to the preparation process for improving the damaged layer on the front side (polishing surface) of heavily doped double-polished wafers by adjusting the structural design of the silicon wafer carrier, changing the heating of the silicon wafer to convection and radiation, and combining this equipment improvement, thereby effectively reducing the particles on the surface of the silicon wafers.

Description

Technical Field

[0001] The present application belongs to the technical field of silicon wafer manufacturing in integrated circuits, and specifically relates to a silicon wafer carrier and a preparation process for improving the damaged layer of a heavily doped double-polished wafer using the carrier. Background Art

[0002] In existing technologies, silicon wafers (wafers) have different specifications based on size, such as 8 inches (200mm), 12 inches (300mm), and 18 inches (450mm). Due to factors such as manufacturing technology difficulty, preparation cost and benefit ratio, the current mainstream silicon wafer (wafer) specification for chip preparation is 12 inches.

[0003] From the perspective of silicon wafer preparation, there are two types of wafers: lightly doped and heavily doped, depending on the doping level (determined by resistivity after doping). Limited by market demand and production costs, lightly doped P-type silicon wafers currently dominate the market. However, with strong market demand for power devices and other components, demand for heavily doped silicon wafers is increasing.

[0004] In actual silicon wafer fabrication, heavily doped silicon wafers, due to their high dopant concentrations, exhibit relatively weak internal gettering during subsequent thermal processing, resulting in insufficient control over impurity capture during device manufacturing. In particular, in processes involving high-temperature thermal cycling, impurities within the substrate (silicon wafer) can easily diffuse into the device's active area, leading to device failure. To overcome this technical challenge and improve device manufacturing yield, heavily doped substrates often require the introduction of external gettering structures on the backside (unpolished) of the wafer to meet impurity gettering requirements. External gettering involves damaging impurities or depositing polycrystalline silicon on the backside (unpolished) surface, introducing secondary defects after thermal treatment to achieve impurity gettering. Based on this design concept, existing silicon wafer backside (unpolished) surface treatment technologies primarily involve directly creating a damaged layer or a thick layer of polysilicon or dense oxide on the backside (unpolished) of the wafer, thereby damaging the backside (unpolished) surface to achieve the desired gettering effect.

[0005] In the prior art, silicon wafers are generally transported using belt-type or tray-type equipment. During the tray-type wafer transport process, heat conduction, heat radiation, or convection are used between the tray and the silicon wafer, and between the reaction chamber and the wafer to ensure the uniformity and consistency of the temperature on the front (polished) and back (unpolished) surfaces of the silicon wafers. However, during this process, since the oxide layer deposition process on the back (unpolished) surface of the heavily doped silicon wafer is usually prepared by vapor deposition, the front (polished) surface of the silicon wafer will contact the tray when the oxide layer is deposited. As a result, the heat transfer during the silicon wafer transport process can easily lead to the deepening of the damage layer on the front (polished) surface of the silicon wafer. This further makes it impossible to completely remove the damaged layer on the silicon wafer surface during the subsequent silicon wafer polishing process, resulting in the inability to effectively reduce the particle defects on the polished surface of the silicon wafer, and the surface cleanliness of the silicon wafer cannot meet customer requirements.

[0006] To overcome the aforementioned surface damage problem on heavily doped silicon wafers, using other technical approaches, such as increasing the polishing removal to completely remove the damaged layer on the front (polished) side of the wafer, can easily deteriorate the wafer's flatness, failing to meet customer requirements while also increasing production costs. Therefore, effectively minimizing surface damage on heavily doped silicon wafers during the deposition process on the back (unpolished) side, within relevant production lines, is crucial for improving the quality of related products. Summary of the Invention

[0007] The purpose of this application is to provide a silicon wafer carrier and a preparation process for improving the damaged layer on the front side (polishing surface) of a heavily doped double-polished wafer using the carrier, thereby laying a certain technical foundation for the quality stability of related silicon wafers (wafers).

[0008] The technical solutions adopted in this application are detailed as follows:

[0009] A silicon wafer carrier, compared to the existing carrier structure, has a circular groove added to the center of the existing circular slot. Specifically:

[0010] The carrier structure includes: a rectangular carrier base as the load-bearing base of the entire structure, and a circular slot for placing silicon wafers in the middle of the rectangular carrier base;

[0011] A circular groove is provided on the bearing base inside the circular card slot; at the same time, a positioning groove (also called a positioning pin groove) and a heat conduction groove that pass through the bearing base are provided on the bearing base inside the circular card slot;

[0012] The positioning groove is a through hole through which a positioning "pin" (positioning pin) passes to raise and lower the silicon wafer. In actual design, in order to accurately adjust the placement of the silicon wafer, the positioning grooves are evenly distributed along the supporting base inside the circular card slot. For example, there are three positioning grooves designed, and the three positioning grooves are located on the same circumference line, and the angle between two adjacent positioning grooves is 120 degrees.

[0013] The heat conduction groove is a through hole used to enhance the heat radiation to the front side (polished surface) of the silicon wafer, and is used to ensure the uniformity of the temperature at the edge and center of the silicon wafer, so as to improve and enhance the uniformity of the deposition thickness during the thin film deposition process. In the actual design, in order to enhance the uniformity of heat radiation, the heat conduction grooves are evenly arranged on the supporting base inside the circular card slot. For example, there are 9 heat conduction grooves designed, one of which is located at the center of the circular card slot, and the remaining 8 are arranged around this center to form a square.

[0014] In specific applications, the front side (polished side) of the silicon wafer is placed in the card slot with the front side (polished side) facing down, and chemical vapor deposition is performed on the back side (non-polished side) of the silicon wafer in the carrier.

[0015] The silicon wafer carrier is made of silicon materials such as silicon carbide, silicon nitride, and polysilicon, so as to prevent the carrier from contaminating the silicon wafer when chemical vapor deposition is performed on the back side (non-polished side) of the silicon wafer. The material is preferably polysilicon.

[0016] When designing specific specifications, the circular slot depth A1 can be designed to be 5.5mm~7.5mm (preferably A1: 6.35mm), and the circular slot inner diameter Φ1 can be designed to be 300~305mm (preferably Φ1: 302mm) to accommodate silicon wafers with a diameter of 300mm but different thicknesses.

[0017] The depth B1 of the central circular groove can be designed to be 3.0mm-6.0mm (preferably B1: 3.54mm), and the inner diameter Φ2 of the circular groove can be designed to be 200mm-280mm (preferably Φ2: 220mm). This prevents the center of the front (polished) surface of a 300mm diameter silicon wafer from directly contacting the carrier plate, while also allowing a certain width to be reserved at the edge of the silicon wafer to facilitate the support of the carrier base on the silicon wafer.

[0018] The diameter of the heat conduction slot Φ3 can be designed to be 0.5mm~1.5mm (preferably Φ3: 1.0mm), and the diameter of the positioning slot Φ4 can be designed to be 2.0mm~3.0mm (preferably Φ4: 2.5mm).

[0019] The rectangular supporting base can be adjusted appropriately according to the size of the deposition reaction chamber, but is generally rectangular with the following specifications: length: 310~320mm, width: 470~500mm; for example, the specific design is: length: 315.5mm, width: 489mm.

[0020] The process for preparing the damaged layer on the front side (polished side) of a heavily doped double-polished silicon wafer using the improved silicon wafer carrier is mainly used to prepare a 300mm heavily doped double-polished silicon wafer with backside gettering capability, and specifically comprises at least the following steps:

[0021] (1) Slicing, chamfering, and double-sided grinding

[0022] For operations such as slicing, chamfering, and double-sided grinding, refer to existing technologies. For details, refer to the following:

[0023] Slicing: Wire cutting technology is used to cut the oriented crystal ingot into silicon wafers. During the slicing process, attention should be paid to controlling the warpage and stress distribution of the silicon wafers after slicing, and controlling the silicon wafer morphology and the depth of the introduced crystal defects during wire cutting.

[0024] Chamfering: Silicon wafer chamfering is a process in which the edges of the silicon wafer are ground with a grinding wheel to remove sharp corners and minor damage to the wafer after slicing. This prevents chipping and cracking caused by sharp edges of the silicon wafer. Therefore, in actual operation, the appropriate grinding wheel angle is used according to the device process requirements to grind the silicon wafer edge into a specific chamfer shape.

[0025] Double-sided grinding: Double-sided grinding of silicon wafers involves slowly feeding the grinding wheel at high speed, utilizing the high-speed rotational force of the grinding wheel to cut the surface of the silicon wafer. This is used to remove surface stress damage (about 20-50 μm in depth) and impurity contamination such as metal ions on the surface of the silicon wafer caused by cutting during the slicing process, thereby achieving a flat surface with a certain geometric accuracy.

[0026] (2) Polishing

[0027] Before deposition on the back side (non-polished side) of heavily doped silicon wafers, it is necessary to ensure that the surface is clean and relatively flat. Therefore, the silicon wafers need to be polished. The polishing process includes but is not limited to: edge polishing, double-side polishing, edge secondary polishing, etc.

[0028] In the polishing process, silicon wafer polishing usually adopts a polishing technology that combines mechanical and chemical treatments. That is, with the appropriate polishing slurry and mechanical polishing process parameters, the silicon wafer surface will be polished to atomic-level flatness by the matched chemical and mechanical forces, thus providing a perfect silicon wafer surface for devices;

[0029] In the relevant process processing, according to the device process requirements, you can choose the existing technology processing;

[0030] (3) Backside (non-polished) deposition

[0031] When chemical deposition is performed on the front side (polished side) of the silicon wafer after polishing in step (2), a chemical vapor deposition process is adopted to deposit and prepare a low-temperature oxide layer;

[0032] The thickness of the prepared low-temperature oxide layer is 800 Å~14000 Å, and the uniformity is <3%;

[0033] During chemical vapor deposition, the rotation speed of the carrier containing the silicon wafer is: 100mm / min~300mm / min;

[0034] The chemical vapor deposition process is chemical vapor deposition under SiH4 / O2 atmosphere and atmospheric pressure;

[0035] It should be noted that because the reaction conditions are atmospheric pressure, chemical vapor deposition must be controlled within the "gas phase transport limit" area. Therefore, its chamber design must ensure equal flow on each silicon wafer surface. Therefore, the silicon wafers are placed horizontally. The specific operation is as follows:

[0036] (1) Place the front side (polished side) of the silicon wafer downward on a silicon wafer carrier (designed in this application) using a robotic arm; and transport the carrier with the silicon wafer to the reaction chamber via a transport system;

[0037] (2) The heating temperature of the heating unit corresponding to the bottom of the silicon wafer carrier is 650-750℃, and the surface temperature of the silicon wafer (silicon wafer) is maintained at 300-600℃ through heat conduction from the carrier;

[0038] (3) The reactants are deposited on the surface of the silicon wafer (silicon wafer) through the nozzle of the reaction chamber to prepare a low-temperature oxide layer; during the chemical deposition process, the thickness of the low-temperature oxide layer accumulated on the back side (non-polished side) of the silicon wafer is adjusted by adjusting the flow rate of the reaction gas and the speed of the carrier;

[0039] (IV) Polishing and inspection of the front (polished surface)

[0040] After the deposition on the back side (non-polished side) of the silicon wafer is completed, the front side (polished side) of the silicon wafer is polished, and the silicon wafer is cleaned and tested to obtain the improved damaged layer on the front side (polished side) of the heavily doped double-polished silicon wafer.

[0041] In combination with the low-temperature oxide layer deposition process on the back side (non-polished side) of heavily doped silicon wafers, this application has made targeted designs for silicon wafer carriers. By adjusting the structural design of the silicon wafer carrier and changing the heating of the silicon wafers to convection and radiation, and combining this equipment improvement, relevant improvements have been made to the preparation process of improving the damaged layer on the front side (polished side) of the heavily doped double-polished wafers. Through these improvements, the generation of a damaged layer on the front side (polished side) can be better avoided, which leads to the problem of central defect aggregation after the final polishing, and better silicon wafer surface cleanliness can be obtained. Ultimately, the technical effect of effectively reducing the particle condition on the silicon wafer surface is achieved without changing the polishing process and removal amount. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A top view of the silicon wafer carrier provided in this application;

[0043] Figure 2 A longitudinal cross-sectional view of the silicon wafer carrier provided in this application;

[0044] Figure 3 These are the results of particle detection on the surface of silicon wafers after vapor deposition and polishing using new and old silicon wafer carriers. The upper picture shows the processing effect using the existing carrier, and the lower picture shows the processing effect using the carrier of this application. DETAILED DESCRIPTION

[0045] The present application will be further explained below with reference to the following examples. Before introducing the specific examples, a brief description of some experimental backgrounds in the following examples is given below.

[0046] Example 1

[0047] like Figure 1 、 Figure 2 As shown, the silicon wafer carrier provided by the present application has a design that adds a circular groove 2 in the center of the existing circular slot 1, compared to the existing carrier structure. Specifically:

[0048] The carrier structure includes: a rectangular carrier base 5 as the load-bearing member of the entire structure, and a circular slot 1 provided in the middle of the rectangular carrier base 5 for placing the silicon wafer;

[0049] A circular groove 2 is provided on the supporting base inside the circular card slot 1; at the same time, a positioning groove 4 (also called a positioning pin groove) and a heat conduction groove 3 are provided on the supporting base 5 inside the circular card slot 1.

[0050] The positioning slots 4 are through-holes through which the positioning pins pass to raise and lower the silicon wafer. In actual design, to accurately adjust the placement of the silicon wafer, the positioning slots 4 are evenly distributed along the supporting base inside the circular slot. For example, there are three positioning slots designed, and the three positioning slots are located on the same circumference, with the angle between two adjacent positioning slots being 120°.

[0051] The heat conduction groove 3 is a through hole used to enhance the heat radiation to the front side (polished surface) of the silicon wafer, and is used to ensure the uniformity of the temperature at the edge and center of the silicon wafer, so as to improve and enhance the uniformity of the deposition thickness during the thin film deposition process. In the actual design, in order to enhance the uniformity of heat radiation, the heat conduction grooves are evenly arranged on the supporting base inside the circular card slot. For example, there are 9 heat conduction grooves designed, one of which is located at the center of the circular card slot, and the remaining 8 are arranged around this center to form a square.

[0052] In specific applications, the front side (polished side) of the silicon wafer is placed in the card slot with the front side (polished side) facing down, and chemical vapor deposition is performed on the back side (non-polished side) of the silicon wafer in the carrier.

[0053] The silicon wafer carrier is made of silicon materials such as silicon carbide, silicon nitride, and polysilicon, so as to prevent the carrier from contaminating the silicon wafer when chemical vapor deposition is performed on the back side (non-polished side) of the silicon wafer. The material is preferably polysilicon.

[0054] When designing specific specifications, the depth A1 of the circular slot 1 can be designed to be 5.5mm~7.5mm (preferably A1: 6.35mm), and the inner diameter Φ1 of the circular slot can be designed to be 300~305mm (preferably Φ1: 302mm) to accommodate silicon wafers with a diameter of 300mm but different thicknesses;

[0055] The depth B1 of the central circular groove 2 can be designed to be 3.0mm-6.0mm (preferably B1: 3.54mm), and the inner diameter Φ2 of the circular groove can be designed to be 200mm-280mm (preferably Φ2: 220mm). This prevents the center of the front (polished) surface of a 300mm diameter silicon wafer from directly contacting the carrier plate, while also allowing a certain width to be reserved at the edge of the silicon wafer to facilitate the support of the carrier base on the silicon wafer.

[0056] The diameter Φ3 of the heat conduction groove 3 can be designed to be 0.5 mm to 1.5 mm (preferably Φ3: 1.0 mm), and the diameter Φ4 of the positioning groove 4 can be designed to be 2.0 mm to 3.0 mm (preferably Φ4: 2.5 mm).

[0057] The rectangular supporting base 5 can be adjusted appropriately according to the size of the deposition reaction chamber, but is generally rectangular with the following specifications: length 310-320 mm, width 470-500 mm; specifically, the design is: length 315.5 mm, width 489 mm.

[0058] In general, the main design idea of the silicon wafer carrier provided in this application is: by adding circular grooves, the contact area between the carrier base and the front side (polished surface) of the silicon wafer is changed, and then the preparation effect of the low-temperature oxide layer prepared during subsequent chemical vapor deposition is improved by improving heat conduction.

[0059] Example 2

[0060] Using the silicon wafer carrier prepared in Example 1, this application further provides a process for improving the damaged layer on the front (polished) surface of heavily doped silicon wafers. This process is primarily used to prepare 300mm heavily doped silicon wafers with backside gettering capability. The specific process is briefly described below.

[0061] (1) Slicing, chamfering, and double-sided grinding

[0062] For operations such as slicing, chamfering, and double-sided grinding, refer to existing technologies. For details, refer to the following:

[0063] Slicing: Wire cutting technology is used to cut the oriented crystal ingot into silicon wafers. During the slicing process, attention should be paid to controlling the warpage and stress distribution of the silicon wafers after slicing, and controlling the silicon wafer morphology and the depth of the introduced crystal defects during wire cutting.

[0064] Chamfering: Silicon wafer chamfering is a process in which the edges of the silicon wafer are ground with a grinding wheel to remove sharp corners and minor damage to the wafer after slicing. This prevents chipping and cracking caused by sharp edges of the silicon wafer. Therefore, in actual operation, the appropriate grinding wheel angle is used according to the device process requirements to grind the silicon wafer edge into a specific chamfer shape.

[0065] Double-sided grinding: Double-sided grinding of silicon wafers is a process in which a high-speed rotating grinding wheel is gradually and slowly fed in, and the high-speed rotation force of the grinding wheel is used to cut the surface of the silicon wafer. It is used to remove surface stress damage of about 20~50μm in depth caused by cutting on the silicon wafer surface during the slicing process and impurity contamination such as metal ions on the surface, so that the silicon wafer has a flat surface with a certain geometric accuracy.

[0066] It needs to be further explained that the crystal rods described in this application are heavily doped crystal rods, which mainly refer to the crystal orientation of <100> Or the crystal direction is <111> The resistance of heavily phosphorus-doped and heavily arsenic-doped single crystal rods is less than 1Ω -cm .

[0067] (2) Polishing

[0068] Before deposition on the back side (non-polished side) of heavily doped silicon wafers, it is necessary to ensure that the surface is clean and relatively flat. Therefore, the silicon wafers need to be polished. The polishing process includes but is not limited to: edge polishing, double-side polishing, edge secondary polishing, etc.

[0069] In the polishing process, silicon wafer polishing usually adopts a polishing technology that combines mechanical and chemical treatments. That is, with the appropriate polishing slurry and mechanical polishing process parameters, the silicon wafer surface will be polished to atomic-level flatness by the matched chemical and mechanical forces, thus providing a perfect silicon wafer surface for devices;

[0070] In the relevant process processing, existing technology can be selected according to the device process requirements.

[0071] (3) Backside (non-polished) deposition

[0072] It should be noted that since this application primarily adjusts the backside (non-polished) deposition process in conjunction with a silicon wafer carrier, the aforementioned key process flows, including ingot slicing, chamfering, double-side grinding, edge polishing, double-side polishing, secondary edge polishing, and subsequent edge etching, final frontside (polished) polishing, cleaning, and testing, can be referred to in the prior art and will not be elaborated upon. The following is a brief introduction to some chemical vapor deposition process parameters and operations.

[0073] When chemical deposition is performed on the front side (polished surface) of the polished silicon wafer (12-inch size) in step (2), a low-temperature oxide layer is prepared by chemical vapor deposition using the new carrier designed in Example 1 in combination with a back side (non-polished surface) deposition device (chemical vapor deposition equipment using carrier transport).

[0074] In this embodiment, the thickness of the prepared low-temperature oxide layer is 4800 Å, and the uniformity is <3%;

[0075] The chemical vapor deposition process is carried out in a SiH4 / O2 atmosphere (generally, the volume ratio of SiH4:O2 is 1-5:9-4. In practice, the volume ratio of SiH4:O2 can be adjusted accordingly according to the thickness of the film to be deposited and the movement speed of the carrier. In this embodiment, chemical vapor deposition is carried out under the conditions of SiH4:O2=1:9 and atmospheric pressure). The specific preparation process is as follows:

[0076] (1) After the silicon wafer is taken out from the "silicon wafer basket" (Cassette) by a robotic arm, it is placed on the silicon wafer carrier (designed in this application) with the front side (polished side) facing down; the carrier with the silicon wafer is transported to the reaction chamber through a conveyor system;

[0077] (2) The heating temperature of the heating unit corresponding to the bottom of the silicon wafer carrier is 650-750°C (700°C is selected in this embodiment), and the surface temperature of the silicon wafer is generally maintained at about 400°C to 500°C (controlled at about 450°C in this embodiment) through heat conduction from the carrier.

[0078] (3) The reactants are deposited on the surface of the silicon wafer (silicon wafer) through the nozzle (injector) of the reaction chamber to prepare a low-temperature oxide layer; during the chemical deposition process, the thickness of the low-temperature oxide layer accumulated on the back side (non-polished side) of the silicon wafer is adjusted by adjusting the flow rate of the reaction gas and the speed of the carrier;

[0079] In this embodiment, the rotation speed of the carrier containing the silicon wafer is controlled to be: 150mm / min;

[0080] (4) When the thickness of the accumulated oxide layer on the back side (non-polished side) of the silicon wafer reaches the predetermined value, the carrier on which the silicon wafer is placed is sent back through the conveyor system, and the silicon wafer is placed in the cooling slot by a robotic arm. After the silicon wafer cools to room temperature, the robotic arm places the silicon wafer back into the cassette.

[0081] (IV) Polishing and inspection of the front (polished surface)

[0082] After the deposition on the back side (non-polished side) of the silicon wafer is completed, the subsequent edge etching and polishing of the front side (polished side) of the silicon wafer are carried out according to the existing processing technology. The final polishing removal of the front side (polished side) of the silicon wafer is kept at about 1μm. The silicon wafer is cleaned to remove impurities such as polishing liquid, particles, and metal on the surface of the silicon wafer. Finally, the surface (front, polished side) of the silicon wafer is inspected for particles using an SP3 particle detector (product of KLA Corporation, USA). The results are shown in Tables 1 and 2. Figure 3 shown.

[0083] The same process as above was used to perform chemical vapor deposition using the existing silicon wafer carrier (i.e., only the circular groove 2 was missing). The surface particles are shown in Table 1 and Figure 3 shown.

[0084] Table 1. Comparison of the processing results of the modified silicon wafer carrier and the original silicon wafer carrier.

[0085] .

[0086] By comparison, it can be seen that at different particle size levels, after using the silicon wafer carrier provided by this application, the heat dissipation is improved, thereby effectively reducing the number of particles on the front side (polished surface) after polishing, thereby helping to improve the uniformity, flatness and other indicators during the vapor deposition process.

Claims

1. A silicon wafer carrier for preparing a front damaged layer of a heavily doped double-polished silicon wafer, characterized in that: A circular groove is designed in the center of the circular slot. The specific carrier structure includes: a rectangular bearing base as the load-bearing base of the entire structure, and a circular slot for placing the silicon wafer in the middle of the rectangular bearing base; A circular groove is provided on the bearing base inside the circular slot; at the same time, a positioning groove and a heat conduction groove penetrating the bearing base are provided on the bearing base inside the circular slot; The positioning groove is a through hole through which the positioning "needle" passes to raise and lower the silicon wafer; The heat conduction groove is a through hole used to enhance heat radiation to the front side of the silicon wafer; The positioning grooves are evenly distributed on the bearing base inside the circular card slot. There are three positioning grooves designed. The three positioning grooves are located on the same circumference line, and the angle between two adjacent positioning grooves is 120 degrees. The heat conduction grooves are evenly distributed on the supporting base inside the circular card slot. There are 9 heat conduction grooves, one of which is located at the center of the circular card slot, and the other 8 are arranged around the center to form a square. When designing specific specifications, the circular slot depth A1 is designed to be 5.5mm~7.5mm, and the circular slot inner diameter Φ1 is designed to be 300~305mm; The depth B1 of the central circular groove is designed to be 3.0mm~6.0mm, and the inner diameter Φ2 of the circular groove is designed to be 200mm~280mm; the diameter Φ3 of the heat conduction groove is designed to be 0.5mm~1.5mm, and the diameter Φ4 of the positioning groove is designed to be 2.0mm~3.0mm; the rectangular bearing base is rectangular, with specifications: length: 310~320mm, width: 470~500mm.

2. The silicon wafer carrier for preparing a front damaged layer of a heavily doped double-polished silicon wafer as claimed in claim 1, characterized in that: The silicon wafer carrier is made of silicon carbide, silicon nitride or polysilicon.

3. The silicon wafer carrier for preparing a front damaged layer of a heavily doped double-polished silicon wafer as claimed in claim 1, characterized in that: The silicon wafer is a 300mm heavily doped double-polished silicon wafer.

4. A process for preparing an improved front damaged layer of a heavily doped double-polished silicon wafer using the silicon wafer carrier according to any one of claims 1 to 3, characterized in that: This process is used to prepare 300mm heavily doped double-polished silicon wafers with a back-side gettering structure. During the preparation process, a chemical vapor deposition process is used to deposit a low-temperature oxide layer on the back side of the silicon wafer. The thickness of the prepared low-temperature oxide layer is 800 Å~14000 Å, and the uniformity is <3%; During chemical vapor deposition, the rotation speed of the carrier containing the silicon wafer is: 100mm / min~300mm / min; The chemical vapor deposition process is chemical vapor deposition in a SiH4 / O2 atmosphere under an atmospheric pressure. During the deposition process, the surface temperature of the silicon wafer is maintained at 300-600°C.

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