H-shaped fin silicon structure ESD protection device applied to SOI-FinFET process

Abstract

The application relates to an integrated circuit electrostatic protection reliability design in the field of semiconductor technology, in particular to an H-shaped fin silicon structure ESD protection device applied to an SOI-FinFET process; a longitudinal fin silicon, a transverse fin silicon, a dielectric and a gate electrode are prepared based on an SOI substrate; the longitudinal fin silicon comprises longitudinal fin silicon one and longitudinal fin silicon two; the longitudinal fin silicon one comprises two kinds of doped regions of first and second semiconductor types, the longitudinal fin silicon two is of the second semiconductor type, the transverse fin silicon is of the second semiconductor type, the longitudinal fin silicon one, the longitudinal fin silicon two and the transverse fin silicon three jointly form an H-shaped fin silicon structure and are electrically connected, and a carrier control region is only a part of the longitudinal fin silicon one, the longitudinal fin silicon two and the transverse fin silicon; a novel ESD protection device can be implemented under the SOI-FinFET process, the device is different from a substrate under an insulating layer which must be used in the electrostatic protection technology related to the Bulk-FinFET process, and a good electrostatic protection method is provided for the SOI-FinFET process.

Description

Technical Field

[0001] This invention relates to the electrostatic discharge (ESD) protection reliability design of integrated circuits in the field of semiconductor technology, specifically an ESD protection device for H-type fin silicon structures applied in SOI-FinFET processes. Background Technology

[0002] As semiconductor device dimensions continue to shrink, transistor channels are also shortening. When the feature size of integrated circuit manufacturing processes shrinks proportionally to 22nm, the short-channel effect becomes increasingly severe. Simply relying on techniques such as increasing channel doping concentration, reducing source-drain junction depth, and decreasing gate oxide thickness to mitigate the short-channel effect of traditional planar transistor structures has reached a bottleneck, with subthreshold current becoming a major obstacle to further process development. Although increasing the channel doping concentration can suppress the short-channel effect to some extent, highly doped channels increase Coulomb scattering, reducing carrier mobility and further decreasing device speed. For traditional MOSFETs, electrons can freely travel between the source and drain, rendering the transistor ineffective as a switch. FinFETs emerged in processes below 45nm and are now widely used in processes below 14nm, representing a novel three-dimensional semiconductor structure. This three-dimensional structure effectively overcomes the increasingly significant short-channel effect resulting from the decreasing size of planar MOSFETs. By controlling the channel from three sides, it significantly improves channel control and reduces leakage current.

[0003] Currently, the mainstream FinFET technologies include two main categories: Bulk (silicon-on-solar) FinFET and SOI (silicon-on-insulator) FinFET. Due to the presence of a buried oxide layer, fabricating FinFETs on an SOI substrate is relatively easy, and the natural electrical isolation between the source and drain, and between devices, effectively suppresses leakage current and avoids latch-up effects. The devices also exhibit lower latency and dynamic power consumption. However, the electrostatic discharge (ESD) protection of SOI-FinFETs presents a significant challenge.

[0004] First, FinFET process technology is incompatible with planar MOSFET process technology. FinFET front-end process uses a three-dimensional structure, including HKMG and strained silicon technologies, while the back-end is a damascus copper process. Traditional MOSFET electrostatic discharge (ESD) protection methods are no longer suitable for FinFET process technology.

[0005] Secondly, because the area of ​​silicon material through which current flows in FinFET devices is very small, the probability of one or more channels burning out due to thermal breakdown is very high, leading to a rapid decline in overall ESD protection performance. Regarding FinFET ESD protection devices, the technologies disclosed in various existing FinFET ESD-related patents (CN201310042256.4, CN201810126004.2, CN201880001727.8, US15285985, US13690179, US14450612, PCT / CN2018 / 106323) all utilize the substrate layer as the active region to form various ESD protection devices. However, for SOI-FinFET devices, due to the presence of the insulating layer, these methods are ineffective.

[0006] Therefore, existing technologies need to find new and effective electrostatic discharge protection devices for SOI-FinFET type devices. Summary of the Invention

[0007] To address this issue, this invention proposes an H-type fin silicon structure ESD protection device for SOI-FinFET process, which can effectively solve the electrostatic protection problem of SOI-FinFET devices.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: an ESD protection device for an H-type fin silicon structure applied in SOI-FinFET process, comprising:

[0009] Based on an SOI substrate, longitudinal fin silicon, lateral fin silicon, dielectric, and gate electrode are fabricated. The longitudinal fin silicon includes longitudinal fin silicon one and longitudinal fin silicon two. Longitudinal fin silicon one contains doped regions of two types of semiconductors, namely type I and type II. Longitudinal fin silicon two is of type II semiconductor, and lateral fin silicon is of type II semiconductor. The three longitudinal fin silicons together form an H-type fin silicon structure and are electrically connected. The carrier control region is only a part of longitudinal fin silicon one, longitudinal fin silicon two, and lateral fin silicon. Parasitic ESD protection devices are formed in longitudinal fin silicon one, and longitudinal fin silicon two and lateral fin silicon act as bodies to fix the potentials of the two types of semiconductors of type II.

[0010] Preferably, the SOI substrate can be prepared using oxygen implantation isolation, bonding method, and Smart Curt standard process methods, and the longitudinal fin silicon and the transverse fin silicon can be perpendicular to each other and electrically connected.

[0011] Preferably, the dielectric can be a high-k dielectric of hafnium-based oxide, and the gate electrode can be a composite gate of polysilicon gate and metal gate.

[0012] Preferably, the longitudinal fin silicon includes doped regions of two semiconductor types, a first type and a second type. A channel region of appropriate first semiconductor type doping is formed in the region of the longitudinal fin silicon directly below the dielectric after channel doping. The source / drain regions of the first semiconductor type are formed on both sides of the longitudinal fin silicon by dielectric self-alignment doping, and a channel region of appropriate first semiconductor type doping is formed in the region of the longitudinal fin silicon directly below the dielectric. The heavily doped regions of the first semiconductor type form ohmic contacts, and the regions are covered with metal silicides and connected to the landpad to form source / drain electrodes.

[0013] Preferably, the longitudinal fin silicon is of the second type of semiconductor. Through channel doping, a channel region of appropriate first type semiconductor doping is formed in the region of the longitudinal fin silicon located directly below the dielectric. Through dielectric self-alignment doping, source and drain regions of second type semiconductor heavily doped are formed on both sides of the longitudinal fin silicon. The second type semiconductor heavily doped regions form ohmic contacts, which are selectively led out through metal silicides.

[0014] Preferably, on a cross-section parallel to and passing through the transverse fin silicon, the carrier control region is only a part of the longitudinal fin silicon one, the longitudinal fin silicon two, and the transverse fin silicon; in the uncontrolled region of the gate electrode inside the fin silicon, an NPN or PNP type parasitic BJT can be formed in the longitudinal fin silicon one as an ESD protection device, or a parasitic SCR can be formed as an ESD protection device, and the longitudinal fin silicon two and the transverse fin silicon serve as a body to draw out the base potential of the parasitic BJT or the corresponding potential of the parasitic SCR.

[0015] The H-type fin silicon structure ESD protection device of the present invention, applied to SOI-FinFET process, can achieve the following beneficial effects:

[0016] 1. A novel ESD protection device can be implemented under the SOI-FinFET process. Unlike the electrostatic protection technology related to the Bulk-FinFET process, which requires the use of a substrate under the insulating layer, this device provides a good electrostatic protection method for the SOI-FinFET process.

[0017] 2. Through the content disclosed in this invention, a large-scale fin silicon array with a fixed base region for electrostatic discharge protection can be implemented under SOI-FinFET process, overcoming the inherent poor thermal conductivity of FinFET and achieving excellent electrostatic discharge protection performance.

[0018] 3. The novel ESD protection device obtained by implementing the SOI-FinFET process according to the content disclosed in this invention has good compatibility with the SOI-FinFET manufacturing process and low implementation cost; at the same time, it reduces the sensitivity to slight process changes and different batches and has good manufacturing stability. Attached Figure Description

[0019] Figure 1 This is a 3D schematic diagram of a standard SOI-FinFET device;

[0020] Figure 2 These are three views of a standard SOI-FinFET device;

[0021] Figure 3A This is a three-dimensional schematic diagram of the basic form of the H-type fin silicon structure ESD protection device applied to SOI-FinFET process;

[0022] Figure 3B This is a three-dimensional schematic diagram of the application form of the H-type fin silicon structure ESD protection device in SOI-FinFET process provided by the embodiments of the present invention.

[0023] Figure 4A These are three views of the basic form of the H-type fin silicon structure ESD protection device applied to SOI-FinFET process;

[0024] Figure 4B This is a three-view drawing of an H-type fin silicon structure ESD protection device applied to SOI-FinFET process;

[0025] Figure 5A This is a front view of a standard SOI-FinFET device;

[0026] Figure 5B This is a front view of the basic form of the H-type finned silicon structure ESD protection device.

[0027] Figure 5C This is a front view of the application form of the H-type fin silicon structure ESD protection device;

[0028] Figure 6 This is an electrical equivalent schematic diagram of an H-type finned silicon structure ESD protection device;

[0029] Figure 7 This is a schematic diagram of a large-scale array of H-type fin silicon structure ESD protection devices.

[0030] Figure 8 This is a schematic diagram of the key process steps of the ESD protection device when it is compatible with SOI-FinFET technology. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0032] Combination Figure 1 and2 As shown, the active region of an SOI-FinFET device is located within the silicon film of an SOI structure, which is part of the SOI structure composed of silicon substrates 100 and 200 and insulating layers 110 and 210. Through FinFET processing, fin silicon structures 120, 121, 220, and 221, dielectrics 140, 141, 240, and 241, and gate electrodes 130, 131, 230, and 231 are fabricated in the silicon film, forming a standard SOI-FinFET device. The vertical fin silicon structures 120 and 220 contain doped regions of both type I and type II semiconductors. Through channel doping, a channel region of appropriate type I semiconductor doping is formed in the area of ​​the fin silicon structures 120 and 220 directly below the dielectrics 140 and 240. The concentration of this doping region affects the turn-on threshold and is determined by the standard SOI-FinFET process. Through self-aligned doping of the dielectrics 140 and 240, heavily doped source / drain regions of type I semiconductor are formed on both sides of the fin silicon structures 120 and 220. The first type of semiconductor, heavily doped regions form ohmic contacts, selectively formed via metal silicide extraction. Fin silicon 121 and 221 are of the second type of semiconductor; through channel doping, appropriately doped channel regions of the first type of semiconductor are formed in the region of the vertical fin silicon directly below the dielectric. The concentration of this doping region affects the turn-on threshold, determined by the standard SOI-FinFET process. Through self-aligned doping of dielectrics 141 and 241, heavily doped source / drain regions of the second type of semiconductor are formed on both sides of fin silicon 121 and 221. The heavily doped regions of the second type of semiconductor form ohmic contacts, selectively formed via metal silicide extraction.

[0033] In this embodiment, the first type of semiconductor is an N-type semiconductor, and the second type of semiconductor is a P-type semiconductor. Thus, the silicon fins 120 and 220, dielectrics 140 and 240, and gate electrodes 130 and 230 form an N-type MOSFET structure, while the silicon fins 121 and 221, dielectrics 141 and 241, and gate electrodes 131 and 231 form a P-type MOSFET structure. These two components constitute the basic circuit structure unit of a standard SOI-FinFET device, which operates normally without electrostatic discharge (ESD) shock and is the target of protection provided by this invention. In FinFET processes below 22nm, dielectrics 140, 141, 240, and 241 are generally high-k dielectrics, and gate electrodes 130, 131, 230, and 231 are composite gates of polysilicon and metal. The focus of this invention is on the characteristic structure of the device; specific differences are determined by the standard process used.

[0034] Combination Figure 2 , Figure 3A and Figure 3BA structure consisting of vertical fin silicon layers 320, 321, 322, 323, and 324, horizontal fin silicon layers 325, 326, and 327, dielectric layers 340 and 341, and gate electrodes 330 and 331 is fabricated in a silicon film to form an H-type fin silicon structure ESD protection device for use in SOI-FinFET technology. The vertical fin silicon layers contain doped regions of both type I and type II semiconductors. Through channel doping, a channel region of appropriate type I semiconductor doping is formed in the area of ​​the vertical fin silicon layers 320, 322, and 324 directly below the dielectric layers 340 and 341. The concentration of this doping region affects the turn-on threshold, which is determined by the standard SOI-FinFET process. The vertical fin silicon layers 320, 321, 322, 323, and 324 are of type I semiconductor. Through self-aligned doping via dielectric layers 340 and 341, heavily doped source / drain regions of type I semiconductor are formed on both sides of the vertical fin silicon layers 320, 322, and 324. The first type of semiconductor, heavily doped regions form ohmic contacts, selectively formed via metal silicide extraction. Vertical fins 321 and 323 are of the second type of semiconductor; through channel doping, appropriately doped channel regions of the first type of semiconductor are formed in the area directly below dielectrics 340 and 341 of the vertical fins 321 and 323. The concentration of this doped region affects the turn-on threshold, determined by the standard SOI-FinFET process. Also via self-aligned doping of dielectrics 340 and 341, heavily doped source / drain regions of the second type of semiconductor are formed on both sides of the vertical fins 321 and 323. These heavily doped regions of the second type of semiconductor form ohmic contacts, selectively formed via metal silicide extraction. Lateral fins 325, 326, and 327 are of the second type of semiconductor and are electrically connected to the vertical fins 320 and 321. Considering compatibility and cost, it is recommended that the lateral fin silicon 325, 326, and 327 be fabricated simultaneously with the vertical fin silicon 320, 321, 322, 323, and 324 in the process flow. The functionality of this invention does not require additional doping of the lateral fin silicon 325, 326, and 327; however, it is not excluded that the lateral fin silicon 325, 326, and 327 may be additionally doped with a second type of semiconductor to reduce internal resistance.

[0035] In this embodiment, the first type of semiconductor is an N-type semiconductor, and the second type of semiconductor is a P-type semiconductor. In FinFET processes below 22nm, dielectrics 140, 141, 240, and 241 are generally high-k dielectrics, and gate electrodes 130, 131, 230, and 231 are composite gates of polysilicon gates and metal gates. The key protection of this invention lies in the characteristic structure of the device, and the specific differences are determined by the standard process used.

[0036] Combination Figure 4A and Figure 4BLongitudinal fin silicon structures 420, 421, 422, 423, and 424, transverse fin silicon structures 425, 426, and 427, dielectric structures 440 and 441, and gate electrode structures 430 and 431 are prepared in silicon films to form an H-type fin silicon structure ESD protection device for SOI-FinFET process.

[0037] like Figure 5A As shown, a standard SOI-FinFET device, consisting of silicon fins 520 and 521, dielectrics 540 and 541, and gate electrodes 530 and 531, is formed on the substrate 500 and the insulating layer 510. For the standard SOI-FinFET device, in order to effectively suppress the short-channel effect and enhance the control capability of the gate electrodes 530 and 531 over the channels in the silicon fins 520 and 521, an electric field controlling the channel is formed from three directions through a semi-enclosed three-dimensional structure, so that the gate motor can completely control the charge carriers in the silicon fins. The charge carrier control region 550 almost covers all the silicon fins 520 and 521.

[0038] like Figure 5B As shown, an H-shaped fin silicon structure ESD protection device, consisting of longitudinal fin silicon 520, 521, lateral fin silicon 523, dielectric 540, and gate electrode 530, is formed on substrate 500 and insulating layer 510. In a cross-section parallel to and passing through lateral fin silicon 523, gate electrode 530 can no longer completely control the carriers within the fin silicon; its carrier control region 551 is only a portion of the longitudinal fin silicon 520, 521, and lateral fin silicon 523. This results in the beneficial effect of constructing an effective parasitic ESD device within the fin silicon of an SOI-FinFET. In this embodiment, maintaining... Figure 2 As shown in Figure 3, under the condition of uniform doping, the parasitic BJT formed in the longitudinal fin silicon 520 serves as an ESD protection device, and the longitudinal fin silicon 521 and the transverse fin silicon 523 serve as the body to fix the potential of the parasitic BJT base region, which brings the beneficial effect of avoiding the contact floating of the base region of the parasitic electrostatic protection device.

[0039] like Figure 5C As shown, an H-shaped fin silicon structure ESD protection device, consisting of longitudinal fin silicon 520, 521, 522, lateral fin silicon 523, 524, dielectric 540, and gate electrode 530, is formed on substrate 500 and insulating layer 510. In a cross-section parallel to and passing through the lateral fin silicon 523, 524, the gate electrode 530 can no longer completely control the carriers within the fin silicon; its carrier control region 552 is only a portion of the longitudinal fin silicon 520, 521, 522 and the lateral fin silicon 523, 524. This results in the beneficial effect of constructing an effective parasitic ESD device in the fin silicon of an SOI-FinFET. In this embodiment, maintaining... Figure 2As shown in Figure 3, under the condition of uniform doping, the parasitic BJT formed in the longitudinal fin silicon 520 serves as an ESD protection device. The longitudinal fin silicon 521, 522 and the transverse fin silicon 523, 524 act as the body to fix the potential of the parasitic BJT base region, which brings the beneficial effect of avoiding the contact floating of the base region of the parasitic electrostatic protection device.

[0040] like Figure 6 As shown, the H-type fin silicon structure formed under SOI-FinFET technology serves as a parasitic BJT 620 for ESD discharge. The collector resistance 611 and emitter resistance 612 are determined by the internal resistance of the vertically fin silicon doped with a first-type semiconductor, while the base resistance 615 is determined by the internal resistance of the laterally fin silicon doped with a second-type semiconductor. Base resistances 613 and 614 are determined by the internal resistance of the vertically fin silicon doped with a second-type semiconductor. The discharged electrostatic charge is discharged through collector lead 602 and emitter lead 601, while base lead 603 controls the base potential of the parasitic BJT 620. In practical applications, it can be used as a trigger terminal for designs such as RC triggering, or it can be directly shorted to emitter lead 601.

[0041] like Figure 7 As shown, due to the small size and low thermal conductivity of silicon fins, a single silicon fin cannot achieve good electrostatic discharge (ESD) protection. To obtain an ESD protection device with high ESD discharge capability, it is necessary to arrange individual H-shaped silicon fin structures into a large-scale array. In this embodiment, a large-scale array of H-shaped silicon fin structure ESD protection devices is formed on the substrate 700 and the insulating layer 710. This array consists of vertical silicon fins 721, 722, 723, 724, 725, 726, 727, and horizontal silicon fins penetrating all the vertical silicon fins, a dielectric 740, and a gate electrode 730. The silicon fins of the first conductivity type serve as ESD discharge structures, while the silicon fins of the second conductivity type serve as floating potential fixing structures, periodically arranged around the silicon fins of the first conductivity type. For example, finned silicon 722, 724, and 726 are used as electrostatic discharge structures, while finned silicon 721, 723, 725, and 727 are used as floating potential fixing structures at intervals of one; finned silicon 722, 723, 725, and 726 are used as electrostatic discharge structures, while finned silicon 721, 724, and 727 are used as floating potential fixing structures at intervals of two; and so on, thus reasonably expanding the range of control over the base region resistance.

[0042] like Figure 8The diagram illustrates one embodiment of the front-end process of the device disclosed in this invention. On an SOI wafer, a buried oxide layer isolates discrete transistors, whereas in bulk silicon devices, this isolation must be achieved through wafer fabrication. Bulk silicon FinFET processes are more complex and present significant challenges to manufacturing and process control. Although SOI substrates are more expensive, the increased cost of the more complex bulk silicon FinFET process largely offsets this expense, allowing its cost to be roughly equivalent to that of bulk silicon processes in mass production. FinFET technology evolves rapidly and cannot be exhaustively described. The key process steps described in this embodiment are merely one method for preparing the H-type fin silicon structure ESD protection device disclosed in this invention, applied to the SOI-FinFET process, and do not affect the protection of this patent for devices that incorporate the features disclosed in this invention using other process methods.

[0043] like Figure 8 As shown in Figure a, an SOI substrate composed of a silicon substrate 801, an insulating layer 802, and a silicon film 803 is prepared. The SOI substrate is fabricated using methods including, but not limited to, SIMOX (simulated oxygen implantation), bonding, and Smart Curt methods. The silicon film 803 is the active region of the device. Figure 8 As shown in b, a SiO2 / Si3N4 layer is deposited on the silicon film 803 as a hard mask 804. As a key step disclosed in this invention, as... Figure 8 As shown in Figure c, a SiO2 layer is deposited on the hard mask 804, and a lateral fin silicon mask 805 is formed through photolithography and etching. The length and position of the lateral fin silicon mask 805 must span the vertical fin silicon, and the width of the lateral fin silicon mask 805 affects the final width of the fin silicon. Figure 8 As shown in Figure d, a polysilicon layer is deposited on the hard mask 804 and the lateral fin silicon mask 805, and then photolithography and etching are performed to form the polysilicon mask 806 shown in the figure. The polysilicon mask 806 still contains a portion of the lateral fin silicon mask. Figure 8 As shown in Figure e, a SiO2 layer is deposited on top of the polysilicon mask 806 and the hard mask 804 to form a SiO2 mask 807. The thickness of the SiO2 layer is controlled by the deposition time, which determines the width of the final fin silicon. Figure 8 As shown in figure f, the SiO2 mask 807 is etched to form sidewalls 808 and 809. At this time, the hard mask 804 acts as a stop layer, while the polysilicon mask 806 still exists. Figure 8 As shown in figure g, the polysilicon mask 806 is completely removed. At this point, only the sidewalls 808 and 809 and a portion of the lateral fin silicon mask 810 remaining in the polysilicon mask 806 are left on the hard mask 804. The sidewalls 808 and 809 and the portion of the lateral fin silicon mask 810 are interconnected as shown in the figure. Figure 8As shown in Figure h, using sidewalls 808 and 809 and part of the lateral fin silicon mask 810 as masks, the hard mask 804 and silicon film 803 are etched until the insulating layer 802 is reached, leaving the H-shaped fin silicon 812 and the H-shaped hard mask 811. Figure 8 As shown in Figure i, CMP removes sidewalls 808 and 809 and part of the lateral fin silicon mask 810, followed by etching to remove the H-shaped hard mask 811, ultimately resulting in an H-shaped fin silicon 812 on the silicon substrate 801 and the insulating layer 802. Following this step, the process steps are consistent with the standard SOI-FinNET process used in practice, including channel implantation, polysilicon gate deposition, high-k dielectric deposition, metal gate deposition, photolithography etching, and source / drain implantation, forming a fin silicon structure as shown in Figure i. Figure 8 The H-type fin silicon structure ESD protection device disclosed in this invention, as shown in j, is applied to SOI-FinFET technology. The above-described process method has good compatibility with standard SOI-FinFET technology and can be integrated into existing process flows at a very low cost.

[0044] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An ESD protection device for an H-type fin silicon structure applied in SOI-FinFET process, characterized in that, include: Based on an SOI substrate, longitudinal fin silicon, lateral fin silicon, dielectric, and gate electrode are fabricated. The longitudinal fin silicon includes longitudinal fin silicon one and longitudinal fin silicon two. Longitudinal fin silicon one contains doped regions of two types of semiconductors, namely type I and type II. Longitudinal fin silicon two is of type II semiconductor, and lateral fin silicon is of type II semiconductor. The three longitudinal fin silicons together form an H-type fin silicon structure and are electrically connected. The carrier control region is only a part of longitudinal fin silicon one, longitudinal fin silicon two, and lateral fin silicon. Parasitic ESD protection devices are formed in longitudinal fin silicon one, and longitudinal fin silicon two and lateral fin silicon act as bulk leads to fix the potentials of the two types of semiconductors of type II. The SOI substrate is fabricated using oxygen implantation isolation, bonding, and Smart Curt standard processes, with vertical silicon fins and horizontal silicon fins perpendicular to each other and electrically connected. The dielectric is a high-k dielectric of hafnium-based oxide, and the gate electrode is a composite gate of polysilicon gate and metal gate; The longitudinal fin silicon includes doped regions of both type I and type II semiconductors. Through channel doping, a channel region of appropriate type I semiconductor doping is formed in the region of the longitudinal fin silicon located directly below the dielectric. The first type of semiconductor type heavily doped source and drain regions are formed on both sides of the longitudinal fin silicon through dielectric self-aligned doping, and an appropriate first type of semiconductor type doped channel region is formed in the region of the longitudinal fin silicon located directly below the dielectric; the first type of semiconductor type heavily doped regions form ohmic contacts and are selectively led out through metal silicides. The longitudinal fin silicon is a type II semiconductor. Through channel doping, a channel region of appropriate type I semiconductor doping is formed in the region of the longitudinal fin silicon located directly below the dielectric. Through dielectric self-aligned doping, source and drain regions of type II semiconductor heavily doped are formed on both sides of the longitudinal fin silicon. The type II semiconductor heavily doped regions form ohmic contacts, which are selectively led out through metal silicides. On a cross-section parallel to and passing through the transverse fin silicon, the carrier control region is only a part of the longitudinal fin silicon one, the longitudinal fin silicon two, and the transverse fin silicon; in the uncontrolled region of the gate electrode inside the fin silicon, NPN or PNP type parasitic BJTs are formed in the longitudinal fin silicon one as ESD protection devices, or parasitic SCRs are formed as ESD protection devices, and the longitudinal fin silicon two and the transverse fin silicon act as bodies to draw out the base potential of the parasitic BJTs or the corresponding potential of the parasitic SCRs.

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