Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate including a first isolation region; forming multiple gate structures and an intermediate layer on the substrate, wherein the intermediate layer is also located on sidewalls of the gate structures, and at least two gate structures span the first isolation region; etching the gate structures on the first isolation region and the intermediate layer between adjacent gate structures, forming first openings in the intermediate layer that penetrate the multiple gate structures on the first isolation region, and during the etching process of the gate structures on the first isolation region and the intermediate layer between adjacent gate structures, the etching selectivity between the gate structures and the intermediate layer is within a preset range. Thus, the performance and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor field, as the integration density of semiconductor devices increases, the size of transistors continues to shrink. As the size of transistors shrinks, the size of gate structures also needs to be reduced. To further reduce the size of the gate structure, form a small-sized gate structure, and achieve electrical isolation between different gates, the gate structure is typically subjected to a gate cutting process to divide the gate structure into multiple gate structures.

[0003] However, in existing processes, the performance and reliability of semiconductor structures still need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is a semiconductor structure and a method for forming the same, so as to improve the performance and reliability of the semiconductor structure.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a first isolation region; a plurality of gate structures located on the substrate, at least two of the gate structures spanning the first isolation region, and, on the first isolation region, each of the two or more gate structures spanning the first isolation region has a first isolation trench extending through the gate structure; and a second dielectric structure located on a surface of the first isolation region, the second dielectric structure also being located on sidewalls of the plurality of gate structures and within the first isolation trench.

[0006] Optionally, the substrate further includes a second isolation region, one of the plurality of gate structures spans the second isolation region, and, on the second isolation region, the gate structure spanning the second isolation region has a second opening passing through the gate structure, and the second dielectric structure is also located in the second opening.

[0007] Optionally, it further includes: a plurality of interconnect structures located in the second dielectric structure, at least one of the interconnect structures spans the first isolation region.

[0008] Optionally, the method further includes: an etch stop layer located between the substrate and the second dielectric structure outside the first isolation region, wherein the etch stop layer is also located on the sidewall surface of the gate structure.

[0009] Optionally, the base includes a substrate and a plurality of fin structures separated from each other and located on the substrate, and the plurality of gate structures spans across the plurality of fin structures.

[0010] The technical solution of the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a first isolation region; multiple gate structures and an intermediate layer located on the substrate, the intermediate layer also located on the side wall of the gate structure, and at least two gate structures spanning the first isolation region; a first opening located in the intermediate layer and passing through the multiple gate structures on the first isolation region.

[0011] Optionally, the material of the intermediate layer includes non-dielectric material or semiconductor material.

[0012] Optionally, the material of the intermediate layer includes: metal compounds, silicon carbide, silicon germanium or multi-element semiconductor materials composed of III-V group elements.

[0013] Optionally, the material of the intermediate layer includes a dielectric material.

[0014] Optionally, it further includes: an isolation structure located in the first opening.

[0015] Optionally, the base includes a substrate and a plurality of fin structures separated from each other and located on the substrate, and the plurality of gate structures spans across the plurality of fin structures.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first isolation region; forming multiple gate structures and an intermediate layer on the substrate, the intermediate layer also being located on the side wall of the gate structure, and at least two gate structures spanning the first isolation region; etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, forming a first opening in the intermediate layer that passes through the multiple gate structures on the first isolation region, and in the process of etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, the etching selectivity ratio of the gate structure and the intermediate layer is within a preset range.

[0017] Optionally, the preset range is 4:5 to 6:5.

[0018] Optionally, the method for forming the intermediate layer includes: forming a plurality of dummy gate structures on the substrate; after forming the dummy gate structures, forming an intermediate layer on the surface of the substrate to cover the sidewall surfaces of the dummy gate structures; after forming the intermediate layer, removing the dummy gate structures.

[0019] Optionally, the method for forming the gate structure includes: after forming the intermediate layer, forming the gate structure in the gate opening.

[0020] Optionally, the method for forming the gate structure includes: before forming the intermediate layer, forming a first dielectric structure on the surface of the substrate, the first dielectric structure having multiple gate openings, and at least two gate openings spanning the first isolation region; and forming a gate structure in the gate openings.

[0021] Optionally, the method for forming the intermediate layer includes: after forming the gate structure, removing the first dielectric structure; and after removing the first dielectric structure, forming the intermediate layer on the surface of the substrate.

[0022] Optionally, the method for forming the first dielectric structure and the gate opening includes: forming a plurality of dummy gate structures on the substrate; after forming the dummy gate structures, forming a first dielectric structure on the substrate surface covering the sidewall surfaces of the dummy gate structures; after forming the first dielectric structure, removing the dummy gate structure.

[0023] Optionally, the material of the intermediate layer includes non-dielectric material or semiconductor material.

[0024] Optionally, the material of the intermediate layer includes: a metal compound, silicon, silicon germanium or a multi-element semiconductor material composed of group III-V elements.

[0025] Optionally, in the process of etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, the gas used includes at least one of Cl 2 , BCl 3 , HCl and SiCl 4 .

[0026] Optionally, the method further includes: removing the intermediate layer after forming the first opening; and forming a second dielectric structure on the surface of the substrate after removing the intermediate layer, wherein the second dielectric structure is also located on the sidewall surface of the gate structure.

[0027] Optionally, in the etching process for removing the intermediate layer, an etching selectivity ratio between the intermediate layer and the gate structure is greater than 5:1.

[0028] Optionally, the material of the second dielectric structure includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, silicon oxynitride and silicon hydroxide.

[0029] Optionally, the method further includes: forming a plurality of interconnect structures in the second dielectric structure, with at least one interconnect structure spanning the first isolation region.

[0030] Optionally, the material of the intermediate layer is a dielectric material; and the method for forming the semiconductor structure further includes: forming an isolation structure in the first opening.

[0031] Optionally, the method further includes: etching the isolation structure and the intermediate layer to form a plurality of interconnect structures in the intermediate layer, wherein at least one interconnect structure spans across the first isolation region.

[0032] Optionally, the method further includes: forming an etch stop layer between the substrate and the intermediate layer, wherein the etch stop layer is also located on the sidewall surface of the gate structure.

[0033] Optionally, the method further includes: etching the etch stop layer on the first isolation region while etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures.

[0034] Optionally, the method for forming the first opening includes: forming an isolation mask structure on the surface of the gate structure and the surface of the intermediate layer, the isolation mask structure having a first isolation opening, the first isolation opening exposing the gate structure on the first isolation region and the surface of the intermediate layer between adjacent gate structures; using the isolation mask structure as a mask, etching the gate structure and the intermediate layer between adjacent gate structures until the gate structure on the first isolation region and the intermediate layer between adjacent gate structures are removed.

[0035] Optionally, the substrate also includes a second isolation region, and one of the multiple gate structures spans the second isolation region; the method for forming the semiconductor structure also includes: removing the gate structure on the second isolation region while removing the gate structure on the first isolation region and the intermediate layer between adjacent gate structures.

[0036] Optionally, the base includes a substrate and a plurality of fin structures separated from each other and located on the substrate, and the gate structure spans across the plurality of fin structures.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] In the method for forming a semiconductor structure provided by the technical solution of the present invention, multiple gate structures and an intermediate layer located on the side wall surface of the gate structure are formed on the substrate, and in the etching process for forming the first opening, the etching selectivity ratio of the gate structure and the intermediate layer is within a preset range. Therefore, when forming the first opening, the etching rate of the gate structure and the etching rate of the intermediate layer can be made close to or the same, thereby reducing the residual intermediate layer material between adjacent gate structures on the first isolation region, as well as the residual gate structure on the side wall surface of the residual intermediate layer and the surrounding substrate surface, thereby improving the performance and reliability of the semiconductor structure.

[0039] Furthermore, since the intermediate layer is removed after forming the first opening, the amount of intermediate layer material remaining at the bottom of the first opening can be further reduced. Furthermore, since a second dielectric structure is formed on the substrate surface, located on the sidewalls of the gate structure after removing the intermediate layer, a larger space is available for forming the second dielectric structure, reducing the difficulty of forming a small-scale electrically insulating structure on the first isolation region. Furthermore, the impact of the process of forming the small-scale electrically insulating structure on the gate structure is avoided, thereby improving the performance and reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figures 1 to 3 It is a cross-sectional structural diagram of the formation process of a semiconductor structure;

[0041] Figures 4 to 10 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0042] Figures 11 to 14 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0043] As described in the background art, the performance and reliability of semiconductor structures in existing processes still need to be improved. The reasons why the performance and reliability of semiconductor structures still need to be improved are described in detail below with reference to the accompanying drawings.

[0044] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0045] Figures 1 to 3 It is a cross-sectional structural diagram of the formation process of a semiconductor structure.

[0046] Please refer to Figure 1 and Figure 2 , Figure 1 It is a schematic diagram of the top view of a semiconductor structure. Figure 2 yes Figure 1 In the cross-sectional schematic diagram along the A-A1 direction, a substrate 100 is provided, wherein the substrate 100 includes an isolation region I; a first dielectric structure 110 is formed on the substrate 100, wherein the first dielectric structure 110 has a plurality of gate openings (not shown), and two of the plurality of gate openings span the isolation region I; and a gate structure 120 is formed within the gate openings.

[0047] Please refer to Figure 3 , Figure 3 and Figure 2The view is directed in the same direction as the first dielectric structure 110. A mask structure 130 is formed on the surfaces of the first dielectric structure 110 and the gate structure 120. The mask structure 130 has a mask opening 131 therein. The mask opening 131 exposes the surfaces of the two gate structures 120 and the surface of the first dielectric structure 110 on the isolation region I. The gate structures 120 are etched using the mask structure 130 as a mask until the two gate structures 120 on the isolation region I are removed, thereby forming an isolation opening 140 on the isolation region I that passes through the two gate structures 120. An isolation structure is formed within the isolation opening 140.

[0048] In the above embodiment, due to the high integration density of the semiconductor structure, the distance between the two adjacent gate structures 120 is very small. Therefore, when the two gate structures 120 on the isolation region I need to be cut, under the limitation of the exposure process, a mask opening 131 is usually formed in the mask structure 130 to simultaneously expose the two gate structures 120 on the isolation region I. At the same time, in order to increase the process window of the etching process for etching the two gate structures 120 on the isolation region I, usually, not only the two gate structures 120 on the isolation region I are etched, but also the first dielectric structure 110 between the two gate structures 120 on the isolation region I is etched and removed. That is, the isolation opening 140 also penetrates the first dielectric structure 110 between the two gate structures 120 on the isolation region I.

[0049] However, due to the etching process of etching the two gate structures 120 on the isolation region I, the etching selection of the gate structure 120 and the first dielectric structure 110 is relatively large, so it is easy to leave the first dielectric structure material 111 on the isolation region I (such as Figure 3 As shown, gate structure material 121 is likely to remain on the sidewalls of the residual first dielectric structure material 111 and on the surrounding surface of the substrate 100. On one hand, the residual gate structure material 121 can easily cause a short circuit between the gate structures 120 on both sides of the isolation region 1, and affect the parasitic capacitance and parasitic resistance of the semiconductor structure, resulting in poor performance and reliability of the semiconductor structure. On the other hand, when the isolation structure is subsequently etched to form an interconnect opening, the residual first dielectric structure material 111 can easily block the bottom of the interconnect opening, resulting in high contact resistance between the interconnect structure within the interconnect opening and the substrate 100, or causing a short circuit between the interconnect structure and the circuit of the substrate 100, resulting in poor performance and reliability of the semiconductor structure.

[0050] To address the aforementioned technical issues, embodiments of the present invention provide a method for forming a semiconductor structure. The method comprises forming an intermediate layer on a substrate, then etching the gate structures on a first isolation region and the intermediate layer between adjacent gate structures, thereby forming a first opening in the intermediate layer that penetrates the multiple gate structures on the first isolation region. Furthermore, during the etching process of the gate structures on the first isolation region and the intermediate layer between adjacent gate structures, the etching selectivity between the gate structures and the intermediate layer is within a preset range. This improves the performance and reliability of the semiconductor structure.

[0051] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Figures 4 to 10 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0053] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 A schematic diagram of the top view structure along the direction X3, Figure 5 yes Figure 4 A schematic cross-sectional structure diagram along the direction X1-X2 is provided in FIG. 2 , wherein the substrate 200 includes a first isolation region I.

[0054] In this embodiment, the base 200 includes a substrate (not shown) and a plurality of fin structures (not shown) separated from each other and located on the substrate. The gate opening 211 spans across the plurality of fin structures.

[0055] In other embodiments, the substrate is a planar substrate.

[0056] The material of the substrate includes semiconductor material.

[0057] In this embodiment, the substrate is made of silicon.

[0058] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0059] In this embodiment, the substrate 200 further includes a second isolation region II.

[0060] In other embodiments, the substrate does not include the second isolation region II.

[0061] Next, a plurality of gate structures and an intermediate layer are formed on the substrate 200. The intermediate layer is also located on the sidewall of the gate structure. Among the plurality of gate openings, one spans the second isolation region II, and at least two span the first isolation region I. For the specific process of forming the gate structure and the intermediate layer, please refer to Figures 4 to 7 .

[0062] Please continue to refer to Figure 4 and Figure 5 A first dielectric structure 210 is formed on the surface of the substrate 200. The first dielectric structure 210 has a plurality of gate openings 211. Among the plurality of gate openings 211 in the first dielectric structure 210, one crosses the second isolation region II, and at least two cross the first isolation region I.

[0063] The gate opening 211 also spans across several of the fin structures.

[0064] The method for forming the first dielectric structure 210 and the gate opening 211 includes: forming a plurality of dummy gate structures (not shown) across the fin structure and gate spacers (not shown) located on the sidewalls of the dummy gate structures on the substrate 200; after forming the dummy gate structures, forming the first dielectric structure 210 on the surface of the substrate 200 to cover the sidewalls of the dummy gate structures; and after forming the first dielectric structure 210, removing the dummy gate structures.

[0065] Specifically, in this embodiment, the method for forming the first dielectric structure 210 covering the sidewall surface of the dummy gate structure includes: forming a first dielectric structure material layer (not shown) on the substrate 200 to cover the surface of the dummy gate structure; and planarizing the first dielectric structure material layer until the top surface of the dummy gate structure is exposed, thereby forming the first dielectric structure 210, wherein the first dielectric structure 210 exposes the top surface of the dummy gate structure.

[0066] The first dielectric structure 210 provides support for the subsequent formation of a gate structure.

[0067] In this embodiment, the method for forming the dummy gate structure includes: forming a dummy gate material film covering the surface of the fin structure on the substrate 200; patterning the dummy gate material film until the surface of the substrate 200 is exposed, and forming a dummy gate structure across the fin structure on the substrate 200, wherein the top surface of the dummy gate structure is higher than the top surface of the fin structure.

[0068] In this embodiment, the method for forming the semiconductor structure further includes: before forming the dummy gate structure, forming a base dielectric layer 201 on the surface of the substrate, the base dielectric layer 201 also being located on a portion of the sidewall surface of the fin structure; after forming the dummy gate structure and the gate sidewalls, and before forming the first dielectric structure 210, forming a source-drain doped layer (not shown in the figure) in the fin structure on both sides of the dummy gate structure; after forming the source-drain doped layer, and before forming the first dielectric structure 210, forming an etch stop layer 212 on the sidewall surface of the dummy gate structure and the surface of the substrate 200.

[0069] The method for forming the source-drain doped layer includes: forming source-drain openings (not shown in the figure) in the fin structure on both sides of the dummy gate structure; and forming the source-drain doped layer in the source-drain openings using an epitaxial process.

[0070] The base dielectric layer 201 functions to electrically insulate adjacent fin structures and between the semiconductor device and the base.

[0071] The etch-stop layer 212 serves to improve oxidation of the dummy gate structure's sidewalls and gate sidewalls when the dummy gate structure is exposed. Furthermore, during the subsequent etching of the first dielectric structure 210 and the intermediate layer, the etch-stop layer 212 protects the gate structure, substrate 200, and substrate dielectric layer 201, thereby reducing damage to the gate structure, substrate 200, and substrate dielectric layer 201. This improves the performance and reliability of the semiconductor structure.

[0072] In this embodiment, the material of the gate spacer includes a low-k dielectric material (k is less than 3.9).

[0073] In this embodiment, the material of the first dielectric structure 210 includes silicon oxide.

[0074] Please refer to Figure 6 , a plurality of gate structures 220 are formed on the substrate 200 , and one of the gate structures 220 spans the second isolation region II, and at least two of the gate structures 220 span the first isolation region I.

[0075] Specifically, in this embodiment, a gate structure 220 is formed in the gate opening 211 , and the gate structure 220 also spans across a number of the fin structures.

[0076] The gate structure 220 includes: a gate dielectric layer (not shown) located on the sidewalls and bottom of the gate opening 211, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0077] The gate dielectric layer may be made of a high-k dielectric material (with a dielectric constant greater than 3.9). The high-k dielectric material may include hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0078] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0079] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0080] The method for forming the gate structure 220 includes: forming a gate dielectric material layer (not shown) on the surface of the first dielectric structure 210 and in the gate opening 211; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, wherein the gate electrode material layer completely fills the gate opening 211; and planarizing the gate electrode material layer, the work function material layer, and the gate dielectric material layer until the surface of the first dielectric structure 210 is exposed to form the gate structure 220.

[0081] The process of forming the gate dielectric material layer includes an oxidation process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or an atomic layer deposition process (ALD).

[0082] The process of forming the work function material layer includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0083] The process of forming the gate electrode material layer includes a metal electroplating process or a deposition process. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0084] The process of planarizing the gate electrode material layer, the work function material layer, and the gate dielectric material layer includes an etch-back process or a chemical mechanical polishing (CMP) process.

[0085] Please refer to Figure 7 After forming the gate structure 220 , the first dielectric structure 210 is removed; after removing the first dielectric structure 210 , an intermediate layer 230 is formed on the surface of the substrate 200 , and the intermediate layer 230 is also located on the sidewall surface of the gate structure 220 .

[0086] In this embodiment, the etch stop layer 212 is located between the substrate 200 and the intermediate layer 230 .

[0087] In this embodiment, the process of removing the first dielectric structure 210 includes at least one of a dry etching process and a wet etching process.

[0088] In this embodiment, the method of forming the intermediate layer 230 includes: forming an intermediate material layer (not shown) on the surface of the substrate 200 and the surface of the gate structure 220; and planarizing the intermediate material layer until the top surface of the gate structure 220 is exposed.

[0089] In this embodiment, the process of planarizing the intermediate material layer includes an etch-back process or a chemical mechanical polishing process.

[0090] In another embodiment, the first dielectric structure is not formed. The method for forming the intermediate layer includes: forming a plurality of dummy gate structures on the substrate that span the fin structure, and an etch stop layer located on the sidewalls of the dummy gate structures and the substrate surface; after forming the dummy gate structures, forming an intermediate layer on the substrate surface that covers the sidewalls of the dummy gate structures; after forming the intermediate layer, removing the dummy gate structures, and forming a plurality of gate openings in the intermediate layer. Of the plurality of gate openings, one spans the second isolation region II, and at least two span the first isolation region I.

[0091] In yet another embodiment, the method of forming a plurality of the gate structures includes: forming the gate structures in the gate openings after forming the intermediate layer.

[0092] The material of the intermediate layer 230 includes a non-dielectric material or a semiconductor material, such as a metal compound, silicon, silicon germanium, or a multi-component semiconductor material composed of group III-V elements.

[0093] In this embodiment, the material of the intermediate layer 230 is silicon.

[0094] Please refer to Figure 8 , etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220, forming a first opening 231 in the intermediate layer 230 that penetrates the multiple gate structures 220 on the first isolation region I, and, in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220, the etching selectivity ratio of the gate structure 220 and the intermediate layer 230 is within a preset range.

[0095] Since a plurality of gate structures 220 and an intermediate layer 230 located on the sidewalls of the gate structures 220 are formed on the substrate 200, and in the etching process for forming the first opening 231, the etching selectivity ratio of the gate structure 220 and the intermediate layer 230 is within a preset range, the etching rate of the gate structure 220 and the etching rate of the intermediate layer can be made close to or the same when the first opening 231 is formed, thereby reducing the residual intermediate layer 230 material between adjacent gate structures 220 on the first isolation region I, as well as the residual gate structure 220 material on the sidewalls of the residual intermediate layer 230 and the surrounding surface of the substrate 200, thereby improving the performance and reliability of the semiconductor structure.

[0096] Specifically, by reducing the residue of the intermediate layer 230 and the residue of the gate structure 220, on the one hand, the risk of short circuit between the gate structures 220 that need to be spaced is reduced, thereby improving the reliability of the semiconductor structure; on the other hand, the influence of the residue of the intermediate layer 230 and the residue of the gate structure 220 on the magnitude of the parasitic capacitance and parasitic resistance of the semiconductor structure is reduced, thereby improving the performance of the semiconductor structure. Moreover, when subsequently forming an interconnection structure that is electrically interconnected with the circuit of the substrate 200, the risk of contact between the interconnection structure and the residue of the intermediate layer 230 and the gate structure 220 can be reduced, thereby reducing the contact resistance between the interconnection structure and the substrate 200 and improving the performance of the semiconductor structure; at the same time, the obstruction of the residue of the intermediate layer 230 and the gate structure 220 when etching the interconnection opening that provides space for the interconnection structure can be reduced, thereby reducing the risk that the interconnection opening cannot expose the surface of the substrate 200, thereby reducing the risk of short circuit between the interconnection structure and the substrate 200 and improving the reliability of the semiconductor structure.

[0097] In this embodiment, the preset range is 4:5 to 6:5.

[0098] By setting the preset range to 4:5 to 6:5, it is possible to better improve the residual intermediate layer 230 material between adjacent gate structures 220, as well as the residual gate structure 220 material on the sidewall surface of the residual intermediate layer 230 and the surrounding substrate 200 surface when forming the first opening 231, so as to better improve the performance and reliability of the semiconductor structure.

[0099] Specifically, in this embodiment, the method for forming the first opening 231 includes: forming an isolation mask structure 240 on the surface of the gate structure 220 and the surface of the intermediate layer 230, the isolation mask structure 240 having a first isolation opening 241, the first isolation opening 241 exposing the gate structure 220 on the first isolation region I and the surface of the intermediate layer 230 between adjacent gate structures 220; using the isolation mask structure 240 as a mask, etching the gate structure 220 and the intermediate layer 230 between adjacent gate structures 220 until the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 are removed.

[0100] In this embodiment, the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 includes a dry etching process.

[0101] In this embodiment, the gas used in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 includes at least one of Cl 2 , BCl 3 , HCl, and SiCl 4 . Because the Cl-containing gas can form etching byproducts with higher volatility during the etching process, the use of this gas can achieve an etching selectivity within a preset range for the gate structure 220 and the intermediate layer 230 in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 .

[0102] In this embodiment, while removing the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 , the gate structure 220 on the second isolation region II is removed, forming a second opening 232 passing through one gate structure 220 in the intermediate layer 230 .

[0103] In this embodiment, while etching the gate structure 220 on the first isolation region I and the intermediate layer 230 between adjacent gate structures 220 , the etch stop layer 212 on the first isolation region I and the second isolation region II is also etched.

[0104] In this embodiment, after the first opening 231 is formed, the isolation mask structure 240 is removed.

[0105] Please refer to Figure 9 After forming the first opening 231 , the intermediate layer 230 is removed; after removing the intermediate layer 230 , a second dielectric structure 250 is formed on the surface of the substrate 200 , and the second dielectric structure 250 is also located on the sidewall surface of the gate structure 220 .

[0106] By removing the intermediate layer 230 and forming the second dielectric structure 250, on the one hand, electrical insulation is achieved between adjacent gate structures 220 and the electrical insulation reliability between the gate structure 220 and the substrate 200 is enhanced. On the other hand, the second dielectric structure 250 provides support for the subsequent formation of an interconnect structure and achieves electrical insulation between the interconnect structures and between the interconnect structure and other semiconductor devices.

[0107] Since the intermediate layer 230 is removed after forming the first opening 231, the process of removing the intermediate layer 230 can further reduce the amount of intermediate layer 230 material remaining at the bottom of the first opening 231. Furthermore, since the second dielectric structure 250 is formed on the surface of the substrate 200 and located on the sidewall surface of the gate structure 220 after removing the intermediate layer 230, a larger space is provided for forming the second dielectric structure 250. This reduces the difficulty of forming a small-scale electrically insulating structure on the first isolation region I and prevents the process of forming the small-scale electrically insulating structure from affecting the gate structure 220, thereby improving the performance and reliability of the semiconductor structure.

[0108] Specifically, when the space for forming the dielectric structure is relatively small, that is, when forming the dielectric structure in a small space, a highly fluid material is required to fill the small space in order to reduce defects within the dielectric structure. Since highly fluid materials need to be solidified through high-temperature annealing after filling the small space, the gate structure material may be affected by the high-temperature annealing, thereby affecting the electrical performance of the semiconductor device. In this embodiment, since the space for forming the second dielectric structure 250 is relatively large, it is not necessary to use highly fluid materials when forming the second dielectric structure 250, nor is it necessary to perform a high-temperature annealing step. This reduces the difficulty of forming a small-scale electrically insulating structure on the first isolation region I, avoids the impact of the process of forming the small-scale electrically insulating structure on the gate structure 220, and improves the performance and reliability of the semiconductor structure.

[0109] Furthermore, since the intermediate layer 230 is removed after forming the first opening 231, and since the second dielectric structure 250 is formed on the surface of the substrate 200 after removing the intermediate layer 230, the second dielectric structure 250 is located simultaneously on the first isolation region I and on the substrate 200 outside the first isolation region I. Therefore, when subsequently forming an interconnect structure electrically interconnected with the substrate 200 or the gate structure 220, an interconnect opening can be formed within the dielectric structure (the second dielectric structure 250) made of the same material to provide space for the interconnect structure. This makes it easier to achieve the same or similar etching rates during the etching process for forming the interconnect opening, and thus, the depths of the interconnect opening on the first isolation region I and the interconnect opening on the substrate outside the first isolation region I are similar. Because the interconnect openings on the first isolation region I and the interconnect openings on the substrate outside the first isolation region I and the second isolation region II have similar depths, the risk of over-etching or under-etching when forming the interconnect openings is reduced. This reduces the risk of shorting the interconnect structure on the first isolation region I and the interconnect opening structure on the substrate outside the first isolation region I, or the risk of damaging other semiconductor devices during the formation of the interconnect openings, thereby improving the reliability of the semiconductor structure. Similarly, the same effects are achieved when forming the interconnect structure simultaneously on the second isolation region II and on the substrate 200 outside the second isolation region II, and will not be further described here.

[0110] In this embodiment, the etching process for removing the intermediate layer 230 has an etching selectivity ratio of greater than 5:1 between the intermediate layer 230 and the gate structure 220. Thus, the larger etching selectivity reduces damage to the gate structure 220 during the etching process for removing the intermediate layer 230, thereby improving the performance of the semiconductor structure.

[0111] In this embodiment, the etching process for removing the intermediate layer 230 has an etching selectivity ratio of 5:1 or greater between the intermediate layer 230 and the etch stop layer 212. Thus, due to the larger etching selectivity, the gate structure 220 and the substrate 200 can be better protected by the etch stop layer 212 during the etching process for removing the intermediate layer 230, thereby reducing damage to the gate structure 220 and the substrate 200 during the etching process for removing the intermediate layer 230 and improving the performance of the semiconductor structure.

[0112] In this embodiment, the material of the second dielectric structure 250 includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, silicon oxynitride, and silicon hydroxide.

[0113] Please refer to Figure 10 , a plurality of interconnect structures 260 are formed in the second dielectric structure 250 , and at least one interconnect structure 260 spans the first isolation region I.

[0114] In other embodiments, at least one interconnect structure further crosses the second isolation region.

[0115] In this embodiment, the method for forming the interconnect structure 260 includes: forming a third dielectric structure 270 on the surfaces of the second dielectric structure 250 and the gate structure 220; forming an interconnect mask structure (not shown) on the surface of the third dielectric structure 270, wherein the interconnect mask structure has a plurality of interconnect mask openings, each of which exposes a portion of the surface of the third dielectric structure 270; etching the third dielectric structure 270, the second dielectric structure 250, and the etch stop layer 212 using the interconnect mask openings as a mask until the surface of the substrate 200 is exposed, thereby forming interconnect openings (not shown) in the third dielectric structure 270 and the second dielectric structure 250; forming an interconnect structure material layer in the interconnect openings and on the surface of the third dielectric structure 270; and planarizing the interconnect structure material layer until the surface of the third dielectric structure 270 is exposed.

[0116] The third dielectric structure 270 is used to improve the surface flatness of the semiconductor structure, reduce the difficulty of forming the interconnection mask structure, and improve the pattern accuracy of the interconnection mask structure. At the same time, during the etching process of forming the interconnection structure, it protects the top surface of the gate structure 220 and reduces damage to the top surface of the gate structure 220 during the etching process, thereby improving the performance and reliability of the semiconductor structure.

[0117] In other embodiments, the third dielectric structure is not formed.

[0118] In this embodiment, exposing the surface of the substrate 200 refers to exposing the surface of the fin structure. In other embodiments, exposing the substrate may also refer to exposing the surface of the substrate other than the fin structure.

[0119] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Figure 8 , including: a substrate 200, the substrate 200 including a first isolation region I; a plurality of gate structures 220 and an intermediate layer 230 located on the substrate 200, the intermediate layer 230 also being located on the sidewall of the gate structure 220, and at least two gate structures 220 spanning the first isolation region I; a first opening 231 located in the intermediate layer 230 and penetrating the plurality of gate structures 220 on the first isolation region I.

[0120] In this embodiment, the base 200 includes a substrate (not shown) and a plurality of fin structures (not shown) separated from each other and located on the substrate. The gate opening 211 spans across the plurality of fin structures.

[0121] In other embodiments, the substrate is a planar substrate.

[0122] The material of the substrate includes semiconductor material.

[0123] In this embodiment, the substrate is made of silicon.

[0124] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SiO2), or germanium-on-insulator (GeO2). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0125] In this embodiment, the substrate 200 further includes a second isolation region II, one of the plurality of gate structures 220 spans the second isolation region II, and, on the second isolation region II, the intermediate layer 230 further includes a second opening 232, the second opening 232 passing through the gate structure 220 spanning the second isolation region II.

[0126] In other embodiments, the substrate does not include the second isolation region II.

[0127] In this embodiment, the semiconductor structure further includes: a base dielectric layer 201 located between the intermediate layer 230 and the surface of the substrate 200. The base dielectric layer 201 is also located on a portion of the sidewall surface of the fin structure. The function of the base dielectric layer 201 is to electrically insulate adjacent fin structures and between the semiconductor device and the substrate.

[0128] In this embodiment, the semiconductor structure further includes an etch stop layer 212 located between the intermediate layer 230 and the surface of the substrate 200 . The etch stop layer 212 is also located on the sidewall surface of the gate structure 220 .

[0129] In this embodiment, the semiconductor structure further includes a gate spacer (not shown) located between the sidewall surface of the gate structure 220 and the etch stop layer 212 .

[0130] In this embodiment, the material of the gate spacer includes a low-k dielectric material (k is less than 3.9).

[0131] In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown) located on the sidewalls and bottom of the gate opening 211, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0132] The gate dielectric layer may be made of a high-k dielectric material (with a dielectric constant greater than 3.9). The high-k dielectric material may include hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0133] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0134] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0135] In this embodiment, the material of the intermediate layer 230 includes a non-dielectric material or a semiconductor material, such as a metal compound, silicon, silicon germanium, or a multi-component semiconductor material composed of group III-V elements.

[0136] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned formation method, please continue to refer to Figure 10 , comprising: a substrate 200, the substrate 200 including a first isolation region I; a plurality of gate structures 220 located on the substrate 200, at least two of the gate structures 220 spanning the first isolation region I, and, on the first isolation region I, each of the two or more gate structures 220 spanning the first isolation region I has a first isolation trench extending through the gate structure 220; and a second dielectric structure 250 located on a surface of the first isolation region I, the second dielectric structure 250 further located on sidewalls of the plurality of gate structures 220 and within the first isolation trench.

[0137] It should be noted that the first isolation groove refers to the first opening 231 (such as Figure 8 ), the opening portion exposing the sidewall surface of the gate structure 200.

[0138] In this embodiment, the base 200 includes a substrate (not shown) and a plurality of fin structures (not shown) separated from each other and located on the substrate. The gate opening 211 spans across the plurality of fin structures.

[0139] In other embodiments, the substrate is a planar substrate.

[0140] The material of the substrate includes semiconductor material.

[0141] In this embodiment, the substrate is made of silicon.

[0142] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SiO2), or germanium-on-insulator (GeO2). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0143] In this embodiment, the substrate 200 further includes a second isolation region II, one of the plurality of gate structures 220 spans the second isolation region II, and on the second isolation region II, the gate structure 220 spanning the second isolation region II has a second opening 232 (such as Figure 8 As shown), the second dielectric structure 250 is also located in the second opening 232 .

[0144] In other embodiments, the substrate does not include the second isolation region II.

[0145] In this embodiment, the semiconductor structure further includes an etch stop layer 212 located between the substrate 200 and the second dielectric structure 250 outside the first isolation region I and the second isolation region II. The etch stop layer 212 is also located on the sidewall surface of the gate structure 220 .

[0146] In this embodiment, the semiconductor structure further includes a gate spacer (not shown) located between the sidewall surface of the gate structure 220 and the etch stop layer 212 .

[0147] In this embodiment, the material of the gate spacer includes a low-k dielectric material (k is less than 3.9).

[0148] In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown) located on the sidewalls and bottom of the gate opening 211, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0149] The gate dielectric layer may be made of a high-k dielectric material (with a dielectric constant greater than 3.9). The high-k dielectric material may include hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0150] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0151] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0152] In this embodiment, the material of the second dielectric structure 250 includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, silicon oxynitride, and silicon hydroxide.

[0153] In this embodiment, the semiconductor structure further includes: a plurality of interconnect structures 260 located in the second dielectric structure 250 , and at least one of the interconnect structures 260 spans the first isolation region I.

[0154] In other embodiments, at least one interconnect structure further crosses the second isolation region.

[0155] In this embodiment, the semiconductor structure further includes a third dielectric structure 270 located on top of the second dielectric structure 250 and the gate structure 220 , and the interconnection structure 260 is also located within the third dielectric structure 270 .

[0156] Figures 11 to 14 is a schematic structural diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. Figures 4 to 10 The main difference between the shown embodiments lies in the material of the intermediate layer.

[0157] Please Figure 6 Based on reference Figure 11 After forming the gate structure 220 , the first dielectric structure 210 is removed; after removing the first dielectric structure 210 , an intermediate layer 330 is formed on the surface of the substrate 200 , and the intermediate layer 330 is also located on the sidewall surface of the gate structure 220 .

[0158] In this embodiment, the etch stop layer 212 is located between the substrate 200 and the intermediate layer 330 .

[0159] In this embodiment, the process of removing the first dielectric structure 210 includes at least one of a dry etching process and a wet etching process.

[0160] In this embodiment, the method of forming the intermediate layer 330 includes: forming an intermediate material layer (not shown) on the surface of the substrate 200 and the surface of the gate structure 220; and planarizing the intermediate material layer until the top surface of the gate structure 220 is exposed.

[0161] In this embodiment, the process of planarizing the intermediate material layer includes an etch-back process or a chemical mechanical polishing process.

[0162] In another embodiment, the first dielectric structure is not formed. The method for forming the intermediate layer includes: forming a plurality of dummy gate structures on the substrate that span the fin structure, and an etch stop layer located on the sidewalls of the dummy gate structures and the substrate surface; after forming the dummy gate structures, forming an intermediate layer on the substrate surface that covers the sidewalls of the dummy gate structures; after forming the intermediate layer, removing the dummy gate structures, and forming a plurality of gate openings in the intermediate layer. Of the plurality of gate openings, one spans the second isolation region II, and at least two span the first isolation region I.

[0163] In yet another embodiment, the method of forming a plurality of the gate structures includes: forming the gate structures in the gate openings after forming the intermediate layer.

[0164] The intermediate layer 330 is made of a dielectric material, so that electrical insulation between adjacent gate structures 220 can be directly achieved through the intermediate layer 330 .

[0165] Please refer to Figure 12 , the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220 are etched, and a first opening 331 is formed in the intermediate layer 330 that penetrates the multiple gate structures 220 on the first isolation region I. Moreover, in the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220, the etching selectivity ratio of the gate structure 220 and the intermediate layer 330 is within a preset range.

[0166] Since multiple gate structures 220 and an intermediate layer 330 located on the sidewalls of the gate structures 220 are formed on the substrate 200, and the etching selectivity of the gate structures 220 and the intermediate layer 330 in the etching process for forming the first opening 331 is within a preset range, the etching rate of the gate structure 220 and the etching rate of the intermediate layer can be made close to or the same when the first opening 331 is formed, thereby reducing the residual intermediate layer 330 material between adjacent gate structures 220 on the first isolation region I, as well as the residual gate structure 220 material on the sidewalls of the residual intermediate layer 330 and the surrounding surface of the substrate 200, thereby improving the performance and reliability of the semiconductor structure.

[0167] Specifically, by reducing the residue of the intermediate layer 330 and the residue of the gate structure 220, on the one hand, the risk of short circuit between the gate structures 220 that need to be spaced is reduced, thereby improving the reliability of the semiconductor structure; on the other hand, the influence of the residue of the intermediate layer 330 and the residue of the gate structure 220 on the magnitude of the parasitic capacitance and parasitic resistance of the semiconductor structure is reduced, thereby improving the performance of the semiconductor structure. Moreover, when subsequently forming an interconnection structure that is electrically interconnected with the circuit of the substrate 200, the risk of contact between the interconnection structure and the residue of the intermediate layer 330 and the gate structure 220 can be reduced, thereby reducing the contact resistance between the interconnection structure and the substrate 200 and improving the performance of the semiconductor structure; at the same time, the obstruction of the residue of the intermediate layer 330 and the gate structure 220 on etching the interconnection opening that provides space for the interconnection structure can be reduced, thereby reducing the risk that the interconnection opening cannot expose the surface of the substrate 200, thereby reducing the risk of short circuit between the interconnection structure and the substrate 200 and improving the reliability of the semiconductor structure.

[0168] In this embodiment, the preset range is 4:5 to 6:5.

[0169] Through the preset range of 4:5 to 6:5, it is possible to better improve the residual intermediate layer 330 material between adjacent gate structures 220, as well as the residual gate structure 220 material on the sidewall surface of the residual intermediate layer 330 and the surrounding substrate 200 surface when forming the first opening 331, so as to better improve the performance and reliability of the semiconductor structure.

[0170] Specifically, in this embodiment, the method for forming the first opening 331 includes: forming an isolation mask structure 240 on the surface of the gate structure 220 and the surface of the intermediate layer 330, the isolation mask structure 340 having a first isolation opening 341, the first isolation opening 341 exposing the gate structure 220 on the first isolation region I and the surface of the intermediate layer 330 between adjacent gate structures 220; using the isolation mask structure 340 as a mask, etching the gate structure 220 and the intermediate layer 330 between adjacent gate structures 220 until the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220 are removed.

[0171] In this embodiment, the process of etching the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220 includes a dry etching process.

[0172] In this embodiment, while removing the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220 , the gate structure 220 on the second isolation region II is removed, forming a second opening 332 passing through one gate structure 220 in the intermediate layer 330 .

[0173] In this embodiment, while etching the gate structure 220 on the first isolation region I and the intermediate layer 330 between adjacent gate structures 220 , the etch stop layer 212 on the first isolation region I and the second isolation region II is also etched.

[0174] In this embodiment, after the first opening 331 is formed, the isolation mask structure 340 is removed.

[0175] Please refer to Figure 13 , an isolation structure 351 is formed in the first opening 331 .

[0176] In this embodiment, an isolation structure 352 is formed in the second opening 332 simultaneously with the formation of the isolation structure 351 .

[0177] The method of forming the isolation structure 351 and the isolation structure 352 includes: forming an isolation material layer (not shown) in the first opening 331 and the second opening 332 and on the surface of the intermediate layer 330; and planarizing the isolation material layer until the surface of the intermediate layer 330 is exposed.

[0178] The process of planarizing the isolation material layer includes an etch-back process or a chemical mechanical polishing process.

[0179] The isolation structure 351 and the isolation structure 352 are made of dielectric material.

[0180] In this embodiment, the process of forming the isolation material layer includes: filling the first opening 331 and the second opening 332 with a high-fluidity material to form an initial isolation material layer (not shown); performing a high-temperature annealing process on the initial isolation material layer to solidify the initial isolation material layer to form the isolation material layer.

[0181] Please refer to Figure 14 , etching the isolation structure 351 and the intermediate layer 330, forming a plurality of interconnection structures 360 in the intermediate layer 330, at least one interconnection structure 360 ​​spans the first isolation region I.

[0182] In other embodiments, at least one interconnect structure further crosses the second isolation region.

[0183] In this embodiment, the method for forming the interconnect structure 360 ​​includes: forming a third dielectric structure 370 on the surface of the intermediate layer 330, the surface of the isolation structure 351, the surface of the isolation structure 352, and the surface of the gate structure 220; forming an interconnect mask structure (not shown) on the surface of the third dielectric structure 370, wherein the interconnect mask structure has a plurality of interconnect mask openings, each interconnect mask opening exposing a portion of the surface of the third dielectric structure 370; etching the third dielectric structure 370, the intermediate layer 330, the isolation structure 351, and the etch stop layer 212 using the interconnect mask openings as a mask until the surface of the substrate 200 is exposed, thereby forming interconnect openings (not shown) in the third dielectric structure 370 and the intermediate layer 330; forming an interconnect structure material layer in the interconnect openings and on the surface of the third dielectric structure 370; and planarizing the interconnect structure material layer until the surface of the third dielectric structure 370 is exposed.

[0184] The function of the third dielectric structure 370 is to improve the surface flatness of the semiconductor structure, reduce the process difficulty of forming the interconnection mask structure, and improve the pattern accuracy of the interconnection mask structure. At the same time, during the etching process of forming the interconnection structure, it protects the top surface of the gate structure 220 and reduces the damage to the top surface of the gate structure 220 during the etching process, thereby improving the performance and reliability of the semiconductor structure.

[0185] In other embodiments, the third dielectric structure is not formed.

[0186] In this embodiment, exposing the surface of the substrate 200 refers to exposing the surface of the fin structure. In other embodiments, exposing the substrate may also refer to exposing the surface of the substrate other than the fin structure.

[0187] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 14 , including a substrate 200, the substrate 200 including a first isolation region I; a plurality of gate structures 220 and an intermediate layer 330 located on the substrate 200, the intermediate layer 330 also being located on the sidewall of the gate structure 220, and at least two gate structures 220 spanning the first isolation region I; a first opening 331 located in the intermediate layer 330 and penetrating the plurality of gate structures 220 on the first isolation region I.

[0188] In this embodiment, the base 200 includes a substrate (not shown) and a plurality of fin structures (not shown) separated from each other and located on the substrate. The gate opening 211 spans across the plurality of fin structures.

[0189] In other embodiments, the substrate is a planar substrate.

[0190] The material of the substrate includes semiconductor material.

[0191] In this embodiment, the substrate is made of silicon.

[0192] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SiO2), or germanium-on-insulator (GeO2). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0193] In this embodiment, the substrate 200 further includes a second isolation region II, one of the plurality of gate structures 220 spans the second isolation region II, and, on the second isolation region II, the intermediate layer 330 further includes a second opening 332, the second opening 332 passing through the gate structure 220 spanning the second isolation region II.

[0194] In other embodiments, the substrate does not include the second isolation region II.

[0195] In this embodiment, the semiconductor structure further includes: a base dielectric layer 201 located between the intermediate layer 330 and the surface of the substrate 200. The base dielectric layer 201 is also located on a portion of the sidewall surface of the fin structure. The function of the base dielectric layer 201 is to electrically insulate adjacent fin structures and between the semiconductor device and the substrate.

[0196] In this embodiment, the semiconductor structure further includes an etch stop layer 212 located between the intermediate layer 330 and the surface of the substrate 200 . The etch stop layer 212 is also located on the sidewall surface of the gate structure 220 .

[0197] In this embodiment, the semiconductor structure further includes a gate spacer (not shown) located between the sidewall surface of the gate structure 220 and the etch stop layer 212 .

[0198] In this embodiment, the material of the gate spacer includes a low-k dielectric material (k is less than 3.9).

[0199] In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown) located on the sidewalls and bottom of the gate opening 211, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0200] The gate dielectric layer may be made of a high-k dielectric material (with a dielectric constant greater than 3.9). The high-k dielectric material may include hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0201] The material of the gate electrode layer includes a metal material, for example, one or a combination of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, and tantalum.

[0202] The material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0203] In this embodiment, the material of the intermediate layer 330 includes a dielectric material.

[0204] In this embodiment, the semiconductor structure further includes an isolation structure 351 located in the first opening 331 .

[0205] In this embodiment, the semiconductor structure further includes an isolation structure 352 located in the second opening 332 .

[0206] In this embodiment, the semiconductor structure further includes: a plurality of interconnect structures 360 located in the intermediate layer 330 , at least one of the interconnect structures 360 spanning the first isolation region I.

[0207] In other embodiments, at least one interconnect structure further crosses the second isolation region.

[0208] In this embodiment, the semiconductor structure further includes: a third dielectric structure 370 located on top surfaces of the intermediate layer 330 and the gate structure 220 , and the interconnection structure 360 ​​is also located in the third dielectric structure 370 .

[0209] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first isolation region; a plurality of gate structures located on the substrate, at least two of which straddle the first isolation region, and each of the two or more gate structures straddling the first isolation region comprises a first isolation trench extending through the gate structure; a second dielectric structure located on a surface of the first isolation region, the second dielectric structure also being located on a plurality of sidewalls of the gate structure and within the first isolation trench; The second dielectric structure is formed in an opening formed after etching away the intermediate layer between the gate structures and the gate structure on the first isolation region; the intermediate layer is located between adjacent gate structures and covers the sidewall surfaces of the gate structures; and in the process of etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, the etching selectivity of the gate structure and the intermediate layer is within a preset range.

2. The semiconductor structure according to claim 1, wherein The substrate also includes a second isolation region, one of the plurality of gate structures spans the second isolation region, and, on the second isolation region, the gate structure spanning the second isolation region has a second opening passing through the gate structure, and the second dielectric structure is also located in the second opening.

3. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of interconnect structures are located in the second dielectric structure, and at least one of the interconnect structures spans the first isolation region.

4. The semiconductor structure according to claim 1, wherein: Also includes: An etch stop layer is located between the substrate and the second dielectric structure outside the first isolation region, and the etch stop layer is also located on the sidewall surface of the gate structure.

5. The semiconductor structure according to claim 1, wherein The base includes a substrate and a plurality of fin structures separated from each other and located on the substrate, and a plurality of gate structures spans across the plurality of fin structures.

6. A semiconductor structure, characterized in that include: a substrate comprising a first isolation region; a plurality of gate structures and an intermediate layer located on the substrate, wherein the intermediate layer is also located on the sidewalls of the gate structures, and at least two gate structures span the first isolation region; a first opening located in the middle layer and extending through the plurality of gate structures on the first isolation region; The intermediate layer is formed in the opening formed after removing the first dielectric structure; the first dielectric structure is formed on the surface of the substrate before forming the intermediate layer, the first dielectric structure has multiple gate openings, and at least two gate openings span the first isolation region; the gate structure is formed in the gate opening.

7. The semiconductor structure according to claim 6, wherein: The material of the intermediate layer includes non-dielectric material or semiconductor material.

8. The semiconductor structure according to claim 7, wherein: The material of the intermediate layer includes: metal compounds, silicon carbide, silicon germanium or multi-element semiconductor materials composed of III-V group elements.

9. The semiconductor structure according to claim 6, wherein: The material of the intermediate layer includes a dielectric material.

10. The semiconductor structure according to claim 6, wherein: Also includes: An isolation structure is located in the first opening.

11. The semiconductor structure according to claim 6, wherein: The base includes a substrate and a plurality of fin structures separated from each other and located on the substrate, and a plurality of gate structures spans across the plurality of fin structures.

12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first isolation region; forming a plurality of gate structures and an intermediate layer on the substrate, wherein the intermediate layer is also located on the sidewall surface of the gate structure, and at least two gate structures span the first isolation region; Etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures to form a first opening in the intermediate layer that penetrates the plurality of gate structures on the first isolation region, wherein in the process of etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, an etching selectivity ratio between the gate structure and the intermediate layer is within a preset range; The method further comprises: After forming the first opening, removing the intermediate layer; after removing the intermediate layer, forming a second dielectric structure on the surface of the substrate, wherein the second dielectric structure is also located on the sidewall surface of the gate structure; Alternatively, before forming the intermediate layer, a first dielectric structure is formed on the surface of the substrate, wherein the first dielectric structure has a plurality of gate openings, and at least two gate openings span the first isolation region; a gate structure is formed in the gate opening; after forming the gate structure, the first dielectric structure is removed; and after removing the first dielectric structure, the intermediate layer is formed on the surface of the substrate.

13. The method for forming a semiconductor structure according to claim 12, wherein: The preset range is 4:5 to 6:

5.

14. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the intermediate layer includes: forming a plurality of dummy gate structures on the substrate; after forming the dummy gate structures, forming an intermediate layer covering the sidewalls of the dummy gate structures on the surface of the substrate; after forming the intermediate layer, removing the dummy gate structures.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the gate structure includes: forming the gate structure in the gate opening after forming the intermediate layer.

16. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the first dielectric structure and the gate opening includes: forming a plurality of dummy gate structures on the substrate; after forming the dummy gate structures, forming a first dielectric structure on the substrate surface covering the sidewall surfaces of the dummy gate structures; after forming the first dielectric structure, removing the dummy gate structures.

17. The method for forming a semiconductor structure according to claim 12, wherein: The material of the intermediate layer includes non-dielectric material or semiconductor material.

18. The method for forming a semiconductor structure according to claim 17, wherein: The material of the intermediate layer includes: metal compounds, silicon, silicon germanium or multi-component semiconductor materials composed of III-V group elements.

19. The method for forming a semiconductor structure according to claim 17, wherein: In the process of etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, the gas used includes at least one of Cl 2 , BCl 3 , HCl and SiCl 4 .

20. The method for forming a semiconductor structure according to claim 12, wherein: The etching process for removing the intermediate layer has an etching selectivity ratio of 5:1 or more for the intermediate layer and the gate structure.

21. The method for forming a semiconductor structure according to claim 12, wherein: The material of the second dielectric structure includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, silicon oxynitride and silicon hydroxide.

22. The method for forming a semiconductor structure according to claim 21, wherein: Also includes: A plurality of interconnect structures are formed in the second dielectric structure, and at least one interconnect structure spans the first isolation region.

23. The method for forming a semiconductor structure according to claim 12, wherein: The material of the intermediate layer is a dielectric material; the method for forming the semiconductor structure further includes: forming an isolation structure in the first opening.

24. The method for forming a semiconductor structure according to claim 23, wherein: Also includes: The isolation structure and the intermediate layer are etched to form a plurality of interconnect structures in the intermediate layer, wherein at least one interconnect structure spans across the first isolation region.

25. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: An etch stop layer is formed between the substrate and the intermediate layer, and the etch stop layer is also located on the sidewall surface of the gate structure.

26. The method for forming a semiconductor structure according to claim 25, wherein: Also includes: While etching the gate structure on the first isolation region and the intermediate layer between adjacent gate structures, the etching stop layer on the first isolation region is also etched.

27. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the first opening includes: forming an isolation mask structure on the surface of the gate structure and the surface of the intermediate layer, the isolation mask structure having a first isolation opening, the first isolation opening exposing the gate structure on the first isolation region and the surface of the intermediate layer between adjacent gate structures; using the isolation mask structure as a mask, etching the gate structure and the intermediate layer between adjacent gate structures until the gate structure on the first isolation region and the intermediate layer between adjacent gate structures are removed.

28. The method for forming a semiconductor structure according to claim 12, wherein: The substrate also includes a second isolation region, and one of the multiple gate structures spans the second isolation region; the method for forming the semiconductor structure also includes: removing the gate structure on the second isolation region while removing the gate structure on the first isolation region and the intermediate layer between adjacent gate structures.

29. The method for forming a semiconductor structure according to claim 12, wherein: The base includes a substrate and a plurality of fin structures separated from each other and located on the substrate, and the gate structure spans across the plurality of fin structures.

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