memory

Abstract

The application provides a memory. By forming a sidewall nitride layer on at least part of the sidewall of a bit line, the bit line can be protected from oxidation under the isolation of the sidewall nitride layer. In particular, when the bit line includes a metal material layer, a sidewall metal nitride layer can be formed on the sidewall of the metal material layer, which not only prevents the metal material layer from being oxidized, but also further improves the electrical conduction performance of the bit line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a memory. BACKGROUND

[0002] With the semiconductor industry entering a new era of high performance and multi-functional integrated circuits, the size of semiconductor elements in integrated circuits is gradually reduced to adapt to the development trend of increasing density of integrated circuits. For the conductive parts in semiconductor elements for realizing electrical transmission, as the size of the conductive parts is continuously reduced, how to ensure the electrical conduction performance is still an important issue in the field. SUMMARY

[0003] The present application aims to provide a memory for ensuring the electrical conduction performance of bit lines. The present application provides a memory, comprising: a substrate, a plurality of active regions are defined in the substrate; a plurality of bit line contact portions are located in the substrate and are electrically connected with the plurality of active regions; a plurality of bit lines, the bit lines cover the bit line contact portions, the bit lines comprise a bottom polysilicon layer, a metal material layer and a dielectric material shielding layer which are sequentially stacked, the sidewall of the metal material layer has a sidewall metal nitride layer; an insulating cover layer, the insulating cover layer covers the dielectric material shielding layer, the sidewall metal nitride layer on the sidewall of the metal material layer and the bottom polysilicon layer.

[0004] Optionally, the bit line further comprises a thin film metal nitride layer, the thin film metal nitride layer is located below the metal material layer, and the bottom of the sidewall metal nitride layer on the sidewall of the metal material layer is connected to the sidewall of the thin film metal nitride layer.

[0005] Optionally, the bottom polysilicon layer is located on the bit line contact portion, and the sidewall of the bottom polysilicon layer has a sidewall silicon nitride layer.

[0006] Optionally, the material of the bit line contact portion comprises polysilicon, and the sidewall of the bit line contact portion has a sidewall silicon oxide layer, the sidewall silicon oxide layer is located between the insulating cover layer and the polysilicon material of the bit line contact portion, and the thickness of the sidewall silicon oxide layer is greater than the thickness of the sidewall silicon nitride layer.

[0007] Optionally, the sidewall of the bit line contact portion has a first sidewall oxide layer, the first sidewall oxide layer is in direct contact with the bit line contact portion.

[0008] Optionally, the thickness of the sidewall metal nitride layer is greater than the thickness of the first sidewall oxide layer.

[0009] Optionally, the memory further comprises an insulating covering layer, the insulating covering layer continuously covers the bit line and the bit line contact, and the dielectric constant of the first sidewall oxide layer is lower than the dielectric constant of the insulating covering layer.

[0010] Optionally, the substrate has a plurality of bit line contact windows, the bit line contact windows expose the active region at least at the bottom, and the plurality of bit line contact portions one-to-one correspond in the plurality of bit line contact windows, and the bottom of the first sidewall oxide layer at least partially contacts the active region.

[0011] Optionally, the bit line contact window extends laterally into the adjacent isolation region beyond the active region in the width direction of the active region, and the first sidewall oxide layer extends laterally into the isolation region from the active region, so that the bottom of the first sidewall oxide layer also contacts the inner wall of the trench in the isolation region.

[0012] In the memory provided by the application, a sidewall nitride layer is further formed on at least part of the sidewall of the bit line, so that the problem of oxidation of the bit line can be avoided under the isolation protection of the sidewall nitride layer, and the electrical conduction performance of the bit line is guaranteed. In particular, when the bit line comprises a metal material layer, a sidewall metal nitride layer can be formed on the sidewall of the metal material layer, which not only prevents the problem of oxidation of the metal material layer, but also helps to further improve the electrical conduction performance of the bit line. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 The structure schematic diagram of the memory in an embodiment of the application;

[0014] Figure 2a The structure schematic diagram of the memory in an embodiment of the application further shows an insulating covering layer;

[0015] Figure 2b The structure schematic diagram of Figure 2a The partial enlarged view of the A area in the structure schematic diagram shown;

[0016] Figure 3 The flowchart of the forming method of the memory in an embodiment of the application;

[0017] Figures 4a to 4f The structure schematic diagram of the forming method of the memory in an embodiment of the application in the preparation process.

[0018] Among them, the reference signs are as follows:

[0019] 100-substrate;

[0020] 110-trench isolation structure;

[0021] 120-bit line contact window;

[0022] 200-bit line contact section;

[0023] 200a - First sidewall oxide layer;

[0024] 210-position line contact material layer;

[0025] 300-bit line;

[0026] 310 - Bottom polycrystalline silicon layer;

[0027] 310a - Sidewall silicon oxide layer;

[0028] 320-Thin metal nitride layer;

[0029] 330 - Metallic material layer;

[0030] 330a - Sidewall metal nitride layer;

[0031] 340 - Dielectric material shielding layer;

[0032] 400 - Insulating shielding layer;

[0033] 500 - Second sidewall oxide layer;

[0034] 600 - Isolation layer. Detailed Implementation

[0035] The memory proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0036] Figure 1 This is a schematic diagram of the memory structure according to one embodiment of the present invention. Figure 2a A schematic diagram of the structure of the insulating cover layer is also shown in one embodiment of the memory of the present invention. Figure 2b for Figure 2a A magnified view of region A in the structural schematic diagram shown.

[0037] Key reference Figure 1 and Figure 2b As shown, the memory includes a substrate 100 and bit lines formed on the substrate 100. Specifically, the bit lines include bit lines 300 and bit line contacts 200 formed below the bit lines 300 and electrically connected to the bit lines 300.

[0038] Specifically, a plurality of active regions AA are formed in the substrate 100, and isolation regions can be formed between adjacent active regions AA to separate the adjacent active regions AA from each other. In this embodiment, a plurality of trench isolation structures 110 are formed in the substrate 100, and the trench isolation structures 110 surround the periphery of the active regions AA to isolate the adjacent active regions AA. It can also be understood that the active regions AA are defined by forming the trench isolation structures 110.

[0039] Further, the active regions AA have first source / drain regions S / D1 and second source / drain regions S / D2. Specifically, each of the active regions AA extends along a first direction, and the first source / drain region S / D1 in each of the active regions AA corresponds to a middle region of the active region AA, and the second source / drain regions S / D2 are formed on both ends of the active region AA (i.e., two second source / drain regions S / D2 are arranged on both sides of the first source / drain region S / D1, respectively).

[0040] In this embodiment, the active regions AA are used to form memory cells, such as memory transistors. The first source / drain regions S / D1 and the second source / drain regions S / D2 can be used to constitute the drain region and the source region of the memory transistor, and the first source / drain regions S / D1 are electrically connected to bit lines (specifically, a bit line contact 200 is formed on each of the first source / drain regions S / D1, so that the first source / drain regions S / D1 can be further electrically connected to the bit line 300 through the bit line contact 200), and the second source / drain regions S / D2 are electrically connected to a storage node contact to be further electrically connected to a storage capacitor through the storage node contact.

[0041] Continuing to refer to FIGS. 1, 2, 3, and 4, Figure 1 and Figure 2b In this embodiment, the bit line contact 200 is formed in the substrate 100. Specifically, a plurality of bit line contact windows are formed in the substrate 100, and the bit line contacts 200 are formed one by one in the bit line contact windows. The bit line contact window exposes at least a part of the active region AA (in this embodiment, the first source / drain region S / D1) at the bottom, so that the bit line contact 200 formed in the bit line contact window electrically contacts the active region AA.

[0042] Further, the bit line contact window extends laterally into the isolation region adjacent to the corresponding active region (in this embodiment, into the trench isolation structure 110) beyond the width of the active region, i.e., the opening size of the bit line contact window in the width direction of the active region is greater than the width size of the active region, so as to expose the first source / drain region S / D1 as large as possible, and the bit line contact window with large opening size is also beneficial to reduce the difficulty of preparation of the bit line contact 200. In addition, the bottom surface of the bit line contact window is higher than the bottom boundary of the first source / drain region S / D1, i.e., the depth of the recess of the bit line contact window in the substrate 100 is less than the doping depth of the first source / drain region S / D1 in the substrate.

[0043] With reference to the drawings again, Figure 1 As shown, the sidewall of the bit line contact 200 is further formed with a first sidewall oxide layer 200a, which is formed by performing an oxidation process on the bit line contact 200, for example. Specifically, the material of the bit line contact 200 can include polysilicon, and the first sidewall oxide layer 200a is a sidewall silicon oxide layer.

[0044] That is, in this embodiment, the first sidewall oxide layer 200a with low dielectric constant is preferentially covered on the sidewall of the bit line contact 200, so as to preliminarily isolate the sidewall of the bit line contact 200 by using the first sidewall oxide layer 200a, which is equivalent to reducing the dielectric constant of the dielectric material between adjacent bit lines, and is beneficial to reduce the coupling capacitance between adjacent bit lines.

[0045] With reference to the drawings again, Figure 2b As shown, the bottom of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 at least partially contacts the active region AA. Further, the first sidewall oxide layer 200a also extends laterally from the active region AA into the isolation region, so that the bottom of the first sidewall oxide layer 200a also contacts the inner wall of the trench in the isolation region. That is, in this embodiment, the first sidewall oxide layer 200a covers the edge of the active region AA and extends to the trench isolation structure 110. At this time, the active region in the bit line contact window is covered by the bit line contact 200 and the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 and is not exposed.

[0046] In addition, an isolation layer 600 is formed on the top surface of the substrate 100, and an opening is formed in the isolation layer 600 corresponding to the region of the bit line contact window. It can be understood that the bit line contact window extends through the isolation layer 600 and downwardly to the substrate 100, and the top surface of the bit line contact portion 200 and the top surface of the isolation layer 600 are flush, and the bit line 300 is formed above the isolation layer 600. In the embodiment, the isolation layer 600 exposes the first source / drain region and covers the second source / drain region, and at this time, the isolation layer 600 can be used to avoid the electrical connection between the bit line 300 formed above the substrate and the second source / drain region.

[0047] With reference to the drawings again, Figure 1 As shown, the bit line 300 is formed on the isolation layer 600 and extends along a predetermined direction, and the bit line 300 also covers a plurality of bit line contact portions 200 arranged on the extension path of the bit line 300. That is, the plurality of bit line contact portions 200 on the extension path of the bit line 300 are electrically connected to the bit line 300, so as to realize the electrical transmission between the bit line 300 and the corresponding active region through the bit line contact portion 200.

[0048] Further, at least part of the sidewall of the bit line 300 also forms a sidewall nitride layer (in the embodiment, the sidewall nitride layer includes a sidewall metal nitride layer 330a and a sidewall silicon nitride layer 310a) based on the nitriding treatment. It should be noted that since the sidewall of the bit line 300 forms the sidewall nitride layer, the bit line 300 can be prevented from being oxidized under the isolation protection of the sidewall nitride layer (for example, when the sidewall of the bit line contact portion 200 is subjected to an oxidation treatment to form a first sidewall oxide layer 200a, the bit line 300 can be prevented from being oxidized under the isolation protection of the sidewall nitride layer). In particular, when the bit line 300 includes a metal material layer, the metal material layer will directly affect the conduction performance after being oxidized.

[0049] In the embodiment, the bit line 300 includes a bottom poly-silicon layer 310, a thin film metal nitride layer 320 and a metal material layer 330 which are sequentially stacked from bottom to top. The material of the metal nitride layer 320 can further include tungsten nitride, titanium nitride or tantalum nitride, and the material of the metal material layer 330 includes tungsten, for example.

[0050] With reference to the drawings again, Figure 1As shown, the sidewall of the metal material layer 330 in the bit line 300 is formed with a sidewall metal nitride layer 330a based on the nitriding treatment, and the bottom of the sidewall metal nitride layer 330a is connected with the sidewall of the thin-film metal nitride layer 320. It can be considered that, in the embodiment, the bottom wall and the sidewall of the metal material layer 330 are both surrounded with the nitride layer, which on one hand avoids the problem that the metal material layer 330 is easily oxidized, and on the other hand is beneficial to improving the electrical conduction performance of the bit line 300. Meanwhile, the metal diffusion barrier function of the metal material layer 330 can be realized by using the metal nitride layer (including the sidewall metal nitride layer 330a), so as to avoid the metal in the metal material layer 330 from diffusing into the peripheral dielectric material layer (not shown in the figure), and prevent the problem of electrical crosstalk of the adjacent bit line.

[0051] In the embodiment, the thickness of the sidewall metal nitride layer 330a on the sidewall of the metal material layer 330 is further greater than the thickness of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200.

[0052] Continuing to refer to Figure 1 As shown, the bottom layer polysilicon layer 310 in the bit line 300 directly contacts the bit line contact 200 formed thereon, and the sidewall of the bottom layer polysilicon layer 310 is formed with a sidewall silicon nitride layer 310a based on the nitriding treatment. The thickness of the sidewall silicon nitride layer 310a is less than the thickness of the sidewall metal nitride layer 330a.

[0053] In the embodiment, the material of the bit line contact 200 can also include polysilicon, and at this time, the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 can include a sidewall silicon oxide layer, and the thickness of the sidewall silicon oxide layer is greater than the thickness of the sidewall silicon nitride layer 310a.

[0054] In a further scheme, the bit line 300 further includes a dielectric material shielding layer 340 formed on the metal material layer 330 to cover the top surface of the metal material layer 330. The dielectric material shielding layer 340, for example, includes a silicon nitride layer.

[0055] Continuing to refer to Figure 2a and Figure 2bAs shown, the memory further includes an insulating covering layer 400 which continuously covers the bit line 300 and the bit line contact 200. In this embodiment, the insulating covering layer 400 covers the dielectric material shielding layer 340, the sidewall metal nitride layer 330a on the sidewall of the metal material layer 330, the thin film metal nitride layer 320, the sidewall silicon nitride layer 310a on the sidewall of the bottom polycrystalline silicon layer 310, and the first sidewall oxide layer 200a on the sidewall of the bit line contact 200.

[0056] That is, by using the insulating covering layer 400, on one hand, the adjacent bit lines BL can be further isolated, and on the other hand, the mechanical strength of the bit line BL can be improved, and the appearance of the bit line BL can be ensured. Specifically, the material of the insulating covering layer 400 includes, for example, silicon nitride.

[0057] Further, the dielectric constant of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 is lower than the dielectric constant of the insulating covering layer 400. In this embodiment, the dielectric constant of the sidewall silicon oxide layer on the sidewall of the bit line contact 200 is lower than the dielectric constant of the silicon nitride material of the insulating covering layer 400. Thus, it is beneficial to reduce the overall dielectric constant of the dielectric material between the adjacent bit lines BL, so as to correspondingly reduce the parasitic capacitance between the adjacent bit lines BL.

[0058] In this embodiment, the insulating covering layer 400 further extends to cover the trench sidewall in the trench isolation structure, and can further cover the isolation layer 600 between the adjacent bit lines BL.

[0059] In addition, with reference to Figure 2b As shown, since the width size of the bit line contact 200 is smaller than the opening size of the bit line contact window, there is a certain distance between the sidewall of the bit line contact 200 and the trench sidewall of the bit line contact window. At this time, the insulating material (for example, the second sidewall oxide layer 500) can be filled between the first sidewall oxide layer 200a and the trench sidewall.

[0060] In the embodiment, the bit line contact is surrounded by the insulating covering layer 400 after the insulating covering layer 400 covers the side of the bit line contact 200, and the second sidewall oxide layer 500 is filled in the inner groove. In addition, the highest interface of the second sidewall oxide layer 500 is further higher than the highest interface of the first sidewall oxide layer 200a. Specifically, the insulating covering layer 400 covers the groove sidewall of the bit line contact and further extends to cover the top surface of the isolation layer 600, so that the highest interface of the insulating covering layer 400 on the isolation layer 600 is higher than the highest interface of the first sidewall oxide layer 200a. In the embodiment, the highest interface of the second sidewall oxide layer 500 and the highest interface of the insulating covering layer 400 on the isolation layer 600 are flush or close to flush.

[0061] Based on the memory as described above, the following will be described in combination with the accompanying drawings Figure 3 and the accompanying drawings Figures 4a to 4f The forming method thereof will be described in detail. In the embodiment, the memory is formed by the following steps. Figure 3 FIG. 1 is a flowchart of a forming method of the memory in an embodiment of the present application, Figures 4a to 4f FIG. 2 is a structural diagram of the forming method of the memory in an embodiment of the present application in the preparation process thereof.

[0062] Firstly, step S100 is performed. Specifically, referring to FIG. 1, a substrate 100 is provided, and a plurality of active regions AA are defined in the substrate 100. In addition, a plurality of bit line contacts 120 are formed in the substrate 100, and the bottom of the bit line contact 120 is exposed to the active region AA. In the embodiment, the bit line contact 120 exposes the first source / drain region in the active region AA. Figure 4a Specifically, a plurality of groove isolation structures 110 can be formed in the substrate 100 to define a plurality of active regions AA. In addition, the first source / drain region and the second source / drain region in the active region AA can be formed by an ion implantation process.

[0063] Continuing to refer to FIG. 1, before the bit line contact 120 is formed, the method further includes: forming an isolation layer 600 on the top surface of the substrate 100, and the isolation layer 600 covers the active region AA below.

[0064] Figure 4a In addition, the bit line contact 120 can be formed by performing a photolithography process based on a mask plate and further performing an etching process on the substrate 100. In the embodiment, the bit line contact 120 penetrates the isolation layer 600 and extends downward to the substrate 100.

[0065] In addition, the bit line contact 120 can be formed by performing a photolithography process based on a mask plate and further performing an etching process on the substrate 100. In the embodiment, the bit line contact 120 penetrates the isolation layer 600 and extends downward to the substrate 100.

[0066] ​Further, the opening size of the bit line contact window 120 is greater than the size of the first source / drain region S / D1. In this way, the first source / drain region S / D1 can be exposed to a greater extent, so that the first source / drain region S / D1 can be electrically contacted by a bit line contact portion formed subsequently with a greater area. For example, in the embodiment, the width size of the bit line contact window 120 is greater than the width size of the first source / drain region S / D1 in a direction perpendicular to the extension direction of the active region and in a direction along the extension direction of the active region. That is, the bit line contact window 120 exposes the first source / drain region S / D1 and also extends laterally to expose the trench isolation structure 110 adjacent to the first source / drain region.

[0067] The opening shape of the bit line contact window 120 can be an ellipse, a circle, a rectangle, a rhombus, or other polygons, and the like, which is not limited herein.

[0068] Then, step S200 is performed, and reference is made to Figure 4b As shown, the bit line contact material layer 210 is filled in the bit line contact window 120. The material of the bit line contact material layer 210 includes, for example, polysilicon.

[0069] Further, the bit line contact material layer 210 can be formed by a planarization process. Specifically, the forming method of the bit line contact material layer 210 includes, for example, performing a chemical mechanical polishing process with the isolation layer 600 as a polishing stop layer, so that the bit line contact material layer 210 formed is aligned and filled in the bit line contact window, and the top surface of the bit line contact material layer 210 is flush with the top surface of the isolation layer 600.

[0070] Then, step S300 is performed, and reference is made to Figure 4c As shown, the bit line 300 is formed on the substrate 100, and the bit line 300 extends along a predetermined direction and covers a plurality of bit line contact material layers 210 arranged on the extension path thereof. In the embodiment, the bit line 300 is formed on the isolation layer 600 and covers the bit line contact material layer 210, and the width size of the bit line 300 is less than the width size of the bit line contact material layer 210, so that the bit line contact material layer 210 is also partially exposed.

[0071] Specifically, the forming method of the bit line 300 comprises the following steps. First, a conductive material layer and a dielectric material layer are sequentially formed on the substrate 100. Then, an etching process is performed to pattern the dielectric material layer and the conductive material layer sequentially, thereby forming a dielectric material shielding layer 340 and a conductive layer respectively, to constitute the bit line 300. Further, when etching the conductive material layer, an etching endpoint detection can be performed with the isolation layer 600 as the endpoint, so that the etching stops on the isolation layer 600, i.e. the etching stops on the bit line contact material layer 210.

[0072] In actual application, when performing the etching process, the substrate structure is placed in an etching chamber and a first etching gas is introduced to etch the conductive material layer. The conductive layer of the bit line 300 formed comprises a bottom polysilicon layer 310, a thin film metal nitride layer 320 and a metal material layer 330 stacked from bottom to top. The material of the thin film metal nitride layer 320 can further comprise tungsten nitride, titanium nitride or tantalum nitride, and the material of the metal material layer 330 comprises tungsten, for example.

[0073] In addition, as described above, the width dimension of the bit line 300 is smaller than that of the bit line contact material layer 210, so that the bit line 300 can cover the bit line contact material layer 210 from the middle region of the bit line contact material layer 210, and the two side edge regions of the bit line contact material layer 210 are exposed from the two sides of the bit line 300.

[0074] Then, step S400 is performed. As shown in FIG. 4, a nitriding process is performed to form a sidewall nitride layer on at least part of the sidewall of the bit line 300. Figure 4d

[0075] Specifically, through the nitriding process, the sidewall of the bottom polysilicon layer 310 in the bit line 300 is nitrided to form a sidewall silicon nitride layer 310a, and the sidewall of the metal material layer 330 in the bit line 300 is also nitrided to form a sidewall metal nitride layer 330a, and the bottom of the sidewall metal nitride layer 330a is also connected to the thin film metal nitride layer 320. In the embodiment, the material of the metal material layer 330 is tungsten, and therefore the material of the sidewall metal nitride layer 330a is tungsten nitride. In addition, through the nitriding process, the top surface of the exposed bit line contact material layer 210 can also be partially nitrided.

[0076] ​In actual application, the nitriding treatment can also be performed in the etching cavity. Specifically, when the bit line 300 is etched in the etching cavity, the first etching gas is stopped from being supplied into the etching cavity after the etching endpoint is detected, and nitrogen gas is supplied into the etching cavity to perform the nitriding treatment on the sidewall of the bit line 300. That is, the sidewall nitride layer on the sidewall of the bit line 300 can be formed directly in the same etching cavity without changing the semiconductor processing equipment, which greatly simplifies the processing flow of the device and shortens the preparation time of the device.

[0077] Then, step S500 is performed, and specifically, as shown in Figure 4e the bit line contact material layer is etched to form the bit line contact 200 in the bit line contact window.

[0078] In actual application, the bit line contact material layer can also be etched in the same etching cavity. Specifically, after the nitriding treatment is performed, the second etching gas is supplied into the etching cavity to etch the bit line contact material layer, so as to further improve the processing efficiency of the device.

[0079] As described above, after the nitriding treatment, a nitride layer can also be formed on the top surface of the bit line contact material layer. However, the thickness of the nitride layer on the top surface of the bit line contact material layer is very small (much smaller than the thickness of the isolation layer 600), so that the trace amount of the nitride layer on the top surface of the bit line contact material layer can be quickly consumed when the bit line contact material layer is etched, and the bit line contact material layer is further etched downward to form the bit line contact 200.

[0080] In an optional scheme, when the bit line contact material layer is etched, the sidewall nitride silicon layer 310a on the sidewall of the bottom polysilicon layer 310 can also be etched in a trace amount, so that the thickness of the sidewall nitride silicon layer 310a on the sidewall of the bottom polysilicon layer 310 is reduced, for example, smaller than the thickness of the sidewall metal nitride layer 330a on the sidewall of the metal material layer 330.

[0081] In a further scheme, the method for forming the memory further includes: step S600, forming a first sidewall oxide layer 200a on the sidewall of the bit line contact 200.

[0082] Specifically, as shown in Figure 4f an oxidation treatment is performed to form the first sidewall oxide layer 200a on the sidewall of the bit line contact 200. In the embodiment, the first sidewall oxide layer 200a is a sidewall silicon oxide layer.

[0083] It should be noted that, when the oxidation treatment is performed, since the sidewall of the metal material layer 330 in the bit line 300 is covered with the sidewall nitride layer (i.e., the sidewall metal nitride layer 330a), the problem of oxidation of the metal material layer 330 during the oxidation treatment can be effectively avoided, and the electrical conduction performance of the bit line 300 is ensured.

[0084] In addition, in the embodiment, before the oxidation treatment is performed, the edge of the active region (the first source / drain region S / D1 in the embodiment) is also exposed from both sides of the bit line contact 200. Based on this, when the oxidation treatment is performed, the bottom of the formed first sidewall oxide layer 200a can be in contact with the active region. In addition, by controlling the process parameters of the oxidation treatment, the first sidewall oxide layer 200a formed can also extend laterally from the active region to the isolation region, so that the bottom of the first sidewall oxide layer 200a is also in contact with the inner wall of the trench in the isolation region. In this way, it is ensured that the active region can be completely covered.

[0085] In an optional solution, the thickness of the first sidewall oxide layer 200a on the sidewall of the bit line contact 200 can be further greater than the thickness of the sidewall silicon nitride layer 310a on the sidewall of the bottom poly-silicon layer 310.

[0086] Further, after the oxidation treatment is performed, an insulating cover layer is formed on the substrate 100.

[0087] Specifically, as shown in Figure 2a and Figure 2b The insulating cover layer 400 at least covers the bit line (i.e., covers the bit line 300 and the bit line contact 200). The material of the insulating cover layer 400 includes, for example, silicon nitride. The insulating cover layer 400 can conformally cover the bit line 300 and the bit line contact 200, and also cover the trench sidewall exposed in the bit line contact window, so that an inner trench can be surrounded by the insulating cover layer 400 at the side of the bit line contact 200.

[0088] Based on this, after the insulating cover layer 400 is formed, a second sidewall oxide layer 500 can also be filled in the bit line contact window, i.e., filled at the side of the bit line contact 200.

[0089] In the embodiment, the insulating covering layer 400 covers the sidewall of the bit line contact window, and also extends to cover the top surface of the isolation layer 600, so that the highest interface of the insulating covering layer 400 on the isolation layer 600 is higher than the highest interface of the first sidewall oxide layer 200a. Then, the second sidewall oxide layer 500 is prepared based on the insulating covering layer 400, so that the highest interface of the second sidewall oxide layer 500 is flush with or close to the highest interface of the insulating covering layer 400 on the isolation layer 600, and the highest interface of the second sidewall oxide layer 500 is higher than the highest interface of the first sidewall oxide layer 200a. In this way, the bit line contact 200 and the first sidewall oxide layer 200a on the sidewall thereof can be stably buried in the bit line contact window, and the overall stability and mechanical strength of the bit line are improved.

[0090] In summary, in the memory provided by the embodiment, the first sidewall oxide layer with low dielectric constant is arranged on the sidewall of the bit line contact, and the insulating covering layer is further arranged to cover the bit line contact and the bit line, so that the overall dielectric constant of the dielectric material between adjacent bit lines is reduced, and the mechanical strength of the bit line is ensured, and the problem of deformation or even collapse of the bit line is avoided.

[0091] In addition, in the embodiment, the sidewall nitride layer is further arranged on at least part of the sidewall of the bit line, which can not only protect the metal material layer in the bit line from being oxidized, but also can play a role of metal diffusion barrier, and further improve the electrical conduction performance of the bit line.

[0092] It should be noted that although the present application has been disclosed with the above preferred embodiments, the above embodiments are not intended to limit the present application. For any skilled person in the art, many possible changes, modifications and modifications of the technical solutions of the present application can be made based on the disclosed technical content, or equivalent embodiments with equivalent changes can be modified. Therefore, any simple modification, equivalent change and modification of the above embodiments based on the technical essence of the present application, which does not deviate from the technical solutions of the present application, still belongs to the protection scope of the technical solutions of the present application.

[0093] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the description are only used to distinguish the components, elements, steps and the like in the description, and are not intended to represent the logical relationship or sequence relationship between the components, elements, steps and the like.

[0094] It is also to be appreciated that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the scope of the present application. It must be noted that, as used herein, the articles "a", "an" and "the" are intended to include one or more items, and can be used interchangeably with "at least one" or "one or more." Furthermore, as used herein, the term "set" and "group" are intended to include one or more items, and can be used interchangeably with "one or more." Where only one item is intended, the phrase "only one" or similar language is used. Also, as used herein, the term "plurality" is intended to include one or more items, and can be used interchangeably with "one or more." Additionally, as used herein, the term "exemplary" is intended to be used to describe an example, an implementation, or an example implementation, and is not intended to convey an indication of a recommended or preferred implementation. Moreover, as used herein, the term "or" is intended to mean any one of the items, a combination of any of the items, or all of the items, unless the context clearly indicates otherwise.

Claims

1. A memory, comprising: The application relates to a memory device, comprising: a substrate, in which a plurality of active regions are defined; a plurality of bit line contacts located in the substrate and connected with the plurality of active regions; a plurality of bit lines covering the bit line contacts, the bit lines comprising a bottom polysilicon layer, a metal material layer and a dielectric material shielding layer which are sequentially stacked, wherein the sidewall of the metal material layer has a sidewall metal nitride layer, the sidewall of the bottom polysilicon layer has a sidewall silicon nitride layer, and the sidewall silicon nitride layer is isolated from the metal material layer; an insulating covering layer directly contacting the dielectric material shielding layer, the sidewall metal nitride layer on the sidewall of the metal material layer and the sidewall silicon nitride layer on the sidewall of the bottom polysilicon layer.

2. The memory of claim 1, wherein, The bit lines further comprise a thin film metal nitride layer located below the metal material layer, and the bottom of the sidewall metal nitride layer on the sidewall of the metal material layer is connected with the sidewall of the thin film metal nitride layer.

3. The memory of claim 1, wherein, The bottom polysilicon layer is located on the bit line contact.

4. The memory of claim 3, wherein, The material of the bit line contact comprises polysilicon, and the sidewall of the bit line contact has a sidewall silicon oxide layer located between the insulating covering layer and the polysilicon material of the bit line contact, and the thickness of the sidewall silicon oxide layer is greater than that of the sidewall silicon nitride layer.

5. The memory of claim 1, wherein, The sidewall of the bit line contact has a first sidewall oxide layer, and the first sidewall oxide layer and the bit line contact are directly contacted.

6. The memory of claim 5, wherein, The thickness of the sidewall metal nitride layer is greater than that of the first sidewall oxide layer.

7. The memory of claim 5, wherein, The insulating covering layer continuously covers the bit lines and the bit line contacts, and the dielectric constant of the first sidewall oxide layer is lower than that of the insulating covering layer.

8. The memory of claim 5, wherein, The substrate has a plurality of bit line contact windows, the active regions are at least partially exposed by the bottom of the bit line contact windows, and the plurality of bit line contacts are one-to-one corresponding in the plurality of bit line contact windows, and the bottom of the first sidewall oxide layer at least partially contacts the active regions.

9. The memory of claim 8, wherein, The bit line contact windows extend laterally into the adjacent isolation regions beyond the width of the active regions, and the first sidewall oxide layer extends laterally into the isolation regions from the active regions, so that the bottom of the first sidewall oxide layer also contacts the inner wall of the trench in the isolation region.

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