Loop filter, timing recovery method and apparatus

Abstract

The application provides a loop filter, a timing recovery method and device. The loop filter comprises N input ends for receiving N first signals; wherein N is any one of integers greater than or equal to 2; a source filter, the source filter comprising an integral signal end and an addition end; a first gain processing module for performing first gain processing on the N first signals to obtain a second signal, and outputting the second signal to the addition end; a second gain processing module for performing second gain processing on the N first signals to obtain a third signal, and outputting the third signal to the integral signal end; and a source filter for performing integration on the third signal received by the integral signal end to obtain a fourth signal, and obtaining a fifth signal according to the second signal received by the addition end and the fourth signal.

Description

Technical Field

[0001] This application relates to the field of receivers in communication systems, and particularly to loop filters, timing recovery methods and apparatus. Background Technology

[0002] In digital communication systems, since data is usually transmitted asynchronously from one device to another, the receiver needs to extract clock information from the received signal in order to adjust the local sampling frequency and phase.

[0003] As is well known, the timing recovery loop of a receiver includes: an analog-to-digital converter (ADC), an adaptive equalizer, a slicer, a timing error detector (TED), a loop filter, and an oscillator (such as a voltage-controlled oscillator (VCO) or a numerically controlled oscillator (NCO)). Figure 1 As shown. The timing error detector has two input signal options: the first is the input signal of the adaptive equalizer (i.e., after the ADC output), hereinafter referred to as ADC-TED; the second is the input signal of the decision unit (i.e., after the adaptive equalizer output), hereinafter referred to as Slicer-TED. Each of these timing error detectors has its advantages and disadvantages. Regardless of which timing error detector is used, the stability of the reception performance cannot be guaranteed. Summary of the Invention

[0004] This application provides a loop filter, a timing recovery method, and an apparatus.

[0005] In a first aspect, embodiments of this application provide a loop filter, including:

[0006] There are N input terminals for receiving N first signals; where N is any integer greater than or equal to 2.

[0007] The source filter includes an integration signal terminal and an addition terminal;

[0008] The first gain processing module is used to perform first gain processing on N first signals to obtain a second signal, and output the second signal to the adder terminal;

[0009] The second gain processing module is used to perform second gain processing on N first signals to obtain a third signal, and output the third signal to the integration signal terminal;

[0010] The source filter is used to integrate the third signal received at the integrator terminal to obtain the fourth signal, and to obtain the fifth signal based on the second and fourth signals received at the adder terminal.

[0011] Secondly, embodiments of this application provide a timing recovery device, including: a timing error detection module and a loop filter;

[0012] The timing error detection module is used to determine N first signals and input the N first signals to the N input terminals of the loop filter; wherein the first signals are timing error information, and N is any integer greater than or equal to 2;

[0013] The loop filter includes: N input terminals, a source filter, a first gain processing module, and a second gain processing module; the source filter includes: an integration signal terminal and an addition terminal;

[0014] N input terminals are used to receive N first signals;

[0015] The source filter includes an integration signal terminal and an addition terminal;

[0016] The first gain processing module is used to perform first gain processing on N first signals to obtain a second signal, and output the second signal to the adder terminal;

[0017] The second gain processing module is used to perform second gain processing on N first signals to obtain a third signal, and output the third signal to the integration signal terminal;

[0018] The source filter is used to integrate the third signal received at the integrator terminal to obtain the fourth signal, and to obtain the fifth signal based on the second and fourth signals received at the adder terminal.

[0019] Thirdly, embodiments of this application provide a timed recovery method, including:

[0020] Determine N first signals; where the first signal is timing error information, and N is any integer greater than or equal to 2;

[0021] A second signal is obtained by performing a first gain processing on N first signals;

[0022] A third signal is obtained by performing a second gain processing on N first signals;

[0023] The third signal is integrated to obtain the fourth signal, and the fifth signal is obtained by adding the second and fourth signals.

[0024] Fourthly, embodiments of this application provide a timed recovery method, applied to any of the aforementioned timed recovery devices, where N is 2. The method includes:

[0025] The second timing error detector is used to perform the first timing recovery on the received eighth signal, so that the sampling phase of the analog-to-digital converter converges to the first target phase. During the first timing recovery process, the adaptive equalizer is trained, and the first switch and the second switch are disconnected.

[0026] After the adaptive equalizer training is completed, the first timing error detector and the second timing error detector are used together to perform a second timing recovery on the received eighth signal, so that the sampling phase of the analog-to-digital converter converges to the second target phase;

[0027] The first timing error detector is used to perform a third timing recovery on the received ninth signal. During the third timing recovery process, the equalization coefficient of the adaptive equalizer is stopped from being updated, and the first switch is closed to measure the mean value of the second original timing error information output by the second timing error detector. The autocorrelation characteristics of the ninth signal are different from those of the eighth signal.

[0028] After measuring the mean value of the second original timing error information output by the second timing error detector, the first timing error detector and the second timing error detector are used together to perform a fourth timing recovery. During the fourth timing recovery process, the equalization coefficient of the adaptive equalizer is updated, the first switch is turned off, and the second switch is turned on to output the mean value of the second original timing error information. The second timing error information is obtained by subtracting the mean value from the second original timing error information.

[0029] The loop filter provided in this application embodiment has N input signals, which makes the loop filter have 2N independent configurable gain parameters, so that the advantages of N input signals can be fully combined.

[0030] The timing recovery device provided in this application uses N timing error information in combination for timing recovery, so that the advantages and disadvantages of the N timing error information complement each other, thereby improving the timing recovery performance. In addition, the loop filter has N input signals, so the loop filter has 2N independent configurable gain parameters, which can fully combine the advantages of the N timing error information, thereby further improving the timing recovery performance.

[0031] The timing recovery method provided in this application embodiment performs third timing recovery on the received ninth signal using only the first timing error detector after the sampling phase of the analog-to-digital converter converges to the second target phase. Since the first timing error detector extracts the first original timing error information based on the second digital signal output by the adaptive equalizer, the inter-symbol interference (ISI) of the second digital signal tends to be 0, ensuring that the stable phase does not change significantly before and after the change in the autocorrelation characteristics of the received signal, i.e., it remains stable at the target phase. Furthermore, the equalization coefficient of the adaptive equalizer is stopped from being updated during the third timing recovery process, so that the first timing error detector is not affected by the adaptive update of the equalization coefficient of the adaptive equalizer. This ensures that the sampling phase of the analog-to-digital converter remains stable at the second target phase during the third timing recovery process. As a result, the target measurement can be performed during the third timing recovery process for a relatively long duration while maintaining high accuracy. Attached Figure Description

[0032] Figure 1 A schematic diagram of the receiver timing recovery loop in a related technology;

[0033] Figure 2 A schematic diagram of the timing recovery loop of the combined ADC-TED and Slicer-TED under the condition of a conventional loop filter;

[0034] Figure 3 for Figure 2 A schematic diagram of the equivalent timing recovery loop;

[0035] Figure 4 This is a block diagram of a timing recovery device provided in one embodiment of the present application;

[0036] Figure 5 This is a schematic diagram of a timing recovery device that uses two timing error detectors in combination, as described in an embodiment of this application.

[0037] Figure 6 This is a schematic diagram of the ADC-TED according to an embodiment of this application;

[0038] Figure 7 This is a schematic diagram of the Slicer-TED according to an embodiment of this application;

[0039] Figure 8 This is a schematic diagram of the target measurement circuit in an embodiment of this application;

[0040] Figure 9 A flowchart of a timed recovery method provided in another embodiment of this application;

[0041] Figure 10A flowchart of a timed recovery method provided in another embodiment of this application. Detailed Implementation

[0042] To enable those skilled in the art to better understand the technical solutions of this application, the loop filter, timing recovery method and apparatus provided in this application will be described in detail below with reference to the accompanying drawings.

[0043] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.

[0044] Where there is no conflict, the various embodiments of this application and the features thereof may be combined with each other.

[0045] As used herein, the term “and / or” includes any and all combinations of at least one related enumerated entry.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of at least one other feature, integral, step, operation, element, component, and / or group thereof is not excluded.

[0047] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0048] The first type of timing error detector (ADC-TED) suffers from severe inter-symbol interference (ISI) in the input signal of the adaptive equalizer. Therefore, extracting timing error information from the input signal of the adaptive equalizer results in large self-noise, leading to large phase jitter and thus poor reception performance. However, the input signal of the adaptive equalizer is only affected by the phase adjustment of the ADC sampling and is not affected by the adaptive update of the equalizer coefficients.

[0049] Conversely, the second type of timing error detector (Slicer-TED) has relatively small phase jitter because most of the ISI has been eliminated from the input signal of the decision device. However, the input signal of the decision device is affected by both the ADC sampling phase adjustment and the adaptive update of the equalizer coefficients. This causes timing recovery and adaptive equalization to interfere with each other, resulting in a slow drift of the sampling phase and ultimately leading to unstable reception performance.

[0050] Note that ADC-TED and Slicer-TED have complementary advantages and disadvantages, so a natural idea is to use them in combination. However, traditional loop filters only have one input signal, so one approach is to multiply the output signals of ADC-TED and Slicer-TED by a certain gain, add them together (i.e., linear combination), and then transmit this result to the traditional loop filter, such as... Figure 2 As shown. While this approach achieves some degree of combined use of ADC-TED and Slicer-TED, it essentially only has three independently configurable gain parameters, failing to fully leverage the advantages of both ADC-TED and Slicer-TED. This is because, although... Figure 2 There are four configurable gain parameters (g) 0s g 0a (g1 and g2), but will Figure 2 Equivalent transformation (assuming g) 0s ≠0) Figure 3 Ultimately, there are only three independently configurable gain parameters.

[0051] Figure 3 In this process, the ratio between ADC-TED and Slicer-TED can only be adjusted by g0′. To suppress the large self-noise of ADC-TED, g0′ must be much smaller than 1. However, this would make Slicer-TED dominant and still subject to the adaptive update of the equalizer coefficients, potentially leading to unstable reception performance. Therefore, g0′ cannot be too small, but this would not be sufficient to suppress the self-noise of ADC-TED.

[0052] However, ADC-TED also presents other problems. To avoid erroneous transmission from the decision feedback equalizer, some communication systems use Tomlinson-Harashima precoding (THP). During system startup, after switching to THP mode, the transmitter first sends a THP Pulse Amplitude Modulation (PAM)2 training signal, and the receiver performs timing recovery and trains the adaptive equalizer. Only after training is complete will the transmitter send the THP PAM16 data signal. In this case, using ADC-TED introduces new problems.

[0053] As is well known, the transmission characteristics (commonly referred to as S-Curve) of a timing error detector are related to the autocorrelation characteristics of the received signal. During the aforementioned startup process, the different autocorrelation characteristics of the THP PAM2 training signal and the THP PAM16 data signal cause a significant change in the stable phase of the ADC-TED. Upon entering the THP PAM16 data signal stage, the timing recovery converges to a new stable phase, thereby degrading equalizer performance and potentially leading to unstable reception performance.

[0054] The current solution involves using target measurement to ensure that timing recovery remains locked at the original target phase when the autocorrelation characteristics of the received signal change. Target measurement refers to measuring the average output of the timing error detector while the sampled phase is stable at the target phase. After the target measurement is completed, the output of the timing error detector is subtracted from this average value before being transmitted to the loop filter, thus ensuring that timing recovery remains locked at the original target phase.

[0055] However, this method does not specifically address how to ensure the sampled phase remains stable at the target phase during the target measurement. Because during the target measurement, without additional measures, the timing recovery loop is in an open-loop state. If the residual frequency offset between the transmitter and receiver is large, and if the target measurement duration is long, the sampled phase will drift away from the target phase. One approach is to ensure the target measurement duration is short enough to prevent the sampled phase from drifting away, but this cannot guarantee sufficient accuracy in measuring the mean of the error signal.

[0056] It should be noted that although the loop filter, timing recovery method and apparatus of the embodiments of this application are based on the combined use of two timing error detectors, ADC-TED and Slicer-Ted, they can also be applied to scenarios where three or more timing error detectors are used in combination for timing recovery.

[0057] Although the loop filter in this application is proposed based on the scenario of using two timing error detectors, ADC-TED and Slicer-Ted, for timing recovery, it can also be applied to other application scenarios, such as any scenario in a phase-locked loop that requires the combined use of two or more phase detectors.

[0058] Before introducing the loop filter, timing recovery method and apparatus of this application, the functions of each component in the timing recovery loop will be introduced first.

[0059] like Figure 1 As shown, an ADC is used to sample the received analog input signal according to the sampling frequency and sampling phase to obtain a first digital signal. The sampling frequency of the ADC can be one time, two times or other oversampling factors of the symbol rate. In order to improve the accuracy of the decision symbol and reduce the bit error rate, an oversampling factor is usually used.

[0060] An adaptive equalizer is used to equalize a first digital signal to obtain a second digital signal.

[0061] A decision unit is used to map a second digital signal to a corresponding output signal, i.e., one of several known possible sign values;

[0062] The timing error detector includes an ADC-TED and a Slicer-TED. The ADC-TED is used to determine timing error information based on a first digital signal and the output signal of a decision unit; the Slicer-TED is used to determine timing error information based on a second digital signal and the output signal of a decision unit.

[0063] A loop filter is used to filter timing error information to obtain filtered timing error information.

[0064] An oscillator is used to control the sampling phase of the ADC based on the filtering timing error information.

[0065] In a first aspect, one embodiment of this application provides a loop filter, comprising:

[0066] There are N input terminals for receiving N first signals; where N is any integer greater than or equal to 2.

[0067] The source filter includes an integration signal terminal and an addition terminal;

[0068] The first gain processing module is used to perform first gain processing on N first signals to obtain a second signal, and output the second signal to the adder terminal;

[0069] The second gain processing module is used to perform second gain processing on N first signals to obtain a third signal, and output the third signal to the integration signal terminal;

[0070] The source filter is used to integrate the third signal received at the integrator terminal to obtain the fourth signal, and to obtain the fifth signal based on the second and fourth signals received at the adder terminal.

[0071] In some exemplary embodiments, the first gain processing module includes: N first multipliers 4021 and first adders 4022;

[0072] The j-th first multiplier 4021 is used to multiply the j-th first signal by the j-th gain parameter to obtain the j-th sixth signal; where j is any integer greater than or equal to 1 and less than or equal to N;

[0073] The first adder 4022 is used to add N sixth signals to obtain the second signal.

[0074] In some exemplary embodiments, the second gain processing module includes: N second multipliers 4023 and a second adder 4024;

[0075] The j-th second multiplier 4023 is used to multiply the j-th first signal by the (j+N)-th gain parameter to obtain the j-th seventh signal; where j is any integer greater than or equal to 1 and less than or equal to N;

[0076] The second adder 4024 is used to add N seventh signals to obtain the third signal.

[0077] In some exemplary embodiments, the source filter further includes an integrator 4025 and a third adder 4026;

[0078] The integrator 4025 is used to integrate the third signal to obtain the fourth signal;

[0079] The third adder 4026 is used to add the second and fourth signals to obtain the fifth signal.

[0080] In some exemplary embodiments, the first signal is timing error information and the fifth signal is filtered timing error information.

[0081] It should be noted that the loop filter of this application embodiment can be applied to scenarios that require the combined use of two or more timing error detectors, as well as any scenario in a phase-locked loop that requires the combined use of two or more phase detectors, and any other scenario that requires the combined use of two or more input signals. The loop filter of this application embodiment does not limit the specific scenario.

[0082] The loop filter provided in this application embodiment has N input signals, which makes the loop filter have 2N independent configurable gain parameters, so that the advantages of N input signals can be fully combined.

[0083] Figure 4 A block diagram of a timing recovery device provided in another embodiment of this application.

[0084] Secondly, referring to Figure 4 Another embodiment of this application provides a timing recovery device, including: a timing error detection module 401 and a loop filter 402;

[0085] The timing error detection module 401 is used to determine N first signals and input the N first signals to the N input terminals of the loop filter; wherein the first signals are timing error information, and N is any integer greater than or equal to 2;

[0086] The loop filter 402 includes: N input terminals, a source filter, a first gain processing module, and a second gain processing module; the source filter includes: an integration signal terminal and an addition terminal;

[0087] N input terminals are used to receive N first signals;

[0088] The source filter includes an integration signal terminal and an addition terminal;

[0089] The first gain processing module is used to perform first gain processing on N first signals to obtain a second signal, and output the second signal to the adder terminal;

[0090] The second gain processing module is used to perform second gain processing on N first signals to obtain a third signal, and output the third signal to the integration signal terminal;

[0091] The source filter is used to integrate the third signal received at the integrator terminal to obtain the fourth signal, and to obtain the fifth signal based on the second and fourth signals received at the adder terminal.

[0092] In some exemplary embodiments, the first gain processing module includes: N first multipliers 4021 and first adders 4022;

[0093] The j-th first multiplier 4021 is used to multiply the j-th first signal by the j-th gain parameter to obtain the j-th sixth signal; where j is any integer greater than or equal to 1 and less than or equal to N;

[0094] The first adder 4022 is used to add N sixth signals to obtain the second signal.

[0095] In some exemplary embodiments, the second gain processing module includes: N second multipliers 4023 and a second adder 4024;

[0096] The j-th second multiplier 4023 is used to multiply the j-th first signal by the (j+N)-th gain parameter to obtain the j-th seventh signal; where j is any integer greater than or equal to 1 and less than or equal to N;

[0097] The second adder 4024 is used to add N seventh signals to obtain the third signal.

[0098] In some exemplary embodiments, the source filter further includes an integrator 4025 and a third adder 4026;

[0099] The integrator 4025 is used to integrate the third signal to obtain the fourth signal;

[0100] The third adder 4026 is used to add the second and fourth signals to obtain the fifth signal, which is the filtering timing error information.

[0101] It should be noted that the loop filter 402 includes two branches: a proportional branch and an integrator branch. The proportional branch includes N first multipliers 4021 and first adders 4022; the integrator branch includes N second multipliers 4023, second adders 4024 and an integrator 4025.

[0102] The loop filter 402 has N input signals (i.e. N first signals, i.e. timing error information) and 2N independent configurable gain parameters. Among them, N gain parameters are the gain parameters of the proportional branch, and the other N gain parameters are the gain parameters of the integral branch. Through these 2N independent configurable gain parameters, the advantages of N timing error information are fully combined.

[0103] In some exemplary embodiments, the timing error detection module 401 includes: N timing error detection units 4011;

[0104] The i-th timing error detection unit 4011 is used to determine the i-th first signal; where i is any integer greater than or equal to 1 and less than or equal to N.

[0105] In other words, timing recovery is achieved by using N timing error detection units 4011 in combination. This involves transmitting the N first signals output by the N timing error detection units 4011 to the loop filter for timing recovery. Since the loop filter has N input signals, which come from the output signals (i.e., the N first signals) of the N timing error detection units 4011 respectively, and has 2N independent configurable gain parameters, it fully combines the advantages of the N timing error detection units 4011.

[0106] In some exemplary embodiments, the i-th timing error detection unit 4011 includes: an i-th timing error detector 40111, which is used to determine the i-th original first signal and use the i-th original first signal as the i-th first signal.

[0107] In some exemplary embodiments, the i-th timing error detection unit 4011 includes: an i-th timing error detector 40111, a target measurement circuit 40112, a first switch 40113, a second switch 40114, and a first subtractor 40115;

[0108] Among them, the i-th timing error detector 40111 is used to determine the i-th original first signal;

[0109] The target measurement circuit 40112 is used to measure the mean of the i-th original first signal;

[0110] One end of the first switch 40113 is connected to the output terminal of the i-th timing error detector 40111, and the other end is connected to the input terminal of the target measurement circuit 40112, used to control the on / off connection between the output terminal of the i-th timing error detector 40111 and the input terminal of the target measurement circuit 40112;

[0111] One end of the second switch 40114 is connected to the output terminal of the target measurement circuit 40112, and the other end is connected to one of the input terminals of the first subtractor 40115, for controlling the on / off connection between the output terminal of the target measurement circuit 40112 and one of the input terminals of the first subtractor 401115.

[0112] The first subtractor 40115 is used to subtract the mean from the i-th original first signal to obtain the i-th first signal.

[0113] In some exemplary embodiments, the timing error detectors 40111 in different timing error detection units 4011 may be the same or different. For example, when N=2, the timing error detector in the first timing error detection unit may be a Slicer-TED, and the timing error detector in the second timing error detection unit may be an ADC-TED, such as... Figure 5As shown, when Slicer-TED and ADC-TED are used together for timing recovery, the loop filter has two input signals, one from the output signal of ADC-TED and the other from the output signal of Slicer-TED, and four independent configurable gain parameters. Therefore, it fully combines the advantages of Slicer-TED and ADC-TED. Specifically, it utilizes the advantages of Slicer-TED to achieve smaller phase jitter in timing recovery, while utilizing the advantages of ADC-TED to ensure that timing recovery is not affected by the adaptive update of the equalization coefficient. This results in a timing recovery device that has both smaller phase jitter and is not affected by the adaptive update of the equalization coefficient, thus improving the performance of timing recovery.

[0114] It should be noted that, Figure 5 The schematic diagram of the timing recovery device is given only as an example of using Slicer-TED and ADC-TED in combination for timing recovery. It does not mean that timing recovery can only be performed by using Slicer-TED and ADC-TED in combination. Other schemes that use two or more timing error detection units in combination for timing recovery are all within the protection scope of the embodiments of this application.

[0115] It should be noted that if the autocorrelation characteristics of the received signal do not change during the timing recovery process; or, although the autocorrelation characteristics of the received signal change, the stable phase of the received signal before and after the change in autocorrelation characteristics is not significantly changed when timing recovery is performed using the i-th timing error detector 40111, then the i-th timing error detection unit 4011 only needs to include the i-th timing error detector 40111; if the autocorrelation characteristics of the received signal change during the timing recovery process, and the stable phase of the received signal before and after the change in autocorrelation characteristics is significantly changed when timing recovery is performed using the i-th timing error detector 40111, then the i-th timing error detection unit 40111 needs to include: the i-th timing error detector 40111, the target measurement circuit 40112, the first switch 40113, the second switch 40114, and the first subtractor 40115.

[0116] For example, when N=2, and the timing error detector in the first timing error detection unit is a Slicer-TED, and the timing error detector in the second timing error detection unit is an ADC-TED, since the stable phase of the received signal before and after the change in the autocorrelation characteristics of the received signal does not change significantly when using Slicer-TED for timing recovery, the first timing error detection unit only needs to include Slicer-TED; while the stable phase of the received signal before and after the change in the autocorrelation characteristics of the received signal changes significantly when using ADC-TED for timing recovery, therefore, in addition to including ADC-TED, the second timing error detection unit also needs to include: a target measurement circuit, a first switch, a second switch, and a first subtractor.

[0117] In some exemplary embodiments, it also includes:

[0118] Analog-to-digital converter 403 is used to sample the received analog input signal to obtain a first digital signal;

[0119] An adaptive equalizer 404 is used to equalize the first digital signal to obtain a second digital signal;

[0120] The decision unit 405 is used to map the second digital signal into a corresponding output signal;

[0121] The i-th timing error detector 40111 is specifically used for:

[0122] The i-th original first signal is determined based on the first digital signal and the output signal;

[0123] Alternatively, the i-th original first signal can be determined based on the second digital signal and the output signal.

[0124] For example, ADC-TED determines the original first signal based on the first digital signal and the output signal of the decision unit, while Slicer-TED determines the original first signal based on the second digital signal and the output signal of the decision unit.

[0125] It should be noted that the i-th timing error detector 40111 can also determine the i-th original first signal based on other principles. The specific principle for determining the i-th original first signal is not intended to limit the protection scope of the embodiments of this application.

[0126] In some exemplary embodiments, the analog-to-digital converter 403 is specifically used for:

[0127] The received analog input signal is sampled according to the sampling frequency and sampling phase to obtain the first digital signal;

[0128] The timed recovery device also includes:

[0129] Oscillator 406 is used to control the sampling phase of the ADC based on the filtering timing error information.

[0130] In some exemplary embodiments, the sampling frequency of the ADC can be one, two, or other oversampling factors of the symbol rate; in order to improve the accuracy of the decision symbols and reduce the bit error rate, an oversampling factor is usually used.

[0131] In some exemplary embodiments, the oscillator 406 may be a VCO or an NCO.

[0132] The timing recovery device provided in this application uses N timing error information in combination for timing recovery, so that the advantages and disadvantages of the N timing error information complement each other, thereby improving the timing recovery performance. In addition, the loop filter has N input signals, so the loop filter has 2N independent configurable gain parameters, which can fully combine the advantages of the N timing error information, thereby further improving the timing recovery performance.

[0133] The following example, using the combined use of Slicer-TED and ADC-TED for timing recovery, illustrates why the timing recovery device of this application can fully combine the advantages of N timing error information.

[0134] Assume the first gain parameter is g 1s The second gain parameter is g 1a The third gain parameter is g 2s The fourth gain parameter is g 2a The raw timing error information output by Slicer-TED is e s(k) The original timing error information output by ADC-TED is e a(k) The mean value of the raw timing error information output by ADC-TED is Therefore, the output signal of the first adder can be expressed as: The output signal of the second adder (i.e., the input signal of the integrator) can be expressed as:

[0135] To illustrate the advantages of the loop filter in this application compared to a traditional loop filter, assumptions are made, and for the sake of simplicity, omissions are made. Therefore, the output signal of the first adder can be equivalently transformed into: The output signal of the second adder is equivalently transformed into:

[0136] In contrast. Figure 3 The output signal of the adder in the upper right corner of a traditional loop filter can be expressed as g'1×(g'0×e). a(k)+e s (k)), the input signal of the integrator can be expressed as g'2×(g'0×e) a (k)+e s (k)).

[0137] Comparing the four formulas above, it can be seen that when the loop filter in this embodiment satisfies: In this case, the loop filter in the embodiment of this application degenerates into a conventional loop filter.

[0138] However, in the embodiments of this application, g can be reduced. 1a The value of this property suppresses phase jitter caused by the large self-noise of the ADC-TED, i.e., when the gain parameter of the loop filter in this embodiment satisfies... At the same time, the timing recovery device of this application embodiment has smaller phase jitter than conventional timing recovery devices (including conventional loop filters).

[0139] More specifically, Figure 3 China e a (k) and e s (k) The ratio between the two can only be adjusted by g0′, and in both the proportional branch and the integral branch, their ratios are the same. However, in the embodiments of this application, e a (k) and e s (k) The ratio between the two can be expressed in the proportional branch by g. 1a / g 1s To adjust, in the integral branch, it can be done through g 2a / g 2s To adjust. In practice, to meet the damping factor requirements of the timing recovery loop, the gain of the proportional branch must be much greater than the gain of the integral branch, for example, g 1s Much greater than g 2s Therefore, the main task is to suppress the large self-noise of ADC-TED in the proportional branch, that is, to set g in the proportional branch. 1a / g 1s Much less than 1, and to take advantage of the ADC-TED's unaffected adaptive updates of equalizer coefficients in the integral branch, g is set in the integral branch. 2a / g 2s It is a relatively large value.

[0140] In summary, the loop filter of this application embodiment fully combines N timing error information through 2N independent configurable gain parameters. For example, it fully combines the advantages of ADC-TED and Slicer-TED, suppresses their respective disadvantages, and even if the timing recovery has small phase jitter, it is not affected by the adaptive update of the equalization coefficient.

[0141] Figure 6 A schematic diagram of a feasible ADC-TED circuit is given. It should be noted that... Figure 6 This is not intended to limit the specific implementation of ADC-TED, nor to limit the scope of protection of the embodiments of this application. Figure 6 As shown, the ADC-TED includes: a first delay unit 601, a second subtractor 602, and a third multiplier 603;

[0142] The first delay unit 601 is used to delay the first digital signal to obtain the third digital signal; if the sampling frequency is twice the symbol rate, then there are two third digital signals; it should be noted that the function of the delay unit 601 is to align the first digital signal with the output signal of the decision unit.

[0143] The second subtractor 602 is used to subtract the two third digital signals to obtain the fourth digital signal;

[0144] The third multiplier 603 is used to multiply the fourth digital signal and the output signal of the decision unit to obtain timing error information, i.e. Among them, e a(k) s(k) is the timing error information output by the ADC-TED, s(k) is the output signal of the decision circuit, T is the sampling period, and y(kT) and y(kT-T / 2) are the third digital signals.

[0145] Figure 7 A schematic diagram of a feasible Slicer-TED circuit is provided. It should be noted that... Figure 7 This is not intended to limit the specific implementation of Slicer-TED, nor to limit the scope of protection of the embodiments in this application. Figure 7 As shown, Slicer-TED includes: a third subtractor 701, a second delay 702, and a fourth multiplier 703;

[0146] The third subtractor 701 is used to subtract the second digital signal from the output signal of the decision unit to obtain the fifth digital signal.

[0147] The second delay unit 702 is used to delay the output signal of the decision unit to obtain a delayed output signal;

[0148] The fourth multiplier 703 is used to multiply the fifth digital signal and the delayed output signal to obtain the timing error information, i.e., e. s (k) = s(k-1)[x(kT)-s(k)]; where x(kT) is the second digital signal, s(k) is the output signal of the decision unit, and e s(k) This provides timing error information for the Slicer-TED output.

[0149] Figure 8 A schematic diagram of a feasible target measurement circuit is provided. It should be noted that... Figure 8 This is not intended to limit the specific implementation of the target measurement circuit, nor is it intended to limit the protection scope of the embodiments of this application. Figure 8 As shown, the target measurement circuit includes: an accumulator 801 and an amplifier 802;

[0150] The accumulator 801 is used to add the original first signals at different times output by the timing error detector connected to the target measurement circuit to obtain the accumulated first signal.

[0151] Amplifier 802 is used to amplify the accumulated first signal by a factor of 1 / n to obtain the mean of the original first signal, i.e. Where n is the number of the original first signals accumulated.

[0152] Figure 9 A flowchart of a timed recovery method provided in another embodiment of this application.

[0153] Secondly, referring to Figure 9 Another embodiment of this application provides a timed recovery method, including:

[0154] Step 900: Determine N first signals; where the first signal is timing error information, and N is any integer greater than or equal to 2.

[0155] In some exemplary embodiments, before determining the N first signals, the method further includes:

[0156] The received analog input signal is sampled to obtain a first digital signal; the first digital signal is equalized to obtain a second digital signal; and the second digital signal is mapped to the corresponding output signal.

[0157] Accordingly, the N first signals are determined as follows:

[0158] The i-th first signal is determined based on the first digital signal and the output signal; or the i-th first signal is determined based on the second digital signal and the output signal; where i is any integer greater than or equal to 1 and less than or equal to N.

[0159] Of course, other methods can also be used to determine the i-th first signal. The specific determination method is not intended to limit the protection scope of the embodiments of this application. The embodiments of this application emphasize that the advantages of N first signals are fully combined to improve the performance of timing recovery.

[0160] Step 901: Perform a first gain processing on the N first signals to obtain the second signal.

[0161] In some exemplary embodiments, performing a first gain processing on N first signals to obtain a second signal includes:

[0162] Multiply the j-th first signal by the j-th gain parameter to obtain the j-th fourth signal; where j is any integer greater than or equal to 1 and less than or equal to N;

[0163] The second signal is obtained by adding N fourth signals together.

[0164] Step 902: Perform a second gain processing on the N first signals to obtain the third signal.

[0165] In some exemplary embodiments, performing a second gain processing on N second signals to obtain a third signal includes:

[0166] Multiply the j-th first signal by the (j+N)-th gain parameter to obtain the j-th fifth signal; where j is any integer greater than or equal to 1 and less than or equal to N;

[0167] The third signal is obtained by adding N fifth signals together.

[0168] Step 903: Integrate the third signal to obtain the fourth signal, and add the second and fourth signals to obtain the fifth signal. The fifth signal is the filtering timing error information.

[0169] In some exemplary embodiments, sampling the received analog input signal includes: sampling the received analog input signal according to a sampling frequency and a sampling phase;

[0170] Accordingly, the method also includes controlling the sampling phase based on the filtering timing error information.

[0171] The timing recovery method provided in this application combines N timing error information for timing recovery, so that the advantages and disadvantages of the N timing error information complement each other, thereby improving the performance of timing recovery. Furthermore, the loop filter has N input signals, which gives the loop filter 2N independent configurable gain parameters, allowing the advantages of the N timing error information to be fully combined, thereby further improving the performance of timing recovery.

[0172] Figure 10 A flowchart of a timed recovery method provided in another embodiment of this application.

[0173] Fourthly, refer to Figure 10 Another embodiment of this application provides a timing recovery method, applied to any of the above-mentioned timing recovery devices, where N is 2. The timing recovery device includes: a timing error detection module and a loop filter.

[0174] In some exemplary embodiments, the first timing error detector may be a Slicer-TED, and the second timing error detector may be an ADC-TED. Of course, other timing error detectors may also be used, and the specific timing error detector is not intended to limit the scope of protection of the embodiments of this application.

[0175] The method includes:

[0176] Step 1000: Use the second timing error detector to perform the first timing recovery on the received eighth signal, so that the sampling phase of the analog-to-digital converter converges to the first target phase. During the first timing recovery process, train the adaptive equalizer and disconnect the first switch and the second switch.

[0177] In some exemplary embodiments, an execution time can be set for the first timing recovery. The first timing recovery is performed within the set time. When the set time is reached, it is considered that the adaptive equalizer has been trained and the sampling phase of the ADC has converged to the first target phase, which means that the next process, namely the second timing recovery, can be executed.

[0178] In some exemplary embodiments, the eighth signal may be the PAM2 training signal of THP, or the PAM training signal of THP with more levels, or a signal using other precoding techniques, or a signal using other preequalization techniques, or any other signal, as long as the autocorrelation characteristics of the eighth signal are different from those of the ninth signal. The embodiments of this application do not limit the specific form of the eighth signal, nor are they intended to limit the protection scope of the embodiments of this application.

[0179] In some exemplary embodiments, when performing a first timing recovery on the received eighth signal using the second timing error detector, the first gain parameter and the third gain parameter are both set to 0, and the second gain parameter and the fourth gain parameter are both set to be greater than 0. The purpose of setting the first gain parameter and the third gain parameter to 0 is to disable the first timing error detector; for example, by... Figure 5 g in 1s and g 2s Setting the second and fourth gain parameters to 0, and making them both greater than 0, is to enable the second timing error detector. For example, setting... Figure 5 g in 1a and g 2a Set to greater than 0.

[0180] Step 1001: After the adaptive equalizer training is completed, the first timing error detector and the second timing error detector are used together to perform a second timing recovery on the received eighth signal, so that the sampling phase of the analog-to-digital converter converges to the second target phase.

[0181] In some exemplary embodiments, an execution time can be set for the second timing recovery. The second timing recovery is performed within the set time. When the set time is reached, it is considered that the sampling phase of the ADC has converged to the second target phase, which means that the next process, namely the third timing recovery, can be executed.

[0182] In some exemplary embodiments, when using a first timing error detector and a second timing error detector in conjunction for a second timing recovery, the first gain parameter, the second gain parameter, the third gain parameter, and the fourth gain parameter are all set to be greater than 0. The purpose of setting the first gain parameter, the second gain parameter, the third gain parameter, and the fourth gain parameter to be greater than 0 is to ensure that both the first timing error detector and the second timing error detector are effective. For example, [the following is an example of a specific implementation:] Figure 5 g in 1s g 2s g 1a and g 2a Set to greater than 0.

[0183] Step 1002: Use the first timing error detector to perform a third timing recovery on the received ninth signal. During the third timing recovery process, stop updating the equalization coefficient of the adaptive equalizer and close the first switch to measure the mean value of the second original first signal output by the second timing error detector. The autocorrelation characteristics of the ninth signal are different from those of the eighth signal.

[0184] In some exemplary embodiments, an execution time can be set for the third timing recovery. The third timing recovery is performed within the set time. When the set time is reached, it is considered that the average value of the second original first signal output by the second timing error detector has been measured, which means that the next process, namely the fourth timing recovery, can be executed.

[0185] In some exemplary embodiments, the ninth signal may be a THP PAM16 data signal, a THP PAM data signal with more levels, a signal using other precoding techniques, a signal using other preequalization techniques, or any other signal, as long as the autocorrelation characteristics of the eighth signal are different from those of the ninth signal. The embodiments of this application do not limit the specific form of the eighth signal, nor are they intended to limit the protection scope of the embodiments of this application.

[0186] In some exemplary embodiments, when performing a third timing recovery on the received ninth signal using the first timing error detector, the third and fourth gain parameters are both set to 0, and the first and second gain parameters are both set to be greater than 0. The purpose of setting the third and fourth gain parameters to 0 is to disable the second timing error detector; for example, by... Figure 5 g in1a and g 2a Setting both the first and second gain parameters to 0 makes the first timing error detector effective. For example, setting the first gain parameter to 0 and the second gain parameter to 0 makes the first timing error detector effective. Figure 5 g in 1s and g 2s Set to greater than 0.

[0187] In some exemplary embodiments, if the value of the accumulator of the target measurement circuit is not 0 before the first switch is closed, the accumulator of the target measurement circuit needs to be cleared to zero before the first switch is closed.

[0188] In some exemplary embodiments, the reason for using the first timing error detector to perform the third timing recovery on the received ninth signal is that the first timing error detector extracts the first original first signal based on the second digital signal output by the adaptive equalizer. The ISI of the second digital signal tends to 0, so that the stable phase will not change significantly before and after the change in the autocorrelation characteristics of the received signal, that is, it remains stable at the target phase.

[0189] In some exemplary embodiments, the purpose of stopping the updating of the equalization coefficients of the adaptive equalizer during the third timing recovery process is to ensure that the first timing error detector is not affected by the adaptive updating of the equalization coefficients, thereby improving the performance of timing recovery and ensuring that the sampling phase of the ADC is stable at the target phase.

[0190] In some exemplary embodiments, when the autocorrelation characteristics of the received signal change, the mean value of the original first signal output by the second timing error detector is no longer 0. Therefore, it is necessary to subtract the corresponding mean value from the original first signal output by the second timing error detector before outputting it to the loop filter. In other words, it is necessary to measure the mean value of the original first signal output by the second timing error detector to ensure that the sampling phase is stable at the target phase.

[0191] Step 1003: After measuring the mean value of the second original first signal output by the second timing error detector, the first timing error detector and the second timing error detector are used together to perform the fourth timing recovery. During the fourth timing recovery process, the equalization coefficient of the adaptive equalizer is updated, the first switch is turned off, and the second switch is turned on to output the mean value of the second original first signal. The second original first signal is obtained by subtracting the mean value from the second original first signal.

[0192] In some exemplary embodiments, when using the first timing error detector and the second timing error detector in conjunction for the fourth timing recovery, the first gain parameter, the second gain parameter, the third gain parameter, and the fourth gain parameter are all set to be greater than 0. The purpose of setting the first gain parameter, the second gain parameter, the third gain parameter, and the fourth gain parameter to be greater than 0 is to ensure that both the first timing error detector and the second timing error detector are effective. For example, [the following is an example of setting the first gain parameter to be greater than 0]. Figure 5 g in 1s g 2s g 1a and g 2a Set to greater than 0.

[0193] The timing recovery method provided in this application embodiment, after the sampling phase of the analog-to-digital converter stabilizes at the target phase, only uses the first timing error detector to perform the third timing recovery on the received ninth signal. Since the first timing error detector extracts the first original timing error information based on the second digital signal output by the adaptive equalizer, and the ISI of the second digital signal tends to 0, the stable phase before and after the change in the autocorrelation characteristics of the received signal will not change significantly, that is, it remains stable at the target phase. Furthermore, the equalization coefficient of the adaptive equalizer is stopped from being updated during the third timing recovery process, so that the first timing error detector is not affected by the adaptive update of the equalization coefficient of the adaptive equalizer. This also ensures that the sampling phase of the analog-to-digital converter remains stable at the target phase during the third timing recovery process. Therefore, the target measurement can be performed during the third timing recovery process for a relatively long duration and with high accuracy.

[0194] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0195] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this application as set forth by the appended claims.

Claims

1. A timed recovery device, comprising: Timing error detection module and loop filter; The timing error detection module is used to determine N first signals and input the N first signals to the N input terminals of the loop filter; wherein the first signals are timing error information, and N is any integer greater than or equal to 2; The loop filter includes: N input terminals, a source filter, a first gain processing module, and a second gain processing module; the source filter includes: an integration signal terminal and an addition terminal. N input terminals are used to receive N first signals; The first gain processing module is used to perform a first gain processing on N first signals to obtain a second signal, and output the second signal to the adder terminal; The second gain processing module is used to perform second gain processing on N first signals to obtain a third signal, and output the third signal to the integration signal terminal; The source filter is used to integrate the third signal received at the integrator terminal to obtain a fourth signal, and to obtain a fifth signal based on the second signal and the fourth signal received at the adder terminal. The first gain processing module includes: N first multipliers and first adders; The j-th first multiplier is used to multiply the j-th first signal by the j-th gain parameter to obtain the j-th sixth signal; where j is any integer greater than or equal to 1 and less than or equal to N; The first adder is used to add N of the sixth signals to obtain the second signal; The second gain processing module includes: N second multipliers and second adders; The j-th second multiplier is used to multiply the j-th first signal by the (j+N)-th gain parameter to obtain the j-th seventh signal; where j is any integer greater than or equal to 1 and less than or equal to N; The second adder is used to add N of the seventh signals to obtain the third signal; The timing error detection module includes: N timing error detection units; The i-th timing error detection unit includes: an i-th timing error detector, a target measurement circuit, a first switch, a second switch, and a first subtractor; where i is any integer greater than or equal to 1 and less than or equal to N; The i-th timing error detector is used to determine the i-th original first signal; The target measurement circuit is used to measure the mean value of the i-th original first signal; One end of the first switch is connected to the output terminal of the i-th timing error detector, and the other end is connected to the input terminal of the target measurement circuit, for controlling the on / off connection between the output terminal of the i-th timing error detector and the input terminal of the target measurement circuit; One end of the second switch is connected to the output terminal of the target measurement circuit, and the other end is connected to one of the input terminals of the first subtractor, for controlling the on / off connection between the output terminal of the target measurement circuit and one of the input terminals of the first subtractor; The first subtractor is used to subtract the mean from the i-th original first signal to obtain the i-th first signal.

2. The timed recovery device according to claim 1, wherein, The source filter further includes: an integrator and a third adder; The integrator is used to integrate the third signal to obtain the fourth signal; The third adder is used to add the second signal and the fourth signal to obtain the fifth signal.

3. The timed recovery device according to claim 1, wherein, The i-th timing error detection unit is used to determine the i-th first signal.

4. The timed recovery device according to claim 3, wherein, The i-th timing error detection unit includes: an i-th timing error detector, which is used to determine the i-th original first signal and use the i-th original first signal as the i-th first signal.

5. A timed recovery method, applied to the timed recovery device according to any one of claims 1 to 4, comprising: Determine N first signals; wherein the first signals are timing error information, and N is any integer greater than or equal to 2; The first signal is obtained by performing a first gain processing on N of the first signals; A third signal is obtained by performing a second gain processing on N of the first signals; Integrate the third signal to obtain the fourth signal, and obtain the fifth signal based on the second signal and the fourth signal; The step of performing a first gain processing on N first signals to obtain a second signal includes: Multiply the j-th first signal by the j-th gain parameter to obtain the j-th sixth signal; where j is any integer greater than or equal to 1 and less than or equal to N; The second signal is obtained by adding N of the sixth signals; The step of performing a second gain processing on N of the first signals to obtain a third signal includes: Multiply the j-th first signal by the (j+N)-th gain parameter to obtain the j-th seventh signal; where j is any integer greater than or equal to 1 and less than or equal to N; The third signal is obtained by adding N of the seventh signals; The determination of the N first signals includes: Determine the i-th original first signal; where i is any integer greater than or equal to 1 and less than or equal to N; Measure the mean of the i-th original first signal; The first signal is obtained by subtracting the mean from the first original signal i.

6. The timed recovery method according to claim 5, wherein N is 2, and the timed recovery device further comprises: Analog-to-digital converters, adaptive equalizers, and decision units; The method includes: The second timing error detector is used to perform the first timing recovery on the received eighth signal, so that the sampling phase of the analog-to-digital converter converges to the first target phase. During the first timing recovery process, the adaptive equalizer is trained, and the first switch and the second switch are disconnected. After the adaptive equalizer training is completed, the first timing error detector and the second timing error detector are used together to perform a second timing recovery on the received eighth signal, so that the sampling phase of the analog-to-digital converter converges to the second target phase; The first timing error detector is used to perform a third timing recovery on the received ninth signal. During the third timing recovery process, the equalization coefficient of the adaptive equalizer is stopped from being updated, and the first switch is closed to measure the mean value of the second original first signal output by the second timing error detector. The autocorrelation characteristics of the ninth signal are different from those of the eighth signal. After measuring the mean value of the second original first signal output by the second timing error detector, the first timing error detector and the second timing error detector are used together to perform a fourth timing recovery. During the fourth timing recovery process, the equalization coefficient of the adaptive equalizer is updated, the first switch is turned off, and the second switch is turned on to output the mean value of the second original first signal. The second timing error information is obtained by subtracting the mean value from the second original first signal. The analog-to-digital converter is used to sample the received analog input signal to obtain a first digital signal; The adaptive equalizer is used to perform equalization processing on the first digital signal to obtain the second digital signal; The decision unit is used to map the second digital signal into the corresponding output signal; The i-th timing error detector is used to determine the i-th original first signal based on the first digital signal and the output signal; or, based on the second digital signal and the output signal, to determine the i-th original first signal; i is 1 or 2.

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