Method and apparatus for LDPC decoding using index messages

Abstract

The present application discloses a method and apparatus for LDPC decoding using index messages. The present invention discloses a low density parity check (LDPC) decoder, the LDPC decoder comprising a variable node unit (VNU), the VNU comprising a plurality of variable nodes configured to perform a sum. A first message mapper of the LDPC decoder receives a first n1-bit index from a likelihood ratio (LLR) input and maps the first n1-bit index to a first numerical value of the variable nodes input to the VNU. A second message mapper of the LDPC decoder receives a second n2-bit index from a check node unit (CNU) and maps the second n2-bit index to a second numerical value of the variable nodes input to the VNU. The CNU comprises a plurality of check nodes that perform parity check operations. The ranges of the first numerical value and the second numerical value are respectively greater than the ranges represented in n1-bit and n2-bit binary.

Description

SUMMARY OF THE INVENTION

[0001] The present disclosure relates to a method and apparatus for low density parity check decoding using index messages. In one embodiment, a low density parity check (LDPC) decoder includes a variable node unit (VNU) that includes a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives a first n1-bit index from a likelihood ratio (LLR) input and maps the first n1-bit index to a first numerical value of a variable node input to the VNU. A second message mapper of the LDPC decoder receives a second n2-bit index from a check node unit (CNU) and maps the second n2-bit index to a second numerical value of a variable node input to the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The ranges of the first numerical value and the second numerical value are respectively greater than the ranges represented in n1-bit and m2-bit binary.

[0002] These and other features and aspects of the various embodiments will be understood in view of the following detailed discussion and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The following discussion refers to the following drawings, where the same reference numerals may be used to identify similar / same components in multiple drawings.

[0004] Figure 1 is a block diagram of an encoding and decoding system and apparatus according to an exemplary embodiment;

[0005] Figure 2A and Figure 2B is a diagram of a low density parity check decoder node and an H matrix according to an exemplary embodiment;

[0006] Figure 3 and Figure 4 is a diagram of a low density parity check decoder according to an exemplary embodiment;

[0007] Figure 5 and Figure 6 is a table of decoder message mapping according to an exemplary embodiment;

[0008] Figures 7-9 is a graph showing the performance of a decoder according to an exemplary embodiment; and

[0009] Figure 10 is a flowchart of a method according to an exemplary embodiment. DETAILED DESCRIPTION

[0010] The present disclosure as a whole relates to encoding and decoding of data to and from channels. For example, data is stored on persistent data storage devices such as hard disk drives (HDDs) and solid-state drives (SSDs), and storage channels facilitate storing data to and retrieving data from recording media. For HDDs, the recording medium is a magnetic disk; while for SSDs, the recording medium is a solid-state memory unit. Although the composition and operation of these types of media may be substantially different, they share characteristics common to many types of communication channels, such as noise and loss. It should be noted that although the embodiments below are described as data channels in data storage devices, the concept may be applicable to other data channels, such as wired and wireless communications.

[0011] Low-density parity-check (LDPC) codes are commonly used in today's storage and communication systems. The LDPC decoder decodes the received noisy codeword by iteratively passing messages between the columns and rows of the parity-check matrix of the code. The columns represent code bits and are also called variable nodes, while the rows represent parity-check constraints and are also called check nodes. The LDPC decoder can implement a minimum-sum decoding algorithm and includes a plurality of variable node units (VNUs) and check node units (CNUs). The VNU uses received bit information, such as input log-likelihood ratios (LLRs), and soft information generated in the CNU in previous iterations to form a new message to be passed to the CNU. The CNU uses messages from the VNU to form a new message to be passed to the VNU in the next decoding iteration. The message generated in the VNU is also used with the input LLR to form a hard decision. The reduction in the number of bits used to represent the input LLR and the message passed between the CNU and the VNU can reduce the power / energy consumed by the decoder.

[0012] The encoder / decoder system Figure 1 . Typically, processing circuit 100 receives a user data sequence 102, which is received, for example, from a host computer and is to be stored on a recording medium 104 (e.g., a disk, a solid-state memory). The user data sequence may include a sequence of ones and zeros of any size. Modulation encoder 106 converts user data 102 into codewords for writing to a disk. Typically, modulation encoder 106 removes sequences known to cause channel errors from codewords (e.g., n consecutive ones or zeros). Codewords 108 may have a fixed length, where they may be processed by an error detection encoder 110, for example, an LDPC encoder. LDPC-encoded data 112 is input to a signal generator 114, where the data is converted into a signal suitable for medium 104, such as a data storage medium (e.g., a disk, a flash memory). In a communication system, medium 104 may be a transmission medium such as a wire or a radio signal.

[0013] Figure 1Also seen in the figure is a corresponding read path that includes detector 116, which detects the state (e.g., signal value) of medium 104 and converts the state into a signal input to LDPC decoder 118. LDPC encoder 118 uses decoding that is compatible with the LDPC encoding performed by encoder 110 and outputs codeword 119 that is input to modulation decoder 120. Modulation decoder 120 uses a decoding scheme that is compatible with the encoding of modulation encoder 106 and outputs recovered user data 122. The operations of processing circuit 100 can be performed by dedicated or general-purpose logic hardware, represented herein as processor 124 and memory 126.

[0014] In the present disclosure, an implementation of LDPC decoder 118 is described, namely indexing messages passed between the operating components of decoder 118. This allows an n-bit index to be used to represent messages whose values can be in the range, for example, from 0 to 2 m -1 (including the end values), where m > n. It should be noted that not every value between 0 and 2 m -1 can be represented, at most 2 n of them, so there may be gaps in the range of values represented by the messages. When the messages are used within the VNU, these indexes will map to values that would typically require more than n bits in binary representation. Using this method, the performance of a reduced bit-width decoder can be improved. A decoder with indexes and a smaller bit-width can be used to approach the performance of a more complex larger bit-width decoder with less power / energy consumption.

[0015] In Figure 2A figures, aspects of LDPC decoder 118 according to an exemplary embodiment are illustrated. The decoder includes a plurality of variable nodes 200, which are part of the aforementioned VNU. A total of eight variable nodes 200 are shown in Figure 2A figures, labeled v1 - v8. Variable nodes 200 communicate with a series of check nodes 202 that are part of the aforementioned CNU. A total of four check nodes are shown in Figure 2A figures, labeled c1 - c4. Other corresponding quantities and arrangements of the corresponding nodes 200, 202 can be provided as needed. The lines connecting variable nodes 200 to check nodes represent two-way communication paths for transmitting messages therebetween. These messages can go from variable nodes to check nodes, as indicated by v2c direction 204, or from check nodes to variable nodes, as indicated by c2v direction 206. In Figure 2B figures, a parity check matrix H is shown, which represents the interconnection between variable nodes and check nodes in the Figure 2A figures.

[0016] The input code bit reliability is initially loaded into variable node 200, where a single bit LLR is provided in each variable node. The bit LLR values in the variable nodes are selectively combined to form v2c messages that are transmitted to the corresponding check nodes 202. For example, check node c1 receives bits from variable nodes v1, v2, and v1. Once received, the v2c messages are evaluated by check node 202 using certain parity constraints to resolve the codeword. In one example, check node 202 may implement an even parity constraint such that the sum of all bits in a given v2c message should reach a zero (even) value. Other parity constraints may be used.

[0017] Messages with these parity computation results are returned in the form of c2v messages. Typically, each iteration of the LDPC algorithm involves generating a set of v2c messages and transmitting them to the check nodes, followed by returning a set of c2v messages to the variable nodes. If there are no errors, the resulting codeword is resolved and the data is output. If there is at least one error, the values of variable node 200 are updated using the c2v messages and in some cases other information. Subsequent iterations may be applied to attempt to resolve the codeword.

[0018] Figure 2A The calculation of the v2c message from the i-th variable node to the j-th variable check node in can be expressed as in the following equation (1), where LLR i is the channel log-likelihood ratio corresponding to the i-th variable node, and r j→i represents the c2v message from the j-th check node to the i-th variable node.

[0019] q i→j = LLR i + ∑ j′∈N(j)\i r j′→i (1)

[0020] The LLR value is a multi-bit estimate of the probability of a two-state null hypothesis regarding the current state of the associated variable node. The higher the magnitude of the LLR i value, the more likely the current bit state (0 or 1) of the i-th variable node is the correct value. The lower the magnitude of the LLR i value, the more likely the alternate bit value (1 or 0) is the correct state.

[0021] Equation (1) indicates that each v2c message includes the information content of the previous messages, as well as soft information that can provide further clues to assist in decoding the codeword. In some cases, the check node may use the information provided by the overall magnitude of the v2c message to adjust the content in the variable node. The corresponding c2v message from the j-th check node to the i-th variable node can be expressed as in the following equation (2).

[0022] r j→i= Π i′∈N(j)\i sign(q i′→j )·min i′∈N(j)\i |q i′→j | (2)

[0023] The LDPC decoder 118 can implement the min - sum algorithm, which approximately computes the more computationally complex belief propagation algorithm when using simplified hardware / software. One problem with the min - sum algorithm is that the waterfall performance degrades compared to that obtainable using a pure belief propagation method, such that the min - sum algorithm provides a worse codeword failure rate at the same raw bit error rate (RBER).

[0024] Another problem with the min - sum algorithm is the limited precision available in the corresponding v2c and c2v messages. As described above, the practical result of this limited precision is the existence of a maximum magnitude that can be implemented in the size of the v2c message. Whether implemented in software or hardware, there will generally be a total of at most n bits available to describe the corresponding v2c and c2v messages. Values such as n = 4 bits, n = 8 bits, etc. may be more suitable for hardware - based decoder implementations. Higher values such as n = 32, n = 64, etc. may be more suitable for software - based implementations. As will be appreciated, the various embodiments disclosed herein are suitable for both types of implementations.

[0025] q ij values can grow very large, such that the v2c message saturates, which, as described above, is the case where the maximum available value has been reached (e.g., a v2c message of length n bits, where each of the n - bit values is a logical 1). As can be seen from equations (1) and (2), in some cases, saturation can be achieved in just a few iterations of the LDPC decoder.

[0026] Accordingly, the embodiments described below include features that can reduce the size of the data transmitted between variable nodes and check nodes while still allowing reasonable performance of the LDPC decoder. Generally, an indexing scheme is used that allows an n - bit message to include numbers whose maximum value can range from 0 to 2 m-1 -1, where m is greater than n. There is some loss of resolution across the range, e.g., only 2 n distinct values can be represented in the range, such that some values in the range are not representable. This indexing scheme can be used for the feature of reducing the saturation effect in the LDPC decoder.

[0027] In Figure 3In [the figure], the block diagram shows the message transmission paths in an LDPC decoder according to an exemplary embodiment. Path 302 goes from the input LLR 300 to the VNU 304. Generally, the input LLR 300 is data read from a storage or communication channel. In some embodiments, the input LLR 300 may include soft data from a soft-output Viterbi algorithm (SOVA) decoder from a hard disk read channel, estimated soft values from a multi-pass read flash memory controller, a communication medium soft decoder, etc. In some of these embodiments, detection and decoding may be jointly performed, which involves passing the output message from the VNU 304 to the output LLR 301 via message path 303. The VNU 304 passes the v2c message to the CNU 308 via path 306. The CNU passes messages to the memory 314 via path 312, and some or all of these messages are passed to the VNU 304 as c2v messages via path 310. The memory 314 also receives / stores the H matrix information 316, for example, as Figure 2B shown.

[0028] The bit widths of the input LLR 300 and the messages going to and from the VNU 304 and the CNU 308 largely determine the power / energy consumption of the decoder. Increasing the number of bits for the binary representation of these messages not only improves the error rate but also increases the hardware complexity and power / energy consumption. The input LLR 300 can come directly from the channel or be the output of a detector. The LDPC decoder can also generate output soft messages to be iteratively exchanged with the detector. In a conventional decoder, the message paths 302, 306, 310, 312 can use a common representation, for example, an n-bit binary message representing 2 n values, for example, 0 to 2 n -1 if unsigned integers are used, or -2 n-1 to 2 n-1 -1 if two's complement signed integers are used. In the embodiments described herein, the message paths 302, 306, 310, 312 utilize a message mapper that can be used to increase the magnitude of the numbers that can be represented in the decoder without increasing the number of bits. Thus, in the above example of unsigned integers, the range of values of the n-bit message can be from 0 to i max , where i max > 2 n -1.

[0029] In Figure 4 , it shows how in Figure 3Implement a message mapper in the LDPC decoder shown. Add message mappers 400, 401 to each VNU unit input. Message mappers 400, 401 map the binary representation of a message (e.g., message index) to a computed value that would require a larger number of bits for the binary representation in the conventional representation. Since the CNU unit typically determines the first minimum value and the second minimum value for a particular check node, it will retain the same set of message values at its output (path 312) as at its input and does not require a mapper. Message mappers 400, 401 can use different mappings between the message index and the output value to resolve the differences between the messages sent by the input LLR 300 and the CNU 308. It should also be noted that message paths 302, 303, 306, 310, and 312 are all shown using n-bit index messages. However, in some embodiments, some paths may use different bit widths. For example, paths 302, 303 between the input LLR 300 / output LLR 301 may use n1-bit index messages, and paths 306, 310, and 312 between the VNU 304 and the CNU 308 may use n2-bit index messages, where in some embodiments, n1≠n2.

[0030] The VNU unit 304 implementing the min-sum algorithm is performing message addition. Therefore, there may be a larger and different set of values at the VNU output 402 than at the set of values at its input. For this reason, at the VNU output, there is a mapper called the VNU scaling unit 404 that maps all possible VNU output values to a set of allowed message values that can be represented by n-bit numbers. The reason this mapper 404 is called a scaling unit is because this unit 404 performs scaling (and minus saturation) to optimize the error rate, error floor, and average iteration count of the decoder. The allowed message values at the VNU scaling output 405 are mapped back to their indices via the inverse message mapper 405.

[0031] As described above, the input LLR 300 can be provided from a flash memory channel (e.g., in an SSD) or a SOVA detector (e.g., in a hard disk drive). In either case, the channel or detector can work with data in native format (e.g., m-bit binary), which is then converted to an n-bit index. The input LLR 300 can output an LLR index (e.g., in an SSD implementation) or a distorted LLR generated by a SOVA detector (e.g., in a hard disk implementation). In cases where a SOVA detector etc. is used, the detector and the VNU 304 can iteratively exchange data as part of a joint detection and decoding process. In such an implementation, an inverse mapper 406 can be used, which provides a mapping that is the inverse of the mapping of the first mapper 400. This provides the n-bit index sent to the output LLR 301, which can also transform the data from index format to native format. It should be noted that these components 406, 301 may not be used in all implementations, such as SSD drives.

[0032] Several specific examples of VNU scaling and message mapping according to an exemplary embodiment are shown in Figure 5 and Figure 6 in the tables. In these examples for VNU scaling, a symmetric mapping around 0 is assumed. Thus, using column 500 as an example, the mapping extends from the input, from -1 to ≤ -13, where the VNU outputs range from -1 to -8 respectively. Figure 5 Columns 500 and 501 in the table of

[0033] are examples of the corresponding 4-bit values and 3-bit values scaled without an index. It should be noted that scaling tends to weaken the distinction between higher value numbers, especially in column 501 where all input values > 3 are set to 3. Figure 6 Columns 502 and 503 are examples of the corresponding 4-bit values and 2-bit values scaled with an index. In column 502, the maximum value 10 is shown, which would require 5 bits to represent as a signed integer. In column 503, any value of A and B is used as the output. It should be noted that a zero input in column 503 can be +A or –A. The reason for this is shown in Figure 6 where there is no zero in the output of the mapping, thus allowing the representation of a range from –B to +B, rather than –B to A, which would be the result of an unmapped two's complement representation.

[0034] In Figures 7-9 a curve shows the measurement of an LDPC decoder using a mapped message according to an exemplary embodiment. Figure 7The curves in [description] show that a 4-bit decoder can approach the performance of a 5-bit decoder by using the indices in the hard disk drive (HDD) read channel. Notably, this performance improvement is achieved with a minimal increase in hardware complexity and no increase in power / energy compared to a 4-bit non-index decoder. The results were obtained on real data from a hard disk drive. In this case, the decoder obtains soft information from a soft input soft output (SISO) detector. The SISO detector and the decoder iteratively exchange soft information during decoding. Additionally, the message indices proposed in an iterative system including the detector and the decoder can extend beyond the decoder. For example, message mapping can be used at the detector input and output or in some other block of the iterative loop.

[0035] Figure 8 The curves in [description] show the performance improvement in the codeword failure rate (CFR) of 2-bit and 3-bit decoders using message indices. In this example, the lower complexity decoders show improved error rates, bringing them closer to the 4-bit decoder performance. In addition to using message indices, in order to achieve the improvement in this example, an iterative correlation index of the input LLR is also used, starting from the large input LLR and decreasing its magnitude as decoding progresses.

[0036] In some embodiments, the same hardware implementation can support both low and high bit widths of decoder messages. This decoder implementation will be able to operate in multiple modes, and in each mode, a different number of bits in the binary representation will be active and different message mappings can be used. This may be useful in, for example, SSDs.

[0037] The power / energy savings of 2-bit and 3-bit decoders compared to a 4-bit decoder are shown in the Figure 9 graph, and can be significant (up to 25% or 35%) especially in the region of low raw bit error rate (RBER). This is useful in SSD applications where decoding can start with a low-energy decoder in, for example, 2-bit mode, and this is sufficient for most codewords at the start or in the middle of the life of the flash memory. Only pages with more (e.g., irrecoverable) errors will need to be decoded with a slightly higher energy 3-bit or even 4-bit decoder mode, but most pages will be successfully decoded with the low-energy 2-bit or 3-bit decoder most of the time. The consecutive decoding attempts are done with the same hardware and there are no additional reads, so no significant hardware changes or significant additional decoding delays are required to achieve this energy / power savings.

[0038] It should be noted that in the case of using different bit-width index messages (e.g., n1 bits and n2 bits) in different paths, the change in the bit-width pattern can affect both paths. For example, one mode can use an n1-bit index message between the VNU and the input / output LLR and an n2-bit index message between the VNU and the CNU. In a different mode, an m1-bit index message is used between the VNU and the input / output LLR, and an m2-bit index message is used between the VNU and the CNU, where m1 > n1 and m2 > n2.

[0039] In Figure 10 it, the flowchart illustrates a method according to an exemplary embodiment. The method involves receiving 1000 a first n-bit index at the LDPC decoder from an LLR input. Mapping 1001 the first n-bit index to a first numerical value having a first range that is greater than the range that can be represented in n-bit binary. Inputting 1002 the first numerical value to a variable node of the VNU of the LDPC decoder, and the VNU determines a sum at the variable node. Converting 1003 the sum to a second n-bit index for a check node unit (CNU) having a plurality of check nodes. Mapping 1004 the second n-bit index to a second numerical value having a second range that is greater than the range that can be represented in n-bit binary. Inputting 1005 the second numerical value to a check node of the CNU, and performing 1006 a parity check at the check node of the CNU. Iteratively performing 1006 the parity check at the CNU and the determination 1002 of the sum at the VNU until the decoder converges to a solution (or fails to converge) and an output value is determined.

[0040] In summary, an LDPC decoder is described that includes a VNU scaling unit, a message index for messages from the CNU to the VNU, and a message index for the input LLR. The LDPC decoder can use a different message index for messages from the CNU to the VNU than for the input LLR to the VNU. In some embodiments, the message indices (for the CNU-to-VNU message and the input LLR) can be iteratively related. The LDPC decoder can be configured to support multiple bit-widths of messages with the same hardware. An iterative decoding system can include a soft input soft output (SISO) detector and a decoder that iteratively exchange soft messages, where message indices are used at the decoder and / or the detector. All of the above embodiments can be used in HDD, SSD, and / or communication systems. In an SSD system, the LDPC decoder can be used multiple times with different message binary representations and different message indices, but without additional reads.

[0041] The various embodiments described above can be implemented using circuits, firmware, and / or software modules that interact to provide a specific result. Those skilled in the art can readily implement such described functions at a modular level or as a whole using knowledge commonly known in the art. For example, the flowcharts and control diagrams shown herein can be used to create computer-readable instructions / code for execution by a processor. Such instructions can be stored on a non-transitory computer-readable medium and transmitted to the processor for execution, as is known in the art. The structures and programs shown above are merely representative examples of embodiments that can be used to provide the functions described above.

[0042] For purposes of illustration and description, the foregoing description of the exemplary embodiments has been presented. It is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Given the above teachings, many modifications and variations are possible. Any or all of the features of the disclosed embodiments can be applied singly or in any combination, not meant to be restrictive but merely illustrative. It is intended that the scope of the invention not be limited by this detailed description, but rather be determined by the claims appended hereto.

[0043] Further examples:

[0044] Example 1. A low-density parity-check (LDPC) decoder, the LDPC decoder comprising:

[0045] A variable node unit (VNU), the VNU including a plurality of variable nodes configured to perform a sum;

[0046] A first message mapper that receives a first n1-bit index from a likelihood ratio (LLR) input and maps the first n1-bit index to a first numerical value input to the variable nodes of the VNU, the first numerical value having a first range that is greater than a range that can be represented in n1-bit binary; and

[0047] A second message mapper that receives a second n2-bit index from a check node unit (CNU) and maps the second n2-bit index to a second numerical value input to the variable nodes of the VNU, the CNU including a plurality of check nodes that perform a parity check operation, the second numerical value having a second range that is greater than a range that can be represented in n2-bit binary.

[0048] Example 2. The LDPC decoder according to Example 1, further comprising:

[0049] A scaling unit that scales the sum output from the VNU to a set of allowed message values of the CNU; and

[0050] A reverse mapper that maps the allowed message values to an n-bit index, and the n-bit index is sent to the CNU to perform the parity check operation.

[0051] Example 3. The LDPC decoder as described in Example 2, wherein the scaling unit performs de-saturation of the sum.

[0052] Example 4. The LDPC decoder as described in Example 1, wherein n1 is equal to n2, and the first mapping between the first n1-bit index and the first numerical value is different from the second mapping between the second n2-bit index and the second numerical value.

[0053] Example 5. The LDPC decoder as described in Example 1, wherein the mapping between the first n1-bit index and the first numerical value changes for different iterations of the LDPC decoder.

[0054] Example 6. The LDPC decoder as described in Example 1, wherein the LLR input is received from a soft output detector, and the first message mapper and the inverse mapper of the first message mapper are used to iteratively exchange message indices between the soft output detector and the VNU.

[0055] Example 7. The LDPC decoder as described in Example 1, wherein the LDPC decoder is configured to operate in a first mode using the n1-bit index and the n2-bit index and in a second mode using corresponding m1-bit index and m2-bit index, where m1 > n1 and m2 > n2, and the first mapper and the second mapper use different mappings in the first mode and the second mode.

[0056] Example 8. The LDPC decoder as described in Example 7, wherein the LLR input is from a flash memory, and the decoding initially starts in the first mode and switches to the second mode in response to an irrecoverable error.

[0057] Example 9. The LDPC decoder as described in Example 8, wherein the switch from the first mode to the second mode does not involve additional reads of the flash memory.

[0058] Example 10. A method, the method comprising:

[0059] Receiving a first n1-bit index from a log-likelihood ratio (LLR) input at a low-density parity-check (LDPC) decoder;

[0060] Mapping the first n-bit index to a first numerical value having a first range that is greater than the range that can be represented in n1-bit binary;

[0061] Input the first numerical value into a variable node of a variable node unit (VNU) of the LDPC decoder, and the VNU determines a sum at the variable node;

[0062] Convert the sum into a second n2-bit index for a check node unit (CNU) including a plurality of check nodes;

[0063] Map the second n2-bit index to a second numerical value having a second range that is larger than a range that can be represented in n2-bit binary;

[0064] Input the second numerical value into the check nodes of the CNU; and

[0065] Perform a parity check at the check nodes of the CNU, wherein the parity check at the CNU and the determination of the sum at the VNU are iteratively performed until an output value is determined.

[0066] Example 11. The method according to Example 10, further comprising:

[0067] Scale the sum output from the VNU to a set of allowed message values of the CNU; and

[0068] Inverse map the allowed message values to an n-bit index, and the n-bit index is sent to the CNU to perform the parity check operation.

[0069] Example 12. The method according to Example 11, wherein scaling the sum includes desaturating the sum.

[0070] Example 13. The method according to Example 10, wherein n1 is equal to n2, and wherein a first mapping between the first n1-bit index and the first numerical value is different from a second mapping between the second n2-bit index and the second numerical value.

[0071] Example 14. The method according to Example 10, wherein the mapping between the first n1-bit index and the first numerical value changes for different iterations of the LDPC decoder.

[0072] Example 15. The method according to Example 10, wherein the LLR input is received from a soft output detector, and the method further comprises iteratively exchanging message indices between the soft output detector and the VNU.

[0073] Example 16. A system, the system comprising:

[0074] A data interface configured to receive data from a storage medium; and

[0075] An LDPC decoder, the LDPC decoder being coupled to the data interface and comprising:

[0076] A first message mapper that receives a first n1-bit index from the data interface and maps the first n1-bit index to a first value;

[0077] A variable node unit (VNU) comprising a plurality of variable nodes configured to receive the first value and perform a sum on the first value; and

[0078] A second message mapper that receives a second n2-bit index from a check node unit (CNU) and maps the second n2-bit index to a second value input to the variable nodes of the VNU, the CNU comprising a plurality of check nodes that perform a parity check operation, the first value and the second value having respective first and second ranges that are greater than the ranges that can be represented in binary by the respective n1 bits and n2 bits.

[0079] Example 17. The system according to Example 16, wherein the data interface includes a soft output detector, and wherein the first message mapper and the inverse mapper of the first message mapper are used to iteratively exchange message indices between the soft output detector and the VNU.

[0080] Example 18. The system according to Example 16, wherein the LDPC decoder is configured to operate in a first mode using the n1-bit index and the n2-bit index and in a second mode using respective m1-bit and m2-bit indices, where m1 > n1 and m2 > n2, and wherein the first mapper and the second mapper use different mappings in the first mode and the second mode.

[0081] Example 19. The system according to Example 18, wherein the storage medium includes a flash memory, and wherein the decoding initially starts in the first mode and switches to the second mode in response to an irrecoverable error.

[0082] Example 20. The system according to Example 19, wherein the switch from the first mode to the second mode does not involve an additional read of the flash memory.

Claims

1. An LDPC (Low Density Parity Check) decoder, the LDPC decoder comprising: A VNU (Variable Node Unit), the VNU including a plurality of variable nodes configured to perform a sum; A first message mapper, the first message mapper receiving a first n1-bit index from an LLR (Log Likelihood Ratio) input and mapping the first n1-bit index to a first numerical value input to the variable nodes of the VNU, the first numerical value having a first range that is greater than a range that can be represented in n1-bit binary; And A second message mapper, the second message mapper receiving a second n2-bit index from a CNU (Check Node Unit) and mapping the second n2-bit index to a second numerical value input to the variable nodes of the VNU, the CNU including a plurality of check nodes that perform a parity check operation, the second numerical value having a second range that is greater than a range that can be represented in n2-bit binary.

2. The LDPC decoder according to claim 1, further comprising: A scaling unit, the scaling unit scaling the sum output from the VNU to a set of allowed message values of the CNU; And An inverse mapper, the inverse mapper mapping the allowed message values to an n-bit index, the n-bit index being sent to the CNU to perform the parity check operation.

3. The LDPC decoder according to claim 2, wherein the scaling unit performs desaturation of the sum.

4. The LDPC decoder according to claim 1, wherein n1 is equal to n2, and wherein a first mapping between the first n1-bit index and the first numerical value is different from a second mapping between the second n2-bit index and the second numerical value.

5. The LDPC decoder according to claim 1, wherein the mapping between the first n1-bit index and the first numerical value changes for different iterations of the LDPC decoder.

6. The LDPC decoder according to claim 1, wherein the LLR input is received from a soft output detector, and wherein the first message mapper and an inverse mapper of the first message mapper are used to iteratively exchange message indices between the soft output detector and the VNU.

7. The LDPC decoder according to claim 1, wherein the LDPC decoder is configured to operate in a first mode using the n1-bit index and the n2-bit index and in a second mode using corresponding m1-bit index and m2-bit index, where m1 > n1 and m2 > n2, and the first message mapper and the second message mapper use different mappings in the first mode and the second mode.

8. The LDPC decoder according to claim 7, wherein the LLR input is from a flash memory, and wherein decoding initially starts in the first mode and switches to the second mode in response to an irrecoverable error.

9. The LDPC decoder according to claim 8, wherein switching from the first mode to the second mode does not involve an additional read of the flash memory.

10. A method, the method comprising: Receiving a first n1-bit index at an LDPC (Low-Density Parity-Check) decoder from a logarithmic LLR (Log-Likelihood Ratio) input; Mapping the first n1-bit index to a first numerical value having a first range that is greater than a range that can be represented in n1-bit binary; Inputting the first numerical value to a variable node of a VNU (Variable Node Unit) of the LDPC decoder, the VNU determining a sum at the variable node; Converting the sum to a second n2-bit index for a CNU (Check Node Unit) including a plurality of check nodes; Mapping the second n2-bit index to a second numerical value having a second range that is greater than a range that can be represented in n2-bit binary; Inputting the second numerical value to the check nodes of the CNU; And Performing a parity check at the check nodes of the CNU, wherein the parity check at the CNU and the determination of the sum at the VNU are iteratively performed until an output value is determined.

11. The method of claim 10, further comprising: Scaling a sum output from the VNU to a set of allowed message values of the CNU; And Inverse mapping the allowed message values to an n-bit index, the n-bit index being sent to the CNU to perform the parity check operation.

12. The method of claim 11, wherein scaling the sum includes desaturating the sum.

13. The method of claim 10, wherein n1 is equal to n2, and wherein a first mapping between the first n1-bit index and the first numerical value is different from a second mapping between the second n2-bit index and the second numerical value.

14. The method of claim 10, wherein the mapping between the first n1-bit index and the first numerical value changes for different iterations of the LDPC decoder.

15. The method of claim 10, wherein the LLR input is received from a soft output detector, the method further comprising iteratively exchanging message indices between the soft output detector and the VNU.

16. A system, the system comprising: A data interface configured to receive data from a storage medium; And An LDPC (Low-Density Parity-Check) decoder coupled to the data interface and including: A first message mapper that receives a first n1-bit index from the data interface and maps the first n1-bit index to a first numerical value; A VNU (Variable Node Unit) including a plurality of variable nodes configured to receive the first numerical value and perform a sum on the first numerical value; and A second message mapper that receives a second n2-bit index from a CNU (check node unit) and maps the second n2-bit index to a second numerical value of the variable nodes input to the VNU, the CNU including a plurality of check nodes that perform parity check operations, the first numerical value and the second numerical value having respective first and second ranges that are greater than the ranges that can be represented in respective n1-bit and n2-bit binary.

17. The system of claim 16, wherein the data interface includes a soft output detector, and wherein the first message mapper and the inverse mapper of the first message mapper are used to iteratively exchange message indices between the soft output detector and the VNU.

18. The system of claim 16, wherein the LDPC decoder is configured to operate in a first mode using the n1-bit index and the n2-bit index and in a second mode using respective m1-bit and m2-bit indices, where m1 > n1 and m2 > n2, and wherein the first message mapper and the second message mapper use different mappings in the first mode and the second mode.

19. The system of claim 18, wherein the storage medium includes a flash memory, and wherein the decoding initially starts in the first mode and switches to the second mode in response to an irrecoverable error.

20. The system of claim 19, wherein the switch from the first mode to the second mode does not involve an additional read of the flash memory.

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