Imaging device, electronic device, and manufacturing method

Abstract

The present disclosure relates to an imaging device, electronic device, and manufacturing method capable of reducing manufacturing costs. The imaging device includes: a first semiconductor element, which includes an imaging element configured to generate pixel signals; and a second semiconductor element, in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signals are embedded via an embedding member, wherein the first signal processing circuit has a structure having at least one more layer than the second signal processing circuit. The imaging device also includes: a first wiring connecting the first semiconductor element and the first signal processing circuit; and a second wiring connecting the first signal processing circuit and the second signal processing circuit. The present disclosure can be applied to imaging devices.

Description

Technical Field

[0001] The present disclosure relates to an imaging device, an electronic device, and a manufacturing method, and relates to an imaging device, an electronic device, and a manufacturing method that are suitable for application to an imaging device including a plurality of chips, for example. Background Art

[0002] The imaging device has high image quality in the form of HD, 4k×2k UHD and further super slow motion function, resulting in an increase in the number of pixels, a high frame rate and a high grayscale.

[0003] The transmission rate is calculated as the number of pixels × frame rate × grayscale. For example, with 4k × 2k = 8M pixels, a frame rate of 240f / s, and a 14-bit grayscale, the result is 8M × 240f / s × 14 bits = 26Gbps. After the imaging element performs signal processing, the RGB output in the color coordinates requires even higher transmission speeds of 26G × 3 = 78Gbps.

[0004] When high-speed transmission is performed using a small number of connection terminals, the signal rate per connection terminal increases, the difficulty of achieving impedance matching in the high-speed transmission path increases, the clock frequency increases, and the loss also increases, resulting in increased power consumption.

[0005] To avoid this, it is preferable to increase the number of connection terminals and split the transmission to reduce the signal rate. However, when the number of connection terminals increases, the packaging of each circuit becomes larger due to the configuration of the terminals required to connect the imaging element to the subsequent signal processing circuit, storage circuit, etc.

[0006] Furthermore, the substrate for electrical wiring required for the subsequent signal processing circuit and memory circuit also requires a finer wiring density in the stacked wiring, which increases the wiring path length and thus increases power consumption.

[0007] When the package of each circuit becomes larger, the substrate itself to be mounted also becomes larger, and ultimately the configuration itself of the imaging device on which the imaging element is mounted becomes larger.

[0008] Therefore, as a technology for reducing the size of the structure of the imaging device, a technology has been proposed in which an imaging element is stacked with circuits such as a signal processing circuit and a storage circuit by performing circuit bonding on a wafer (WoW) in a wafer state (see Patent Document 1).

[0009] By using WoW stacking technology, semiconductors can be connected through many fine wirings, which reduces the transmission speed of each semiconductor and suppresses power consumption.

[0010] List of citations

[0011] Patent Literature

[0012] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-099582 Summary of the Invention

[0013] Problems to be solved by the invention

[0014] However, in the case of WoW, there is no problem as long as the chips of the wafers to be stacked have the same size, but when the sizes of the individual chips making up the wafer are different, the size must be adjusted to the largest chip size, and there is a possibility of deterioration in the manufacturing efficiency of each circuit and increased costs.

[0015] Furthermore, regarding the yield of each wafer, a defective chip on each wafer to be stacked will also cause the chips on other stacked wafers to be considered defective. Since the yield of the entire stacked wafer is the product (multiplication) of the yields of each wafer, there is a possibility of yield degradation and cost increase.

[0016] Another technology has been proposed for connecting chips of different sizes by forming small bumps. In this case, since the chips of different sizes selected as good products are connected via bumps, the impact on the manufacturing efficiency of each wafer and the yield of each chip is minimal.

[0017] However, due to the difficulty in forming small bumps and the limited connection pitch, the number of connection terminals may not be larger than that of the WoW. Furthermore, since connections are made during the assembly process, increasing the number of connection terminals may lead to a decrease in connection yield and increased costs. Furthermore, since connections during the assembly process are also made individually, the time required for connection increases, potentially increasing process costs.

[0018] The present disclosure has been made in view of such circumstances, and an object thereof is to reduce the manufacturing cost of an imaging device.

[0019] Solution to the problem

[0020] According to one aspect of the present technology, a first imaging device includes: a first semiconductor element, which includes an imaging element configured to generate a pixel signal; and a second semiconductor element, in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded by an embedded component, wherein the first signal processing circuit has a structure with at least one more layer than the second signal processing circuit.

[0021] A first electronic device according to one aspect of the present technology includes a first imaging device.

[0022] According to one aspect of the present technology, a second imaging device includes: a first semiconductor element, which includes an imaging element configured to generate a pixel signal; a second semiconductor element, in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded by an embedded component; and wiring connecting the first signal processing circuit and the second signal processing circuit, wherein the wiring connects a terminal set in a wiring layer of the lowest layer of the first signal processing circuit and a terminal set in a wiring layer of the lowest layer of the second signal processing circuit.

[0023] A second electronic device according to an aspect of the present technology includes a second imaging device.

[0024] A manufacturing method according to one aspect of the present technology is a manufacturing method for manufacturing an imaging device, wherein the imaging device includes: a first semiconductor element, which includes an imaging element configured to generate pixel signals in units of pixels; a second semiconductor element, in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signals are embedded by an embedding component; and wiring connecting the first signal processing circuit and the second signal processing circuit, the manufacturing method including: a step of transferring the first signal processing circuit and the second signal processing circuit onto the first semiconductor element; a step of forming a first film on the first signal processing circuit and the second signal processing circuit; a step of exposing a portion of a first terminal in a wiring layer of the lowest layer of the first signal processing circuit and a portion of a second terminal in a wiring layer of the lowest layer of the second signal processing circuit; and a step of forming wiring connecting the first terminal and the second terminal.

[0025] In a first imaging device and a first electronic device according to one aspect of the present technology, there are provided: a first semiconductor element including an imaging element configured to generate a pixel signal; and a second semiconductor element in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded by an embedded component, wherein the first signal processing circuit has a structure having at least one more layer than the second signal processing circuit.

[0026] In a second imaging device and a second electronic device according to one aspect of the present technology, there are provided: a first semiconductor element including an imaging element configured to generate a pixel signal; a second semiconductor element in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded by an embedded component; and wiring connecting the first signal processing circuit and the second signal processing circuit, wherein the wiring connects a terminal set in a wiring layer of the lowest layer of the first signal processing circuit and a terminal set in a wiring layer of the lowest layer of the second signal processing circuit.

[0027] In a manufacturing method according to one aspect of the present technology, the manufactured imaging device includes: a first semiconductor element, which includes an imaging element configured to generate pixel signals in units of pixels; a second semiconductor element, in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signals are embedded by an embedding component; and wiring connecting the first signal processing circuit and the second signal processing circuit, the manufacturing method includes: a step of transferring the first signal processing circuit and the second signal processing circuit onto the first semiconductor element; a step of forming a first film on the first signal processing circuit and the second signal processing circuit; a step of exposing a portion of a first terminal set in a wiring layer of the lowest layer of the first signal processing circuit and a portion of a second terminal set in a wiring layer of the lowest layer of the second signal processing circuit; and a step of forming wiring connecting the first terminal and the second terminal.

[0028] Note that the imaging device and the electronic device may be independent devices, or may be internal blocks forming one device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a graph used to illustrate yield.

[0030] Figure 2 It is a diagram for explaining the reduction in manufacturing efficiency.

[0031] Figure 3 This is a diagram for explaining connection using bumps.

[0032] Figure 4 A diagram for explaining an outline of a method for manufacturing an imaging device.

[0033] Figure 5 A diagram for explaining a configuration example of an imaging device.

[0034] Figure 6 It is a diagram for explaining a method of manufacturing an imaging device.

[0035] Figure 7 It is a diagram for explaining a method of manufacturing an imaging device.

[0036] Figure 8 It is a diagram for explaining a method of manufacturing an imaging device.

[0037] Figure 9 It is a diagram for explaining a method of manufacturing an imaging device.

[0038] Figure 10 It is a diagram for explaining a method of manufacturing an imaging device.

[0039] Figure 11 It is a diagram for explaining a method of manufacturing an imaging device.

[0040] Figure 12 This is a diagram for explaining the ease of rewiring.

[0041] Figure 13 This is a diagram for explaining another configuration example of the imaging device.

[0042] Figure 14 This is a diagram for explaining another configuration example of the imaging device.

[0043] Figure 15 A diagram for explaining an outline of a method for manufacturing an imaging device.

[0044] Figure 16 It is a diagram for explaining a method of manufacturing an imaging device.

[0045] Figure 17 It is a diagram for explaining a method of manufacturing an imaging device.

[0046] Figure 18 It is a diagram for explaining a method of manufacturing an imaging device.

[0047] Figure 19 This is a diagram for explaining the production of wiring.

[0048] Figure 20 is a diagram illustrating an example of an electronic device.

[0049] Figure 21 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0050] Figure 22 : is a block diagram showing an example of the functional configuration of a camera and a CCU.

[0051] Figure 23 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0052] Figure 24 2 is an explanatory diagram showing an example of installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0053] Hereinafter, forms for implementing the present technology (hereinafter, referred to as embodiments) will be described.

[0054] Here, in explaining the present disclosure, the wafer-on-wafer (WoW) disclosed in Patent Document 1 will be explained.

[0055] For example, Figure 1 As shown, WoW is a technology for bonding and stacking an imaging device and circuits including an IC (such as a signal processing circuit and a memory circuit) in a wafer state.

[0056] Figure 1WoW is schematically shown, in which a wafer W1 on which a plurality of imaging elements 11 are formed, a wafer W2 on which a plurality of memory circuits 12 are formed, and a wafer W3 on which a plurality of logic circuits 13 are formed are bonded and stacked in a finely aligned state.

[0057] By cutting the structure stacked in this manner into individual pieces, for example, Figure 2 The imaging device shown.

[0058] Figure 2 The imaging device 1 is constructed by stacking an on-chip lens, an on-chip color filter 10, an imaging element 11, a memory circuit 12, a logic circuit 13, and a supporting substrate 14 in this order from the top.

[0059] Here, by applying the WoW technology, the wiring 21 - 1 electrically connecting the imaging element 11 and the memory circuit 12 and the wiring 21 - 2 electrically connecting the memory circuit 12 and the logic circuit 13 can be connected at a fine pitch.

[0060] As a result, since the number of wirings can be increased, the transmission speed in each signal line can be lowered, and power saving can be achieved.

[0061] However, because the imaging element 11, memory circuit 12, and logic circuit 13 to be stacked each require different areas, spaces Z1 where neither circuits nor wiring are formed are created on the left and right sides of the diagram for the memory circuit 12, which has a smaller area than the largest imaging element 11. Furthermore, spaces Z2 where neither circuits nor wiring are formed are created on the left and right sides of the diagram for the logic circuit, which has a smaller area than the memory circuit 12.

[0062] That is, the spaces Z1 and Z2 are generated because the areas required by the imaging element 11, the storage circuit 12, and the logic circuit 13 are different from each other, and Figure 2 This is caused by lamination with the imaging element 11 which is the reference and requires the largest area.

[0063] This configuration reduces the manufacturing efficiency of the imaging device 1 , and as a result, the manufacturing cost increases.

[0064] In addition, Figure 1 In FIG, among the imaging elements 11, storage circuits 12, and logic circuits 13 formed in the respective wafers W1 to W3, defective structures are represented by filled squares. Figure 1 It is shown that two defects occur in each of the wafers W1 to W3.

[0065] like Figure 1 As shown in FIG. 1 , defects in the imaging element 11, the storage circuit 12, and the logic circuit 13 formed in each wafer W1 to W3 do not necessarily occur at the same location. Figure 1As shown, in the imaging device 1 formed by lamination, six defects marked with crosses occur on the wafer W1 of the imaging element 11 .

[0066] As a result, in an imaging device 1 with six defects, the imaging element 11, the memory circuit 12, and the logic circuit 13 are each considered to have six defects, even though at least two of the three components, namely, the imaging element 11, the memory circuit 12, and the logic circuit 13, are not defective. Therefore, the number of defects obtained by integrating the number of wafers is six, while the original number of defects for each component may be two.

[0067] As a result, the yield of the imaging device 1 decreases, and the manufacturing cost increases.

[0068] In addition, if Figure 3 As shown, it is conceivable to cut the imaging element 11, the memory circuit 12, and the logic circuit 13 having different chip sizes into individual pieces, selectively arrange only good products, and connect them by forming small bumps.

[0069] exist Figure 3 In the imaging device 1, an on-chip lens, an on-chip color filter 10, and an imaging element 11 are stacked from the top. A memory circuit 12 and a logic circuit 13 are stacked in the same layer below them. A support substrate 14 is also provided below them and stacked. Furthermore, the imaging element 11 is electrically connected to the memory circuit 12 and logic circuit 13, which are arranged in the same layer, via small bumps 31.

[0070] exist Figure 3 In the imaging device 1 , chips of different sizes selected as good products are connected via the bumps 31 , and the influence of the difference in manufacturing efficiency of each wafer and the yield of each chip is reduced.

[0071] However, it is difficult to form the small bump 31, and to reduce the Figure 3 The connection distance d2 shown is limited so that the connection distance d2 cannot be less than that in the case of using WoW. Figure 2 The connection distance d1.

[0072] To this end, a bump stack is used Figure 3 The imaging device 1 cannot have more than 100 Figure 2 The imaging device 1 has a larger number of connection terminals. Figure 3 When bumps are used for connection, as in the imaging device 1, increasing the number of connection terminals leads to a decrease in yield associated with bonding, and an increase in cost, due to the bonding being performed during the mounting process. Furthermore, since bump connection is also a separate operation during the mounting process, each process takes a long time, and the process cost also increases.

[0073] As described above, the imaging element of the present disclosure reduces costs associated with manufacturing from the viewpoints of manufacturing efficiency, installation cost, and process cost.

[0074] <About Wafer Stacking>

[0075] Figure 4 WO2011 / 050740 is a diagram for explaining a structure in which a plurality of wafers are stacked by the WoW technology applied when manufacturing the imaging device of the present disclosure.

[0076] When manufacturing the imaging device of the present disclosure, two wafers are stacked with wiring precisely aligned, and the two wafers include: a wafer 101 on which a plurality of imaging elements (complementary metal oxide semiconductor (CMOS) image sensors) or charge coupled devices (CCDs)) 120 are formed; and a supporting substrate 102 on which a storage circuit 122 and a logic circuit 121 are further configured.

[0077] On the wafer 101 , a plurality of imaging elements 120 are formed by a semiconductor process.

[0078] A plurality of memory circuits 122 are arranged on the support substrate 102 . The memory circuits 122 are formed on the wafer 104 through a semiconductor process, cut into individual chips, and then individually electrically inspected to confirm that they are good chips.

[0079] On the support substrate 102 , a plurality of logic circuits 121 are arranged. These logic circuits 121 are formed on the wafer 103 through a semiconductor process, cut into individual chips, and then individually electrically inspected to confirm that they are good chips.

[0080] <Configuration Example of Imaging Device>

[0081] Figure 4 1 is a diagram for explaining a structure in which a plurality of wafers are stacked by combining a chip on wafer (CoW) technology and a WoW technology applied when manufacturing the imaging device of the present disclosure. Figure 4 The CoW technology and WoW technology shown are used to stack multiple wafers and then cut into single pieces to form the imaging device 111 ( Figure 5 ).

[0082] The imaging device of the present disclosure has, for example, Figure 5 Note that Figure 5 In FIG. 1 , the upper portion is a side sectional view, and the lower portion is a diagram showing the horizontal arrangement relationship among the imaging element 120 , the logic circuit 121 , and the memory circuit 122 when viewed from the upper surface.

[0083] exist Figure 5In the imaging device 111 at the top, starting from the top in the figure, the on-chip lens, on-chip color filter 131 and imaging element 120 are stacked, and the logic circuit 121 and storage circuit 122 are arranged and stacked on the left and right sides of the same layer below, and the support substrate 132 is formed below. Figure 5 As shown in the upper part, Figure 5 The imaging device 111 includes a semiconductor element layer E1 including an imaging element 120 formed from a wafer 101 , and a semiconductor element layer E2 including a logic circuit 121 and a memory circuit 122 formed on a support substrate 132 .

[0084] Among the terminals 120 a of the imaging element 120 , the terminal 120 a on the memory circuit 122 is electrically connected to the terminal 122 a of the memory circuit 122 through a wiring 134 connected by CuCu connection.

[0085] although Figure 5 Although not shown, a configuration may be adopted in which the terminal 120a on the logic circuit 121 among the terminals 120a of the imaging element 120 may be configured to be connected to the terminal 121a of the logic circuit 121 by CuCu connection.

[0086] exist Figure 5 In the example shown in the upper part of , an example is shown in which the imaging element 120 and the logic circuit 121 are not directly connected, but are indirectly connected by being constructed so that the logic circuit 121 and the storage circuit 122 are connected through the wiring 136 and the storage circuit 122 and the imaging element 120 are connected.

[0087] In the semiconductor element layer E2 in which the logic circuit 121 and the memory circuit 122 are formed, the space around the logic circuit 121 and the memory circuit 122 is filled with the oxide film 133. As a result, in the semiconductor element layer E2, the logic circuit 121 and the memory circuit 122 are buried in the oxide film 133.

[0088] Furthermore, an oxide film bonding layer 135 is formed by oxide film bonding at the boundary between the semiconductor element layer E1 on which the imaging element 120 is formed and the semiconductor element layer E2 on which the logic circuit 121 and the memory circuit 122 are formed, and the semiconductor element layer E1 is bonded together. Furthermore, the oxide film bonding layer 135 is formed by oxide film bonding, and the semiconductor element layer E2 of the logic circuit 121 and the memory circuit 122 is bonded to the supporting substrate 132.

[0089] The terminal 121a of the logic circuit 121 is buried in the oxide film 133. The terminal 122a of the memory circuit 122 is buried in a bulking layer 137. Although the bulking layer 137 will be described later, the terminal 122a of the memory circuit 122 is configured to be located close to the terminal 120a of the imaging element 120, which is the connection destination, due to the provision of the bulking layer 137.

[0090] When comparing the logic circuit 121 and the memory circuit 122, the memory circuit 122 has at least one more layer than the logic circuit 121. Here, an example is given in which at least one more layer of the thickening layer 137 is provided. The layer corresponding to the thickening layer 137 may be multiple layers.

[0091] Thickening layer 137 may also be configured as an oxide film. In the case where thickening layer 137 is configured as an oxide film, it may include the same material as oxide film 133 stacked on thickening layer 137. In this case, thickening layer 137 and oxide film 133 may be considered as one layer. In this embodiment, this layer is configured to be thick. "Configured to be thick" means that the thickness is greater than the thickness of oxide film 133 of a circuit (e.g., logic circuit 121) without thickening layer 137.

[0092] In other words, when the predetermined layer A of the logic circuit 121 is compared with the layer B of the memory circuit 122 corresponding to the predetermined layer A of the logic circuit 121, the layer B is configured to be thicker than the layer A. The layer B includes the thickening layer 137, and by including the thickening layer 137, the layer B is configured to be thicker than the layer A.

[0093] In addition, if Figure 5 As shown in the lower portion of FIG, when viewed from the top surface, the logic circuit 121 and the memory circuit 122 are arranged so as to be contained within the range where the imaging element 120 of the uppermost layer exists. This arrangement reduces the amount of free space other than the logic circuit 121 and the memory circuit 122 in the layers of the logic circuit 121 and the memory circuit 122, which improves manufacturing efficiency.

[0094] exist Figure 4 On the supporting substrate 102, when each imaging device 111 is cut into individual pieces, the logic circuit 121 and the storage circuit 122 are precisely adjusted and reconfigured so as to be within the range of the imaging element 120 when viewed from their respective upper surfaces.

[0095] < Figure 5 Method for manufacturing an imaging device in>

[0096] Next, we will refer to Figures 6-11 illustrate Figure 5 A method for manufacturing the imaging device 111.

[0097] exist Figure 6 In steps S11 to S14, logic circuits 121 are manufactured. In step S11, wafer 103 is prepared on which logic circuits 121 are formed. In each logic circuit 121 on wafer 103, terminals 121a are formed on logic circuit 121, oxide film 133 is formed to cover terminals 121a, and oxide film bonding layer 135 is further formed.

[0098] In step S12, the dicing tape 151 is attached to the wafer 103. Furthermore, the wafer 103 to which the dicing tape 151 is attached is fixed to a ring frame 152 (also referred to as a dicing frame or the like).

[0099] In step S13, the wafer 103 is diced to cut out the logic circuits 121. In step S14, gaps are formed between the cut out logic circuits 121 by stretching the wafer 103. From this state, each logic circuit 121 is peeled off from the dicing tape 151 and transferred to the support substrate 102 (step S15).

[0100] Note that Figure 6 As shown, logic circuits 121 having different sizes may be formed on one wafer 103 and cut into individual pieces.

[0101] exist Figure 7 In steps S21 to S24, memory circuits 122 are manufactured. In step S21, wafer 104 is prepared on which memory circuits 122 are formed. In each memory circuit 122 on wafer 104, terminals 122a are formed on memory circuit 122, and thickening layer 137 is formed to cover terminals 122a. Furthermore, oxide film 133 is formed on thickening layer 137, and oxide film bonding layer 135 is further formed.

[0102] Compared to the logic circuit 121, the memory circuit 122 has a structure in which a thickening layer 137 is added. The thickening layer 137 is provided to facilitate redistribution of circuit wiring. The thickening layer 137 may include an oxide film.

[0103] In the Figure 6 The logic circuit 121 (wafer 103) shown in step S11 is connected to Figure 7 When compared with the memory circuit 122 (wafer 104 ) shown in step S21 , the difference is that the memory circuit 122 has the thickening layer 137 formed thereon, while the logic circuit 121 does not have the thickening layer 137 formed thereon.

[0104] exist Figure 7 In step S22 , the dicing tape 153 is attached to the wafer 104 . Furthermore, the wafer 104 to which the dicing tape 153 is attached is fixed to the ring frame 154 .

[0105] In step S23, the wafer 104 is diced to cut out the memory circuits 122. In step S24, gaps are formed between the cut memory circuits 122 by stretching the wafer 104. From this state, the individual memory circuits 122 are peeled from the dicing tape 153 and transferred to the support substrate 102 (step S15).

[0106] As described above, in step S15 , the separately manufactured logic circuit 121 and memory circuit 122 are transferred onto the supporting substrate 102 .

[0107] Note that Figure 7 As shown, memory circuits 122 having different sizes may be formed on one wafer 104 and diced into individual pieces.

[0108] When the manufacturing process reaches step S15 ( Figure 6 or Figure 7 ) in a state where the logic circuit 121 and the memory circuit 122 are placed on the support substrate 102, in step S31 ( Figure 8 ) is thinned.

[0109] The logic circuit 121 and the memory circuit 122 before thinning have different heights as shown in step S15. In other words, the memory circuit 122 is formed higher than the logic circuit 121 by an amount corresponding to the formation of the thickened layer 137.

[0110] In step S31 , the silicon layers (wafers 103 and 104 , hereinafter appropriately referred to as silicon layers 103 and 104 ) of the upper portions of the logic circuit 121 and the memory circuit 122 in the figure are thinned to a height that does not affect device characteristics.

[0111] In step S32, rear-side rewiring is performed. This description takes as an example the case where rewiring is performed on the memory circuit 122 but not on the logic circuit 121. Rewiring is performed by opening the portion of the silicon layer 104 of the memory circuit 122 where the wiring 134 is desired to be formed and filling this portion with a conductive material such as copper.

[0112] In step S33 ( Figure 9 ), alignment is performed so that the wiring 134 from the terminal 122a of the storage circuit 122 in the support substrate 102 and the wiring 134 from the terminal 120a of the imaging element 120 in the wafer 101 are in positions appropriately facing each other.

[0113] Then, the wafer 101 and the support substrate 102 are bonded by WoW bonding, so that the wiring 134 from the terminal 122a of the memory circuit 122 in the support substrate 102 is connected to the wiring 134 from the terminal 120a of the imaging element 120 in the wafer 101 by CuCu bonding. This process results in a state in which each memory circuit 122 of the support substrate 102 is electrically connected to each imaging element 120 of the wafer 101.

[0114] In step S34, the support substrate 102 is peeled off. For example, the support substrate 102 is removed by debonding or etching.

[0115] In step S35 , embedding is performed. As shown in step S35 , an oxide film 133 serving as an insulating film is formed. At this time, the surface of the oxide film 133 is flattened at a height corresponding to the logic circuit 121 and the memory circuit 122 .

[0116] In step S36 ( Figure 10 ), a through silicon via (TSV) 161 is formed. The TSV 161 is formed in a portion for forming a wiring 136 connecting the logic circuit 121 and the memory circuit 122.

[0117] In step S37 , the wiring 136 is formed by filling, for example, copper (Cu), tungsten (W), polysilicon, or the like in the TSVs 161 and in the horizontal redistribution portions connecting the TSVs 161 .

[0118] In step S38, an oxide film 133 serving as an insulating film is formed so as to also cover the wiring 136, and the chip including the configured memory circuit 122 and logic circuit 121 is buried. At this time, the surface of the oxide film 133 is flattened at a height corresponding to the logic circuit 121 and the memory circuit 122.

[0119] In step S39 ( Figure 11 ), the support substrate 162 is attached to the oxide film 133 formed in step S38. In step S40, the silicon layer (corresponding to the layer of the wafer 101) which is the upper layer in the figure of the imaging element 120 is thinned.

[0120] In step S41 , an on-chip lens and an on-chip color filter 131 are provided on the imaging element 120 , and dicing into individual pieces is performed to complete the imaging device 111 .

[0121] With such a configuration, since the connection between the circuits of the imaging element 120 and the storage circuit 122 can be a connection of terminals formed with a wiring density of fine wiring through semiconductor lithography technology similar to WoW, the number of connection terminals can be increased and the signal processing speed in each wiring can be reduced, thereby reducing power consumption.

[0122] In addition, when the circuits of the imaging element 120 and the logic circuit 121 are formed to be connected to each other, since the connection can be made by forming terminals with a wiring density of fine wiring, the number of connection terminals can be increased and the signal processing speed in each wiring can be reduced, thereby reducing power consumption.

[0123] Furthermore, since only good chips are connected to the logic circuit 121 and the memory circuit 122 , defects in each wafer, which is a disadvantage of WoW, are reduced, thereby reducing the occurrence of yield loss.

[0124] In addition, if Figure 5 As shown in the lower part, unlike WoW, since each of the storage circuit 122 to be connected and the logic circuit can be configured in an independent island shape by making the size as small as possible regardless of the chip size of the imaging element 120, the manufacturing efficiency of the logic circuit 121 to be connected and the storage circuit 122 can be improved.

[0125] As a result, since the imaging element 120 requires a minimum pixel size to react to light, the manufacturing process for the imaging element 120 does not necessarily require a fine wiring process, thereby reducing process costs. Furthermore, in the manufacturing process for the logic circuit 121, power consumption can be reduced by using a state-of-the-art fine wiring process. Furthermore, the manufacturing efficiency of the logic circuit 121 and the memory circuit 122 can be improved. Consequently, the costs associated with manufacturing the imaging device 111 can be reduced.

[0126] In addition, due to the structure in which chips can be realigned and joined within a wafer, stacking can be performed in one chip even in the case of different types of processes (where analog circuits such as power ICs and clocks, logic circuits 121, and components made by completely different processes are difficult to produce within the same wafer) or even when there are differences in wafer sizes.

[0127] Furthermore, the logic circuit 121 and the memory circuit 122 have been described above as examples of circuits connected to the imaging element 120. However, circuits other than the logic circuit 121 and the memory circuit 122 may be used as long as they are signal processing circuits required for the operation of the imaging element 120, such as circuits related to the control of the imaging element 120 or circuits related to the processing of captured pixel signals. The signal processing circuits required for the operation of the imaging element 120 may be, for example, a power supply circuit, an image signal compression circuit, a clock circuit, an optical communication conversion circuit, or the like.

[0128] <About Thickening Layer>

[0129] In the above-described example, an example has been shown in which the memory circuit 122 is provided with the thickening layer 137 and the logic circuit 121 is not provided with the thickening layer 137. Figure 5 The configuration of the imaging device 111 is shown in the upper portion of FIG. The terminal 122a of the memory circuit 122 and the terminal 120a of the imaging element 120 are connected via a wiring 134. The terminal 121a of the logic circuit 121 and the terminal 120a of the imaging element 120 are not connected.

[0130] The terminal 122a of the memory circuit 122 is disposed closer to the terminal 120a than the terminal 121a of the logic circuit 121. That is, the terminal 122a connected to the terminal 120a is disposed closer to the terminal 120a than the terminal 121a not connected to the terminal 120a. By providing the memory circuit 122 with the thickening layer 137, the terminal 122a of the memory circuit 122 can be disposed closer to the terminal 120a of the imaging element 120.

[0131] In other words, by providing the thickening layer 137 for the memory circuit 122 , the thickness of the silicon layer 104 of the memory circuit 122 can be formed thinner, and the terminal 122 a of the memory circuit 122 can be provided at a position close to the terminal 120 a of the imaging element 120 .

[0132] This will refer to Figure 12 Provide explanation. Figure 12 A is a diagram for explaining a case where the thickening layer 137 is not provided (in other words, a case where the imaging device 111 is manufactured in a normal manufacturing step). Figure 12 B is a diagram for explaining a case where the thickening layer 137 is provided (in other words, a case where the imaging device 111 is manufactured in the above-mentioned manufacturing steps).

[0133] like Figure 12 As shown in the left figure of FIG. 1A , the logic circuit 121 and the memory circuit 122′ have a configuration in which an oxide film bonding layer 135, an oxide film 133, and a silicon layer 103 (silicon layer 104′) are stacked on a supporting substrate 102. Note that in order to distinguish it from the memory circuit 122 to which the present technology is applied, the memory circuit 122 without the thickening layer 137 is described as a memory circuit 122′ by adding a prime symbol.

[0134] like Figure 12 As shown in the right figure of A, Figure 12 The imaging element 120 is further stacked in the state shown in the left figure of A. Furthermore, the terminal 120a of the imaging element 120 and the terminal 122a' of the memory circuit 122' are connected by a wiring 134'. The length of the wiring 134' is defined as a length L1.

[0135] In the case of providing the thickening layer 137, as Figure 12As shown in the left figure of FIG. 1B , the logic circuit 121 has a structure in which an oxide film bonding layer 135, an oxide film 133, and a silicon layer 103 are stacked on the support substrate 102. Furthermore, the memory circuit 122 has a structure in which an oxide film bonding layer 135, an oxide film 133, a thickening layer 137, and a silicon layer 103 are stacked on the support substrate 102.

[0136] like Figure 12 As shown in the right figure of B, Figure 12 The imaging element 120 is further stacked in the state shown in the left diagram of FIG. Furthermore, the terminal 120a of the imaging element 120 and the terminal 122a of the memory circuit 122 are connected by a wiring 134. The length of the wiring 134 is defined as a length L2.

[0137] like Figure 12 As shown in the left figure of FIG. 2B , the silicon layer 103 and the silicon layer 104 have different thicknesses, and the silicon layer 104 is formed to be thinner than the silicon layer 103 by the thickness of the thickening layer 137 .

[0138] The length L1 and the length L2 are the lengths of the wiring 134 (134'), but the lengths depend on the thickness of the silicon layer 104. Therefore, when the thickness of the silicon layer 104 is thin, the length of the wiring 134 becomes short. Figure 12 In the case of the example shown, it is obvious that the length L1 > the length L2 is satisfied.

[0139] Generally, it is easier to form short wiring than long wiring. For example, when forming vias to form wiring 134, shallower vias can be formed more easily in a shorter time than deeper vias.

[0140] According to the present technology, since the thickness of the silicon layer 104 of the memory circuit 122 can be formed to be thin, in step S32 ( Figure 8 ), it is easy to form the wiring 134 on the terminal 122a of the storage circuit 122.

[0141] As described above, a configuration may be adopted in which a circuit (chip) requiring redistribution is provided with the thickened layer 137 to facilitate redistribution.

[0142] In the above example, the logic circuit 121 and the memory circuit 122 are used as an example of a circuit connected to the imaging element 120. However, a circuit other than the logic circuit 121 and the memory circuit 122 may be used as long as it is a signal processing circuit required for the operation of the imaging element 120, such as a circuit related to the control of the imaging element 120 or a circuit related to the processing of captured pixel signals.

[0143] In the above example, the memory circuit 122 is provided with the thickening layer 137. However, a configuration in which the logic circuit 121 is provided with the thickening layer 137 is also possible. Furthermore, a configuration in which the thickening layer 137 is provided in both the logic circuit 121 and the memory circuit 122 is also possible. Furthermore, in the case in which both the logic circuit 121 and the memory circuit 122 are provided with the thickening layer 137, the thickness of the thickening layer 137 may be the same or different.

[0144] This technology can also be applied to devices having a configuration in which multiple circuits (chips) are mounted on a single chip. That is, multiple chips can be formed as chips with or without a thickening layer, and can be mounted on a single chip. Furthermore, when multiple chips with a thickening layer are mounted on a single chip, the thickness of the thickening layer can be different for each chip.

[0145] <About Wiring Connecting Circuits>

[0146] For example, in Figure 5 In the imaging device 111 shown in the upper portion of FIG, the logic circuit 121 and the storage circuit 122 are connected via wiring 136. Figure 5 As shown in the upper part of FIG, the wiring 136 is provided to connect the terminal 121a in the logic circuit 121 and the terminal 122a of the storage circuit 122. The wiring 136 may have a Figure 13 The shape shown.

[0147] exist Figure 13 In the illustrated imaging device 111, a terminal 121b of the logic circuit 121 and a terminal 122b of the memory circuit 122 are connected by a wiring 201. The terminal 121b is a terminal on the side closer to the memory circuit 122 among the terminals 121a of the logic circuit 121. The terminal 122b is a terminal on the side closer to the logic circuit 121 among the terminals 122a of the memory circuit 122.

[0148] The terminal 121b and the terminal 122b are provided as terminals connected to the wiring 201. Note that here, an example has been described in which the terminal 121b on the side close to the memory circuit 122 among the terminals 121a provided in the logic circuit 121 is a terminal connected to the wiring 201, but the terminal 121b to be connected to the wiring 201 may be newly provided. Similarly, here, an example has been described in which the terminal 122b on the side close to the logic circuit 121 among the terminals 122a provided in the memory circuit 122 is a terminal connected to the wiring 201, but the terminal 122b to be connected to the wiring 201 may be newly provided.

[0149] The wiring 201 is formed along the side surfaces of the silicon layer 103 of the logic circuit 121 , the oxide film bonding layer 135 provided on the imaging element 120 side, and the side surfaces of the silicon layer 104 of the memory circuit 122 , and is formed to connect the terminal 121 b and the terminal 122 b .

[0150] This wiring can also be applied to Figure 14 The imaging device 211 is constructed as shown. Figure 14 The imaging device 211 shown is Figure 5 Compared with the imaging device 111 shown in the upper portion of FIG, the difference in structure is that the memory circuit 222 of the imaging device 211 is not provided with the thickening layer 137. In addition, in terms of structure, the logic circuit 221 and the memory circuit 222 of the imaging device 211 are provided with terminals 221b and 222b, respectively, and the logic circuit 221 and the memory circuit 222 are connected via the terminals 221b and 222b connected by wiring 242.

[0151] Note that in Figure 14 In the imaging device 211 shown in FIG. 1 , the logic circuit 221 and the imaging element 220 are connected via the wiring 234. However, similar to Figure 5 The imaging device 111 shown may adopt a configuration in which the logic circuit 221 and the imaging element 220 are not connected via the wiring 234. That is, the present technology can be applied regardless of whether the logic circuit 221 and the imaging element 220 are directly connected.

[0152] Will further explain Figure 14 The imaging device 211 is shown in FIG. Figure 14 In the imaging device 211 in FIG. 1 , starting from the top in the figure, the on-chip lens, the on-chip color filter 231, and the imaging element 220 are stacked, and the memory circuit 222 and the logic circuit 221 are arranged and stacked on the left and right sides of the same layer below, and the support substrate 232 is formed below. That is, as shown in FIG. Figure 14 As shown, Figure 14 The imaging device 211 includes a semiconductor element layer E1 including an imaging element 220 formed from a wafer 101 , and a semiconductor element layer E2 including a memory circuit 222 and a logic circuit 221 formed on a support substrate 232 .

[0153] Among the terminals 220 a of the imaging element 220 , the terminal 220 a on the logic circuit 221 is electrically connected to the terminal 211 a of the logic circuit 221 through a wiring 234 connected by CuCu connection.

[0154] Furthermore, among the terminals 220 a of the imaging element 220 , the terminal 220 a on the memory circuit 222 is electrically connected to the terminal 222 a of the memory circuit 222 through a wiring 234 connected by CuCu connection.

[0155] In the semiconductor element layer E2 in which the logic circuit 221 and the memory circuit 222 are formed, the space around the memory circuit 222 and the logic circuit 221 is filled with the oxide film 233. As a result, in the semiconductor element layer E2, the memory circuit 222 and the logic circuit 221 are buried in the oxide film 233.

[0156] Furthermore, an oxide film bonding layer 235 is formed by oxide film bonding at the boundary between the semiconductor element layer E1 on which the imaging element 220 is formed and the semiconductor element layer E2 on which the memory circuit 222 and the logic circuit 221 are formed, and the semiconductor element layer E1 is bonded together. Furthermore, the oxide film bonding layer 235 is formed by oxide film bonding, and the semiconductor element layer E2 of the memory circuit 222 and the logic circuit 221 is bonded to the supporting substrate 232.

[0157] The logic circuit 221 and the memory circuit 222 are connected by a wiring 242. The wiring 242 is provided to connect the terminal 221b of the logic circuit 221 and the terminal 222b of the memory circuit 222. A protective film 241 is provided on a portion of the wiring 242 for manufacturing as described later.

[0158] The terminal 221 b and the terminal 222 b are provided separately from the terminal 221 a and the terminal 222 a , respectively, and are provided as terminals connecting the logic circuit 221 and the memory circuit 222 .

[0159] Wiring 242 extends from terminal 221b along the side surfaces of logic circuit 221, oxide film bonding layer 235, and memory circuit 222, and is connected to terminal 222b. Furthermore, protective film 241 is provided between wiring 242 and the side surfaces of logic circuit 221, oxide film bonding layer 235, and memory circuit 222.

[0160] <Regarding the Manufacturing of Imaging Device 211>

[0161] Figure 15 This is a diagram for explaining a method of manufacturing an imaging device in which a logic circuit 221 and a memory circuit 222 , which have been singulated and confirmed as good quality chips, are directly formed in the imaging element 220 on the wafer 101 .

[0162] Multiple imaging elements 220 are formed on wafer 101 using a semiconductor process. Furthermore, multiple logic circuits 221, which were formed on wafer 103 using a semiconductor process, diced into individual chips, and then individually electrically inspected and confirmed as good quality chips, and multiple memory circuits 222, which were formed on wafer 104 using a semiconductor process, diced into individual chips, and then individually electrically inspected and confirmed as good quality chips, are selected and reconfigured on imaging element 220 formed on wafer 101.

[0163] That is, since the logic circuit 221 and the memory circuit 222 confirmed as good chips are reconfigured on the imaging element 220 , here, both the logic circuit 221 and the memory circuit 222 are configured to be smaller than the imaging element 220 .

[0164] <Method of Manufacturing Imaging Device 211>

[0165] Next, we will refer to Figures 16-18 Description Figure 14 The manufacturing method of the imaging device 211 is as follows Figure 15 As shown, the logic circuit 221 and the storage circuit 222 are directly transferred to the imaging element 220.

[0166] In step S51 , the logic circuit 221 and the memory circuit 222 that have been electrically inspected and confirmed as good are transferred to the imaging element 220 on the wafer 101 , and wirings 234 are formed at the terminals 220 a , 221 a , and 222 a .

[0167] In addition, the wiring 234 from the terminal 221a of the logic circuit 221 and the terminal 222a of the storage circuit 222 are appropriately aligned with the position of the wiring 234 from the terminal 220a of the imaging element 220 in the wafer 101, connected by CuCu bonding, and the facing layers are bonded by forming an oxide film bonding layer 235 by oxide film bonding.

[0168] When the logic circuit 221 and the memory circuit 222 are transferred to the imaging element 220 , the terminal 221 b of the logic circuit 221 and the terminal 222 b of the memory circuit 222 are placed to face each other.

[0169] When manufacturing logic circuit 221, terminal 221b is formed together with terminal 221a. Furthermore, when manufacturing memory circuit 222, terminal 222b is formed together with terminal 222a. For example, terminals 221b and 222b can be formed simultaneously with forming the underlying wiring of logic circuit 221 and memory circuit 222. Therefore, manufacturing can be performed without adding multiple steps for forming terminals 221b and 222b.

[0170] In step S52, a protective film 241 is formed to protect the logic circuit 221 and the memory circuit 222. The protective film 241 is formed on the three sides of the logic circuit 221 that are not in contact with the imaging element 220. Furthermore, the protective film 241 is formed on the three sides of the memory circuit 222 that are not in contact with the imaging element 220. The protective film 241 may contain, for example, SiN or SiO2. Furthermore, the protective film 241 may have a multilayer (stacked film) structure rather than a single layer.

[0171] In step S53, the silicon layer 103 of the logic circuit 221 and the silicon layer 104 of the memory circuit 222 are thinned. A protective film 241 is formed on the silicon layer 103 of the logic circuit 221 and the silicon layer 104 of the memory circuit 222 and is polished together during the thinning. When removing contaminants or dust after silicon thinning, a portion of the protective film 241 is peeled off, and the surface can be cleaned.

[0172] In step S54 ( Figure 17 ), a patterning process is used to expose dedicated terminals (i.e., terminals 221b and 222b in this case) for connecting the logic circuit 221 and the memory circuit 222. In step S54, a predetermined material may be buried in the gap between the logic circuit 221 and the memory circuit 222 to facilitate patterning, and then exposure processing may be performed after ensuring surface flatness.

[0173] In step S55, a wiring 242 is formed to connect the terminal 221b and the terminal 222b. The wiring 242 includes a metal such as copper (Cu), tungsten (W), or aluminum (Al). The wiring 242 is formed using a resist patterning and processing process. Alternatively, as shown in FIG. Figure 19 As shown, the wiring 242 can also be formed by using the following method: opening the resist 301 only at the portion connecting the terminal 221b and the terminal 222b, exposing to form a metal sputtering film, and peeling off the resist 301.

[0174] In step S56, the silicon layer of the upper part of the logic circuit 221 and the storage circuit 222 in the figure is thinned to a height that does not affect the device characteristics, an oxide film 233 serving as an insulating film is formed, and a chip including the reconfigured logic circuit 221 and storage circuit 222 is buried.

[0175] In step S57 ( Figure 18 ), the support substrate 232 is bonded to the logic circuit 221 and the memory circuit 222. At this time, the layer of the support substrate 232 facing the logic circuit 221 and the memory circuit 222 is bonded by forming an oxide film bonding layer 235 through oxide film bonding.

[0176] In step S58 , upside-down inversion is performed so that the imaging element 220 is on the upper side, and the silicon layer, which is the upper layer in the figure of the imaging element 220 , is thinned.

[0177] In step S59 , an on-chip lens and an on-chip color filter 231 are provided on the imaging element 220 , and dicing into individual pieces is performed to complete the imaging device 211 .

[0178] As described above, a structure can be obtained in which the logic circuit 221 and the memory circuit 222 are connected via the wiring 242. The wiring 242 is connected to the terminal 221b and the terminal 222b that are dedicated to connecting the wiring 242. The terminal 221b and the terminal 222b can be formed simultaneously with the wiring layer of the lowest layer when manufacturing the logic circuit 221 and the memory circuit 222. That is, the terminal 221b and the terminal 222b can be formed without increasing the number of steps for forming the terminal 221b and the terminal 222b.

[0179] Furthermore, the step of forming the wiring 242 connecting the terminals 221 b and 222 b does not include a process of penetrating the substrate or engraving the substrate to a deep position, so that the wiring 242 can be easily formed.

[0180] The steps for forming wiring 242 are steps S52 to S55 described above. These steps do not include processes for forming deep trenches in the silicon layer, drilling holes in the AR coating and embedding metal in the case of an imaging device having an anti-reflection structure, or chemical mechanical polishing (CMP) of the metal. Since wiring 242 can be formed using manufacturing steps that do not require these processes, wiring 242 can be easily formed.

[0181] Furthermore, by forming the protective film 241 , insulation between chips can be maintained in the configuration.

[0182] The present technology is applicable not only to the imaging device having the above-described configuration but also to imaging devices having other configurations.

[0183] This technology can also be applied to devices having a configuration in which multiple circuits (chips) are mounted on a single chip. That is, multiple chips can be formed as chips with or without a thickening layer, and can be mounted on a single chip. Furthermore, when multiple chips with a thickening layer are mounted on a predetermined chip, the thickness of the thickening layer can be made different for each chip.

[0184] Furthermore, by configuring the wiring connecting the chips as the above-described wiring 242 , advantages such as ease of manufacturing can be obtained.

[0185] <Application examples of electronic equipment>

[0186] The above-mentioned imaging element can be applied to various electronic devices, for example, imaging devices such as digital cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0187] Figure 20 This is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0188] Figure 20 The illustrated imaging device 501 includes an optical system 502 , a shutter device 503 , an imaging element 504 , a drive circuit 505 , a signal processing circuit 506 , a monitor 507 , and a memory 508 , and can capture still images and moving images.

[0189] The optical system 502 has one or more lenses, and guides light from a subject (incident light) to the imaging element 504 and forms an image on a light-receiving surface of the imaging element 504 .

[0190] The shutter device 503 is provided between the optical system 502 and the imaging element 504 , and controls a light irradiation period and a light shielding period with respect to the imaging element 504 in accordance with control of the drive circuit 505 .

[0191] The imaging element 504 includes a package containing the above-described imaging element. The imaging element 504 accumulates signal charge for a certain period of time based on the light formed into an image on the light receiving surface via the optical system 502 and the shutter device 503. The signal charge accumulated in the imaging element 504 is transferred based on the drive signal (timing signal) supplied from the drive circuit 505.

[0192] The driving circuit 505 outputs a driving signal for controlling a transfer operation of the imaging element 504 and a shutter operation of the shutter device 503 to drive the imaging element 504 and the shutter device 503 .

[0193] The signal processing circuit 506 performs various signal processing on the signal charge output from the imaging element 504. An image (image data) obtained by the signal processing by the signal processing circuit 506 is supplied to the monitor 507 for display or supplied to the memory 508 for storage (recording).

[0194] Likewise, in the imaging device 501 having the above-described structure, by applying the above-described imaging device 111 (imaging device 211 ) to the optical system 502 and the imaging element 504 , it is possible to improve the yield and reduce the manufacturing cost.

[0195] <Example of use of imaging element>

[0196] For example, the above-described imaging element can be used in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below.

[0197] - A device for capturing images for viewing, for example, a digital camera or a portable device with a camera function.

[0198] - Traffic devices, such as on-board sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic parking and identifying the driver's condition, surveillance cameras that monitor moving vehicles and roads, and ranging sensors that measure the distance between vehicles.

[0199] - Home appliances, such as televisions, refrigerators, and air conditioners, to capture images of user gestures and operate the devices based on the gestures.

[0200] - Medical or healthcare devices, for example, endoscopes or devices for angiography by receiving infrared light.

[0201] - Security devices, such as surveillance cameras for crime prevention or cameras for personal identification.

[0202] - Devices for beauty care, such as a dermatometer for taking images of the skin and a microscope for taking images of the scalp.

[0203] - Sports devices, such as action cameras or wearable cameras for sports purposes, etc.

[0204] - Agricultural equipment, such as cameras used to monitor the condition of fields and crops.

[0205] <Application Examples of Endoscopic Surgery Systems>

[0206] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0207] Figure 21 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0208] Figure 21 The figure shows a state where an operator (doctor) 11131 is performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various instruments used for endoscopic surgery are mounted.

[0209] The endoscope 11100 includes a lens barrel 11101, a region of which a predetermined length from the distal end is inserted into a body cavity of a patient 11132, and a camera 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called hard scope having a hard lens barrel 11101, but the endoscope 11100 may be configured as a so-called soft scope having a soft lens barrel.

[0210] An opening portion into which an objective lens is fitted is provided at the distal end of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the distal end of the lens barrel through a light guide extending into the interior of the lens barrel 11101, and the light is emitted toward an observation object in the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 may be a straight-view mirror, an oblique-view mirror, or a side-view mirror.

[0211] The camera head 11102 is equipped with an optical system and an imaging element. Light reflected from the observation object (observation light) is focused on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0212] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), and the like, and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102 and performs various types of image processing such as development processing (demosaic processing) on the image signal to display an image based on the image signal.

[0213] The display device 11202 displays an image based on an image signal on which image processing has been performed by the CCU 11201 under the control of the CCU 11201 .

[0214] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light for capturing an image of a surgical site or the like to the endoscope 11100 .

[0215] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs instructions for changing the imaging conditions (such as the type of irradiation light, magnification, and focal length) of the endoscope 11100.

[0216] The treatment instrument control device 11205 controls the driving of the energy treatment instrument 11112 for purposes such as cauterization and incision of tissue and sealing of blood vessels. The pneumoperitoneum device 11206 infuses gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, ensuring the field of view of the endoscope 11100 and ensuring the operator's working space. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats, such as text, images, or graphics.

[0217] Note that the light source device 11203 that supplies irradiation light for imaging the surgical site to the endoscope 11100 may include, for example, an LED, a laser light source, or a white light source including a combination thereof. In the case where the white light source includes a combination of RGB laser light sources, since the output intensity and output timing of each color (various wavelengths) can be controlled with high precision, the white balance of the captured image can be adjusted in the light source device 11203. In addition, in this case, by emitting laser light from each RGB laser light source onto the observed object in a time-division manner and controlling the drive of the imaging element of the camera 11102 in synchronization with the emission timing, it is also possible to capture images corresponding to each RGB in a time-division manner. According to this method, a color image can be obtained without providing a color filter in the imaging element.

[0218] Furthermore, the light source device 11203 can be controlled to change the intensity of the light output at predetermined intervals. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity to acquire and synthesize images in a time-division manner, it is possible to generate a high dynamic range image free of so-called blocked shadows and overexposed highlights.

[0219] In addition, the light source device 11203 can be configured to supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by using the wavelength dependence of light absorption in body tissue, so-called narrowband imaging is performed to image predetermined tissues such as blood vessels in the surface layer of the mucosa with high contrast by emitting light having a narrowband domain compared to the irradiation light (i.e., white light) during ordinary observation. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by emitting fluorescence generated by excitation light. In fluorescence observation, for example, excitation light can be irradiated onto body tissue to observe fluorescence from the body tissue (autofluorescence imaging), or a reagent such as indocyanine green (ICG) can be locally injected into the body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be emitted to obtain a fluorescence image. The light source device 11203 can be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0220] Figure 22 It shows Figure 21 A block diagram showing an example of the functional configuration of the camera 11102 and the CCU 11201 is shown.

[0221] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicatively connected to each other via a transmission cable 11400.

[0222] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light received from the distal end of the lens barrel 11101 is guided to the camera head 11102 and incident on the lens unit 11401. The lens unit 11401 is constructed by combining a plurality of lenses including a zoom lens and a focus lens.

[0223] The imaging unit 11402 includes an imaging element. The number of imaging elements constituting the imaging unit 11402 may be one (so-called single-board type) or multiple (so-called multi-board type). In the case where the imaging unit 11402 is configured as a multi-board type, for example, image signals corresponding to RGB can be generated by each imaging element, and a color image can be obtained by synthesizing the image signals. Alternatively, the imaging unit 11402 may include a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a three-dimensional (3D) display. By performing a 3D display, the operator 11131 can more accurately grasp the depth of the living tissue in the surgical site. Note that in the case where the imaging unit 11402 is configured as a multi-board type, a plurality of lens units 11401 corresponding to the respective imaging elements may be provided.

[0224] In addition, the imaging unit 11402 does not have to be provided in the camera head 11102. For example, the imaging unit 11402 can be provided just behind the objective lens inside the lens barrel 11101.

[0225] The driving unit 11403 includes an actuator and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. As a result, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0226] The communication unit 11404 includes a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0227] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0228] Note that imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the so-called automatic exposure (AE) function, automatic focus (AF) function, and automatic white balance (AWB) function are provided in the endoscope 11100.

[0229] The camera control unit 11405 controls the driving of the camera 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0230] The communication unit 11411 includes a communication device for transmitting and receiving various types of information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

[0231] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0232] The image processing unit 11412 performs various types of image processing on the image signal which is RAW data transmitted from the camera 11102 .

[0233] The control unit 11413 performs various types of control related to imaging of a surgical site, etc., performed by the endoscope 11100 and display of captured images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0234] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image of the surgical site, etc., based on the image signal processed by the image processing unit 11412. In this case, the control unit 11413 can use various image recognition technologies to identify various objects within the captured image. For example, the control unit 11413 can detect the edge shape and color of objects contained in the captured image to identify surgical instruments such as forceps, specific body parts, bleeding, and fog when using the energy treatment device 11112. When causing the display device 11202 to display the captured image, the control unit 11413 uses the recognition results to overlay various types of surgical support information on the image of the surgical site. Since the surgical support information is superimposed and presented to the operator 11131, the burden on the operator 11131 can be reduced, allowing the operator 11131 to perform the surgery reliably.

[0235] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 together is an electrical signal cable compatible with communication of electrical signals, an optical fiber compatible with optical communication, or a composite cable thereof.

[0236] Here, in the example shown, wired communication is performed by using the transmission cable 11400 , but wireless communication may be performed between the camera head 11102 and the CCU 11201 .

[0237] <Application Examples of Mobile Objects>

[0238] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, unmanned aerial vehicle, ship, and robot.

[0239] Figure 23 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0240] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Figure 23 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of integrated control unit 12050, a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0241] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 controls a drive force generating device, such as an internal combustion engine or a drive motor, that generates the vehicle's drive force; a drive force transmission mechanism that transmits the drive force to the wheels; a steering mechanism that adjusts the vehicle's steering angle; and a brake device that generates the vehicle's braking force.

[0242] The main system control unit 12020 controls the operation of various devices attached to the vehicle body according to various programs. For example, the main system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as headlights, taillights, brake lights, flashers, and fog lights. In this case, instead of key presses, radio waves transmitted from a portable device or signals from various switches can be input to the main system control unit 12020. The main system control unit 12020 receives the input of these radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0243] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as people, cars, obstacles, signs, and text on the road, or detect distances.

[0244] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0245] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. For example, the driver state detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver has fallen asleep.

[0246] The microcomputer 12051 can calculate control target values for the driving force generation device, the steering mechanism, or the braking device based on the information inside and outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control instructions to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of vehicles, tracking driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, and vehicle lane departure warning.

[0247] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040 to achieve autonomous driving that does not rely on the driver's operation.

[0248] Furthermore, the microcomputer 12051 can output control commands to the main system control unit 12020 based on information outside the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlights based on the positions of the preceding vehicle or oncoming vehicles detected by the vehicle exterior information detection unit 12030, performing coordinated control to prevent glare, such as switching the headlights from high beam to low beam.

[0249] The sound and image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Figure 23 In the example of FIG, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0250] Figure 24 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0251] exist Figure 24 , vehicle 12100 has imaging units 12101 , 12102 , 12103 , 12104 and 12105 as imaging unit 12031 .

[0252] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at locations such as the front of the vehicle 12100, the sideview mirrors, the rear bumper, and the rear door, as well as the upper side of the windshield inside the vehicle. Imaging unit 12101 disposed on the front of the vehicle and imaging unit 12105 disposed on the upper side of the windshield inside the vehicle primarily obtain images of the front of the vehicle 12100. Imaging units 12102 and 12103 disposed on the sideview mirrors primarily obtain images of the sides of the vehicle 12100. Imaging unit 12104 disposed on the rear bumper or rear door primarily obtains images of the rear of the vehicle 12100. The front images acquired by imaging units 12101 and 12105 are primarily used to detect vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0253] also, Figure 24 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located on the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, which are located on the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained.

[0254] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or an imaging element having pixels for phase difference detection.

[0255] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can determine the distance to each 3D object within imaging ranges 12111-12114 and the temporal change in that distance (relative speed to vehicle 12100). This allows it to identify the 3D object located on the travel path of vehicle 12100, particularly the closest 3D object, that is, the 3D object traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as the leading vehicle. Furthermore, microcomputer 12051 can set a predetermined distance between vehicles ahead of the leading vehicle and perform automatic braking control (including tracking stop control) and automatic acceleration control (including tracking start control). In this way, coordinated control, such as automatic driving, can be performed to achieve autonomous driving without relying on driver input.

[0256] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify and extract 3D object data regarding 3D objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other 3D objects such as utility poles, thereby enabling automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as those visible to the driver of vehicle 12100 and those difficult to see. Microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the likelihood of a collision exceeds a set value, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, or initiates forced deceleration or evasive steering via drive system control unit 12010, thereby providing driving assistance for collision avoidance.

[0257] At least one of the imaging units 12101-12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101-12104. For example, pedestrian identification may be performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras, and performing pattern matching on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio and video output unit 12052 controls the display unit 12062 so that the identified pedestrian is covered with a rectangular outline for emphasis. Furthermore, the audio and video output unit 12052 causes the display unit 12062 to display an icon indicating the pedestrian at a desired location.

[0258] Furthermore, in this specification, a system represents an entire device including a plurality of devices.

[0259] Note that the effects described in this specification are merely examples and not limitations, and there may also be other effects.

[0260] Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present technology.

[0261] Note that the present technology may also have the following configurations.

[0262] (1) An imaging device comprising:

[0263] a first semiconductor element including an imaging element configured to generate a pixel signal; and

[0264] A second semiconductor element having a first signal processing circuit and a second signal processing circuit configured to process the pixel signal embedded therein by an embedding member, wherein

[0265] The first signal processing circuit has a structure having at least one more layer than the second signal processing circuit.

[0266] (2) The imaging device according to (1) above, further comprising:

[0267] A first wiring connects the first semiconductor element and the first signal processing circuit.

[0268] (3) The imaging device according to (2) above, further comprising:

[0269] A second wiring connects the first signal processing circuit and the second signal processing circuit.

[0270] (4) The imaging device according to (3) above, wherein

[0271] A first wiring connects a terminal of the first semiconductor element and a first terminal of the first signal processing circuit, and

[0272] The second wiring connects a second terminal of the first signal processing circuit that is different from the first terminal and a third terminal of the second signal processing circuit.

[0273] (5) The imaging device according to any one of (1) to (4) above, wherein

[0274] The layer is an oxide film.

[0275] (6) The imaging device according to any one of (1) to (5) above, wherein

[0276] A distance between a terminal of the first semiconductor element and a terminal of the first signal processing circuit is shorter than a distance between a terminal of the first semiconductor element and a terminal of the second signal processing circuit.

[0277] (7) The imaging device according to any one of (1) to (6) above, wherein

[0278] The first signal processing circuit is a storage circuit, and the second signal processing circuit is a logic circuit.

[0279] (8) An electronic device including an imaging device, the imaging device comprising:

[0280] a first semiconductor element including an imaging element configured to generate a pixel signal; and

[0281] A second semiconductor element having a first signal processing circuit and a second signal processing circuit configured to process the pixel signal embedded therein by an embedding member, wherein

[0282] The first signal processing circuit has a structure having at least one more layer than the second signal processing circuit.

[0283] (9) An imaging device comprising:

[0284] a first semiconductor element including an imaging element configured to generate a pixel signal;

[0285] a second semiconductor element in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded via an embedding member; and

[0286] a wiring connecting the first signal processing circuit and the second signal processing circuit, wherein

[0287] The wiring connects a terminal provided in a lowermost wiring layer of the first signal processing circuit and a terminal provided in a lowermost wiring layer of the second signal processing circuit.

[0288] (10) The imaging device according to (9) above, wherein

[0289] The wiring is provided along a side surface of the first signal processing circuit and a side surface of the second signal processing circuit.

[0290] (11) The imaging device according to (10) above, wherein

[0291] A portion of the wiring is provided along a layer formed on a bonding surface between the first semiconductor element and the second semiconductor element.

[0292] (12) The imaging device according to (9) or (11) above, wherein

[0293] At least one or more layers are provided between the wiring and the first signal processing circuit and between the wiring and the second signal processing circuit.

[0294] (13) The imaging device according to (12) above, wherein

[0295] The one or more layers are insulating films.

[0296] (14) An electronic device including an imaging device, the imaging device comprising:

[0297] a first semiconductor element including an imaging element configured to generate a pixel signal;

[0298] a second semiconductor element in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded via an embedding member; and

[0299] a wiring connecting the first signal processing circuit and the second signal processing circuit, wherein

[0300] The wiring connects a terminal provided in a lowermost wiring layer of the first signal processing circuit and a terminal provided in a lowermost wiring layer of the second signal processing circuit.

[0301] (15) A method for manufacturing an imaging device, the imaging device comprising:

[0302] A first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels;

[0303] a second semiconductor element in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded via an embedding member; and

[0304] a wiring connecting the first signal processing circuit and the second signal processing circuit,

[0305] The manufacturing method comprises:

[0306] a step of transferring the first signal processing circuit and the second signal processing circuit to the first semiconductor element;

[0307] forming a first film on the first signal processing circuit and the second signal processing circuit;

[0308] exposing a portion of a first terminal provided in a lowermost wiring layer of the first signal processing circuit and a portion of a second terminal provided in a lowermost wiring layer of the second signal processing circuit; and

[0309] A step of forming a wiring connecting the first terminal and the second terminal.

[0310] (16) The manufacturing method according to (15) above, further comprising:

[0311] After forming the first film, thinning the first signal processing circuit and the second signal processing circuit.

[0312] Reference Signs List

[0313] 101 wafer 102 support substrate

[0314] 103 wafer 104 wafer

[0315] 111 imaging device 120 imaging element

[0316] 121 logic circuit 122 storage circuit

[0317] 131 on-chip color filter 132 supporting substrate

[0318] 133 oxide film 134 wiring

[0319] 135 oxide film bonding layer 136 wiring

[0320] 137 thickening layer 151 cutting belt

[0321] 152 ring frame 153 cutting belt

[0322] 154 annular frame 162 supports the substrate

[0323] 201 wiring 204 imaging element

[0324] 211 Imaging device 220 Imaging element

[0325] 221 logic circuit 222 storage circuit

[0326] 231 on-chip color filter 232 supporting substrate

[0327] 233 oxide film 234 wiring

[0328] 235 oxide film bonding layer 241 protective film

[0329] 242 wiring 252 wiring

[0330] 301 resist

Claims

1. An imaging device comprising: a first semiconductor element including an imaging element configured to generate a pixel signal; a second semiconductor element in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded via an embedding member; and a second wiring connecting the first signal processing circuit and the second signal processing circuit, wherein The second wiring connects a terminal provided in the lowermost wiring layer of the first signal processing circuit and a terminal provided in the lowermost wiring layer of the second signal processing circuit. At least one or more layers are provided between the second wiring and the first signal processing circuit and between the second wiring and the second signal processing circuit, and The first signal processing circuit has a structure having at least one more layer than the second signal processing circuit, wherein the at least one more layer is a thickened layer, thereby shortening the length of the first wiring connecting the first semiconductor element and the first signal processing circuit.

2. The imaging device according to claim 1, wherein The second wiring is provided along a side surface of the first signal processing circuit and a side surface of the second signal processing circuit.

3. The imaging device according to claim 2, wherein A portion of the second wiring is provided along a layer formed on a bonding surface between the first semiconductor element and the second semiconductor element.

4. The imaging device according to claim 1, wherein The at least one layer or the plurality of layers are insulating films.

5. The imaging device according to claim 1, wherein A first wiring connects a terminal of the first semiconductor element and a first terminal of the first signal processing circuit, and The second wiring connects a second terminal of the first signal processing circuit that is different from the first terminal and a third terminal of the second signal processing circuit.

6. The imaging device according to any one of claims 1 to 5, wherein The at least one additional layer is an oxide film.

7. The imaging device according to any one of claims 1 to 4, wherein A distance between a terminal of the first semiconductor element and a terminal of the first signal processing circuit is shorter than a distance between a terminal of the first semiconductor element and a terminal of the second signal processing circuit.

8. The imaging device according to any one of claims 1 to 5, wherein The first signal processing circuit is a storage circuit, and the second signal processing circuit is a logic circuit.

9. An electronic device comprising the imaging device according to any one of claims 1 to 8.

10. A method for manufacturing an imaging device, the imaging device comprising: A first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels; a second semiconductor element in which a first signal processing circuit and a second signal processing circuit configured to process the pixel signal are embedded by an embedding member, wherein the first signal processing circuit has a structure having at least one more layer than the second signal processing circuit, the at least one more layer being a thickened layer, thereby shortening the length of a first wiring connecting the first semiconductor element and the first signal processing circuit; and a second wiring connecting the first signal processing circuit and the second signal processing circuit, The manufacturing method comprises: a step of transferring the first signal processing circuit and the second signal processing circuit to the first semiconductor element; forming a first film on the first signal processing circuit and the second signal processing circuit; exposing a portion of a first terminal provided in a lowermost wiring layer of the first signal processing circuit and a portion of a second terminal provided in a lowermost wiring layer of the second signal processing circuit; and a step of forming a second wiring connecting the first terminal and the second terminal.

11. The manufacturing method according to claim 10, further comprising: After forming the first film, thinning the first signal processing circuit and the second signal processing circuit.

Images