Display device

Abstract

A display device may include: a substrate having a display area, a peripheral area surrounding the display area and including a first peripheral area and a second peripheral area, a first pad area located on one side of the peripheral area, and a second pad area located on the other side of the peripheral area; a first upper power line disposed in the first pad area on the substrate; a conductive member disposed in the first peripheral area located adjacent to the first pad area on the substrate; a protective insulating layer disposed on the conductive member; a planarization layer disposed on the protective insulating layer; an upper connecting member disposed in the first pad area and the first peripheral area on the planarization layer, and electrically connecting the first upper power line and the conductive member through a first contact hole and a second contact hole, the first contact hole being formed to pass through the planarization layer and the protective insulating layer on the conductive member, and the second contact hole being formed to pass through the planarization layer and the protective insulating layer on the first upper power line; and a sub-pixel structure disposed in the display area on the protective insulating layer. Therefore, the display device can reduce heat generation that may occur in the first peripheral area and voltage drop that may occur in the display area.

Description

Technical Field

[0001] Embodiments generally relate to a display device and more particularly to a display device including a power line. Background Art

[0002] Flat panel display devices are used as display devices replacing cathode ray tube display devices due to their light-weight and thin characteristics. As representative examples of such flat panel display devices, there are liquid crystal display devices and organic light emitting diode display devices.

[0003] Recently, a display device with an enlarged size and high resolution has been developed. The display device may include a display area, a peripheral area, and a first pad area and a second pad area. In this case, a pixel may be arranged in the display area, and an image may be displayed by the pixel. In addition, a signal line and a power line electrically connected to the pixel may be arranged in a peripheral area surrounding the display area. In addition, a first pad electrode may be arranged in a first pad area located on one side of the peripheral area. A second pad electrode may be arranged in a second pad area located on the opposite side of the peripheral area. An external device may generate a signal, power, etc., and the signal and power may be provided to the pixel through a first pad electrode and a second pad electrode and a line. When the display device is driven with high brightness, the current may be concentrated in the power line arranged in the peripheral area, so that the temperature may rise. In this case, the heating phenomenon may cause a short circuit of the power line or a deformation of the insulating layer located around the power line. In addition, as the size of the display area increases, a voltage drop phenomenon may occur. In other words, defects of the display device may be caused by the heating phenomenon of the power line occurring in the peripheral area and the voltage drop phenomenon occurring in the display area. Summary of the invention

[0004] Technical issues

[0005] An object of the present invention is to provide a display device comprising power lines.

[0006] However, the purpose of the inventive concept is not limited thereto. Therefore, the purpose of the inventive concept can be expanded without departing from the spirit and scope of the inventive concept.

[0007] Technical Solution

[0008] In order to achieve the above-mentioned purpose of the present invention, the display device according to the embodiment of the present invention includes a substrate, a first upper power line, a conductive member, a protective insulating layer, an upper connecting member and a sub-pixel structure. The substrate includes a display area, a peripheral area surrounding the display area and including a first peripheral area and a second peripheral area, a first pad area on one side of the peripheral area, and a second pad area on the opposite side of the peripheral area. The first upper power line is arranged in the first pad area on the substrate. The conductive member is arranged in the first peripheral area adjacent to the first pad area on the substrate. The protective insulating layer is arranged on the conductive member. The planarization layer is arranged on the protective insulating layer. The upper connecting member is arranged in the first pad area and the first peripheral area on the planarization layer, and the first upper power line and the conductive member are electrically connected through a first contact hole and a second contact hole, the first contact hole is formed in the protective insulating layer and the planarization layer located on the conductive member, and the second contact hole is formed in the protective insulating layer and the planarization layer located on the first upper power line. The sub-pixel structure is arranged in the display area on the protective insulating layer.

[0009] In an embodiment, the display device may further include a first connection pattern and a second connection pattern. The first connection pattern may be disposed between the protective insulating layer and the planarization layer to overlap with the first contact hole, and may cover the top surface of the conductive member so that the conductive member is not exposed. The second connection pattern may be disposed between the protective insulating layer and the planarization layer to overlap with the second contact hole, and may cover the top surface of the first upper power line so that the first upper power line is not exposed.

[0010] In an embodiment, the conductive member may include a first extension portion and a second extension portion. The first extension portion may extend in a first direction parallel to the top surface of the substrate and may be located in the first peripheral region. The second extension portion may extend from one side of the first extension portion in a second direction, the second direction being a direction from the first peripheral region to the display region, and the second extension portion may be located in a portion of the first peripheral region and the display region.

[0011] In an embodiment, the first contact hole may be located to correspond to the first extension portion, and may have a stripe shape when viewed in a plan view.

[0012] In an embodiment, a length of the first contact hole in the first direction may be equal to a length of the first extension in the first direction.

[0013] In an embodiment, the sub-pixel structure may include a lower electrode disposed in the display area on the planarization layer, a light emitting layer disposed on the lower electrode, and an upper electrode disposed on the light emitting layer.

[0014] In an embodiment, the upper electrode may be electrically connected to the second extension through a third contact hole formed in the protection insulating layer and the planarization layer on the second extension, and the second extension may be defined as a first sub-power line.

[0015] In an embodiment, the display device may further include a third connection pattern and a first electrode pattern. The third connection pattern may be disposed between the protective insulating layer and the planarization layer to overlap with the third contact hole, and may cover the top surface of the second extension portion so that the second extension portion is not exposed. The first electrode pattern may be disposed between the upper electrode and the third connection pattern.

[0016] In an embodiment, the display device may further include a first lower power line arranged in the second pad area on the substrate, a second lower power line arranged in the second pad area and in a second peripheral area adjacent to the second pad area on the substrate, and a fan-out line arranged between the substrate and the first lower power line and the second lower power line in the second pad area and the second peripheral area.

[0017] In an embodiment, the first power may be provided to the first lower power line. The second power having a voltage level different from that of the first power may be provided to the second lower power line. The data signal may be provided to the fan-out line.

[0018] In an embodiment, the display device may further include a lower connection member disposed on the planarization layer in the second pad region and the second peripheral region. The lower connection member may electrically connect the first lower power line and the first sub-power line through a fourth contact hole and a fifth contact hole, the fourth contact hole being formed in the protective insulating layer and the planarization layer located on the first lower power line, and the fifth contact hole being formed on the first sub-power line adjacent to the second peripheral region.

[0019] In an embodiment, the display device may further include a fourth connection pattern and a fifth connection pattern. The fourth connection pattern may be disposed between the protective insulating layer and the planarization layer to overlap with the fourth contact hole, and may cover the fourth contact hole so that the first lower power line is not exposed. The fifth connection pattern may be disposed between the protective insulating layer and the planarization layer to overlap with the fifth contact hole, and may cover the fifth contact hole so that the first sub-power line is not exposed.

[0020] In an embodiment, the light emitting layer may not be provided in a portion in which the third contact hole is formed.

[0021] In an embodiment, the display device may further include an upper inspection pad located at the same layer as the first upper power line and the conductive member. The upper inspection pad may be arranged in a first direction parallel to the top surface of the substrate in the first peripheral region.

[0022] In an embodiment, the display device may further include a second upper power line disposed in the first pad area and the first peripheral area on the substrate. The second upper power line may be located at a level lower than that of the first upper power line and the conductive member. The first power may be supplied to the first upper power line, and the second power having a voltage level different from the voltage level of the first power may be supplied to the second upper power line.

[0023] In an embodiment, the second upper power line may include a first line extension, a second line extension, and a third line extension. The first line extension may be located in the first peripheral region and may extend in a first direction parallel to the top surface of the substrate. The second line extension may extend from one side of the first line extension in a third direction to be located in the first pad region, the third direction being the direction from the first peripheral region to the first pad region. The third line extension may extend from the opposite side of the first line extension in a second direction to be located in the display region, and may intersect with the conductive member, the second direction being the direction from the first peripheral region to the display region.

[0024] In an embodiment, the display device may further include a second sub power line disposed in the first peripheral region and a portion of the display region. The second sub power line may extend in the second direction and may be electrically connected to the third line extension portion in the first peripheral region.

[0025] In an embodiment, the second sub power line may be located at the same layer as the first upper power line and the conductive member.

[0026] In an embodiment, the display device may further include a first pad electrode disposed in the first pad region on the substrate and a second pad electrode disposed in the second pad region on the substrate.

[0027] In an embodiment, the display device may further include a first power circuit board to which a first power is applied, a second power circuit board to which a second power having a voltage level different from that of the first power is applied, and a driving circuit board to which a data signal is applied. The first power circuit board and the second power circuit board may be electrically connected to the first pad electrode, and the first power circuit board, the second power circuit board, and the driving circuit board may be electrically connected to the second pad electrode.

[0028] Beneficial Effects

[0029] Since the display device according to an exemplary embodiment of the present invention includes a conductive member, and the first contact hole formed on the conductive member has a relatively wide area, the heating phenomenon that may occur in the first peripheral region can be reduced. In addition, since the display device includes a third contact hole, and the upper electrode receives the first power from the first sub-power line in each sub-pixel region, the voltage drop phenomenon that may occur in the display region can be reduced. Therefore, according to the display device, the heating phenomenon that may occur in the first peripheral region and the voltage drop phenomenon that may occur in the display region can be reduced.

[0030] However, the effects of the present invention are not limited thereto. Therefore, the effects of the present invention can be expanded without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present invention.

[0032] Figure 2 It is used to describe the Figure 1 A plan view of a circuit board in a display device.

[0033] Figure 3 is used to describe electrical connections to Figure 1 A block diagram of an external device of a display device.

[0034] Figure 4 It shows that the setting Figure 1 Circuit diagram of a sub-pixel in a sub-pixel area.

[0035] Figure 5 It is shown Figure 1 A partial enlarged plan view of area A.

[0036] Figure 6 It is along Figure 5 A cross-sectional view taken along line II'.

[0037] Figure 7 It is along Figure 5 A cross-sectional view taken along line II-II'.

[0038] Figure 8 It is along Figure 5 A cross-sectional view taken along line III-III'.

[0039] Fig. 9 It is shown Figure 1 A partial enlarged plan view of area B.

[0040] Fig.10 It is along Fig. 9 A cross-sectional view taken along line IV-IV'.

[0041] Fig.11 It is along Fig. 9 A cross-sectional view taken along line V-V'.

[0042] Fig.12 It is along Fig. 9 A cross-sectional view taken along line VI-VI'.

[0043] Figures 13 to 26 is a view illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0044] Hereinafter, a display device according to an embodiment of the present invention and a method of manufacturing a display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same or similar components.

[0045] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present invention, Figure 2 It is used to describe the Figure 1 A plan view of a circuit board in a display device, and Figure 3 is used to describe electrical connections to Figure 1 A block diagram of an external device of a display device.

[0046] Reference Figure 1 , Figure 2 and Figure 3 , the display device 100 may include a first pad electrode 471 , a second pad electrode 472 , a first power circuit board 841 , a second power circuit board 941 , a driving circuit board 900 , and the like.

[0047] The display device 100 may include: a display area 10; a peripheral area 20 substantially surrounding the display area 10; a first pad area 61 located on one side of the peripheral area 20; and a second pad area 62 located on the opposite side of the peripheral area 20. In this case, the peripheral area 20 may include the first peripheral area 21 and the second peripheral area 22. For example, when viewed in a plan view of the display device 100, the first pad area 61 may be located on an upper portion of the display area 10, and the first peripheral area 21 may be placed between the display area 10 and the first pad area 61. In addition, the second pad area 62 may be located on a lower portion of the display area 10, and the second peripheral area 22 may be placed between the display area 10 and the second pad area 62.

[0048] The plurality of sub-pixel regions 30 may be arranged throughout the entire display region 10 in a first direction D1 and a second direction D2 , the first direction D1 being parallel to the top surface of the display device 100 , and the second direction D2 being orthogonal to the first direction D1 . Figure 4A sub-pixel SP may be provided in each of the sub-pixel regions 30 , and the sub-pixel SP may include a transistor, an organic light emitting diode, etc. An image may be displayed in the display region 10 through the sub-pixel SP.

[0049] For example, the subpixel SP may include a first subpixel, a second subpixel, and a third subpixel. The first subpixel may include a first organic light emitting diode for emitting red light, the second subpixel may include a second organic light emitting diode for emitting green light, and the third subpixel may include a third organic light emitting diode for emitting blue light.

[0050] In an exemplary embodiment, a first organic light emitting diode may be overlapped with a transistor included in a first sub-pixel, a second organic light emitting diode may be overlapped with a transistor included in a second sub-pixel, and a third organic light emitting diode may be overlapped with a transistor included in a third sub-pixel. In some embodiments, a first organic light emitting diode may be overlapped with a portion of a transistor included in a first sub-pixel and a portion of a transistor included in a sub-pixel different from the first sub-pixel, a second organic light emitting diode may be overlapped with a portion of a transistor included in a second sub-pixel and a portion of a transistor included in a sub-pixel different from the second sub-pixel, and a third organic light emitting diode may be overlapped with a portion of a transistor included in a third sub-pixel and a portion of a transistor included in a sub-pixel different from the third sub-pixel. For example, an RGB stripe scheme in which rectangles having the same size are sequentially arranged, an S stripe scheme including a blue organic light emitting diode having a relatively large area, a WRGB scheme also including a white organic light emitting diode, a PenTile scheme in which an RG-GB pattern is repeatedly arranged, and a WRGB scheme including a blue organic light emitting diode. TM The first to third organic light emitting diodes are arranged according to a scheme, etc.

[0051] In addition, the sub-pixel SP may include at least one driving transistor, at least one switching transistor, at least one capacitor, etc. In an exemplary embodiment, the sub-pixel SP may include a driving transistor (eg, Figure 4 The first transistor TR1), six switch transistors (eg, Figure 4 2 to 7 transistors TR2, TR3, TR4, TR5, TR6 and TR7), a storage capacitor (eg, Figure 4 Storage capacitor CST) etc.

[0052] However, although the display device 100 according to the present invention has been described as having a rectangular shape when viewed in a plan view, the shape of the display device 100 is not limited thereto. For example, the display device 100 may have a polygonal shape (a triangular shape, a diamond shape), a circular shape, an elliptical shape, or a track shape when viewed in a plan view.

[0053] A plurality of lines may be provided in the peripheral region 20. For example, the lines may include a data signal line, a gate signal line, an emission control signal line, a gate initialization signal line, an initialization voltage line, a first power line, a second power line, etc. The lines may extend from the peripheral region 20 to the display region 10 to be electrically connected to the sub-pixels SP. In addition, a gate driver, a data driver, etc. may be provided in the peripheral region 20.

[0054] In an exemplary embodiment, a conductive member (eg, Figure 5 The first extension portion of the conductive member 360 may be disposed in the first peripheral region 21, and as Figure 1 As shown in , the first contact hole 361 formed in the protective insulating layer and the planarization layer to be described below may be located on the conductive member. In other words, the first contact hole 361 may be positioned to correspond to the conductive member and may have a strip shape when viewed in a plan view. In addition, the length of the first contact hole 361 in the first direction D1 may be substantially equal to the length of the conductive member in the first direction D1. In other words, a portion of the top surface of the conductive member may be exposed through the first contact hole 361.

[0055] Refer again Figures 1 to 3 , the first pad electrode 471 may be disposed in the first pad region 61, and the second pad electrode 472 may be disposed in the second pad region 62. Only the first power circuit board 841 and the second power circuit board 941 may be electrically connected to the first pad electrode 471, and the first power circuit board 841, the second power circuit board 941, and the driving circuit board 900 may be electrically connected to the second pad electrode 472. In other words, the driving circuit board 900 may not be disposed in the first pad region 61, and the first pad electrode 471 and the driving circuit board 900 may not be in direct contact with each other. For example, the first power circuit board 841 and the second power circuit board 941 may be alternately arranged in the first pad region 61, and the second power circuit board 941, the first power circuit board 841, and the driving circuit board 900 may be alternately arranged in the second pad region 62.

[0056] The external device 101 may be electrically connected to the display device 100 through the first power circuit board 841, the second power circuit board 941, and the driving circuit board 900. For example, one side of each of the first power circuit board 841, the second power circuit board 941, and the driving circuit board 900 may be in direct contact with the first pad electrode 471 and the second pad electrode 472, and the opposite side of each of the first power circuit board 841, the second power circuit board 941, and the driving circuit board 900 may be in direct contact with the external device 101.

[0057] In addition, the external device 101 may generate a data signal, a gate signal, an emission control signal, a gate initialization signal, an initialization voltage, a first power, a second power, etc. In an exemplary embodiment, the data signal, the gate signal, the emission control signal, the gate initialization signal, and the initialization voltage generated from the external device 101 may be provided to the display device 100 through the driving circuit board 900. The first power generated from the external device 101 may be provided to the display device 100 through the first power circuit board 841, and the second power generated from the external device 101 may be provided to the display device 100 through the second power circuit board 941. For example, the voltage level of the first power (e.g., Figure 4 The low power voltage ELVSS) may be lower than the voltage level of the second power (eg, Figure 4 high power voltage ELVDD).

[0058] In addition, a driving integrated circuit may be mounted on each of the first power circuit board 841, the second power circuit board 941, and the driving circuit board 900. In other exemplary embodiments, the driving integrated circuit may be mounted on the display device 100 while being adjacent to the first pad electrode 471 and the second pad electrode 472, or each of the first power circuit board 841, the second power circuit board 941, and the driving circuit board 900 may not include a driving integrated circuit.

[0059] Figure 4 It shows that the setting Figure 1 Circuit diagram of a sub-pixel in a sub-pixel area.

[0060] Reference Figure 4 , the display device 100 may include sub-pixels SP correspondingly disposed in the sub-pixel region 30, and the sub-pixels SP may include an organic light emitting diode OLED (eg, Figure 6 sub-pixel structure 200), first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6 and TR7 (eg, Figure 6 semiconductor element 250), a storage capacitor CST, a high power voltage (ELVDD) line (eg, Figure 5 The second upper power line 740 and Fig. 9A second lower power line 950), a low power voltage (ELVSS) line (eg, Figure 5 The first on power line 640 and Fig.19 The first lower power line 840 of the embodiment of the present invention may include a first lower power line 840 of the embodiment of the present invention, an initialization voltage (VINT) line, a data signal (DATA) line, a gate signal (GW) line, a gate initialization signal (GI) line, an emission control signal (EM) line, a diode initialization signal (GB) line, etc. As described above, the first transistor TR1 may correspond to a driving transistor, and the second to seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7 may correspond to switching transistors. Each of the first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7 may include a first terminal, a second terminal, a channel, and a gate terminal. In an exemplary embodiment, the first terminal may be a source terminal, and the second terminal may be a drain terminal. In some embodiments, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

[0061] The organic light emitting diode OLED may output light based on the driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. In an exemplary embodiment, the second terminal of the organic light emitting diode OLED may receive a low power voltage ELVSS (e.g., a first power), and the first terminal of the organic light emitting diode OLED may receive a high power voltage ELVDD (e.g., a second power). For example, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. In some embodiments, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal. In an exemplary embodiment, the anode terminal of the organic light emitting diode OLED may be connected to Figure 6 The cathode terminal of the organic light emitting diode OLED may correspond to the lower electrode 290 of Figure 6 Corresponding to the upper electrode 340.

[0062] The first transistor TR1 may generate a driving current ID. In an exemplary embodiment, the first transistor TR1 may operate in a saturation region. In this case, the first transistor TR1 may generate a driving current ID based on a voltage difference between a gate terminal and a source terminal of the first transistor TR1. In addition, a grayscale may be represented based on the magnitude of the driving current ID supplied to the organic light emitting diode OLED. In some embodiments, the first transistor TR1 may operate in a linear region. In this case, a grayscale may be represented based on the sum of the time during which the driving current is supplied to the organic light emitting diode OLED in one frame.

[0063] The gate terminal of the second transistor TR2 may receive a gate signal GW. The first terminal of the second transistor TR2 may receive a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. For example, a gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the second transistor TR2 through a gate signal (GW) line. The second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the second transistor TR2 may operate in a linear region.

[0064] The gate terminal of the third transistor TR3 may receive a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the third transistor TR3 through a gate signal (GW) line. The third transistor TR3 may connect the gate terminal of the first transistor TR1 and the second terminal of the first transistor TR1 during the activation period of the gate signal GW.

[0065] An input terminal of the initialization voltage line to which the initialization voltage VINT is supplied may be connected to first terminals of the fourth transistor TR4 and the seventh transistor TR7 , and an output terminal of the initialization voltage line may be connected to the second terminal of the fourth transistor TR4 and the first terminal of the storage capacitor CST.

[0066] The gate terminal of the fourth transistor TR4 may receive the gate initialization signal GI. The first terminal of the fourth transistor TR4 may receive the initialization voltage VINT. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. The fourth transistor TR4 may supply the initialization voltage VINT to the gate terminal of the first transistor TR1 during the activation period of the gate initialization signal GI. In this case, the fourth transistor TR4 may operate in a linear region. In other words, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an exemplary embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1. In other exemplary embodiments, the initialization voltage may have a voltage level sufficiently higher than the voltage level of the data signal maintained by the storage capacitor in the previous frame, and the initialization voltage may be applied to the gate terminal of the first transistor. In an exemplary embodiment, the gate initialization signal GI may be substantially the same as the gate signal GW one horizontal time ago.

[0067] The gate terminal of the fifth transistor TR5 may receive an emission control signal EM. The first terminal of the fifth transistor TR5 may be connected to a high power voltage (ELVDD) line. The second terminal of the fifth transistor TR5 may be connected to a first terminal of the first transistor TR1. For example, an emission control signal EM may be provided from an emission control driver, and the emission control signal EM may be applied to the gate terminal of the fifth transistor TR5 through an emission control signal (EM) line. The fifth transistor TR5 may supply a high power voltage ELVDD to the first terminal of the first transistor TR1 during an activation period of the emission control signal EM. On the contrary, the fifth transistor TR5 may cut off the supply of the high power voltage ELVDD during a deactivation period of the emission control signal EM. In this case, the fifth transistor TR5 may operate in a linear region. Since the fifth transistor TR5 supplies the high power voltage ELVDD to the first terminal of the first transistor TR1 during an activation period of the emission control signal EM, the first transistor TR1 may generate a drive current ID. In addition, since the fifth transistor TR5 cuts off the supply of the high power voltage ELVDD during a deactivation period of the emission control signal EM, the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0068] The sixth transistor TR6 (eg, Figure 6The gate terminal of the semiconductor element 250 of the sixth transistor TR6 can receive the emission control signal EM. The first terminal of the sixth transistor TR6 can be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 can be connected to the first terminal of the organic light emitting diode OLED. The sixth transistor TR6 can supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the emission control signal EM. In this case, the sixth transistor TR6 can operate in a linear region. In other words, since the sixth transistor TR6 supplies the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the emission control signal EM, the organic light emitting diode OLED can output light. In addition, since the sixth transistor TR6 electrically separates the first transistor TR1 and the organic light emitting diode OLED from each other during the deactivation period of the emission control signal EM, the data signal DATA supplied to the second terminal of the first transistor TR1 (precisely, the data signal that has been threshold voltage compensated) can be supplied to the gate terminal of the first transistor TR1.

[0069] The gate terminal of the seventh transistor TR7 may receive the diode initialization signal GB. The first terminal of the seventh transistor TR7 may receive the initialization voltage VINT. The second terminal of the seventh transistor TR7 may be connected to the first terminal of the organic light emitting diode OLED. The seventh transistor TR7 may supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during the activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 may operate in a linear region. In other words, the seventh transistor TR7 may initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB. In some embodiments, the gate initialization signal GI and the diode initialization signal GB may be substantially the same signal.

[0070] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between a high power voltage (ELVDD) line and a gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power voltage (ELVDD) line. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the deactivation period of the gate signal GW. The deactivation period of the gate signal GW may include the activation period of the emission control signal EM, and the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED during the activation period of the emission control signal EM. Therefore, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED based on the voltage level maintained by the storage capacitor CST.

[0071] However, although the subpixel SP according to the present invention has been described as including seven transistors and one storage capacitor, the configuration of the present invention is not limited thereto. For example, the subpixel SP may have a configuration including at least one transistor and at least one storage capacitor.

[0072] Figure 5 It is shown Figure 1 A partial enlarged plan view of area A, Figure 6 It is along Figure 5 A cross-sectional view taken along line II' of Figure 7 It is along Figure 5 A cross-sectional view taken along line II-II', and Figure 8 It is along Figure 5 A cross-sectional view taken along line III-III'.

[0073] Reference Figure 5 , Figure 6 , Figure 7 and Figure 8, the display device 100 may further include a substrate 110, a buffer layer 115, a semiconductor element 250, a protective insulating layer 400, a first upper power line 640, a second upper power line 740, an upper inspection pad 660, a conductive member 360, a conductive pattern 510, a first connection pattern 365, a second connection pattern 645, a third connection pattern 235, a fourth connection pattern 655, a first sub-power line 650, a second sub-power line 750, a signal line 610, a sub-pixel structure 200, an upper connection member 295, a first electrode pattern 305, a pixel defining layer 310, a package substrate 450, etc. In this case, the semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a gate electrode 170, an interlayer insulating layer 190, a source electrode 210, and a drain electrode 230, and the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340.

[0074] A substrate 110 including a transparent or opaque material may be provided. The substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda-lime glass substrate, an alkali-free glass substrate, etc. In some embodiments, the substrate 110 may be configured as a transparent resin substrate having flexibility. In an exemplary embodiment, the substrate 110 may have a configuration in which a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are stacked in sequence. The first barrier layer and the second barrier layer may include an inorganic material such as silicon oxide, and may block water and / or moisture from penetrating through the first organic layer and the second organic layer. In addition, the first organic layer and the second organic layer may include an organic material having flexibility, such as a polyimide resin.

[0075] Since the display device 100 includes a display area 10 in which a plurality of sub-pixel areas 30 are arranged, a peripheral area 20 including a first peripheral area 21 and a second peripheral area 22, a first pad area 61 and a second pad area 62, Figure 6 , Figure 7 and Figure 8 As shown in FIG. 1 , the substrate 110 may also be divided into a display area 10 in which a plurality of sub-pixel areas 30 are arranged, a peripheral area 20 including a first peripheral area 21 and a second peripheral area 22, a first pad area 61 and a second pad area 62 (see FIG. 1 ). Figure 1 ).

[0076] The buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may be disposed on the substrate 110 throughout the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62. For example, the buffer layer 115 may prevent metal atoms or impurities from diffusing from the substrate 110 to the semiconductor element 250, and may control the heat transfer rate during the crystallization process for forming the active layer 130 to obtain a substantially uniform active layer 130. In addition, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be disposed on the substrate 110, or no buffer layer 115 may be disposed. The buffer layer 115 may include a silicon compound, a metal oxide, or the like. The buffer layer 115 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbonitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x )、ZrO x ), titanium oxide (TiO x )wait.

[0077] The active layer 130 may be disposed in the sub-pixel region 30 on the buffer layer 115. The active layer 130 may include a metal oxide semiconductor, an inorganic semiconductor (eg, amorphous silicon or polycrystalline silicon), an organic semiconductor, etc. The active layer 130 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0078] The gate insulating layer 150 may be disposed on the active layer 130. The gate insulating layer 150 may be disposed on the buffer layer 115 in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62. For example, the gate insulating layer 150 may fully cover the active layer 130 on the buffer layer 115, and may have a substantially flat top surface without generating steps around the active layer 130. In some embodiments, the gate insulating layer 150 may be disposed on the buffer layer 115 along the contour of the active layer 130 with a uniform thickness to cover the active layer 130. The gate insulating layer 150 may include a silicon compound, a metal oxide, and the like. In other exemplary embodiments, the gate insulating layer 150 may have a multilayer structure having a plurality of insulating layers including mutually different materials, and the insulating layers may have mutually different thicknesses.

[0079] The gate electrode 170 may be disposed in the sub-pixel region 30 on the gate insulating layer 150. The gate electrode 170 may be disposed on a portion of the gate insulating layer 150 where the active layer 130 is positioned below (e.g., to overlap with the channel region of the active layer 130). The gate electrode 170 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, the gate electrode 170 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0080] The second upper power line 740 may be disposed in the first pad region 61 and the first peripheral region 21 on the gate insulating layer 150. In an exemplary embodiment, the second upper power line 740 may be located at a level lower than that of the first upper power line 640 and the conductive member 360, and may be electrically connected to the first pad electrode 471 disposed thereon. Figure 2 The second upper power line 740 may include a first line extension portion 741, a second line extension portion 742, and a third line extension portion 743. For example, the first line extension portion 741 may be located in the first peripheral region 21 and may extend in the first direction D1. In other words, the first line extension portion 741 may overlap the first peripheral region 21. The second line extension portion 742 may extend from one side of the first line extension portion 741 in a third direction D3 to be located in the first pad region 61, and the third direction D3 is a direction from the first peripheral region 21 to the first pad region 61 (for example, a direction opposite to the second direction D2). In other words, the second line extension portion 742 may protrude from one side of the first line extension portion 741 in the third direction D3, and may extend in the third direction D3 to be electrically connected to the second power circuit board 941 through the first pad electrode 471. The third wire extension 743 may extend from the opposite side of the first wire extension 741 in the second direction D2, which is a direction from the first peripheral area 21 to the display area 10, and may intersect the conductive member 360. In other words, the third wire extension 743 may protrude from the opposite side of the first wire extension 741 in the second direction D2, and may be located below the conductive member 360. In addition, the first wire extension 741, the second wire extension 742, and the third wire extension 743 may be formed integrally with each other.

[0081] The second power (eg, Figure 4The high power voltage ELVDD) can be provided to the second upper power line 740. The second power can be provided to the lower electrode 290 through the second upper power line 740 and the second sub-power line 750. The second sub-power line 750 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In some embodiments, the second upper power line 740 may have a multi-layer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0082] However, although one third line extension portion 743 has been described as protruding from the first line extension portion 741 in the second direction D2 for convenience, Figure 5 As shown in FIG. 1 , the second upper power line 740 may include one first line extension 741 and a plurality of third line extensions 743. In addition, each of the third line extensions 743 may be electrically connected to the second sub power line 750 in the first peripheral region 21, and the second sub power line 750 may extend in the second direction D2 and may be disposed in the sub-pixel region 30.

[0083] The conductive pattern 510 may be disposed in the first peripheral region 21 on the gate insulating layer 150 in parallel with the third line extension 743. In other words, the conductive pattern 510 may be disposed below the conductive member 360 and may intersect with the conductive member 360. The conductive pattern 510 may electrically connect the upper inspection pad 660 and the signal line 610 through the contact holes 511 and 512. The conductive pattern 510 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, the conductive pattern 510 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses. In an exemplary embodiment, the gate electrode 170, the conductive pattern 510, and the second upper power line 740 may be located at the same layer.

[0084] The interlayer insulating layer 190 may be disposed on the gate electrode 170, the conductive pattern 510, and the second upper power line 740. The interlayer insulating layer 190 may be disposed in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62 on the gate insulating layer 150. In an exemplary embodiment, the interlayer insulating layer 190 may include: a contact hole 511 exposing one side of the conductive pattern 510; a contact hole 512 exposing the opposite side of the conductive pattern 510; and a contact hole 751 exposing a portion of the third line extension 743 adjacent to the display region 10. For example, the interlayer insulating layer 190 may fully cover the gate electrode 170, the conductive pattern 510, and the second upper power line 740 on the gate insulating layer 150, and may have a substantially flat top surface without generating steps around the gate electrode 170 and the second upper power line 740. In some embodiments, the interlayer insulating layer 190 may be disposed on the gate insulating layer 150 along the contours of the gate electrode 170, the conductive pattern 510, and the second upper power line 740 with a uniform thickness to cover the gate electrode 170, the conductive pattern 510, and the second upper power line 740. The interlayer insulating layer 190 may include a silicon compound, a metal oxide, etc. In other exemplary embodiments, the interlayer insulating layer 190 may have a multilayer structure having a plurality of insulating layers including mutually different materials, and the insulating layers may have mutually different thicknesses.

[0085] The source electrode 210 and the drain electrode 230 may be disposed in the sub-pixel region 30 on the interlayer insulating layer 190. The source electrode 210 may be connected to the source region of the active layer 130 via a contact hole formed by removing the first portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the drain electrode 230 may be connected to the drain region of the active layer 130 via a contact hole formed by removing the second portion of the gate insulating layer 150 and the interlayer insulating layer 190. Each of the source electrode 210 and the drain electrode 230 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0086] Thus, the semiconductor element 250 including the active layer 130 , the gate insulating layer 150 , the gate electrode 170 , the interlayer insulating layer 190 , the source electrode 210 , and the drain electrode 230 may be provided.

[0087] However, although the semiconductor element 250 has been described as having a top gate structure, the configuration of the present invention is not limited thereto. For example, the semiconductor element 250 may have a bottom gate structure.

[0088] In addition, although the display device 100 has been described as including one semiconductor element, the configuration of the present invention is not limited thereto. For example, the display device 100 may include at least one semiconductor element and at least one storage capacitor.

[0089] The conductive member 360 may be disposed in the first peripheral region 21 and the display region 10 on the interlayer insulating layer 190. For example, the conductive member 360 may include a first extension and a second extension. In this case, the first extension may extend in the first direction D1 in the first peripheral region 21 and may be positioned in parallel with the first line extension 741. For example, the first line extension 741 may be positioned near the first pad region 61 in the first peripheral region 21, and the first extension may be positioned near the display region 10 in the first peripheral region 21. As described above, the first contact hole 361 may be located on the first extension of the conductive member 360, and the first contact hole 361 may be positioned to correspond to the first extension. In other words, the first contact hole 361 may extend in the first direction D1 and may expose a portion of the top surface of the first extension. The second extension may extend from one side of the first extension in the second direction D2 and may be located in a portion of the first peripheral region 21 and the display region 10. In addition, the second extension may be disposed in the sub-pixel region 30, and the third contact hole 651 may be located on the second extension in the sub-pixel region 30. The second extension portion may be defined as a first sub power line 650. The first extension portion and the second extension portion may be formed integrally with each other.

[0090] In an exemplary embodiment, the conductive member 360 may receive the first power (eg, Figure 4 The first power can be supplied to the upper electrode 340 through the first sub-power line 650. The conductive member 360 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the conductive member 360 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN), etc. x ), silver-containing alloys, tungsten nitride (WN x ), copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiN x ), chromium nitride (CrN x ), Tantalum Nitride (TaN x ), strontium ruthenium oxide (SrRu x O y), zinc oxide (ZnO x )、Indium Tin Oxide (ITO), Tin Oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In some embodiments, the conductive member 360 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0091] However, although for convenience, one second extension portion has been described as extending from the first extension portion in the second direction D2 in the display area 10, Figure 5 As shown in , the conductive member 360 may include one first extension portion and a plurality of second extension portions. In addition, each of the second extension portions may be disposed in the sub-pixel region 30.

[0092] The upper inspection pad 660 may be disposed on the interlayer insulating layer 190 in the first peripheral region 21 to overlap with the first line extension 741 of the second upper power line 740. The upper inspection pad 660 may be located at the same layer as the first upper power line 640 and the conductive member 360, and may be arranged in the first peripheral region 21 in the first direction D1. Each of the upper inspection pads 660 may also include an extension extending in the second direction D2, wherein one side of the extension may be connected to the upper inspection pad 660, and the opposite side of the extension may be adjacent to the conductive member 360. The opposite side of the extension may be electrically connected to the signal line 610 through the conductive pattern 510. For example, the upper inspection pad 660 may be used as an OS pad configured to check the disconnection state and short circuit of the data line (e.g., the signal line 610). In some embodiments, for accurate inspection, an opening may be formed in the second upper power line 740 located below each upper inspection pad 660. Each of the upper inspection pads 660 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other exemplary embodiments, each of the upper inspection pads 660 may have a multi-layer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0093] The first upper power line 640 may be disposed in the first pad region 61 on the interlayer insulating layer 190. In an exemplary embodiment, the first upper power line 640 may be located at a level higher than that of the second upper power line 740 and may be electrically connected to the first pad region 61 disposed on the interlayer insulating layer 190. Figure 247. In other words, one side of the first upper power line 640 may be electrically connected to the first power circuit board 841 in the first pad region 61. In other words, one side of the first upper power line 640 may be electrically connected to the first power circuit board 841 through the first pad electrode 471, and the opposite side of the first upper power line 640 may be electrically connected to the upper connection member 295. In this case, the second contact hole 641 may be located on the opposite side of the first upper power line 640 so that the opposite side of the first upper power line 640 may be electrically connected to the upper connection member 295, and the second contact hole 641 may expose a portion of the top surface of the first upper power line 640. In addition, the first upper power line 640 may be disposed in parallel with the second line extension 742.

[0094] The first power (eg, Figure 4 The low power voltage ELVSS) can be provided to the first upper power line 640. The first power can be provided to the upper electrode 340 through the first upper power line 640, the upper connection member 295, the conductive member 360 and the first sub-power line 650. The first upper power line 640 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In some embodiments, the first upper power line 640 may have a multi-layer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0095] The signal line 610 may be disposed in a portion of the first peripheral region 21 and the display region 10 on the interlayer insulating layer 190 , and may extend in the second direction D2 . Figure 5 The data signal DATA may be applied to the signal line 610, and the signal line 610 may correspond to Figure 5 In other words, the signal line 610 may be electrically connected to the semiconductor element 250 and another semiconductor element (eg, Figure 4 The signal line 610 may include a second transistor TR2 of the semiconductor element, and may provide a data signal DATA to the semiconductor element. The signal line 610 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, the signal line 610 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0096] The second sub power line 750 may be disposed in a portion of the first peripheral region 21 and the display region 10 in parallel with the signal line 610 on the interlayer insulating layer 190, and may extend in the second direction D2. The second sub power line 750 may be electrically connected to the second upper power line 740 through the contact hole 751 in the first peripheral region 21, and the second power may be applied to the second sub power line 750. For example, the second sub power line 750 may be connected to the second upper power line 740 through the contact hole 751. Figure 4 In other words, in another cross-sectional view of the display device 100, the second sub-power line 750 may be electrically connected to the lower electrode 290 disposed in the sub-pixel region 30, and may provide the lower electrode 290 with a second power (eg, Figure 4 The second sub power line 750 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, the second sub power line 750 may have a multi-layer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0097] The first sub-power line 650 may be disposed in a portion of the first peripheral region 21 and the display region 10 on the interlayer insulating layer 190 in parallel with the signal line 610 and the second sub-power line 750, and may extend in the second direction D2. As described above, the first sub-power line 650 may extend from the first extension portion of the conductive member 360 in the first peripheral region 21, and the first power may be applied to the first sub-power line 650. For example, the first sub-power line 650 may correspond to Figure 4 The low power voltage (ELVSS) line. Figure 6 As shown in FIG. 6 , the first sub-power line 650 may be electrically connected to the upper electrode 340 through the third contact hole 651, and the first power (eg, Figure 4 A low power voltage ELVSS) is applied to the upper electrode 340. In an exemplary embodiment, the conductive member 360, the first upper power line 640, the upper inspection pad 660, the signal line 610, the second sub power line 750, and the first sub power line 650 may be located at the same layer.

[0098] The protective insulating layer 400 may be disposed in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62 on the source electrode 210 and the drain electrode 230, the signal line 610, the second sub power line 750, the first sub power line 650, the conductive member 360, the upper inspection pad 660, and the first upper power line 640. In an exemplary embodiment, the protective insulating layer 400 may include a contact hole exposing a portion of a top surface of the drain electrode 230, a contact hole exposing a portion of a top surface of the first sub power line 650, a contact hole exposing a portion of a top surface of the conductive member 360, a contact hole exposing a portion of a top surface of the first upper power line 640, and the like.

[0099] The protective insulating layer 400 can fully cover the source electrode 210 and the drain electrode 230, the signal line 610, the second sub-power line 750, the first sub-power line 650, the conductive member 360, the upper inspection pad 660 and the first upper power line 640 on the interlayer insulating layer 190, and can have a substantially flat top surface without generating steps around the source electrode 210 and the drain electrode 230, the signal line 610, the second sub-power line 750, the first sub-power line 650, the conductive member 360, the upper inspection pad 660 and the first upper power line 640. In some embodiments, the protective insulating layer 400 may be disposed on the interlayer insulating layer 190 along the contours of the source electrode 210 and the drain electrode 230, the signal line 610, the second sub-power line 750, the first sub-power line 650, the conductive member 360, the upper inspection pad 660, and the first upper power line 640 with a substantially uniform thickness to cover the source electrode 210 and the drain electrode 230, the signal line 610, the second sub-power line 750, the first sub-power line 650, the conductive member 360, the upper inspection pad 660, and the first upper power line 640. The protective insulating layer 400 may include a silicon compound, a metal oxide, etc. In other exemplary embodiments, the protective insulating layer 400 may have a multilayer structure having a plurality of insulating layers including mutually different materials, and the insulating layers may have mutually different thicknesses.

[0100] The first connection pattern 365 may be disposed in the contact hole exposing a portion of the top surface of the conductive member 360, the second connection pattern 645 may be disposed in the contact hole exposing a portion of the top surface of the first upper power line 640, the third connection pattern 235 may be disposed in the contact hole exposing a portion of the top surface of the drain electrode 230, and the fourth connection pattern 655 may be disposed in the contact hole exposing a portion of the top surface of the first sub power line 650. In other words, at least a portion of each of the first to fourth connection patterns 365, 645, 235, and 655 may be interposed between the protective insulating layer 400 and the planarization layer 270. The first connection pattern 365 may completely cover the conductive member 360 exposed by the contact hole, the second connection pattern 645 may completely cover the first upper power line 640 exposed by the contact hole, the third connection pattern 235 may completely cover the drain electrode 230 exposed by the contact hole, and the fourth connection pattern 655 may completely cover the first sub power line 650 exposed by the contact hole. For example, in the method of manufacturing the display device 100, the conductive member 360, the first sub-power line 650, the first upper power line 640, and the drain electrode 230 may be formed by using copper, and each of the first to fourth connection patterns 365, 645, 235, and 655 may be formed by using indium tin oxide. After the planarization layer 270 is formed on the protective insulating layer 400, an etching process for forming a contact hole of the planarization layer 270 overlapping the contact hole formed in the protective insulating layer 400 may be performed. The first to fourth connection patterns 365, 645, 235, and 655 may be provided to protect the conductive member 360, the first sub-power line 650, the first upper power line 640, and the drain electrode 230 while performing the etching process. In some embodiments, each of the first to fourth connection patterns 365, 645, 235, and 655 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, each of the first to fourth connection patterns 365 , 645 , 235 , and 655 may have a multi-layer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0101] The planarization layer 270 may be disposed on the first to fourth connection patterns 365, 645, 235, and 655. The planarization layer 270 may be disposed in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62 on the protective insulating layer 400. The planarization layer 270 may have a contact hole overlapping with a contact hole of the protective insulating layer 400 that exposes a portion of the top surface of the conductive member 360, and the contact hole may be defined as a first contact hole 361. In addition, the planarization layer 270 may have a contact hole overlapping with a contact hole of the protective insulating layer 400 that exposes a portion of the top surface of the first upper power line 640, and the contact hole may be defined as a second contact hole 641. In addition, the planarization layer 270 may have a contact hole overlapping with a contact hole of the protective insulating layer 400 that exposes a portion of the top surface of the first sub power line 650, and the contact hole may be defined as a third contact hole 651. In addition, the planarization layer 270 may have a contact hole overlapping with the contact hole of the protective insulating layer 400 exposing a portion of the top surface of the drain electrode 230 , and the lower electrode 290 may be electrically connected to the semiconductor element 250 through the contact hole.

[0102] For example, the planarization layer 270 may have a relatively thick thickness. In this case, the planarization layer 270 may have a substantially flat top surface. In order to achieve such a flat top surface of the planarization layer 270, a planarization process may be additionally performed on the planarization layer 270. In some embodiments, the planarization layer 270 may be provided with a uniform thickness along the contours of the first connection pattern to the fourth connection pattern 365, 645, 235 and 655 on the protective insulating layer 400. The planarization layer 270 may be formed of an organic material or an inorganic material. In an exemplary embodiment, the planarization layer 270 may include an organic material. For example, the planarization layer 270 may include a photoresist, a polyacryl resin, a polyimide resin, a polyamide resin, a siloxane resin, an acryl resin, an epoxy resin, etc.

[0103] The lower electrode 290 may be disposed in the sub-pixel region 30 on the planarization layer 270. The lower electrode 290 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, the lower electrode 290 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0104] The upper connection member 295 may be disposed in the first peripheral region 21 and the first pad region 61 on the planarization layer 270. The upper connection member 295 may extend in the first direction D1 in the first peripheral region 21, and may overlap with a portion of the first upper power line 640 and the conductive member 360. The upper connection member 295 may electrically connect the conductive member 360 and the first upper power line 640 through the first contact hole 361 and the second contact hole 641. In other words, the first power applied to the first upper power line 640 may be provided to the conductive member 360 through the upper connection member 295. The upper connection member 295 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the upper connection member 295 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0105] The first electrode pattern 305 may be disposed in the third contact hole 651. The first electrode pattern 305 may be disposed between the upper electrode 340 and the fourth connection pattern 655, and may completely cover the fourth connection pattern 655 exposed by the third contact hole 651. For example, in the method of manufacturing the display device 100, after forming the light emitting layer 330, a laser drilling process for removing the light emitting layer 330 formed on the first electrode pattern 305 to overlap with the third contact hole 651 may be performed. The light emitting layer 330 formed on the first electrode pattern 305 may be removed by the laser drilling process. While performing the laser drilling process, the first electrode pattern 305 may protect the fourth connection pattern 655. The first electrode pattern 305 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, the first electrode pattern 305 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0106] The pixel defining layer 310 may be disposed on the planarization layer 270 in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62. The pixel defining layer 310 may cover both side portions of the lower electrode 290 and may expose a portion of the top surface of the lower electrode 290. In addition, the pixel defining layer 310 may cover both side portions of the first electrode pattern 305 and may expose a portion of the top surface of the first electrode pattern 305. In addition, the pixel defining layer 310 may cover the upper connection member 295 in the first peripheral region 21 and the first pad region 61. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer 310 may include an organic material.

[0107] The light emitting layer 330 may be disposed in the display region 10 on a portion of the first electrode pattern 305, the pixel defining layer 310, and the lower electrode 290. As described above, the light emitting layer 330 may expose a portion of the top surface of the first electrode pattern 305 by a laser drilling process. In other words, the light emitting layer 330 may not be disposed in a portion in which the third contact hole 651 is formed. The light emitting layer 330 may have a multilayer structure including an organic light emitting layer (EML), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), and the like. The organic light emitting layer (EML) of the light emitting layer 330 may be formed by using at least one of light emitting materials for emitting different colors of light (i.e., red light, green light, blue light, etc.) according to sub-pixels. Alternatively, the organic light emitting layer (EML) of the light emitting layer 330 may be formed by stacking a plurality of light emitting materials for generating different colors of light (such as red light, green light, and blue light) to emit white light as a whole. In this case, a color filter may be disposed on the light emitting layer 330, and the light emitting layer 330 is disposed on the lower electrode 290. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. In some embodiments, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin or a color photoresist.

[0108] The upper electrode 340 may be disposed in the display region 10 on the substrate 110. For example, the upper electrode 340 may be disposed on the light emitting layer 330 in the display region 10, and may be in direct contact with the first electrode pattern 305 exposed by the light emitting layer 330. In other words, the upper electrode 340 may be disposed along the contours of the light emitting layer 330 and the first electrode pattern 305. As described above, the first power applied to the first upper power line 640 may be transmitted to the upper electrode 340 through the second connection pattern 645, the upper connection member 295, the first connection pattern 365, the conductive member 360, the first sub-power line 650, the fourth connection pattern 655, and the first electrode pattern 305. The upper electrode 340 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other exemplary embodiments, the upper electrode 340 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0109] Thus, a sub-pixel structure 200 including a lower electrode 290 , a light emitting layer 330 , and an upper electrode 340 may be provided.

[0110] The encapsulation substrate 450 may be disposed in the display area 10 on the upper electrode 340. The encapsulation substrate 450 may face the substrate 110 and may not be disposed in the first pad area 61 and the second pad area 62. The encapsulation substrate 450 may include a material substantially the same as that of the substrate 110. For example, the encapsulation substrate 450 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like. In other exemplary embodiments, the encapsulation substrate 450 may include a transparent inorganic material or a flexible plastic. For example, the encapsulation substrate 450 may include a transparent resin substrate having flexibility. In this case, in order to improve the flexibility of the display device 100, the encapsulation substrate 450 may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. The stacked structure may include a first inorganic layer, an organic layer, and a second inorganic layer.

[0111] For example, a conventional display device may have a large size and a high resolution. When the display device is driven at high brightness, the current is concentrated in the first upper power line 640 disposed in the first peripheral region 21 and the first pad region 61, so that the temperature rises (e.g., a heating phenomenon). In this case, the heating phenomenon may cause a short circuit of the first upper power line 640 or a deformation of the insulating layer located around the first upper power line 640. In addition, as the display area 10 becomes wider, a voltage drop (IR drop) phenomenon may occur. In addition, defects of the conventional display device may be caused by the heating phenomenon of the first upper power line 640 occurring in the first peripheral region 21 and the voltage drop phenomenon occurring in the display area 10.

[0112] In an exemplary embodiment, since the display device 100 includes the conductive member 360 and the first contact hole 361 formed on the conductive member 360 has a relatively wide area, the contact area between the upper connection member 295 and the conductive member 360 can be relatively increased. In addition, since the upper electrode 340 is electrically connected to the first upper power line 640 through the third contact hole 651, the upper electrode 340 can receive the first power. Therefore, according to the display device 100, both the heating phenomenon and the voltage drop phenomenon can be reduced.

[0113] Fig. 9 It is shown Figure 1 A partial enlarged plan view of area B, Fig.10 It is along Fig. 9 A cross-sectional view taken along line IV-IV' of Fig.11 It is along Fig. 9 A cross-sectional view taken along line V-V' of Fig.12 It is along Fig. 9 A cross-sectional view taken along line VI-VI'.

[0114] Reference Fig. 9 , Fig.10 , Fig.11 and Fig.12 The display device 100 may further include a fan-out line 420, a first lower power line 840, a second lower power line 950, a lower inspection pad 760, a fifth connection pattern 385, a sixth connection pattern 845, a seventh connection pattern 665, a sub-pixel structure 200, a lower connection member 395, a second electrode pattern 315, and the like.

[0115] Although for ease of description, it has been assumed Fig.10 The sub-pixel structure 200 has Figure 6 The sub-pixel structure 200 has the same reference numerals as the reference numerals, but Fig.10 The sub-pixel structure 200 and Figure 6 The sub-pixel structures 200 may be different from each other. In other words, Fig.10 The sub-pixel structure 200 may be a sub-pixel structure disposed in the display area 10 and adjacent to the second peripheral area 22, and Figure 6 The sub-pixel structure 200 may be a sub-pixel structure disposed in the display region 10 and adjacent to the first peripheral region 21. However, Fig.10 The light emitting layer 330 and the upper electrode 340 shown in FIG. Figure 6 The light emitting layer 330 and the upper electrode 340 shown in FIG. 5 are the same.

[0116] The fan-out line 420 may be disposed in the second pad region 62 and the second peripheral region 22 on the gate insulating layer 150. In an exemplary embodiment, the fan-out line 420 may be located between the substrate 110 and the first lower power line 840 and the second lower power line 950. One side of the fan-out line 420 may be provided by Figure 2 The second pad electrode 472 is electrically connected to the driving circuit board 900 , and the opposite side of the fan-out line 420 may be electrically connected to the lower inspection pad 760 . Figure 4 The data signal DATA can be provided from the driving circuit board 900 to the fan-out line 420. The data signal DATA can be provided to the fan-out line 420 through the lower inspection pad 760 and the signal line 610. Figure 4 The second transistor TR2. The fan-out line 420 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In some embodiments, the fan-out line 420 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses. In an exemplary embodiment, the fan-out line 420 may be located at the same layer as the gate electrode 170 and the second upper power line 740.

[0117] The first lower power line 840 may be disposed in the second pad region 62 on the interlayer insulating layer 190. In an exemplary embodiment, the first lower power line 840 may be located at a level higher than that of the fan-out line 420 and may be electrically connected to the first lower power line 840 disposed on the second pad region 62. Figure 2 The first power circuit board 841 in the second pad region 62 of the first lower power line 840 may be electrically connected to the first power circuit board 841 in the second pad region 62 of the first lower power line 840. In other words, one side of the first lower power line 840 may extend in the second direction D2 to be electrically connected to the first power circuit board 841 through the second pad electrode 472, and the opposite side of the first lower power line 840 may be electrically connected to the lower connection member 395. In this case, the fifth contact hole 842 may be located on the opposite side of the first lower power line 840 so that the opposite side of the first lower power line 840 may be electrically connected to the lower connection member 395, and the fifth contact hole 842 may expose a portion of the top surface of the first lower power line 840.

[0118] The first power (eg, Figure 4 The low power voltage ELVSS) can be provided to the first lower power line 840. The first power can be provided to the upper electrode 340 through the first lower power line 840, the lower connection member 395 and the first sub-power line 650. The first lower power line 840 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In some embodiments, the first lower power line 840 may have a multi-layer structure including a plurality of metal layers formed of different materials from each other, and the metal layers may have different thicknesses from each other.

[0119] The second lower power line 950 may be disposed in the second pad region 62 on the interlayer insulating layer 190. In an exemplary embodiment, the second lower power line 950 may be located at a level higher than that of the fan-out line 420 and may be located at the same layer as the first lower power line 840. In addition, the second lower power line 950 may be electrically connected to the first lower power line 840 disposed on the second pad region 62 through the second pad electrode 472. Figure 2 The second power circuit board 941 in the second pad area 62 of the second lower power line 950. In addition, the second lower power line 950 may include a first line extension portion 951 and a second line extension portion 952. For example, the first line extension portion 951 may be located in the second peripheral area 22 and may extend in the first direction D1. In other words, the first line extension portion 951 may overlap the second peripheral area 22. The second line extension portion 952 may extend from one side of the first line extension portion 951 in the second direction D2 to be located in the second pad area 62. In other words, the second line extension portion 952 may protrude from the first and second portions of the first line extension portion 951 in the second direction D2, and may extend in the second direction D2 to be electrically connected to the second power circuit board 941 through the second pad electrode 472.

[0120] The second power (eg, Figure 4 A high power voltage ELVDD) may be provided to the second lower power line 950. The second power may be provided to the lower electrode 290 through the second lower power line 950 and the second sub-power line 750. The second lower power line 950 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In some embodiments, the second lower power line 950 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0121] The lower inspection pad 760 may be disposed in the second peripheral region 22 on the interlayer insulating layer 190 while being spaced apart from the second lower power line 950. For example, the second lower power line 950 may be positioned close to the second pad region 62 in the second peripheral region 22, and the lower inspection pad 760 may be positioned close to the display region 10 in the second peripheral region 22. The lower inspection pad 760 may be located at the same layer as the first lower power line 840 and the second lower power line 950, and may be arranged in the second peripheral region 22 in the first direction D1. Each of the lower inspection pads 760 may also include an extension extending in the third direction D3, and the extension may correspond to the signal line 610. In an exemplary embodiment, the interlayer insulating layer 190 may cover the fan-out line 420, and may have a contact hole 761 exposing a portion of the fan-out line 420 in the second peripheral region 22. Each of the lower inspection pads 760 may be electrically connected to the fan-out line 420 through the contact hole 761. For example, the lower inspection pad 760 may be used as an OS pad configured to inspect the disconnection state and short circuit of a data line (e.g., signal line 610). Each of the lower inspection pads 760 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, each lower inspection pad 760 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0122] In an exemplary embodiment, the protective insulating layer 400 may include a contact hole exposing a first portion of the top surface of the first sub-power line 650, a contact hole exposing a portion of the top surface of the first lower power line 840, a contact hole exposing a second portion of the top surface of the first sub-power line 650, and the like.

[0123] The fifth connection pattern 385 may be disposed in the contact hole exposing the first portion of the top surface of the first sub power line 650, the sixth connection pattern 845 may be disposed in the contact hole exposing a portion of the top surface of the first lower power line 840, and the seventh connection pattern 665 may be disposed in the contact hole exposing the second portion of the top surface of the first sub power line 650. In other words, at least a portion of each of the fifth to seventh connection patterns 385, 845, and 665 may be interposed between the protective insulating layer 400 and the planarization layer 270. The fifth connection pattern 385 may completely cover the first portion of the first sub power line 650 exposed by the contact hole, the sixth connection pattern 845 may completely cover the first lower power line 840 exposed by the contact hole, and the seventh connection pattern 665 may completely cover the second portion of the first sub power line 650 exposed by the contact hole. For example, in the method of manufacturing the display device 100, the first sub power line 650 and the first lower power line 840 may be formed by using copper, and each of the fifth to seventh connection patterns 385, 845, and 665 may be formed by using indium tin oxide. After the planarization layer 270 is formed on the protective insulating layer 400, an etching process for forming a contact hole of the planarization layer 270 overlapping the contact hole formed in the protective insulating layer 400 may be performed. The fifth to seventh connection patterns 385, 845, and 665 may be provided to protect the first sub power line 650 and the first lower power line 840 while performing the etching process. In some embodiments, each of the fifth to seventh connection patterns 385, 845, and 665 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, each of the fifth to seventh connecting patterns 385 , 845 , and 665 may have a multi-layer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0124] In an exemplary embodiment, the planarization layer 270 may have a contact hole overlapping with the contact hole of the protective insulation layer 400 exposing the first portion of the top surface of the first sub power line 650, and the contact hole may be defined as the fourth contact hole 391. In addition, the planarization layer 270 may have a contact hole overlapping with the contact hole of the protective insulation layer 400 exposing a portion of the top surface of the first lower power line 840, and the contact hole may be defined as the fifth contact hole 842. In addition, the planarization layer 270 may have a contact hole overlapping with the contact hole of the protective insulation layer 400 exposing the second portion of the top surface of the first sub power line 650, and the contact hole may be defined as the sixth contact hole 652.

[0125] The lower connection member 395 may be disposed in the second peripheral region 22 and the second pad region 62 on the planarization layer 270. The lower connection member 395 may extend in the first direction D1 in the second peripheral region 22, and may overlap a portion of the first lower power line 840 and the first sub-power line 650. The lower connection member 395 may electrically connect the first sub-power line 650 and the first lower power line 840 through the fourth contact hole 391 and the fifth contact hole 842. In other words, the first power applied to the first lower power line 840 may be provided to the first sub-power line 650 through the lower connection member 395. In some embodiments, a conductive member (such as Figure 5 The conductive member 360 of the lower connection member 395 may be formed in the second peripheral region 22. For example, the conductive member may overlap with one side of the lower connection member 395 adjacent to the boundary between the second peripheral region 22 and the display region 10, and may be disposed at the same layer as the gate electrode 170. The lower connection member 395 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In some embodiments, the lower connection member 395 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0126] The second electrode pattern 315 may be disposed in the sixth contact hole 652. The second electrode pattern 315 may be disposed between the upper electrode 340 and the seventh connection pattern 665, and may completely cover the seventh connection pattern 665 exposed by the sixth contact hole 652. For example, in the method of manufacturing the display device 100, after forming the light emitting layer 330, a laser drilling process for removing the light emitting layer 330 formed on the second electrode pattern 315 to overlap with the sixth contact hole 652 may be performed. The light emitting layer 330 formed on the second electrode pattern 315 may be removed by the laser drilling process. While performing the laser drilling process, the second electrode pattern 315 may protect the seventh connection pattern 665. The second electrode pattern 315 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other exemplary embodiments, the second electrode pattern 315 may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

[0127] As mentioned above, it is possible to provide Figures 1 to 12 The display device 100 shown in FIG.

[0128] Since the display device 100 according to the exemplary embodiment of the present invention includes the conductive member 360, and the first contact hole 361 formed on the conductive member 360 has a relatively wide area, the heating phenomenon that may occur in the first peripheral region 21 can be reduced. In addition, since the display device 100 includes the third contact hole 651, and the upper electrode 340 receives the first power from the first sub-power line 650 in each sub-pixel region 30, the voltage drop phenomenon that may occur in the display region 10 can be reduced. Therefore, according to the display device 100, both the heating phenomenon that may occur in the first peripheral region 21 and the voltage drop phenomenon that may occur in the display region 10 can be reduced.

[0129] However, although the display device 100 according to the present invention has been specifically described as an organic light emitting diode display device, the configuration of the present invention is not limited thereto. In other exemplary embodiments, the display device 100 may include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), or an electrophoretic image display device (EPD).

[0130] Figures 13 to 26 is a view showing a method of manufacturing a display device according to an exemplary embodiment of the present invention. For example, Fig.13 , Fig.14 , Fig.18 and Fig.19 is a plan view showing a method of manufacturing a display device, Figures 15 to 17 and Figure 20 to Figure 26 is a cross-sectional view illustrating a method of manufacturing a display device.

[0131] Reference Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 ,like Fig.15 , Fig.16 and Fig.17 As shown in , a substrate 110 including a transparent or opaque material may be provided. The substrate 110 may be formed by using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. The substrate 110 may include a display area 10 in which a plurality of sub-pixel areas 30 are arranged, a peripheral area 20 including a first peripheral area 21 and a second peripheral area 22, a first pad area 61 and a second pad area 62 (see Figure 1 ).

[0132] like Fig.15 , Fig.16 and Fig.17As shown in , a buffer layer 115 may be formed on the substrate 110. The buffer layer 115 may be formed on the substrate 110 throughout the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62. Depending on the type of the substrate 110, at least two buffer layers 115 may be provided on the substrate 110, or the buffer layer 115 may not be formed. The buffer layer 115 may be formed by using a silicon compound, a metal oxide, or the like. The buffer layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like.

[0133] like Fig.15 As shown in FIG, an active layer 130 may be formed in the sub-pixel region 30 on the buffer layer 115. The active layer 130 may be formed by using a metal oxide semiconductor, an inorganic semiconductor, an organic semiconductor, etc. The active layer 130 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0134] like Fig.15 , Fig.16 and Fig.17 As shown in , a gate insulating layer 150 may be formed on the active layer 130. The gate insulating layer 150 may be formed on the buffer layer 115 in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62. The gate insulating layer 150 may cover the active layer 130 in the sub-pixel region 30 on the buffer layer 115, and may extend in a direction from the sub-pixel region 30 to the peripheral region 20. For example, the gate insulating layer 150 may fully cover the active layer 130 on the buffer layer 115, and may have a substantially flat top surface without generating steps around the active layer 130. In some embodiments, the gate insulating layer 150 may be formed with a uniform thickness along the contour of the active layer 130 on the buffer layer 115 to cover the active layer 130. The gate insulating layer 150 may be formed by using a silicon compound, a metal oxide, or the like.

[0135] like Fig.15 As shown in , a gate electrode 170 may be formed in the sub-pixel region 30 on the gate insulating layer 150. The gate electrode 170 may be formed on a portion of the gate insulating layer 150 under which the active layer 130 is positioned. The gate electrode 170 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0136] like Fig.13 and Fig.16As shown in , a second upper power line 740 may be formed in the first pad region 61 and the first peripheral region 21 on the gate insulating layer 150. The second upper power line 740 may include a first line extension 741, a second line extension 742, and a third line extension 743. For example, the first line extension 741 may be located in the first peripheral region 21 and may extend in the first direction D1. The second line extension 742 may extend from one side of the first line extension 741 in the third direction D3 to be located in the first pad region 61. The third line extension 743 may extend from the opposite side of the first line extension 741 in the second direction D2. The first line extension 741, the second line extension 742, and the third line extension 743 may be formed integrally with each other. The second upper power line 740 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0137] like Fig.14 and Fig.17 As shown in FIG, fan-out lines 420 may be formed in the second pad region 62 and the second peripheral region 22 on the gate insulating layer 150. The fan-out lines 420 may be formed by using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These may be used alone or in combination with each other.

[0138] like Fig.13 As shown in FIG, a conductive pattern 510 may be formed on the gate insulating layer 150 in parallel with the third line extension 743 in the first peripheral region 21. The conductive pattern 510 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0139] In an exemplary embodiment, the gate electrode 170 , the conductive pattern 510 , the second upper power line 740 , and the fan-out line 420 may be simultaneously formed by using the same material.

[0140] like Fig.13 , Fig.15 , Fig.16 and Fig.17As shown in , an interlayer insulating layer 190 may be formed on the gate electrode 170, the conductive pattern 510, the second upper power line 740, and the fan-out line 420. The interlayer insulating layer 190 may be formed on the gate insulating layer 150 in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62. The interlayer insulating layer 190 may include a contact hole 511 exposing one side of the conductive pattern 510 in the first peripheral region 21, a contact hole 512 exposing the opposite side of the conductive pattern 510, and a contact hole 751 exposing a portion of the third line extension 743 adjacent to the display region 10, and may include a contact hole 761 exposing a portion of the fan-out line 420 in the second peripheral region 22. For example, the interlayer insulating layer 190 may fully cover the gate electrode 170, the conductive pattern 510, the second upper power line 740, and the fan-out line 420 on the gate insulating layer 150, and may have a substantially flat top surface without generating steps around the gate electrode 170, the conductive pattern 510, the second upper power line 740, and the fan-out line 420. In some embodiments, the interlayer insulating layer 190 may be formed with a uniform thickness along the contours of the gate electrode 170, the conductive pattern 510, the second upper power line 740, and the fan-out line 420 on the gate insulating layer 150 to cover the gate electrode 170, the conductive pattern 510, the second upper power line 740, and the fan-out line 420. The interlayer insulating layer 190 may be formed by using a silicon compound, a metal oxide, or the like.

[0141] Reference Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 ,like Fig. 20 As shown in , a source electrode 210 and a drain electrode 230 may be formed in the sub-pixel region 30 on the interlayer insulating layer 190. The source electrode 210 may be connected to the source region of the active layer 130 via a contact hole formed by removing the gate insulating layer 150 and the first portion of the interlayer insulating layer 190, and the drain electrode 230 may be connected to the drain region of the active layer 130 via a contact hole formed by removing the gate insulating layer 150 and the second portion of the interlayer insulating layer 190. Each of the source electrode 210 and the drain electrode 230 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0142] Thus, the semiconductor element 250 including the active layer 130 , the gate insulating layer 150 , the gate electrode 170 , the interlayer insulating layer 190 , the source electrode 210 , and the drain electrode 230 may be formed.

[0143] like Fig.18 and Fig.21As shown in , a conductive member 360 may be formed in the first peripheral region 21 and the display region 10 on the interlayer insulating layer 190. For example, the conductive member 360 may include a first extension and a second extension. In this case, the first extension may extend in the first direction D1 in the first peripheral region 21 and may be positioned parallel to the first line extension 741. In addition, the second extension may be formed in the sub-pixel region 30. The second extension may be defined as a first sub-power line 650. The first extension and the second extension may be formed integrally with each other. The conductive member 360 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the conductive member 360 may include gold, silver, aluminum, platinum, nickel, titanium, palladium, magnesium, calcium, lithium, chromium, tantalum, tungsten, copper, molybdenum, scandium, neodymium, iridium, aluminum-containing alloys, aluminum nitride, silver-containing alloys, tungsten nitride, copper-containing alloys, molybdenum-containing alloys, titanium nitride, chromium nitride, tantalum nitride, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. These may be used alone or in combination with each other.

[0144] like Fig.18 and Fig.21 As shown in FIG. 1 , a first upper power line 640 may be formed in the first pad region 61 on the interlayer insulating layer 190. The first upper power line 640 may be formed in parallel with the second line extension 742. The first upper power line 640 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0145] like Fig.18 , Fig. 20 and Fig.21 As shown in FIG. 1 , a signal line 610 may be formed in a portion of the first peripheral region 21 and the display region 10 on the interlayer insulating layer 190, and the signal line 610 may extend in the second direction D2. One side of the signal line 610 may overlap with the contact hole 512 of the interlayer insulating layer 190, and may be connected to the conductive pattern 510 through the contact hole 512. The signal line 610 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0146] like Fig.18 and Fig.21As shown in FIG. 1 , a second sub-power line 750 may be formed in parallel with the signal line 610 and the first sub-power line 650 in a portion of the first peripheral region 21 and the display region 10 on the interlayer insulating layer 190, and the second sub-power line 750 may extend in the second direction D2. The second sub-power line 750 may be connected to the second upper power line 740 through a contact hole 751 in the first peripheral region 21. The second sub-power line 750 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0147] like Fig.18 and Fig.21 As shown in , an upper inspection pad 660 may be formed in the first peripheral region 21 on the interlayer insulating layer 190 to overlap with the first line extension 741 of the second upper power line 740. The upper inspection pads 660 may be arranged in the first direction D1 in the first peripheral region 21. Each of the upper inspection pads 660 may also include an extension extending in the second direction D2, wherein one side of the extension may be connected to the upper inspection pad 660, and the opposite side of the extension may overlap with the contact hole 511 of the interlayer insulating layer 190, and may be connected to the conductive pattern 510 through the contact hole 511. Each of the upper inspection pads 660 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0148] like Fig.19 and Fig. 22 As shown in FIG, a first lower power line 840 may be formed in the second pad region 62 on the interlayer insulating layer 190. The first lower power line 840 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0149] like Fig.19 and Fig. 22 As shown in FIG. 1 , a second lower power line 950 may be formed in the second pad region 62 and the second peripheral region 22 on the interlayer insulating layer 190. The second lower power line 950 may include a first line extension 951 and a second line extension 952. For example, the first line extension 951 may be located in the second peripheral region 22 and may extend in the first direction D1. The second line extension 952 may extend from one side of the first line extension 951 in the second direction D2 to be located in the second pad region 62. The second lower power line 950 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0150] like Fig.19 and Fig. 22As shown in , the lower inspection pad 760 may be formed in the second peripheral region 22 on the interlayer insulating layer 190, while the lower inspection pad 760 is spaced apart from the second lower power line 950. For example, the second lower power line 950 may be formed in the second peripheral region 22 near the second pad region 62, and the lower inspection pad 760 may be formed in the second peripheral region 22 near the display region 10. The lower inspection pads 760 may be arranged in the first direction D1 in the second peripheral region 22. Each of the lower inspection pads 760 may also include an extension extending in the third direction D3, and the extension may correspond to the signal line 610. Each of the lower inspection pads 760 may be connected to the fan-out line 420 through a contact hole 761 of the interlayer insulating layer 190. Each of the lower inspection pads 760 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0151] In an exemplary embodiment, the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub-power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950 and the lower inspection pad 760 may be simultaneously formed by using the same material.

[0152] Reference Figure 1 , a first pad electrode 471 may be formed in the first pad region 61 on the substrate 110, and a second pad electrode 472 may be formed in the second pad region 62 on the substrate 110. For example, the first pad electrode 471 and the second pad electrode 472 may be formed simultaneously with the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950, and the lower inspection pad 760 by using the same material as the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950, and the lower inspection pad 760.

[0153] like Figures 18 to 22As shown in the figure, a protective insulating layer 400 can be formed in the display area 10, the peripheral area 20, the first pad area 61 and the second pad area 62 on the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub-power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950 and the lower inspection pad 760. The protective insulating layer 400 can fully cover the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub-power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950 and the lower inspection pad 760 on the interlayer insulating layer 190, and can have a substantially flat top surface without generating steps around the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub-power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950 and the lower inspection pad 760. In some embodiments, a protective insulating layer 400 may be formed on the interlayer insulating layer 190 with a substantially uniform thickness along contours of the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub-power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950, and the lower inspection pad 760 to cover the source electrode 210, the drain electrode 230, the conductive member 360, the first upper power line 640, the signal line 610, the second sub-power line 750, the upper inspection pad 660, the first lower power line 840, the second lower power line 950, and the lower inspection pad 760. The protective insulating layer 400 may be formed by using a silicon compound, a metal oxide, or the like.

[0154] After forming the protective insulating layer 400, a contact hole exposing a portion of the top surface of the drain electrode 230, a contact hole exposing a portion of the top surface of the first sub-power line 650, a contact hole exposing a portion of the top surface of the conductive member 360, a contact hole exposing a portion of the top surface of the first upper power line 640, a contact hole exposing a first portion of the top surface of the first sub-power line 650, a contact hole exposing a portion of the top surface of the first lower power line 840, and a contact hole exposing a second portion of the top surface of the first sub-power line 650 can be formed in the protective insulating layer 400.

[0155] A first connection pattern 365 may be formed in a contact hole that partially exposes the top surface of the conductive member 360, a second connection pattern 645 may be formed in a contact hole that partially exposes the top surface of the first upper power line 640, a third connection pattern 235 may be formed in a contact hole that partially exposes the top surface of the drain electrode 230, a fourth connection pattern 655 may be formed in a contact hole that partially exposes the top surface of the first sub-power line 650, a fifth connection pattern 385 may be formed in a contact hole that exposes a first portion of the top surface of the first sub-power line 650, a sixth connection pattern 845 may be formed in a contact hole that partially exposes the top surface of the first lower power line 840, and a seventh connection pattern 665 may be formed in a contact hole that exposes a second portion of the top surface of the first sub-power line 650. The first to seventh connection patterns 365, 645, 235, 655, 385, 845, and 665 may be formed to protect the conductive member 360, the first upper power line 640, the drain electrode 230, the first sub power line 650, and the first lower power line 840. Each of the first to seventh connection patterns 365, 645, 235, 655, 385, 845, and 665 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0156] A planarization layer 270 may be formed on the first to seventh connection patterns 365, 645, 235, 655, 385, 845, and 665. The planarization layer 270 may be formed in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62 on the protective insulating layer 400. For example, the planarization layer 270 may have a relatively thick thickness. In this case, the planarization layer 270 may have a substantially flat top surface. In order to achieve such a flat top surface of the planarization layer 270, a planarization process may be additionally performed on the planarization layer 270. In some embodiments, the planarization layer 270 may be formed with a uniform thickness along the contours of the first to seventh connection patterns 365, 645, 235, 655, 385, 845, and 665 on the protective insulating layer 400. The planarization layer 270 may be formed by using an organic material. For example, the planarization layer 270 may include photoresist, polyacryl-based resin, polyimide-based resin, polyamide-based resin, siloxane-based resin, acryl-based resin, epoxy-based resin, or the like.

[0157] After forming the planarization layer 270, a contact hole overlapping with the contact hole of the protective insulation layer 400 exposing a portion of the top surface of the conductive member 360 may be formed in the planarization layer 270, and the contact hole may be defined as a first contact hole 361. A contact hole overlapping with the contact hole of the protective insulation layer 400 exposing a portion of the top surface of the first upper power line 640 may be formed in the planarization layer 270, and the contact hole may be defined as a second contact hole 641. A contact hole overlapping with the contact hole of the protective insulation layer 400 exposing a portion of the top surface of the first sub power line 650 may be formed in the planarization layer 270, and the contact hole may be defined as a third contact hole 651. A contact hole overlapping with the contact hole of the protective insulation layer 400 exposing a portion of the top surface of the drain electrode 230 may be formed in the planarization layer 270. A contact hole overlapping with the contact hole of the protective insulating layer 400 exposing the first portion of the top surface of the first sub power line 650 may be formed in the planarization layer 270, and the contact hole may be defined as a fourth contact hole 391. A contact hole overlapping with the contact hole of the protective insulating layer 400 exposing the portion of the top surface of the first lower power line 840 may be formed in the planarization layer 270, and the contact hole may be defined as a fifth contact hole 842. A contact hole overlapping with the contact hole of the protective insulating layer 400 exposing the second portion of the top surface of the first sub power line 650 may be formed in the planarization layer 270, and the contact hole may be defined as a sixth contact hole 652.

[0158] Reference Figure 5 , Fig. 9 , Fig.23 , Fig.24 and Fig.25 ,like Fig.23 As shown in FIG. 2 , a lower electrode 290 may be formed in the sub-pixel region 30 on the planarization layer 270. The lower electrode 290 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0159] like Figure 5 and Fig.24 As shown in , an upper connection member 295 may be formed in the first peripheral region 21 and the first pad region 61 on the planarization layer 270. The upper connection member 295 may extend in the first direction D1 in the first peripheral region 21, and may overlap with a portion of the first upper power line 640 and the conductive member 360. The upper connection member 295 may be connected to the conductive member 360 and the first upper power line 640 through the first contact hole 361 and the second contact hole 641, respectively. The upper connection member 295 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0160] like Figure 5 and Fig.23 As shown in , the first electrode pattern 305 may be formed in the third contact hole 651. The first electrode pattern 305 may completely cover the fourth connection pattern 655 exposed by the third contact hole 651. The first electrode pattern 305 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0161] like Fig. 9 , Fig.10 and Fig.25 As shown in FIG. 1 , a lower connection member 395 may be formed in the second peripheral region 22 and the second pad region 62 on the planarization layer 270. The lower connection member 395 may extend in the first direction D1 in the second peripheral region 22 and may overlap a portion of the first lower power line 840 and the first sub power line 650. The lower connection member 395 may be connected to the first sub power line 650 and the first lower power line 840 through the fourth contact hole 391 and the fifth contact hole 842, respectively. In some embodiments, a conductive member (such as a conductive member) may be formed in the second peripheral region 22. Figure 5 The conductive member 360 of the lower connection member 395 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0162] like Fig. 9 and Fig.10 As shown in , the second electrode pattern 315 may be formed in the sixth contact hole 652. The second electrode pattern 315 may completely cover the seventh connection pattern 665 exposed by the sixth contact hole 652. The second electrode pattern 315 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0163] In exemplary embodiments, the lower electrode 290 , the upper connection member 295 , the first electrode pattern 305 , the lower connection member 395 , and the second electrode pattern 315 may be simultaneously formed by using the same material.

[0164] like Fig.23 , Fig.24 and Fig.25As shown in FIG. 1 , a pixel defining layer 310 may be formed in the display region 10, the peripheral region 20, the first pad region 61, and the second pad region 62 on the planarization layer 270. The pixel defining layer 310 may cover both side portions of the lower electrode 290, both side portions of the first electrode pattern 305, both side portions of the second electrode pattern 315, the upper connection member 295, and the lower connection member 395. The pixel defining layer 310 may be formed by using an organic material.

[0165] Reference Figure 5 , Fig. 9 and Fig.26 , a light emitting layer 330 may be formed in the display region 10 on the pixel defining layer 310, the lower electrode 290, the first electrode pattern 305, and the second electrode pattern 315. The light emitting layer 330 may have a multilayer structure including an organic light emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. The organic light emitting layer of the light emitting layer 330 may be formed by using at least one of the light emitting materials for emitting different color lights (i.e., red light, green light, blue light, etc.) according to the sub-pixels. Alternatively, the organic light emitting layer of the light emitting layer 330 may be formed by stacking a plurality of light emitting materials for generating different color lights (such as red light, green light, and blue light) to emit white light as a whole.

[0166] After forming the light emitting layer 330 , a portion of a top surface of the first electrode pattern 305 and a portion of a top surface of the second electrode pattern 315 may be exposed through a laser drilling process.

[0167] The upper electrode 340 may be formed in the display region 10 on the substrate 110. For example, the upper electrode 340 may be formed in the display region 10 on the light emitting layer 330, and the upper electrode 340 may be in direct contact with the first electrode pattern 305 and the second electrode pattern 315 exposed by the light emitting layer 330. In other words, the upper electrode 340 may be formed along the contours of the light emitting layer 330, the first electrode pattern 305, and the second electrode pattern 315. The upper electrode 340 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0168] Thus, the sub-pixel structure 200 including the lower electrode 290 , the light emitting layer 330 , and the upper electrode 340 may be formed.

[0169] An encapsulation substrate 450 may be formed in the display region 10 on the upper electrode 340. The encapsulation substrate 450 may face the substrate 110 and may not be formed in the first pad region 61 and the second pad region 62. The encapsulation substrate 450 may include a material substantially the same as that of the substrate 110. For example, the encapsulation substrate 450 may be formed by using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, or the like.

[0170] Reference Figure 2 , a first power circuit board 841 and a second power circuit board 941 may be formed on the first pad electrode 471 , and the first power circuit board 841 , the second power circuit board 941 , and the driving circuit board 900 may be formed on the second pad electrode 472 .

[0171] Therefore, it is possible to produce Figures 1 to 12 The display device 100 shown in FIG.

[0172] The foregoing is an illustration of the embodiments and should not be construed as limiting them. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it will be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

[0173] Industrial Applicability

[0174] The present invention can be applied to various electronic devices including display devices. For example, the present invention can be applied to many electronic devices such as vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0175] Description of Reference Numerals

[0176] 10: Display area

[0177] 20: Outer Area

[0178] 21: First Outer Area

[0179] 22: Second Outer Area

[0180] 30: Sub-pixel area

[0181] 61: First pad area

[0182] 62: Second pad area

[0183] 100: Display device

[0184] 115: Buffer layer

[0185] 101: External Devices

[0186] 110: Base

[0187] 130: Active layer

[0188] 150: Gate insulation layer

[0189] 170: Gate electrode

[0190] 190: Interlayer insulation layer

[0191] 200: Sub-pixel structure

[0192] 210: Source electrode

[0193] 230: Drain electrode

[0194] 235: Third connection pattern

[0195] 250: Semiconductor components

[0196] 270: Planarization layer

[0197] 290: Lower electrode

[0198] 295: Upper connecting member

[0199] 305: first electrode pattern

[0200] 310: Pixel limiting layer

[0201] 315: Second electrode pattern

[0202] 330: Luminous layer

[0203] 340: Upper electrode

[0204] 360: Conductive components

[0205] 365: First connection pattern

[0206] 385: Fifth connection pattern

[0207] 395: Lower connecting member

[0208] 400: Protective insulation layer

[0209] 420: Fan-out line

[0210] 450: Package substrate

[0211] 471: First pad electrode

[0212] 472: Second pad electrode

[0213] 510: Conductive pattern

[0214] 610: Signal line

[0215] 640: First on the power line

[0216] 645: Second connection pattern

[0217] 650: First sub-power line

[0218] 655: Fourth connection pattern

[0219] 660: Upper inspection pad

[0220] 665: Seventh connection pattern

[0221] 740: Second Upper Power Line

[0222] 750: Second sub-power line

[0223] 760: Lower inspection pad

[0224] 840: First power line

[0225] 841: First Power Circuit Board

[0226] 845: Sixth connection pattern

[0227] 900: Driver circuit board

[0228] 950: Second power line

[0229] 941: Second power circuit board

Claims

1. A display device, comprising: A substrate comprising: a display area; a peripheral area surrounding the display area and including a first peripheral area and a second peripheral area; a first pad area located on one side of the peripheral area; and a second pad area located on an opposite side of the peripheral area; a first upper power line disposed on the substrate in the first pad region; a conductive member disposed on the substrate in the first peripheral region adjacent to the first pad region; A protective insulating layer, disposed on the conductive member; A planarization layer, disposed on the protective insulating layer; an upper connection member disposed in the first pad region and the first peripheral region on the planarization layer and configured to electrically connect the first upper power line and the conductive member through a first contact hole formed in the protective insulating layer and the planarization layer located on the conductive member and a second contact hole formed in the protective insulating layer and the planarization layer located on the first upper power line; and A sub-pixel structure is arranged in the display area on the protective insulating layer, The first contact hole is located to correspond to the conductive member and has a stripe shape when viewed in a plan view.

2. The display device according to claim 1, further comprising: a first connection pattern disposed between the protective insulating layer and the planarization layer to overlap the first contact hole and configured to cover a top surface of the conductive member so that the conductive member is not exposed; as well as A second connection pattern is disposed between the protective insulating layer and the planarization layer to overlap the second contact hole and is configured to cover a top surface of the first upper power line so that the first upper power line is not exposed.

3. The display device according to claim 1, wherein: The conductive member comprises: a first extending portion extending in a first direction parallel to a top surface of the substrate and located in the first peripheral region; and A second extending portion extends from one side of the first extending portion in a second direction and is located in a portion of the first peripheral region and the display region, wherein the second direction is a direction from the first peripheral region to the display region.

4. The display device according to claim 3, wherein: The first contact hole is located to correspond to the first extension portion, and has a stripe shape when viewed in a plan view.

5. The display device according to claim 4, wherein: A length of the first contact hole in the first direction is equal to a length of the first extension portion in the first direction.

6. The display device according to claim 3, wherein: The sub-pixel structure comprises: A lower electrode, disposed on the planarization layer in the display area; a light-emitting layer, disposed on the lower electrode; and The upper electrode is arranged on the light-emitting layer.

7. The display device according to claim 6, wherein: The upper electrode is electrically connected to the second extension portion through a third contact hole formed in the protective insulating layer and the planarization layer located on the second extension portion, and The second extension portion is defined as a first sub-power line.

8. The display device according to claim 7, further comprising: a third connection pattern disposed between the protective insulating layer and the planarization layer to overlap the third contact hole and configured to cover a top surface of the second extension portion so that the second extension portion is not exposed; as well as The first electrode pattern is arranged between the upper electrode and the third connection pattern.

9. The display device according to claim 7, further comprising: a first lower power line disposed on the substrate in the second pad region; a second lower power line disposed on the substrate in the second pad region and in the second peripheral region adjacent to the second pad region; as well as A fan-out line is provided between the substrate and the first lower power line and the second lower power line in the second pad region and the second peripheral region.

10. The display device according to claim 9, wherein: A first power is provided to the first lower power line, A second power having a voltage level different from that of the first power is supplied to the second lower power line, and A data signal is provided to the fan-out line.

11. The display device according to claim 9, further comprising a lower connecting member, which is arranged on the planarization layer in the second pad area and the second peripheral area, and is configured to electrically connect the first lower power line and the first sub-power line through a fourth contact hole and a fifth contact hole, the fourth contact hole being formed in the protective insulating layer and the planarization layer located on the first lower power line, and the fifth contact hole being formed on the first sub-power line adjacent to the second peripheral area.

12. The display device according to claim 11, further comprising: a fourth connection pattern disposed between the protective insulating layer and the planarization layer to overlap the fourth contact hole and configured to cover the fourth contact hole so that the first lower power line is not exposed; as well as A fifth connection pattern is disposed between the protective insulating layer and the planarization layer to overlap the fifth contact hole and is configured to cover the fifth contact hole so that the first sub power line is not exposed.

13. The display device according to claim 7, wherein: The light emitting layer is not provided in a portion in which the third contact hole is formed. 14 . The display device of claim 1 , further comprising an upper inspection pad located at the same layer as the first upper power line and the conductive member and arranged in a first direction parallel to a top surface of the substrate in the first peripheral region.

15. The display device according to claim 1, further comprising a second upper power line provided in the first pad area and the first peripheral area on the substrate and located at a level lower than that of the first upper power line and the conductive member, in, A first power is provided to the first upper power line, and Second power having a voltage level different from that of the first power is supplied to the second upper power line.

16. The display device according to claim 15, wherein: The second upper power line comprises: a first line extension portion located in the first peripheral region and extending in a first direction parallel to the top surface of the substrate; a second wire extension portion extending from one side of the first wire extension portion in a third direction to be located in the first pad region, the third direction being a direction from the first peripheral region to the first pad region; and A third line extension portion extends from an opposite side of the first line extension portion in a second direction to be located in the display region and is configured to intersect the conductive member, the second direction being a direction from the first peripheral region to the display region. 17 . The display device according to claim 16 , further comprising a second sub power line provided in a portion of the first peripheral region and the display region, extending in the second direction, and electrically connected to the third line extension portion in the first peripheral region.

18. The display device according to claim 17, wherein: The second sub-power line is located at the same layer as the first upper power line and the conductive member.

19. The display device according to claim 1, further comprising: a first pad electrode disposed on the substrate in the first pad region; as well as A second pad electrode is disposed in the second pad region on the substrate.

20. The display device according to claim 19, further comprising: a first power circuit board to which a first power is applied; a second power circuit board to which second power having a voltage level different from that of the first power is applied; as well as a driving circuit board to which a data signal is applied, wherein the first power circuit board and the second power circuit board are electrically connected to the first pad electrode, and The first power circuit board, the second power circuit board, and the driving circuit board are electrically connected to the second pad electrode.

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