Display substrate, display panel, and display device

Abstract

The present disclosure relates to a display substrate, a display panel, and a display device. The display substrate includes: a base substrate, including a display area and a peripheral area surrounding the display area; a common electrode, located in the peripheral area and surrounding the display area; a crack detection line, located in the peripheral area and surrounding the display area, the crack detection line being located on a side of the common electrode away from the display area; and at least one electrostatic discharge circuit, located in the peripheral area; wherein the at least one electrostatic discharge circuit includes at least one first thin film transistor, the at least one first thin film transistor including an active layer, a gate located on a side of the active layer away from the base substrate, and a source and a drain located on a side of the gate away from the base substrate, the source and drain of the at least one first thin film transistor being electrically connected to the crack detection line, and the gate of the at least one first thin film transistor being electrically connected to the common electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] With the development of active matrix organic light-emitting diodes (AMOLED) in the field of display technology, it is urgent to improve the yield rate of its products. Static electricity is one of the main factors that lead to product defects. Summary of the Invention

[0003] In one aspect of the present disclosure, a display substrate is provided, comprising:

[0004] A base substrate, comprising a display area and a peripheral area surrounding the display area;

[0005] a common electrode located in the peripheral area and surrounding the display area;

[0006] a crack detection line located in the peripheral area and surrounding the display area, the crack detection line being located on a side of the common electrode away from the display area; and

[0007] at least one electrostatic discharge circuit located in the peripheral area;

[0008] In which, the at least one electrostatic release circuit includes at least one first thin film transistor, the at least one first thin film transistor includes an active layer, a gate located on the side of the active layer away from the substrate, and a source and a drain located on the side of the gate away from the substrate, the source and the drain of the at least one first thin film transistor are electrically connected to the crack detection line, and the gate of the at least one first thin film transistor is electrically connected to the common electrode.

[0009] In some embodiments, the display area includes: a first boundary, a second boundary, a third boundary and a fourth boundary, the peripheral area includes a first peripheral region located outside the first boundary, a second peripheral region located outside the second boundary, a third peripheral region located outside the third boundary and a fourth peripheral region located outside the fourth boundary; the common electrode includes a first part located in the first peripheral region and a second part located in the second peripheral region, the third peripheral region and the fourth peripheral region, and the gate of the at least one first thin film transistor is electrically connected to the first part of the common electrode.

[0010] In some embodiments, the display substrate further comprises:

[0011] a plurality of sub-pixels located in the display area; and

[0012] The unit test circuit is located in the first peripheral area and is electrically connected to the plurality of sub-pixels and the crack detection line respectively.

[0013] In some embodiments, the at least one electrostatic discharge circuit includes two electrostatic discharge circuits, one located on either side of the unit test circuit.

[0014] In some embodiments, at least a portion of the crack detection line located in the first peripheral region is located in the same layer and made of the same material as the source and drain of the at least one first thin film transistor, and at least a portion of the crack detection line located in the second peripheral region, the third peripheral region, and the fourth peripheral region is located in the same layer and made of the same material as the gate of the at least one first thin film transistor.

[0015] In some embodiments, the source and drain of the at least one first thin film transistor are short-circuited by a metal layer, and the source and drain of the at least one first thin film transistor are located in the same layer as the metal layer and are made of the same material.

[0016] In some embodiments, the at least one first thin film transistor includes at least one row of first thin film transistors arranged along the extension direction of the crack detection line, each row of first thin film transistors includes multiple first thin film transistors, the gates of the multiple first thin film transistors are connected in sequence along the arrangement direction of the row of first thin film transistors, and the gates of each row of first thin film transistors are connected to each other on both sides along the extension direction of the crack detection line.

[0017] In some embodiments, the crack detection line includes a first crack detection segment and a second crack detection segment parallel to each other, and the at least one first thin film transistor includes two rows of first thin film transistors, both located between the first crack detection segment and the second crack detection segment, and each row of first thin film transistors includes a plurality of first thin film transistors arranged along the extension direction of the first crack detection segment or the second crack detection segment.

[0018] In some embodiments, the gates of the two rows of first thin film transistors are connected to each other in a ring shape on both sides along an extension direction of the crack detection line.

[0019] In some embodiments, the display substrate further comprises:

[0020] a first gate insulating layer, located on a side of the base substrate adjacent to the gate of the at least one first thin film transistor and covering the active layer of the at least one first thin film transistor;

[0021] a second gate insulating layer, located on a side of the first gate insulating layer away from the base substrate and covering the gate of the at least one first thin film transistor; and

[0022] an interlayer insulating layer, located on a side of the second gate insulating layer away from the base substrate;

[0023] The source and drain of the at least one first thin film transistor are located on a side of the interlayer insulating layer away from the base substrate, and are electrically connected to the active layer through at least one first via hole penetrating the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

[0024] In some embodiments, the display substrate further comprises:

[0025] at least one pattern block, located on a side of the crack detection line away from the at least one first thin film transistor and located in the same layer as an active layer of the at least one first thin film transistor;

[0026] The interlayer insulating layer covers a side of the at least one graphic block away from the base substrate, and a portion of the interlayer insulating layer covering the at least one graphic block is provided with at least one second via hole penetrating the interlayer insulating layer.

[0027] In some embodiments, the at least one graphic block includes at least one row of graphic blocks, each row of graphic blocks includes a plurality of graphic blocks arranged along the extension direction of the crack detection line, the at least one first thin film transistor includes at least one row of first thin film transistors, each row of first thin film transistors includes a plurality of first thin film transistors arranged along the extension direction of the crack detection line, and the plurality of graphic blocks correspond one-to-one to the plurality of first thin film transistors.

[0028] In some embodiments, the at least one second via includes at least one row of second vias extending along the extension direction of the crack detection line, each row of second vias includes a plurality of second vias arranged at intervals along the extension direction of the crack detection line, and at least a portion of the plurality of second vias is aligned with at least one first via in the at least one first thin film transistor in a direction perpendicular to the crack detection line and parallel to the substrate.

[0029] In some embodiments, the crack detection line includes a first crack detection segment and a second crack detection segment parallel to each other, and the at least one row of second vias includes at least one row of second vias located on a side of the first crack detection segment away from the at least first thin film transistor and at least one row of second vias located on a side of the second crack detection segment away from the at least first thin film transistor.

[0030] In some embodiments, the display substrate further includes a plurality of sub-pixels located in the display area, at least one of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit includes:

[0031] at least one second thin film transistor, located in the display area;

[0032] The gate of the at least one first thin film transistor is located in the same layer and made of the same material as the gate of the at least one second thin film transistor, and the source and drain of the at least one first thin film transistor are located in the same layer and made of the same material as the source and drain of the at least one second thin film transistor.

[0033] In some embodiments, the at least one first thin film transistor and the at least one second thin film transistor are both P-type thin film transistors.

[0034] In some embodiments, the number of first thin film transistors in the at least one first thin film transistor is greater than or equal to 16.

[0035] In some embodiments, the voltage of the common electrode is -1 to -7V.

[0036] In some embodiments, the voltage of the common electrode is -3V.

[0037] In some embodiments, the portion of the crack detection line located in the first peripheral area is U-shaped or L-shaped, and the bent portion of the U-shape or L-shape has a cut angle.

[0038] In another aspect of the present disclosure, a display panel is provided, comprising the aforementioned display substrate.

[0039] In another aspect of the present disclosure, a display device is provided, comprising the aforementioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0041] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0042] Figure 1 is a schematic diagram showing the regional distribution of an embodiment of a display substrate according to the present disclosure;

[0043] Figure 2 is a schematic diagram of a circuit principle according to an embodiment of the display substrate of the present disclosure;

[0044] Figure 3 is a schematic diagram showing a partial layout of an electrostatic discharge circuit in accordance with an embodiment of the present disclosure;

[0045] Figure 4 yes Figure 3 Enlarged schematic diagram of circle A in the middle;

[0046] Figure 5 yes Figure 4 Schematic diagram of the structure of the middle BB section;

[0047] Figure 6 is a schematic diagram showing the regional distribution of another embodiment of a display substrate according to the present disclosure;

[0048] Figure 7 FIG. 1 is a schematic diagram showing a partial layout of an electrostatic discharge circuit in another embodiment of a display substrate according to the present disclosure. DETAILED DESCRIPTION

[0049] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure, its application, or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of parts and steps, the composition of materials, numerical expressions, and numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0050] The terms "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The terms "include" or "comprises" and similar terms mean that the elements before the term include the elements listed after the term, and do not exclude the possibility of also including other elements. The terms "upper", "lower", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0051] In the present disclosure, when a specific device is described as being located between a first device and a second device, an intervening device may or may not be present between the specific device and the first device or the second device. When a specific device is described as being connected to another device, the specific device may be directly connected to the other device without an intervening device, or may be not directly connected to the other device but with an intervening device.

[0052] All terms (including technical or scientific terms) used in this disclosure have the same meaning as those understood by one of ordinary skill in the art to which this disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in, for example, general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined herein.

[0053] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0054] The panel crack detection (PCD) lines of AMOLED displays are long, and static electricity easily accumulates during the manufacturing process. If this accumulated static electricity is not promptly discharged, it may break down the thin film transistors (TFTs) driving the adjacent PCD lines or the TFTs in the scanning unit within the panel, causing individual pixels to fail or the entire panel to fail.

[0055] Some related technologies release static electricity accumulated in PCD lines by switching between different layers. The inventors have discovered that switching between layers does not completely eliminate static electricity. In multi-layer metal wiring processes, when an antenna effect occurs in lower metal layers, it can be eliminated by jumping the wires upwards. However, when an antenna effect occurs in the highest metal layer, jumping the wires is not effective in dissipating static electricity.

[0056] In view of this, embodiments of the present disclosure provide a display substrate, an AMOLED display panel, and a display device, which can effectively eliminate static electricity accumulated in PCD lines.

[0057] Figure 1 FIG. 1 is a schematic diagram showing the regional distribution of an embodiment of a display substrate according to the present disclosure.

[0058] refer to Figure 1 In some embodiments, the display substrate includes a base substrate 1, a common electrode 5, a crack detection line 2, and at least one electrostatic discharge circuit 3. The base substrate 1 may be made of glass, ceramic, polyimide, or the like. The base substrate 1 includes a display area 1A and a peripheral area 1B surrounding the display area 1A. The display substrate may further include a plurality of sub-pixels 10 located in the display area 1A, each sub-pixel being capable of displaying any color such as red, green, blue, or white, thereby enabling the display substrate to present a picture. The peripheral area 1B is located outside the display area 1A (i.e., on the side away from the display area 1A) and is a non-display area.

[0059] exist Figure 1 In the embodiment, display area 1A includes a first boundary 1a, a second boundary 1b, a third boundary 1c, and a fourth boundary 1d. First boundary 1a is opposite third boundary 1c, and second boundary 1b is opposite fourth boundary 1d. Peripheral area 1B includes a first peripheral region outside first boundary 1a, a second peripheral region outside second boundary 1b, a third peripheral region outside third boundary 1c, and a fourth peripheral region outside fourth boundary 1d.

[0060] refer to Figure 1 , the common electrode 5 is located in the peripheral area 1B and surrounds the display area 1A. Specifically, the common electrode 5 may include a first portion located in the first peripheral area and second portions located in the second peripheral area, the third peripheral area, and the fourth peripheral area. Figure 1 In the embodiment, the second portion of the common electrode 5 continuously extends to the second peripheral area, the third peripheral area and the fourth peripheral area, and extends to the first peripheral area on both sides of the display area 1A.

[0061] The PCD line 2 is located in the peripheral area 1B and surrounds the display area 1A. The PCD line 2 is located on a side of the common electrode 5 away from the display area. Figure 1 In FIG, the PCD line 2 includes two loops, one loop passes through the left half of the first peripheral zone, the second peripheral zone, and the left half of the third peripheral zone, and the other loop passes through the right half of the first peripheral zone, the fourth peripheral zone, and the right half of the third peripheral zone.

[0062] At least one electrostatic discharge circuit 3 is also located in the peripheral area 1B and is electrically connected to the common electrode 5 and the PCD line 2 to achieve electrostatic discharge of the PCD line 2. Figure 1 In the embodiment, at least one electrostatic discharge circuit 3 is located in the first peripheral area and includes two electrostatic discharge circuits.

[0063] refer to Figure 1 In some embodiments, the display substrate further includes a cell test (CT) circuit 6. The CT circuit 6 is located in the first peripheral area and is electrically connected to the plurality of sub-pixels 10 and the PCD lines 2 respectively. Figure 1 The two electrostatic discharge circuits can be located on both sides of the unit test circuit respectively.

[0064] The CT circuit 6 may include a plurality of TFTs. The gate of each TFT is connected to the switch signal line SW d One of the source or drain electrodes of the plurality of TFTs is electrically connected to the plurality of sub-pixels, and the other of the source or drain electrodes of the plurality of TFTs is electrically connected to one end of the loop of PCD line 2, the first control voltage line D1, and the second control voltage line D2. For example, a green sub-pixel among the plurality of sub-pixels 10 is connected to one end of the loop of PCD line 2 via the TFT.

[0065] The other end of the loop of PCD line 2 is connected to the switching voltage signal V GHWhen the display substrate has no cracks or the cracks are small, and the circuit of PCD line 2 is not broken, the voltage of the PCD line is the same as the first control voltage line D1 and the second control voltage line D2 during testing, causing all sub-pixels in the display area to appear dark. If the display substrate has a large crack, causing the circuit of the PCD line to be broken, the voltage of the PCD line will be different from the first control voltage line D1 and the second control voltage line D2 during testing, causing the sub-pixel corresponding to the TFT connected to PCD line 2 (for example, the green sub-pixel) to become brighter, which is reflected in the green bright line in the dark state image in the display area, thereby confirming that the display substrate has cracks.

[0066] Figure 2 FIG. 1 is a schematic diagram showing a circuit principle of an embodiment of a display substrate according to the present disclosure. Figure 3 FIG. 1 is a schematic diagram showing a partial layout of an electrostatic discharge circuit in an embodiment of a display substrate according to the present disclosure. Figure 4 yes Figure 3 Enlarged schematic diagram of circle A in the middle. Figure 5 yes Figure 4 Schematic diagram of the structure of the BB section.

[0067] refer to Figure 2-Figure 5 In some embodiments, the at least one electrostatic discharge circuit 3 includes at least one first TFT 30. The at least one first TFT 30 includes an active layer 32, a gate 31 located on a side of the active layer 32 away from the base substrate 1, and a source 35 and a drain 36 located on a side of the gate 31 away from the base substrate 1. The source 35 and the drain 36 of the at least one first TFT 30 are electrically connected to the PCD line 2. The gate 31 of the at least one first TFT 30 is electrically connected to the common electrode 5.

[0068] The active layer 32 can be made of polycrystalline silicon. The source 35 and drain 36 of the at least one first TFT 30 are electrically connected to the PCD line 2 and to the active layer 32. The gate 31 of the at least one first TFT 30 is electrically connected to the common electrode 5. In some embodiments, the common electrode 5 can be set to a negative constant voltage, for example, -1 to -7V, and further optionally -3V.

[0069] This connection method makes the at least one first TFT 30 in the electrostatic discharge circuit 3 act as a capacitor. The source 35 and drain 36 of the first TFT 30, along with the active layer 32 to which they are electrically connected, act as one plate of the capacitor, while the gate 31 of the first TFT 30 acts as the other plate. Because the gate 31 is electrically connected to the common electrode 5, the capacitor plate corresponding to the gate 31 is continuously at a low potential. When positive or negative static charge forms on the PCD line 2, the static charge charges the source 35, drain 36, and active layer 32 of the first TFT 30, discharging the static charge generated by the antenna effect on the PCD line 2. This effectively protects the display substrate and the AMOLED display panel using it from static breakdown, thereby improving the overall product yield.

[0070] exist Figure 3 In the embodiment, a portion of the PCD line 2 is bent into a U-shape in the first peripheral region, and the first TFTs 30 in the electrostatic discharge circuit 3 are located at the bottom of the U-shape. The bent portion of the U-shape can be chamfered to reduce the risk of tip discharge. The at least one first TFT 30 includes at least one row of first TFTs 30. Each row of first TFTs 30 includes a plurality of first TFTs 30 arranged along the direction in which the PCD line 2 extends. The gates of the plurality of first TFTs 30 are sequentially connected along the arrangement direction of the row of first TFTs 30. The gates of each row of first TFTs 30 are interconnected on both sides along the direction in which the PCD line 2 extends.

[0071] The number of first TFTs 30 can be set according to the layout space on the display substrate. In some embodiments, the number of first TFTs 30 is greater than or equal to 16. If needed, the first TFTs 30 can also be made into a form with fewer and larger sizes.

[0072] exist Figure 2 and Figure 3 In the embodiment, the PCD line 2 includes a first PCD segment and a second PCD segment that are parallel to each other. The first PCD segment and the second PCD segment are located in the same PCD loop. The at least one first TFT 30 includes two rows of first TFTs 30, each located between the first PCD segment and the second PCD segment. Each row of first TFTs 30 includes a plurality of first TFTs 30 arranged along the extension direction of the first PCD segment or the second PCD segment.

[0073] refer to Figure 2 、 Figure 4 and Figure 5In some embodiments, the source electrode 35 and drain electrode 36 of at least one first TFT 30 are short-circuited by a metal layer 37. The source electrode 35 and drain electrode 36 of the at least one first TFT 30 are located in the same layer and made of the same material as the metal layer 37. For example, the source electrode 35 and drain electrode 36 of the first TFT 30 can be made of a conductive material such as molybdenum, copper, aluminum, gold, silver, or titanium as the metal layer 37. In this way, the source electrode 35, drain electrode 36, and metal layer 37 can be formed using the same patterning process, simplifying the manufacturing process. Here and below, "same layer, same material" refers to a layer structure formed by forming a film layer for forming a specific pattern using the same film-forming process, and then patterning the film layer using the same mask in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0074] refer to Figure 5 In some embodiments, while using an electrostatic discharge circuit to release the PCD lines, a PCD line routing layer switching technique is employed. Specifically, at least a portion of the PCD lines 2 located in the first peripheral region is located on the same layer and made of the same material as the source 35 and drain 36 of the at least one first TFT 30. This allows at least a portion of the PCD lines 2 in this region to be formed through the same patterning process as the source 35 and drain 36 of the at least one first TFT 30, simplifying the manufacturing process. Furthermore, at least a portion of the PCD lines 2 located in the second, third, and fourth peripheral regions is located on the same layer and made of the same material as the gate 31 of the at least one first TFT 30. This inter-layer jumpering of the PCD lines 2 reduces the conductor area with an antenna effect and allows static electricity accumulated on the PCD lines 2 to be discharged to the first TFT 30.

[0075] exist Figure 3 In the embodiment, the gate electrodes 31 of each row of first TFTs 30 can be sequentially connected along the arrangement direction of the row of first TFTs 30. The gate electrodes 31 of each row of first TFTs 30 are connected to each other on both sides along the arrangement direction of the row of first TFTs 30. For an electrostatic discharge circuit having two rows of first TFTs 30, the gate electrodes 31 of the two rows of first TFTs 30 can be annular and extended to be electrically connected to the common electrode 5.

[0076] refer to Figure 5In some embodiments, the display substrate 1 further includes: a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14. The first gate insulating layer 12 is located on a side of the base substrate 1 adjacent to the gate 31 of the at least one first TFT 30, and covers the active layer 32 of the at least one first TFT 30. The second gate insulating layer 13 is located on a side of the first gate insulating layer 12 away from the base substrate, and covers the gate 31 of the at least one first TFT 30. The interlayer insulating layer 14 is located on a side of the second gate insulating layer 13 away from the base substrate 1. Figure 5 In the embodiment, a buffer layer 11 may be provided on the base substrate 1, and the active layer 32 may be provided on the surface of the buffer layer 11. In other embodiments, the active layer 32 may be directly provided on the surface of the base substrate 1.

[0077] The source electrode 34 and the drain electrode 36 are arranged on a side of the interlayer insulating layer 14 away from the substrate 1 and are electrically connected to the active layer 32 through at least one first via hole 39 penetrating the interlayer insulating layer 14, the second gate insulating layer 13 and the first gate insulating layer 12. Figure 4 In the embodiment, the source electrode 35 and the drain electrode 36 of each first TFT 30 are electrically connected to the active layer 32 through three first via holes 39. The display substrate 1 further includes a planarization layer 15 located on a side of the interlayer insulating layer 14 away from the substrate 1. The planarization layer 15 covers the source electrode 34 and the drain electrode 36 of at least one first TFT 30.

[0078] refer to Figure 1 In some embodiments, the display substrate further comprises: a plurality of sub-pixels 10 located in the display area, at least one of the plurality of sub-pixels 10 comprising a pixel circuit. The pixel circuit comprises at least one second TFT. In some embodiments, the gate of the at least one first TFT 30 is located in the same layer and made of the same material as the gate of the at least one second TFT, and the source and drain of the at least one first TFT 30 are located in the same layer and made of the same material as the source and drain of the at least one second TFT. In this way, the source 35 and drain 36 of the first TFT 30 in the electrostatic discharge circuit 3 can be formed using the same patterning process as the source and drain of the second TFT in the display area 1A, and the gate 31 of the first TFT 30 in the electrostatic discharge circuit 3 can be formed using the same patterning process as the gate of the second TFT in the display area 1A, thereby simplifying the manufacturing process.

[0079] In some embodiments, the second TFT in the display area 1A is a P-type TFT. To simplify the manufacturing process, at least one first TFT 30 may also be a P-type TFT so as to be formed using the same patterning process. In other embodiments, the first TFT 30 may also be an N-type TFT.

[0080] When forming multiple second TFTs, the source and drain of each second TFT are connected to the active layer through a via hole, which makes the characteristics of each second TFT affected by the via holes of other second TFTs around it. Figure 3 In some embodiments, the display substrate further includes: at least one pattern block 4, located on a side of the PCD line away from the at least one first TFT 30 and co-located with the active layer of the at least one first TFT 30. Both the pattern block 4 and the active layer may be formed of polysilicon to simplify the manufacturing process.

[0081] The interlayer insulating layer 14 covers a side of the at least one pattern block 4 away from the base substrate 1, and at least one second via hole 41 is provided through the interlayer insulating layer 14 in the area covering the at least one pattern block 4. Forming the second via hole 41 around the first TFT 30 reduces the difference between the via hole environment around the first TFT 30 and the via hole environment around the second TFT in the display area, thereby making the characteristics of the first TFT 30 and the second TFT in the display area more consistent.

[0082] In addition, the area corresponding to the pattern block 4 does not include the gate 31, source 35, and drain 36 of the first TFT 30. By providing the second via 4, this area can be exposed more consistently with the area where the first TFT 30 is provided, thereby ensuring etching uniformity of the electrostatic discharge circuit.

[0083] refer to Figure 3 In some embodiments, at least one pattern block 4 includes at least one row of pattern blocks 4, and each row of pattern blocks 4 includes a plurality of pattern blocks 4 arranged along the extension direction of the PCD line. The plurality of pattern blocks 4 in each row of pattern blocks 4 may correspond one-to-one to the plurality of first TFTs 30. Figure 3 In the embodiment, the number of pattern blocks 4 in each row of pattern blocks 4 is equal to the number of first TFTs 30 in an adjacent row of first TFTs 30. Each pattern block 4 may correspond to at least one second via hole 41, for example, three second via holes 41. This can reduce the difference between the via hole environment surrounding each first TFT 30 and the via hole environment surrounding the second TFTs in the display area.

[0084] The at least one second via 41 includes at least one row of second vias 41 extending along the direction in which the PCD line 2 extends. Each row of second vias 41 includes a plurality of second vias 41 spaced apart along the direction in which the PCD line 2 extends. At least a portion of the plurality of second vias 41 is aligned with at least one first via 39 in the at least one first TFT 30 in a direction perpendicular to the PCD line 2 and parallel to the base substrate 1. This allows the via environment surrounding the first via 39 in the first TFT 30 to be more similar to the via environment surrounding the second TFT in the display area, thereby further aligning the characteristics of the first TFT 30 with those of the second TFT in the display area.

[0085] refer to Figure 1 and Figure 3 In some embodiments, the PCD line 2 includes a first PCD segment and a second PCD segment that are parallel to each other. The at least one row of second vias 41 includes at least one row of second vias 41 located on a side of the first PCD segment away from the at least one first TFT 30, and at least one row of second vias 41 located on a side of the second PCD segment away from the at least one first TFT 30. The first PCD segment is located on a side of the second PCD segment adjacent to the display area 1A. The two rows of first TFTs 30 are located between the first and second PCD segments and are electrically connected to the first and second PCD segments, respectively. Two rows of pattern blocks 4 and second vias 41 may be provided on a side of the first PCD segment adjacent to the display area 1A, and one row of pattern blocks 4 and second vias 41 may be provided on a side of the second PCD segment away from the display area 1A.

[0086] Figure 6 FIG. 4 is a schematic diagram showing the regional distribution of another embodiment of a display substrate according to the present disclosure. Figure 7 FIG. 1 is a schematic diagram showing a partial layout of an electrostatic discharge circuit in another embodiment of a display substrate according to the present disclosure.

[0087] refer to Figure 6 and Figure 7 Compared to the aforementioned embodiments of the display substrate disclosed herein, in some embodiments, a portion of the PCD line 2 is bent into an L-shape in the first peripheral region, and the first TFT 30 in the electrostatic discharge circuit 3 is located in the side region of the L-shape. The bent portion of the L-shape can be chamfered to reduce the risk of tip discharge.

[0088] The display substrate embodiments disclosed herein are applicable to various display panels and display devices. Therefore, the present disclosure also provides a display panel, such as an AMOLED display panel, comprising the aforementioned display substrate. The present disclosure also provides a display device comprising the aforementioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0089] Thus far, various embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details known in the art have not been described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

[0090] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art will understand that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that the above embodiments may be modified or some technical features may be replaced with equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display substrate, comprising: A base substrate, comprising a display area and a peripheral area surrounding the display area; a common electrode located in the peripheral area and surrounding the display area; a crack detection line located in the peripheral area and surrounding the display area, wherein the crack detection line is located on a side of the common electrode away from the display area; and at least one electrostatic discharge circuit located in the peripheral area; In which, the at least one electrostatic release circuit includes at least one first thin film transistor, the at least one first thin film transistor includes an active layer, a gate located on the side of the active layer away from the substrate, and a source and a drain located on the side of the gate away from the substrate, the source and the drain of the at least one first thin film transistor are electrically connected to the crack detection line, and the gate of the at least one first thin film transistor is electrically connected to the common electrode.

2. The display substrate according to claim 1, wherein The display area includes: a first boundary, a second boundary, a third boundary and a fourth boundary; the peripheral area includes a first peripheral region located outside the first boundary, a second peripheral region located outside the second boundary, a third peripheral region located outside the third boundary and a fourth peripheral region located outside the fourth boundary; the common electrode includes a first portion located in the first peripheral region and a second portion located in the second peripheral region, the third peripheral region and the fourth peripheral region; the gate of the at least one first thin film transistor is electrically connected to the first portion of the common electrode.

3. The display substrate according to claim 2, further comprising: A plurality of sub-pixels are located in the display area; and The unit test circuit is located in the first peripheral area and is electrically connected to the plurality of sub-pixels and the crack detection line respectively.

4. The display substrate according to claim 3, wherein: The at least one electrostatic discharge circuit includes two electrostatic discharge circuits, which are respectively located on two sides of the unit test circuit.

5. The display substrate according to claim 2, wherein: At least part of the crack detection line located in the first peripheral area is located in the same layer as the source and drain of the at least one first thin film transistor, and at least part of the crack detection line located in the second peripheral area, the third peripheral area and the fourth peripheral area is located in the same layer as the gate of the at least one first thin film transistor. The display substrate according to claim 1 , wherein: The source and drain of the at least one first thin film transistor are short-circuited via a metal layer, and the source and drain of the at least one first thin film transistor are located in the same layer as the metal layer and are made of the same material.

7. The display substrate according to claim 1, wherein: The at least one first thin film transistor includes at least one row of first thin film transistors arranged along the extension direction of the crack detection line, each row of first thin film transistors includes a plurality of first thin film transistors, the gates of the plurality of first thin film transistors are connected in sequence along the arrangement direction of the row of first thin film transistors, and the gates of each row of first thin film transistors are connected to each other on both sides along the extension direction of the crack detection line.

8. The display substrate according to claim 7, wherein: The crack detection line includes a first crack detection segment and a second crack detection segment parallel to each other, and the at least one first thin film transistor includes two rows of first thin film transistors, both located between the first crack detection segment and the second crack detection segment, and each row of first thin film transistors includes a plurality of first thin film transistors arranged along an extension direction of the first crack detection segment or the second crack detection segment.

9. The display substrate according to claim 8, wherein: The gate electrodes of the two rows of first thin film transistors are connected to each other to form a ring shape on both sides along the extending direction of the crack detection line.

10. The display substrate according to claim 1, further comprising: a first gate insulating layer, located on a side of the base substrate adjacent to the gate of the at least one first thin film transistor and covering the active layer of the at least one first thin film transistor; a second gate insulating layer, located on a side of the first gate insulating layer away from the base substrate and covering the gate of the at least one first thin film transistor; and an interlayer insulating layer, located on a side of the second gate insulating layer away from the base substrate; The source and drain of the at least one first thin film transistor are located on a side of the interlayer insulating layer away from the base substrate, and are electrically connected to the active layer through at least one first via hole penetrating the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

11. The display substrate according to claim 10, further comprising: at least one pattern block, located on a side of the crack detection line away from the at least one first thin film transistor and located in the same layer as an active layer of the at least one first thin film transistor; The interlayer insulating layer covers a side of the at least one graphic block away from the base substrate, and a portion of the interlayer insulating layer covering the at least one graphic block is provided with at least one second via hole penetrating the interlayer insulating layer.

12. The display substrate according to claim 11, wherein: The at least one graphic block includes at least one row of graphic blocks, each row of graphic blocks includes a plurality of graphic blocks arranged along the extension direction of the crack detection line, the at least one first thin film transistor includes at least one row of first thin film transistors, each row of first thin film transistors includes a plurality of first thin film transistors arranged along the extension direction of the crack detection line, and the plurality of graphic blocks correspond one-to-one to the plurality of first thin film transistors.

13. The display substrate according to claim 11, wherein: The at least one second via includes at least one row of second vias extending along the extension direction of the crack detection line, each row of second vias includes a plurality of second vias arranged at intervals along the extension direction of the crack detection line, and at least a portion of the plurality of second vias is aligned with at least one first via in the at least one first thin film transistor in a direction perpendicular to the crack detection line and parallel to the substrate.

14. The display substrate according to claim 13, wherein: The crack detection line includes a first crack detection segment and a second crack detection segment parallel to each other, and the at least one row of second via holes includes at least one row of second via holes located on a side of the first crack detection segment away from the at least one first thin film transistor and at least one row of second via holes located on a side of the second crack detection segment away from the at least one first thin film transistor.

15. The display substrate according to claim 1 , further comprising a plurality of sub-pixels located in the display area, at least one of the plurality of sub-pixels comprising a pixel circuit, the pixel circuit comprising: at least one second thin film transistor, located in the display area; The gate of the at least one first thin film transistor is located in the same layer and made of the same material as the gate of the at least one second thin film transistor, and the source and drain of the at least one first thin film transistor are located in the same layer and made of the same material as the source and drain of the at least one second thin film transistor.

16. The display substrate according to claim 15, wherein: The at least one first thin film transistor and the at least one second thin film transistor are both P-type thin film transistors.

17. The display substrate according to claim 1, wherein The number of the first thin film transistors in the at least one first thin film transistor is greater than or equal to 16.

18. The display substrate according to claim 1, wherein The voltage of the common electrode is -1~-7V.

19. The display substrate according to claim 18, wherein: The voltage of the common electrode is -3V.

20. The display substrate according to claim 2, wherein: The portion of the crack detection line located in the first peripheral area is U-shaped or L-shaped, and the bent portion of the U-shaped or L-shaped portion has a cut angle.

21. A display panel comprising the display substrate according to any one of claims 1 to 20.

22. A display device comprising the display panel according to claim 21.

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