Methods and apparatus for synchronization and data transmission

Abstract

An electronic circuit includes: a main controller; and multiple modules; wherein the main controller includes: a timing signal generator arranged to generate a timing signal; and a data signal generator arranged to generate a data signal; wherein the main controller is arranged to generate a combined signal based on both the timing signal and the data signal; and wherein the main controller is arranged to broadcast the combined signal to the multiple modules. By broadcasting the timing signal and the data signal together to the modules, available bandwidth is effectively utilized without requiring numerous separate signal paths to each module or time multiplexing of the signals. Therefore, accurate time synchronization can be achieved, enabling the system to operate effectively at high switching frequencies. Since the switches on the modules are not directly controlled by the main controller, the system provides a distributed architecture where the processing of received signals can be performed locally on each module.

Description

[0001] This invention relates to electronic circuits, such as those in power electronics, and particularly to the transmission of timing and control signals for controlling subsystems within power electronic circuits, such as those in power converters.

[0002] Power electronic circuits can be thought of as switching circuits that control the flow of electrical energy. Examples of power electronic devices are switch-mode power supplies, power converters, and power inverters, such as those used for motor drives. Power electronics are crucial in today's energy distribution and management systems. More than 80% of the electricity generated today is processed by power electronic systems.

[0003] In power electronic devices with a large number of switches, controlling these switches becomes cumbersome. For example, keeping a large number of switches synchronized with each other requires extensive architecture, such as individual wires or PCB traces to each switch.

[0004] Examples of existing modular multilevel converters (MMC)2 include... Figure 1 As shown. From an energy conversion perspective, MMC offers many benefits, but also introduces many complexities. For example, Figure 1 The half-bridge MMC inverter topology shown has 2M modules, four per leg (and it is a three-phase MMC, therefore with three legs, as indicated by labels A, B, and C). Each of these modules 4 has a half-bridge switching circuit comprising two switches. All switches throughout the MMC 2 require synchronous control; therefore, each switch requires a control signal from the main microcontroller 6. Thus, the MMC 2 has 3 x 2M x 2 = 12M switches and correspondingly 12M separate signal paths (e.g., wires or traces) for delivering those switch signals from the microcontroller 6 (signal paths are shown as dashed lines). Furthermore, each module 4 typically has certain sensors, such as voltage sensors, current sensors, and / or temperature sensors, and transmits data from these sensors back to the main microcontroller, each signal transmitted along another signal path. Figure 1 Not shown in the diagram. In this device, the important thing is... Figure 1 All switching actions of all MOSFETs in the converter are synchronized to achieve proper voltage and current regulation at the input and output. The number of required signal paths presents scalability issues. Therefore, in the case of a large number of modules, some degree of multiplexing must be used to reduce the total number of signal paths and connections to the microcontroller. However, multiplexing is not always feasible. While MMCs typically operate at relatively low frequencies (e.g., 50Hz or 60Hz) and can therefore tolerate small variations in timing signals sent along multiple signal paths (e.g., introduced by multiplexing), this architecture begins to fail at higher frequencies due to insufficient synchronization of control signals.

[0005] According to a first aspect of the present invention, an electronic circuit is provided, comprising:

[0006] Main controller; and

[0007] Multiple modules;

[0008] The main controller includes:

[0009] A timing signal generator is configured to generate timing signals; and

[0010] A data signal generator is configured to generate data signals;

[0011] The main controller is configured to generate a combined signal based on both the timing signal and the data signal; and

[0012] The main controller is configured to broadcast the combined signal to the plurality of modules.

[0013] According to another aspect of the present invention, an electronic circuit is provided, comprising:

[0014] Main controller; and

[0015] Multiple modules;

[0016] The main controller includes:

[0017] A timing signal generator is configured to generate timing signals; and

[0018] A data signal generator is configured to generate data signals;

[0019] The main controller is configured to modulate the data signal onto the timing signal to generate a combined signal; and

[0020] The main controller is configured to broadcast the combined signal to the plurality of modules.

[0021] By broadcasting the timing signal along with the data signal to the modules, available bandwidth is effectively utilized without requiring numerous separate signal paths to each module (or virtually each switch) or time multiplexing of the signals. Therefore, accurate time synchronization can be achieved between the master controller and the modules (and thus across all modules), allowing the system to operate efficiently at high switching frequencies while maintaining good synchronization. Since the switches on the modules are not directly controlled by the master controller, the system provides a distributed architecture where the processing of received signals can be done locally on each module. For example, each module can have its own microcontroller, arranged to process the received data and control the module's various components (e.g., power electronic switches), while ensuring it is synchronized with the received timing signal, and thus synchronized with all other modules. This distributed architecture reduces the processing load on any single microcontroller (e.g., with...). Figure 1 Compared to existing designs depicted in [the previous design], where a single microcontroller in the main controller controls everything. Furthermore, each microcontroller can have its own local clock, with switching synchronization achieved via a common timing signal.

[0022] The term synchronization mentioned here simply means that modules share a common timing signal, thus maintaining a precise or well-defined time relationship with each other. For modules to be considered synchronized, they are not required to run uniformly or actually perform the same actions simultaneously, but only that the actions performed by each module occur in a well-defined time relationship with the actions of other modules.

[0023] Alternatively, the circuit is a power electronic circuit.

[0024] In some examples, the master controller is configured to modulate data signals onto timing signals to generate a combined signal. This advantageously provides a simple method for generating combined data and timing signals using simple, "off-the-shelf" components.

[0025] Alternatively, the timing signal can be a precisely timed trigger signal, wherein the timing signal generator can be configured to send the precisely timed trigger signal to the data signal generator, and wherein the data signal generator can be arranged to transmit data at precise times based on the precisely timed trigger signal. This advantageously allows the precise timing of the transmitted signal to be extracted from the transmitted signal, thereby providing the module with a timing signal accurate enough to use for synchronization. In other words, the data signal is sent at precise times, such that the start (or end) of the data can be considered a timing signal.

[0026] In some implementations, the precisely timed trigger signal and data signal can be generated by the same unit. For example, a precision data generator (such as a precision UART module) can generate its own precise timing signal and send its data signal at the precise time defined by the timing signal.

[0027] Not all modules may need to transmit data along with the timing signal, but in a preferred example, each of the multiple modules is arranged to extract a data signal from the combined signal. The data signal may contain information common to all modules and / or it may contain data specific to each module, which the relevant modules can extract through appropriate processing.

[0028] It should be understood that the data in the data signal can be independent of the data in the timing signal. In other words, the data signal and the timing signal can each be an independent data stream. Therefore, although these two data streams are combined and transmitted together, they are used for independent purposes. The timing signal is used for module time synchronization, while the data signal contains the digital data to be processed and used by the module.

[0029] The data signal is preferably a serial digital data signal. The serialization of the data makes it easy to modulate onto or transmit according to a timing signal. The digital nature of the data allows it to be processed by fast and efficient binary logic gates. The data to be transmitted can be converted into a serial data stream by any suitable means. However, a particularly suitable mechanism is the Universal Asynchronous Receiver Transmitter (UART) module. UART modules are common and are often included in standard microcontrollers, making them particularly suitable.

[0030] In some examples, the timing signal is a square wave. In this paper, "square wave" refers to any rectangular pulse wave with a sharp transition between phases, and is not limited to two phases of equal length ("on" and "off" phases). This also makes it particularly suitable for processing. The sharp edges of a square wave are ideal for timing purposes because timing information can be extracted from the signal quickly and efficiently using edge detection circuitry, thus easily achieving synchronization with minimal processing.

[0031] When the main controller is configured to modulate a data signal onto a timing signal to generate a combined signal, the main controller can be arranged to modulate the data signal onto a phase of the timing signal (i.e., an on or off phase). Generally, modulating the data signal onto the timing signal partially obscures the information in the timing signal because the combined signal is no longer a pure square wave. For the data portion of the combined signal to be easily demodulated, it needs to have sufficient amplitude for level detection. While the data and timing portions may have different amplitudes, this introduces further complexity to the demodulation scheme. In particular, in some circuits (such as MMCs or DC-DC converters), many modules may be connected in series, thus lacking a common ground reference (i.e., common ground potential). The received signal from the module is preferably passed through a digital isolator for easy analysis by the module's processor. To avoid complexity, it is therefore preferable that the data signal and timing signal have substantially the same amplitude. Thus, the data signal will, to some extent, distort the shape of the square wave generated by the main controller as the timing signal. However, even when the data signal is modulated onto only one phase of the timing signal, i.e. only the “low” phase or only the “high” phase of the timing signal, the other phase is still distinct and clearly shaped, thus providing clear information that can be used to extract timing information at the other end (i.e., in the module).

[0032] The main controller is preferably arranged to start after the phase begins with a minimum delay T. delay (see Figure 4a The data signal is modulated onto the phase of the timing signal. This delay also separates the data transmission from the edge of the phase of the timing signal on which the data is modulated by a defined amount. This ensures that the timing edge of the timing signal at the beginning of the aforementioned phase is still available to provide timing information to the module. This delay is preferably long enough that the receiving module can clearly distinguish the first edge of the timing signal from the first edge of the data signal. In some examples, the delay can be as short as 1.5 bits to clearly separate the timing edge from the start of the data. In some systems, it is not possible to know exactly when the data signal will be transmitted. However, as long as the delay T... delay Add the time T required to send the data signal data Less than the duty cycle DT of the timing signal s Then the module will successfully receive data and synchronize correctly with the host.

[0033] Data signals and timing signals can be combined using any form of modulation. However, in a preferred embodiment, the main controller is arranged to modulate the data signal onto the timing signal by performing a logical AND operation on the data signal and the timing signal. The use of logical AND operations is particularly simple and can be implemented at low cost, requiring little (or no) processing power. Using binary AND operations, i.e., operating only on high and low signals (i.e., "0" and "1"), means that the amplitudes of the data signal and timing signal must be the same as discussed above, but the advantage of simplicity is obvious. In particular, while AND operations can be implemented in software, for example as part of a microprocessor, in a preferred example, hardware AND gates are configured to perform logical AND operations. Hardware gates require no processing overhead at all and can simply combine the two input signals in real time as they are generated. In this case, the data signal generator (e.g., including a UART module) and the timing generator (e.g., including a pulse width modulator (PWM) module) can be implemented on a common microprocessor, where the output signals (data signal and timing signal) are output on the microprocessor's pins. Then, the AND gate can be a separate hardware component that takes input from two microprocessor output pins and provides its output directly to the module (e.g., via wires or PCB traces). It should be understood that for the AND operation to be valid, the data signal must be high when no data is being transmitted. This is the case with UART modules. In other examples, alternative logic can be used to combine timing signals with data signals that are typically low when not being transmitted (e.g., using XOR gates and NOT gates).

[0034] Since the switches in the modules are no longer directly controlled by the main controller, but are instead controlled based on a locally generated clock in each module, synchronization between modules can be achieved by generating a clock in each module, but resetting the clock periodically according to a timing signal broadcast by the main controller. Therefore, in a preferred embodiment, each of the multiple modules is arranged to reset its local clock based on a received combined signal.

[0035] Each of the multiple modules may include a PWM module arranged to generate a PWM output with a frequency and duty cycle, and arranged to reset its PWM output based on a reset signal, wherein a combined signal received from the main controller is combined with the PWM output of the PWM module to generate the reset signal. A PWM cycle consists of two phases, an "on" phase and an "off" phase. The duty cycle is the ratio of the "on" phase to the entire cycle. The frequency is the number of complete PWM cycles per second. This arrangement provides a feedback loop so that the output of the PWM module affects its own reset signal. The advantage of this arrangement is that it avoids problems that might otherwise occur in the data portion of the combined signal.

[0036] The combined signal itself cannot be used alone to reset the PWM module because the data portion embedded (e.g., modulated into) the signal would generate random and unpredictable resets of the PWM signal, preventing the desired synchronization from being achieved. Instead, using a feedback arrangement, the edge of the timing signal triggers a reset of the PWM module, initiating a square wave output similar to the timing signal. In some examples, the PWM resets upon receiving a rising edge. In other examples, the PWM resets upon receiving a falling edge. When this synchronization signal is subsequently fed back to the PWM reset input, it overrides any resets that might be triggered by state changes in the data portion of the combined signal, ensuring that the PWM module does not reset upon the combined signal input. Optionally, the combined signal received from the master controller is combined with the PWM output of the PWM module using a first logical OR operation. The logical OR operation is well-suited to allow the PWM output to override any state changes in the combined signal. Alternatively, the combined signal received from the master controller is combined with the PWM output of the PWM module using a logical AND operation. Optionally, a hardware AND gate is configured to perform this logical AND operation.

[0037] In some examples, once the PWM output is reset, it outputs a "1" (or "high") signal (defined by its frequency and duty cycle inputs) for the duration of its duty cycle. In some examples, the frequency and duty cycle inputs of the PWM module are matched to those of the master controller. Therefore, the reset input of the PWM module remains high during its duty cycle. In this example, this input resets on the rising edge, thus preventing further reset of the PWM module until the end of its duty cycle. It should be understood that in this arrangement, the duty cycle of the PWM module must be long enough to exceed the length of the modulated data portion of the combined signal to ensure that the data portion cannot reset the PWM module and therefore cannot cause unnecessary changes to the locally generated clock (i.e., the output of the PWM module).

[0038] As mentioned above, OR gates can be implemented in software, but preferably, hardware OR gates are configured to perform a first logical OR operation. Hardware OR gates are fast, inexpensive, and simple. As mentioned above, other functions of modules such as PWM modules and data decoders such as UART modules can be implemented on standard microcontrollers, while OR gates can be separate hardware components.

[0039] Preferably, the duty cycle of the square wave ensures that the modules will always be able to distinguish the edges of the timing signal, despite the variations in their PWM counters introduced during manufacturing. As mentioned above, the "on-time" of the PWM module needs to be long enough to last longer than the data portion of the combined signal. This can be achieved by appropriately setting the duty cycle, but also depends on the frequency (i.e., period) of the PWM signal. Typically, the PWM module counts up from 0 to a given value that defines the period (and frequency) before reset and restart (unless, of course, a reset is received earlier at the reset input). This period is divided into "on" and "off" times based on the duty cycle input. The PWM module counts based on a clock input (e.g., the local microprocessor clock). However, there is no guarantee that the clock used to drive the PWM module (and thus generate the local synchronization clock signal synchronized with the master controller) has the exact correct frequency. Manufacturing tolerances can cause variations of a few percentage points in clock speed. Therefore, there is no guarantee that the frequency of the PWM module input to each of the multiple modules is the same as the frequency used to generate the master timing signal. Conversely, it is desirable to ensure that the local PWM module does not run faster. For proper synchronization, the local PWM module must be reset via its reset input, triggered by a timing signal, rather than by the end of its own normal cycle. Therefore, preferably, the frequency of the PWM module is set lower than the frequency of the timing signal generated by the master controller. In a preferred embodiment, the frequency of the PWM module is no more than 10% lower than the frequency of the timing signal generated by the master controller. While in principle any lower frequency is suitable, in practice, it is advantageous to make the local frequency as close as possible to the expected frequency (while ensuring it is more persistent than the master controller's timing signal, even in the event of manufacturing changes), because the local controller can then be used for short periods without the master controller, and synchronization will not be significantly flawed. This could occur, for example, in the event of signal loss due to interference, or during startup before the first timing signal is received.

[0040] In addition to generating local timing signals that match (i.e. synchronize) with the master controller (or at least a portion of which is synchronized with the master controller, such as synchronizing with the rising or falling edge of each signal), the module also needs to receive (and in some examples demodulate) data signals transmitted along with the timing signals as part of a combined signal.

[0041] In an example where the main controller is arranged to modulate a data signal onto a timing signal to generate a combined signal, optionally, the received data is demodulated by one or more of a plurality of modules. For this purpose, each of the plurality of modules can be arranged to combine the combined signal received from the main controller with an inverted form of the PWM output of the PWM module to generate a local module data signal, which is then passed to a data signal decoder. The inverted output can be generated from a non-inverted output, for example, using a standard inverter circuit. In some cases, the PWM module may output both inverted and non-inverted versions of its signal as a standard; in this case, the inverted output can be obtained directly from the PWM module. In this case, when the main output is ON (“1” or “high”) to override the incoming combined signal, as described above, the inverted output is the opposite, and therefore OFF (“0” or “low”), thus allowing the data portion of the signal to be read. In a preferred example, the combined signal received from the main controller is combined with the inverted form of the PWM output of the PWM module using a second logical OR operation. As described above, a hardware OR gate can be configured to perform the second logical OR operation. Since the inverted output of the OR gate is "0" during the high-level period of the timing signal, the output remains unchanged. Therefore, it's clear that this OR gate is unnecessary. However, this is advantageous, especially when the transmitted signal is received by the UART module, as the idle UART module preferably receives a high signal. Therefore, the inverted PWM signal generates a high-level signal during the "off" phase of the PWM module to prevent erroneous operation of the UART when there is no data transmission.

[0042] The aforementioned mechanisms for transmitting timing and data signals allow critical real-time signals of the system to be reliably transmitted from the main controller to each of the multiple modules, thereby effectively utilizing available bandwidth while maintaining synchronization even at high frequencies, such as above 100 Hz, more preferably above 1 kHz, and even more preferably above 10 kHz. These real-time signals must arrive at the modules without delay to allow for proper circuit processing and rapid response. For example, switching signals in an MMC or DC-DC converter must be highly accurate in real time so that the circuit outputs the correct voltage as required. This information typically includes timing signals (to ensure synchronization) and target values ​​in some form, such as a target duty cycle (e.g., for switching circuits), target voltage, or target current. This target information can be transmitted in the data signal and received (and optionally demodulated) by the microprocessor of the local module, where it can be used to perform appropriate control of the local circuitry, such as appropriate switching control.

[0043] In addition to these real-time signals, other data typically needs to be transmitted between the main controller and the modules. In particular, additional sensor data from the modules should generally be fed back from the modules to help determine operational actions, such as health status or error detection. This sensor data typically does not need to be transmitted in real time but is correlated on a slower timescale. Therefore, attempting to transmit this data using the same mechanisms as the timing and data signals described above can be inefficient. Therefore, to allow the transmission of additional slower-time (or “soft-time”) signals independent of the critical real-time signals, the power electronic circuitry preferably further includes a bidirectional data transmission network comprising transceivers in the main controller and transceivers in at least one of the multiple modules, optionally in each of the multiple modules, the bidirectional data transmission network being arranged to transmit additional data between the main controller and at least one or optionally each of the multiple modules.

[0044] Bidirectional data transmission networks can operate on completely independent principles and with slower or less immediate transmission methods because sensor data is generally not as time-sensitive as timing signals and the information transmitted with them. In some preferred embodiments, the bidirectional data transmission network is asynchronous. To provide a non-limiting example, the bidirectional data transmission network could be a CAN bus (Controller Area Network). The bidirectional data transmission network can be arranged to transmit at least one of voltage measurements, current measurements, and temperature measurements from each of multiple modules to the main controller.

[0045] According to another aspect, the present invention provides a method for transmitting timing signals and data signals from a main controller to multiple modules in an electronic circuit, the method comprising:

[0046] The main controller generates timing signals;

[0047] The main controller generates data signals;

[0048] The main controller generates a combined signal based on timing signals and data signals; and

[0049] The main controller broadcasts the combined signal to each of the multiple modules.

[0050] According to another aspect, the present invention provides a method for transmitting timing signals and data signals from a main controller to each of a plurality of modules in an electronic circuit, the method comprising:

[0051] The main controller generates timing signals;

[0052] The main controller generates data signals;

[0053] The main controller modulates the data signal onto a timing signal to generate a combined signal; and

[0054] The main controller broadcasts the combined signal to each of the multiple modules.

[0055] It should be understood that all preferred or optional features described above with respect to the apparatus can be equally applied to the method. Features of any aspect or embodiment described herein can be applied, where appropriate, to any other aspect or embodiment described herein. When referring to different embodiments or sets of embodiments, it should be understood that these embodiments are not necessarily different, but can overlap.

[0056] Some preferred embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which:

[0057] Figure 1 A modular multilevel converter (MMC) as known in the art is shown.

[0058] Figure 2a The device according to the invention is shown schematically.

[0059] Figure 2b An alternative device according to the invention is shown schematically.

[0060] Figure 3a A more detailed view of the device according to the invention is shown schematically, such as... Figure 2a As shown.

[0061] Figure 3b A more detailed view of the device according to the invention is shown schematically, such as... Figure 2b As shown.

[0062] Figure 4a The combined output signal according to the present invention is shown.

[0063] Figure 4b An alternative combination output signal and a PWM output signal according to the present invention are shown.

[0064] Figure 1 A modular multilevel converter (MMC)2, as known in the art, is illustrated. Modular multilevel converters offer a wide range of advantages, including distributed power loss, extremely low losses during switching, and low switching block voltage, but at the cost of complexity. An MMC may comprise multiple "converter legs" ( Figure 1 Three are shown in the diagram, each leg containing two "converter arms". Each "arm" includes a large number of low-voltage MMC modules 4 connected in series with an inductor. The MMC 2 uses different switching times of various switching networks to achieve the desired voltage (V). A V B V CAs shown by the ellipsis in the figure, there are a large number of MMC modules 4. The dashed lines connecting each MMC module 4 to the main microcontroller 6 represent the numerous physically separate signal paths required to synchronously control all the switches of this MMC 2.

[0065] Each module 4 includes two solid-state switches (Q H and Q L In this case, it is a MOSFET, and a capacitor (or battery). Figure 1 In the half-bridge example, each module 4 of the converter requires two input signals to operate the MOSFET. For a larger number of modules 4, it becomes impractical to drive each gate signal through each of these modules 4 using a single microcontroller 6; therefore, in larger implementations, some form of multiplexing (typically time-based multiplexing) is preferred. The gate signal for each module 4 must be electrically isolated from the main controller 6 and cannot be directly driven by the microcontroller's pins.

[0066] For MMC 2 to function properly, it is important that the switching actions of all MOSFETs are synchronized so that the DC terminals of converter 2 (V) are aligned. DC+ and V DC- ) and the AC terminal (V) of converter 2 A V B V C Appropriate voltage and current regulation is achieved at this point. In addition to these synchronized gating signals, signals are also transmitted from each module 4 (the sensors within module 4) to the main controller 6. Each module 4 has its own voltage sensor, and there may be other sensors besides, such as current and temperature sensors. Figure 1 In the MMC 2, all signals described herein are routed to and from the main controller 6. On average, the MMC converter 2 will switch at a frequency of 50-60Hz (slow), which can be reasonably achieved using a single main controller 6. However, in some cases, it is desirable to achieve switching frequencies up to 20kHz, such as in large power converters where multiple microcontrollers or pulse-width modulation (PWM) modules must work together. In such cases, synchronization is crucial.

[0067] Therefore, one object of the preferred embodiments of the present invention is to solve the specific problem of synchronizing and controlling the switching action of a number of series-connected low-voltage power electronic switching networks, particularly controlling distributed DC-DC converters.

[0068] Figure 2aThe device according to the invention is schematically illustrated, arranged to synchronize signals sent by a main controller 26 to N modules 24. The signals from the main controller 26 are divided into "real-time" signals 8 and "soft-time" signals 10. Real-time signals 8 are those that must be transmitted at precise times for the device to function properly, for example... Figure 1 The gated signals of a MOSFET are real-time signals, requiring microsecond or nanosecond precision. Soft-time signals are signals that do not need to be transmitted at precise times; for example, temperature sensor signals are soft-time signals, and in some cases, they are also voltage and current sensor signals.

[0069] The soft timing signal 10 is communicated via a standard communication bus. The soft timing signal 10 is transmitted from the main controller 26 to the module 24 using any suitable transmitter / receiver 28a, and received by the module 24 via any suitable transmitter / receiver 28b. Preferably, the soft timing signal 10 is bidirectional, allowing data to be sent to and received by each module 24 and the main controller 26. In some examples, the same communication channel as the real-time signal 8 can be used to transmit the soft timing signal 10. However, in other embodiments, the transmission of the real-time signal 8, particularly the data along with the timing signal (discussed below), requires a significant portion of the line bandwidth, thus necessitating the use of a separate communication channel. A specific, non-limiting example of a suitable network for transmitting the soft timing signal is the CAN bus. The advantages of the CAN bus are its high robustness and ability to interconnect a large number of subsystems for data exchange, while saving on physical hardwired interconnects.

[0070] To transmit real-time data signals, a digital serial signal 22 (generated by digital serial signal generator 23) including real-time data packets is combined with a timing signal 20 (generated by timing signal generator 21) using an AND gate (or any specific implementation, such as a combination of logic gates, whose output is exactly the same as the output provided by the AND gate), i.e., the digital serial signal is modulated onto the timing signal. This combined real-time data 8 is transmitted to module 24, where the module uses timing decoder 30 and digital signal decoder 32 to separate the data. Digital serial signal 22 is used to simultaneously transmit real-time data packets to all modules at regular time intervals defined by timing signal generator 21. These real-time data packets can, for example, provide duty cycle information to module 24. Data packets can be sent at any time during the period when timing signal 20 is high. Timing signal 20 is used to synchronize clock and / or switching operations on module 24. Timing signal 20 is not used to help synchronize digital signal generator 23 and digital signal decoder 32.

[0071] Figure 2b Showing Figure 2a Alternatives to the equipment. Identical parts are marked with the same reference numerals. In Figure 2bThe equipment does not include Figure 2a Instead of separate timing signal generator 21 and digital serial signal generator 23, this example includes a precisely timed data transmission device 25. In this example, synchronization is achieved by generating digital serial signals at precisely timed intervals using a precisely timed digital serial signal generator (precisely timed data transmission device 25), such as a "precisely timed UART module." For example, such a component can be implemented in a field-programmable gate array (FPGA), an integrated circuit designed to be configured by a customer or designer after manufacturing. In this example, the digital signal generator outputs data at precise time intervals, which can then be extracted from the received signal and used as replacements for the timing signal 20 of the timing signal generator 21.

[0072] Figure 3a schematically shown Figure 2a Examples of possible specific implementations of the device are shown below. In this example, the invention is implemented using off-the-shelf components, and signals are encoded and decoded in hardware, thereby freeing up computation time for the main microcontroller 40 and the module microcontroller 42.

[0073] The soft-time signal 10 is input and output to the first CAN module 44a in the main microcontroller 40, and to the second CAN module 44b in the module microcontroller 42, as indicated by their respective arrows. The first CAN module 44a transmits data to the CAN transceiver 41, which then transmits the data via the CAN bus 43 to the isolated CAN transceiver 45 within the module 24.

[0074] To transmit real-time signals, the pulse width modulation module (PWM module) 46 is provided with a specific master period, which is a unitless count value referred to here as P, and a specific "on" time D (i.e., duty cycle). This "on" time D is a number between 0 and 1, representing the portion of the period P to be "on". The PWM module counts from 0 to P (the counting rate depends on the local clock of the main microcontroller 40). When the count is 0, the timing signal generated by the PWM module 46 goes high. The PWM module counts from 0 to P, and when a specific value (the product of P and D) is reached, the signal falls from high to low. The counter then resets when the total value P is reached. The duty cycle D defines the length of the high-level portion of the timing signal, and it is best defined to be long enough that all the required data can be placed within a portion of the high-level signal.

[0075] Preferably, the data output is synchronized with a timing signal generated by the PWM module 46. This can be optionally achieved by the PWM module 46 transmitting a trigger signal 48 to the Universal Asynchronous Receiver Transmitter (UART) module 50 when the timing signal goes high (e.g., when the PWM count is 0). This allows the UART module 50 to begin transmitting data already generated by the main microcontroller 40 when the timing signal goes high. This maximizes the possible duration of data transmission. A small delay can be introduced to provide clear separation between the rising edge of the data signal and the rising edge of the PWM timing signal.

[0076] The timing signal 20 generated by the PWM module and the data signal 22 transmitted by the UART module 50 are combined using an AND gate 52 or an equivalent AND gate arrangement. This real-time signal 8 is then transmitted (i.e. broadcast) to the digital isolator 54 within each module 24.

[0077] The purpose of digital isolator 54 is to allow communication between two different systems with different ground potentials. Digital isolator 54 is needed because each module 24 is "stacked" on top of another, and the ground signal of each module is referenced to the positive signal of the module "below" it in the stack, rather than each module referencing a common ground. Therefore, digital isolator 54 is used.

[0078] The first OR gate 56 or equivalent arrangement is configured to take the output of the digital isolator 54 as the first input and the output of the first module PWM 58 as the second input. The module microcontroller 42 provides the first module PWM 58 with a duty cycle D that is the same as the duty cycle D of the PWM module 46 of the main controller 26. The time period of the first module PWM 58 is 1.05P, meaning it is set to provide 1.05 times the period of the main PWM 46 of the main controller 26. In this embodiment, the first module PWM 58 is reset by a rising edge at its reset input. The rising edge of the input signal from the digital isolator 54 thus causes the first module PWM 58 to reset its counter. After receiving this rising edge and resetting the first module PWM 58, the first module PWM 58 then outputs a high signal X to the OR gate 56, with a duty cycle D that is the same as that of the PWM module 46 of the main controller 26. The duty cycle D is preset and independent of the input signal received by the first module PWM 58. The period of the first module PWM 58 is set to be 1.05 times longer than the period of the master controller PWM 46, so that the first module PWM 58 will not reset to a high signal PWM 46 earlier than the master controller reaches its maximum time period, due to a faster local clock (typically provided by the module microcontroller 42), but only as a result of receiving a rising edge signal from the digital isolator 54. This can, of course, be achieved using a period much larger than 1.05P, or even a period of P=∞. However, in most power electronics applications, a period of P=∞ is undesirable because no switching will occur without an external reset, and this could have disastrous consequences. In one embodiment of the invention, module 24 is used to power on the host 26, and setting this time period to infinity would cause undesirable problems in the process. The first module PWM 58 outputs this high signal as an input to OR gate 56 to ensure that PWM 58 is not reset due to a rising edge generated by the data signal received from the digital isolator 54. Therefore, the PWM 58 is triggered by the rising edge of the timing signal and then overwrites the data signal within a period defined by the duty cycle D (which is equal to the product of P and D), a period chosen to be long enough to last longer than the data transmission.

[0079] The first module, PWM 58, also outputs a signal. This signal is the two's complement of signal X, meaning that where the timing signal is high, the two's complement signal is low, and vice versa. The signal is provided as the first input to the second OR gate 60 or its equivalent. The second input to the second OR gate 60 is the signal received from the digital isolator 54. The output of the second OR gate 60 causes the complement signal to be generated during the "high" period of the original timing signal. The output of the second OR gate 60 will be low, so the output of the second OR gate 60 retains all the content during the "high" cycle in the output, thus the output of the second OR gate 60 is a reconstruction of the digital serial signal 22 generated by the digital serial signal generator 23. The output signal of the second OR gate 60 is sent to the receive port of the UART module 62, which recovers... The data signals are input to the main UART 50.

[0080] Considering the example of a power converter, each module 24 could then use this data to, for example, set the duty cycle (or on-time) of another pulse width modulator (on each module), such as the one involved in the switching process of a particular module 24. All modules 24 receive the same duty cycle information set by the host 26 to provide the desired output voltage. The module microcontroller 42 can optionally implement this information directly. Alternatively, the module microcontroller 42 of each module 24 can then individually adjust the duty cycle selected by the host 26 based on their own individual internal states to provide the desired voltage more accurately.

[0081] Figure 3b schematically shown Figure 2b Examples of possible specific implementations of the device represented in the text. Figure 3b Similar components have been used with Figure 3a The same reference numerals are used for labeling, but in this example, a precisely timed UART module 51 is used instead. Figure 3a The PWM module 46 and UART module 50 are used. Although UART module 51 is referred to herein as a "precisely timed" UART module, it can actually be the same as a standard UART module (i.e., UART module 50), but it can provide a highly accurate trigger signal 31 indicating the precise time for the start of data transmission. Modules 24 can then use the start, end, or any other suitable point in the data transmission signal to reset their timers, thereby achieving synchronization. In this example, the timing signal is therefore the data trigger signal 31 provided to UART module 51 by trigger timing signal generator 53, which triggers UART module 51 to output certain data at precisely timed time intervals. The precision of transmitting this data allows each module 24 to derive a timing signal from the received signal, which can then be used for synchronization. Due to the use of the precisely timed UART module 51, the received signal can be directly fed into UART module 62 to recover the data signal. No need to enter an OR gate first.

[0082] In this example, the idle output of UART module 51 is "1" or "high," so AND gate 57 receives a high signal from UART 51 when no data is being transmitted. The device is arranged such that another input to AND gate 57 is... The complement of the signal output by the PWM. As described below, the PWM module 58 is arranged to output a "high" signal during the data transmission cycle and a "low" signal otherwise, so that the signal received by the AND gate 57... The signal is "low" during the data transmission cycle and "high" otherwise, as shown in the figure. The PWM module 58 is arranged to reset on the falling edge of the input signal. To signal the start of data transmission, a "low" signal (possibly as part of a longer pattern) is added to the beginning of the transmission signal before the data packet. The "high" to "low" transition transmitted by the UART module 51 causes AND gate 57 to switch to a "low" signal, which in turn produces a falling edge on the reset input of the first module PWM 58. This falling edge signals the PWM module 58 of each module to reset its counter and allows the PWM 58 to recognize that data transmission has begun.

[0083] Then, as described above, the PWM module 58 counts to a preset value, and when it counts to this value, it outputs a "low" signal. The "low" signal is fed back to AND gate 57. This "low" signal means that regardless of the signal provided to the AND gate by the data packet, AND gate 57 will maintain an output "low" signal and therefore will not reset PWM 58. Once the preset count value P*D is reached, the PWM output signal... The signal returns to "high", but at this point the data transmission will end and the combined signal will return to "high". Therefore, a reset will not occur until the next falling edge of the combined signal is received from the digital isolator 54 (or until the total cycle of PWM 58 has been reached, but as mentioned above, PWM 58 is arranged so that this cycle should never be reached before a new falling edge is received at the reset input).

[0084] Figure 4a It shows the result of Figure 2a and Figure 3a The AND gate outputs possible combination signals 80, where the data signal is modulated onto the timing signal. As described above, the main controller 26 is preferably arranged with a minimum delay T. delay The data signal is modulated onto the phase of the timing signal. T delay exist Figure 4a The interval T between data packets is shown as indicated by reference numeral 82 in the attached diagram. S The length T of the data packet is indicated by the symbol 74 in the attached diagram. data This is indicated by reference numeral 76 in the attached diagram. In this case, unlike the precisely timed UART module 51, the length of the data signal 76 may differ from the timing signal DT shown by reference numeral 84 in the attached diagram. S The length of the data packet T data You can send DT at any time S .

[0085] Figure 4b The diagram shows a representation of the combined timing and data signals 70, which is... Figure 2b and Figure 3b The output of the transmission device 25 or UART module 51 shown, and the representation of timing signals, 72, the timing signal is from Figure 2b and Figure 3b The PWM module 58 of the device shown outputs a signal. The precisely timed UART module 51 outputs a signal where the interval between data packets is T. S The data packet is marked as 74 and its length is T. data 76. The timing signal 72 output by the PWM module is arranged to have the same period T as the combined signal 70. S 74, and the duty cycle D of PWM 58 is configured to make the "off time" of the PWM output signal. The length of 78 is at least equal to the data packet T. data The length of 76 is the same. In the example shown, the length of "disconnection time" is the same as that of data packet T. data The length is the same as 76, but the "disconnect time" can be longer than that; for example, the "disconnect time" can be longer than the packet length T. data It is 1.05 times longer to make the process more robust.

[0086] Those skilled in the art will appreciate that the invention has been described by way of description of one or more particular embodiments thereof, but is not limited thereto; many variations and modifications are possible within the scope of the appended claims.

Claims

1. An electronic circuit, comprising: Main controller; and Multiple modules, each including a local clock; The main controller includes: A timing signal generator is configured to generate timing signals; and A data signal generator is configured to generate a data signal, wherein the data in the data signal is independent of the data in the timing signal; The main controller is configured to generate a combined signal based on both the timing signal and the data signal. The main controller is configured to broadcast the combined signal to the plurality of modules; and Each of the plurality of modules is arranged to reset the local clock of the module based on a received combined signal.

2. The electronic circuit according to claim 1, wherein, Each of the plurality of modules is arranged to extract the data signal from the combined signal.

3. The electronic circuit according to claim 1 or 2, wherein, The data signal is a serial digital data signal.

4. The electronic circuit according to claim 1 or 2, wherein, The timing signal is a precisely timed trigger signal, the timing signal generator is configured to send the precisely timed trigger signal to the data signal generator, and the data signal generator is arranged to transmit data at precise time based on the precisely timed trigger signal.

5. The electronic circuit according to claim 1, wherein, The main controller is configured to modulate the data signal onto the timing signal to generate the combined signal.

6. The electronic circuit according to claim 5, wherein, The timing signal is a square wave.

7. The electronic circuit according to claim 6, wherein, The main controller is configured to modulate the data signal onto a phase of the timing signal.

8. The electronic circuit according to claim 7, wherein, The main controller is configured to modulate the data signal onto the phase of the timing signal, with a delay after the start of the phase.

9. The electronic circuit according to any one of claims 6, 7 or 8, wherein, The main controller is configured to modulate the data signal onto the timing signal by performing a logical AND operation on the data signal and the timing signal.

10. The electronic circuit according to claim 9, wherein, The hardware AND gate is configured to perform the logical AND operation.

11. The electronic circuit according to claim 1, wherein, Each of the plurality of modules includes a PWM module, the PWM module being arranged to generate a PWM output having a frequency and a duty cycle, and being arranged to reset its PWM output based on a reset signal, wherein the combined signal received from the main controller is combined with the PWM output of the PWM module to generate the reset signal.

12. The electronic circuit according to claim 11, wherein, The combined signal received from the main controller is combined with the PWM output of the PWM module using a first logical OR operation.

13. The electronic circuit according to claim 12, wherein, The hardware OR gate is configured to perform the first logical OR operation.

14. The electronic circuit according to claim 13, wherein, The combined signal received from the main controller is combined with the PWM output of the PWM module using a logical AND operation.

15. The electronic circuit according to claim 14, wherein, The hardware AND gate is configured to perform the aforementioned logical AND operation.

16. The electronic circuit according to any one of claims 11 to 15, wherein, The frequency of the PWM module is set to be lower than the frequency of the timing signal generated by the main controller.

17. The electronic circuit according to claim 16, wherein, The frequency of the PWM module is no more than 10% lower than the frequency of the timing signal generated by the main controller.

18. The electronic circuit according to claim 11, wherein, Each of the plurality of modules is arranged to combine the combined signal received from the main controller with the inverted form of the PWM output of the PWM module to generate a local module data signal, which is then passed to a data signal decoder.

19. The electronic circuit according to claim 18, wherein, The combined signal received from the main controller is combined with the inverted form of the PWM output of the PWM module using a second logical OR operation.

20. The electronic circuit according to claim 19, wherein, The hardware OR gate is configured to perform the second logical OR operation.

21. The electronic circuit according to claim 1 or 2, further comprising a bidirectional data transmission network, the bidirectional data transmission network including a transceiver in the main controller and a transceiver in each of the plurality of modules, the bidirectional data transmission network being arranged to transmit additional data between the main controller and each of the plurality of modules.

22. The electronic circuit according to claim 21, wherein, The bidirectional data transmission network is asynchronous.

23. The electronic circuit according to claim 21, wherein, The bidirectional data transmission network is configured to transmit at least one of the voltage measurement, current measurement, and temperature measurement values ​​from each of the plurality of modules to the main controller.

24. A method for transmitting timing signals and data signals from a main controller to multiple modules in an electronic circuit, the method comprising: The main controller generates timing signals; The main controller generates a data signal, wherein the data in the data signal is independent of the data in the timing signal; The main controller generates a combined signal based on the timing signal and the data signal; The main controller broadcasts the combined signal to each of the multiple modules; and Each of the plurality of modules resets its local clock based on the received combined signal.

25. The method of claim 24, wherein the main controller generates the combined signal by: The main controller modulates the data signal onto the timing signal to generate a combined signal.

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