Imaging device, method in the imaging device, and electronic apparatus

Abstract

Improve the image quality in a solid-state imaging device that performs time delay integration. A correlated double sampling circuit generates a frame in which a predetermined number of lines are arranged, and each line includes a plurality of digital signals. A TDI frame memory retains the (K-1)th frame generated before the Kth frame. A time delay integration circuit performs a time delay integration process of adding a line having a predetermined address in the Kth frame and a line having an address at a certain distance from the predetermined address in the (K-1)th frame.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging device. In particular, the present technology relates to a solid-state imaging device that performs analog-to-digital conversion for each pixel, an imaging apparatus, and a method of controlling the solid-state imaging device. Background Art

[0002] To date, time delay integration (TDI) sensors have been used in factory automation (FA) or aerial photography fields. A TDI sensor performs TDI processing for integrating the amount of electric charge with a time shift corresponding to the moving speed of an object. For example, a solid-state imaging device has been proposed which performs TDI processing by using a charge coupled device (CCD) that transfers electric charge with a time shift and a circuit that accumulates the amount of its electric charge in a floating diffusion layer to generate an integration signal (for example, refer to NPL1).

[0003] Citation List

[0004] Non-Patent Literature

[0005] NPL 1: Hyun Jung Lee et al., “Charge-Coupled CMOS TDI Imager”, [online], [searched on July 22, 2019], Internet <URL: http: / / www.imagesensors.org / Past%20Workshops / 2017%20Workshop / 2017%20Papers / P16.pdf> Summary of the Invention

[0006] Technical Problem

[0007] In the related art, improvement in luminance and reduction in noise are achieved by TDI processing. However, in the above-described solid-state imaging device, as the number of pixels at the charge transfer source increases, it is necessary to increase the capacity of the floating diffusion layer at the charge transfer destination. The increase in capacity causes deterioration of pixel sensitivity, and further causes deterioration of the image quality of image data due to the deterioration of pixel sensitivity. As described above, the solid-state imaging device has a problem of deterioration of image quality due to deterioration of sensitivity.

[0008] The present technology has been made in view of such circumstances. It is necessary to improve the image quality in a solid-state imaging device that performs time delay integration.

[0009] Technical Solution to Solve the Problem

[0010] The present technology is made to solve the above problems. According to a first aspect of the present technology, there is provided an imaging device, which includes: a first substrate including a plurality of pixels arranged in a matrix, each of the plurality of pixels being configured to output a pixel signal; and a second substrate stacked with the first substrate, the second substrate including: at least a part of an analog-to-digital circuit configured to output a digital signal based on the pixel signal; an arithmetic circuit configured to receive the digital signal; a first storage circuit connected to the arithmetic circuit; a second storage circuit connected to the arithmetic circuit; and an image processing circuit connected to the second storage circuit.

[0011] According to a second aspect of the present technology, there is provided a method in an imaging device, the method including: outputting a pixel signal from each of a plurality of pixels arranged in a matrix; outputting a digital signal based on the pixel signal from an analog-to-digital circuit; and receiving the digital signal by an arithmetic circuit, wherein the imaging device includes: a first substrate including the plurality of pixels; and a second substrate stacked with the first substrate and including at least a part of the analog-to-digital circuit, the arithmetic circuit, a first storage circuit, a second storage circuit, and an image processing circuit.

[0012] According to a third aspect of the present technology, there is provided an electronic device, which includes: an optical component configured to converge and guide incident light; and an imaging device configured to receive the incident light, the imaging device including: a first substrate including a plurality of pixels arranged in a matrix, each of the plurality of pixels being configured to output a pixel signal in response to the incident light; and a second substrate stacked with the first substrate, the second substrate including: at least a part of an analog-to-digital circuit configured to output a digital signal based on the pixel signal; an arithmetic circuit configured to receive the digital signal; a first storage circuit connected to the arithmetic circuit; a second storage circuit connected to the arithmetic circuit; and an image processing circuit connected to the second storage circuit.

[0013] In addition, in the first, second, or third aspect, the arithmetic circuit may include a column CDS processing circuit and a column TDI arithmetic circuit.

[0014] In addition, in the first, second, or third aspect, a frame of the digital signal may include a first phase level and a second phase level, and the first storage circuit may be configured to store the first phase level.

[0015] In addition, in the first, second, or third aspect, the arithmetic circuit may be configured to obtain a difference between the second phase level and the first phase level and store the difference in the first storage circuit.

[0016] In addition, in the first, second, or third aspect, the image processing circuit may be configured to perform a predetermined first image processing on the difference. The first image processing may be at least one of an image recognition process, a black level correction process, an image correction process, and a demosaicing process.

[0017] In addition, in the first, second, or third aspect, the arithmetic circuit may be configured to: after the image processing circuit performs the predetermined first image processing, obtain a sum of a predetermined first line of the frame and a second line adjacent to the first line of the frame, and store the sum in the second storage circuit.

[0018] In addition, in the first, second, or third aspect, the image processing circuit may be configured to perform a second image processing on the sum. The second substrate may include an output circuit configured to output a result of the second image processing.

[0019] In addition, in the first, second, or third aspect, each pixel may include a floating diffusion portion.

[0020] Advantages of the present invention

[0021] Compared with the case of transferring the charge amounts of a plurality of pixels to a floating diffusion layer, it is possible to improve pixel sensitivity using a small-capacity floating diffusion layer. The improvement in pixel sensitivity can improve the image quality of image data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a block diagram of an exemplary configuration of an imaging device in a first embodiment of the present technology.

[0023] Figure 2 Illustratively shows an exemplary use of an imaging device in a first embodiment of the present technology.

[0024] Figure 3 Illustrates an exemplary layered structure of a solid-state imaging element in a first embodiment of the present technology.

[0025] Figure 4 is a block diagram of an exemplary configuration of an optical receiving chip in a first embodiment of the present technology.

[0026] Figure 5 is a block diagram of an exemplary configuration of a circuit chip in a first embodiment of the present technology.

[0027] Figure 6 Illustrates an exemplary configuration of a pixel analog-to-digital (AD) conversion unit in a first embodiment of the present technology.

[0028] Figure 7 It is a block diagram of an exemplary configuration of an analog-to-digital converter (ADC) in the first embodiment of the present technology.

[0029] Figure 8 It is a circuit diagram of an exemplary configuration of a pixel circuit, a differential input circuit, and a positive feedback circuit in the first embodiment of the present technology.

[0030] Figure 9 It is a block diagram of an exemplary configuration of a signal processing circuit in the first embodiment of the present technology.

[0031] Figure 10 It is a circuit diagram of an exemplary configuration of an arithmetic circuit in the first embodiment of the present technology.

[0032] Figure 11 It illustrates an exemplary state of the arithmetic circuit in the first embodiment of the present technology when the P-phase level of the first frame is retained.

[0033] Figure 12 It illustrates an exemplary state of the arithmetic circuit in the first embodiment of the present technology when CDS processing is performed on the first frame.

[0034] Figure 13 It illustrates an exemplary state of the arithmetic circuit in the first embodiment of the present technology when a frame is retained.

[0035] Figure 14 It illustrates an exemplary state of the arithmetic circuit in the first embodiment of the present technology when the P-phase level of the second frame is retained.

[0036] Figure 15 It illustrates an exemplary state of the arithmetic circuit in the first embodiment of the present technology when CDS processing is performed on the second frame.

[0037] Figure 16 It illustrates an exemplary state of the arithmetic circuit in the first embodiment of the present technology when TDI processing is performed on the second frame.

[0038] Figure 17 It illustrates an exemplary TDI processing in the first embodiment of the present technology.

[0039] Figure 18 It is a timing diagram of an exemplary operation of a solid-state imaging element in the first embodiment of the present technology.

[0040] Figure 19 Illustrative diagrams show the calculations of the signal processing circuit in the first embodiment of the present technology.

[0041] Figure 20Illustrated is an exemplary state of a solid-state imaging device while maintaining the P-phase level in a first embodiment of the present technology.

[0042] Figure 21 Illustrated is an exemplary state of a solid-state imaging device during CDS processing in a first embodiment of the present technology.

[0043] Figure 22 Illustrated is an exemplary state of a solid-state imaging device during image processing after CDS processing in a first embodiment of the present technology.

[0044] Figure 23 Illustrated is an exemplary state of a solid-state imaging device during TDI processing in a first embodiment of the present technology.

[0045] Figure 24 Illustrated is an exemplary state of a solid-state imaging device during image processing after TDI processing in a first embodiment of the present technology.

[0046] Figure 25 Illustrated is an exemplary state of a solid-state imaging device when outputting a frame in a first embodiment of the present technology.

[0047] Figure 26 Is a flowchart of an exemplary operation of a solid-state imaging device in a first embodiment of the present technology.

[0048] Figure 27 Is a block diagram of an exemplary configuration of a circuit chip in a second embodiment of the present technology.

[0049] Figure 28 Is a block diagram of an exemplary configuration of a column CDS processing unit and a column TDI arithmetic unit in a second embodiment of the present technology.

[0050] Figure 29 Is a timing diagram of an exemplary operation of a solid-state imaging device in a second embodiment of the present technology.

[0051] Figure 30 Is a circuit diagram of an exemplary configuration of a CDS circuit and a TDI circuit in a third embodiment of the present technology.

[0052] Figure 31 Is a block diagram of an exemplary configuration of a signal processing circuit in a third embodiment of the present technology.

[0053] Figure 32 Is a circuit diagram of an exemplary configuration of a CDS circuit and a TDI circuit in a fourth embodiment of the present technology.

[0054] Figure 33 Is a block diagram of an exemplary configuration of a signal processing circuit in a fourth embodiment of the present technology.

[0055] Figure 34 It is a circuit diagram of an exemplary configuration of a CDS circuit in the fifth embodiment of the present technology.

[0056] Figure 35 It is a block diagram of an exemplary configuration of a signal processing circuit in the fifth embodiment of the present technology. Detailed implementation manners

[0057] Hereinafter, manners for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.

[0058] 1. First Embodiment (Example of Performing TDI Processing after CDS Processing)

[0059] 2. Second Embodiment (Example of Different Arrangement Positions of CDS Circuit and TDI Circuit and Performing TDI Processing after CDS Processing)

[0060] 3. Third Embodiment (Example of Adding a Buffer and Performing TDI Processing after CDS Processing)

[0061] 4. Fourth Embodiment (Example of Sharing a CDS Circuit between Two Columns and Performing TDI Processing after CDS Processing)

[0062] 5. Fifth Embodiment (Example of Sharing a CDS Circuit between Four Columns and Performing TDI Processing after CDS Processing)

[0063] <1. First Embodiment>

[0064] "Exemplary Configuration of Imaging Device"

[0065] Figure 1 It is a block diagram of an exemplary configuration of an imaging device 100 in the first embodiment of the present technology. The imaging device 100 that captures image data includes an optical unit 110, a solid-state imaging element 200, a storage unit 120, a control unit 130, and a communication unit 140.

[0066] The optical unit 110 converges incident light and guides the incident light to the solid-state imaging element 200. The solid-state imaging element 200 captures image data. The solid-state imaging element 200 supplies the image data to the storage unit 120 through a signal line 209.

[0067] The storage unit 120 stores the image data. The control unit 130 controls the solid-state imaging element 200 so that the solid-state imaging element 200 captures image data. For example, the control unit 130 supplies a vertical synchronization signal VSYNC indicating a shooting timing to the solid-state imaging element 200 through a signal line 208.

[0068] The communication unit 140 reads the image data from the storage unit 120 and transmits the image data outward.

[0069] Figure 2 The explanatory diagram illustrates an exemplary use of the imaging device 100 in the first embodiment of the present technology. As illustrated, the imaging device 100 is used, for example, in a factory provided with a conveyor belt 510.

[0070] The conveyor belt 510 moves the object 511 at a constant speed in a predetermined direction. The imaging device 100 fixed near the conveyor belt 510 captures the object 511 to generate image data. For example, the image data is used to check for defects and the like. Thus, FA is achieved.

[0071] Note that the imaging device 100 captures the object 511 moving at a constant speed, but the configuration is not limited thereto. Like aerial photography, the imaging device 100 can capture the object while moving toward the object at a constant speed.

[0072] "Exemplary configuration of the solid-state imaging element"

[0073] Figure 3 The diagram illustrates an exemplary layered structure of the solid-state imaging element 200 in the first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and a light-receiving chip 201 stacked on the circuit chip 202. The above two chips are electrically connected through connection parts such as vias. Note that instead of vias, Cu-Cu bonding or bumps can achieve the electrical connection of the above two chips.

[0074] Figure 4 It is a block diagram of an exemplary configuration of the light-receiving chip 201 in the first embodiment of the present technology. The light-receiving chip 201 is provided with a pixel array unit 210 and a peripheral circuit 212.

[0075] The pixel array unit 210 includes a plurality of pixel circuits 220 arranged in a two-dimensional grid pattern. In addition, the pixel array unit 210 is divided into a plurality of pixel blocks 211. For example, each pixel block 211 includes pixel circuits 220 arranged in a matrix of 4 rows × 2 columns.

[0076] For example, circuits for supplying a direct current (DC) voltage and the like are arranged in the peripheral circuit 212.

[0077] Figure 5It is a block diagram of an exemplary configuration of a circuit chip 202 in a first embodiment of the present technology. A digital-to-analog converter (DAC) 251, a pixel driving circuit 252, a time code generation unit 253, a pixel AD conversion unit 254, and a vertical scanning circuit 255 are arranged on the circuit chip 202. A control circuit 256, a signal processing circuit 400, an image processing circuit 260, and an output circuit 257 are also arranged on the circuit chip 202.

[0078] The DAC 251 generates a reference signal by digital-to-analog (DA) conversion within a predetermined AD conversion cycle. For example, a sawtooth ramp signal is used as the reference signal. The DAC 251 supplies the reference signal to the pixel AD conversion unit 254.

[0079] The time code generation unit 253 generates a time code indicating the time within the AD conversion cycle. The time code generation unit 253 is implemented by a counter, for example. For example, a Gray code counter is used as the counter. The time code generation unit 253 supplies the time code to the pixel AD conversion unit 254.

[0080] The pixel driving circuit 252 drives each pixel circuit 220 so that each pixel circuit 220 generates an analog pixel signal.

[0081] The pixel AD conversion unit 254 performs AD conversion to convert the analog signal (i.e., the pixel signal) of each pixel circuit 220 into a digital signal. The pixel AD conversion unit 254 is divided into a plurality of clusters 300. The clusters 300 are set one-to-one with the pixel blocks 211. Each cluster 300 converts the analog signal in the corresponding pixel block 211 into a digital signal.

[0082] The pixel AD conversion unit 254 generates image data in which digital signals are arranged as a frame by AD conversion, and supplies the image data to the signal processing circuit 400. Hereinafter, each group of digital signals arranged in the horizontal direction in the frame is referred to as a "line". A row address indicating the position of the line in the vertical direction is assigned to each line.

[0083] The vertical scanning circuit 255 drives the pixel AD conversion unit 254 so that the pixel AD conversion unit 254 performs AD conversion.

[0084] The signal processing circuit 400 performs predetermined signal processing on the frame. As the signal processing, various types of processing including CDS processing and TDI processing are performed. The signal processing circuit 400 supplies the processed frame to the image processing circuit 260.

[0085] The image processing circuit 260 performs predetermined image processing on the frames from the signal processing circuit 400. As the image processing, image recognition processing, black level correction processing, image correction processing, demosaicing processing, or the like is performed. The image processing circuit 260 supplies the processed frames to the output circuit 257.

[0086] The output circuit 257 outputs the frames after image processing to the outside.

[0087] The control circuit 256 synchronizes with the vertical synchronization signal VSYNC to control the respective operation timings of the DAC 251, the pixel driving circuit 252, the vertical scanning circuit 255, the signal processing circuit 400, the image processing circuit 260, and the output circuit 257.

[0088] (Exemplary configuration of the pixel AD conversion unit)

[0089] Figure 6 An exemplary configuration of the pixel AD conversion unit 254 in the first embodiment of the present technology is illustrated. The pixel AD conversion unit 254 includes a plurality of ADCs 310 arranged in a two-dimensional grid pattern. The ADCs 310 are arranged one-to-one with the pixel circuits 220. In the case where the number of rows and columns of the pixel circuits 220 are N (N is an integer) and M (M is an integer), respectively, N×M ADCs 310 are arranged.

[0090] The same number of ADCs 310 as the number of pixel circuits 220 in the pixel block 211 are arranged in each cluster 300. In the case where the pixel circuits 220 are arranged in a 4-row×2-column matrix in each pixel block 211, the ADCs 310 are arranged in a 4-row×2-column matrix in each cluster 300.

[0091] Each ADC 310 performs AD conversion on the analog pixel signal generated by the corresponding pixel circuit 220. In the AD conversion, each ADC 310 compares the pixel signal with a reference signal and retains the time code when the comparison result is inverted. Then, each ADC 310 outputs the retained time code as the digital signal after AD conversion.

[0092] In addition, repeater units 360 are arranged for each column of the cluster 300. In the case where the number of columns of the cluster 300 is M / 2, M / 2 repeater units 360 are arranged. Each repeater unit 360 transmits the time code. Each repeater unit 360 transmits the time code from the time code generation unit 253 to the ADC 310. In addition, each repeater unit 360 transmits the digital signal from each ADC 310 to the signal processing circuit 400. The transmission of the digital signal is also referred to as the "reading" of the digital signal.

[0093] In addition, in the figure, the numbers in each pair of parentheses indicate the exemplary read order of the digital signals of the ADC 310. For example, first, the digital signals of the odd-numbered columns in the first row are read, second, the digital signals of the even-numbered columns in the first row are read. Third, the digital signals of the odd-numbered columns in the second row are read, and fourth, the digital signals of the even-numbered columns in the second row are read. Thereafter, similarly, the digital signals of the odd-numbered columns and the digital signals of the even-numbered columns in each row are read in sequence.

[0094] Note that the ADC 310 is arranged one-to-one with the pixel circuit 220, but the configuration is not limited thereto. A plurality of pixel circuits 220 may share one ADC 310.

[0095] "Exemplary Configuration of the ADC"

[0096] Figure 7 is a block diagram of an exemplary configuration of the ADC 310 in the first embodiment of the present technology. The ADC 310 includes a differential input circuit 320, a positive feedback circuit 330, a latch control circuit 340, and a plurality of latch circuits 350.

[0097] In addition, a part of the differential input circuit 320 and the pixel circuit 220 are arranged on the light receiving chip 201. The remaining part of the differential input circuit 320 and the circuits at its subsequent stage are arranged on the circuit chip 202.

[0098] The differential input circuit 320 compares the pixel signal from the pixel circuit 220 with the reference signal from the DAC 251. The differential input circuit 320 supplies a comparison result signal indicating the comparison result to the positive feedback circuit 330.

[0099] The positive feedback circuit 330 adds a partial output to the input (comparison result signal), and supplies the input with the added partial output as an output signal VCO to the latch control circuit 340.

[0100] According to the control signal xWORD from the vertical scan circuit 255, the latch control circuit 340 causes the plurality of latch circuits 350 to hold the time code when the output signal VCO is inverted.

[0101] Under the control of the latch control circuit 340, the latch circuit 350 holds the time code from the repeater unit 360. The latch circuit 350 is set for the bit length of the time code. For example, when the time code is 15 bits, 15 latch circuits 350 are arranged in the ADC 310. In addition, the repeater unit 360 reads the held time code as a digital signal after AD conversion.

[0102] The configuration illustrated in the figure allows the ADC 310 to convert the pixel signal from the pixel circuit 220 into a digital signal.

[0103] "Exemplary Configuration of Pixel Circuit, Differential Input Circuit, and Positive Feedback Circuit"

[0104] Figure 8 It is a circuit diagram of an exemplary configuration of a pixel circuit 220, a differential input circuit 320, and a positive feedback circuit 330 in the first embodiment of the present technology.

[0105] The pixel circuit 220 includes a reset transistor 221, a floating diffusion layer 222, a transfer transistor 223, a photodiode 224, and a discharge transistor 225. For example, n-channel metal oxide semiconductor (nMOS) transistors are used as the reset transistor 221, the transfer transistor 223, and the discharge transistor 225.

[0106] The photodiode 224 generates charges through photoelectric conversion. The discharge transistor 225 discharges the charges accumulated in the photodiode 224 according to a drive signal OFG from the pixel drive circuit 252.

[0107] The transfer transistor 223 transfers the charges from the photodiode 224 to the floating diffusion layer 222 according to a transfer signal TX from the pixel drive circuit 252.

[0108] The floating diffusion layer 222 accumulates the transferred charges and generates a voltage corresponding to the amount of charge.

[0109] The reset transistor 221 initializes the floating diffusion layer 222 according to a reset signal RST from the pixel drive circuit 252.

[0110] The differential input circuit 320 includes p-channel metal oxide semiconductor (pMOS) transistors 321, 324, and 326 and nMOS transistors 322, 323, 325, and 327. Among the above transistors, the nMOS transistors 322, 323, and 325 are arranged on the light receiving chip 201, and the remaining transistors are arranged on the circuit chip 202.

[0111] The nMOS transistors 322 and 325 form a differential pair, and the sources of these two transistors are commonly connected to the drain of the nMOS transistor 323. In addition, the drain of the nMOS transistor 322 is connected to the drain of the pMOS transistor 321 and the gates of the pMOS transistors 321 and 324. The drain of the nMOS transistor 325 is connected to the drain of the pMOS transistor 324, the gate of the pMOS transistor 326, and the drain of the reset transistor 221. In addition, a reference signal REF from the DAC 251 is input into the gate of the nMOS transistor 322.

[0112] A predetermined bias voltage Vb is applied to the gate of the nMOS transistor 323, and a predetermined ground voltage is applied to the source of the nMOS transistor 323.

[0113] The pMOS transistors 321, 324, and 326 form a current mirror circuit. The power supply voltage VDDH is applied to the source of each of the pMOS transistors 321, 324, and 326. The power supply voltage VDDH is higher than the power supply voltage VDDL described later.

[0114] The power supply voltage VDDL is applied to the gate of the nMOS transistor 327. In addition, the drain of the nMOS transistor 327 is connected to the drain of the pMOS transistor 326, and the source of the nMOS transistor 327 is connected to the positive feedback circuit 330.

[0115] The positive feedback circuit 330 includes pMOS transistors 331, 332, 334, and 335 and nMOS transistors 333, 336, and 337. The pMOS transistors 331 and 332 and the nMOS transistor 333 are connected in series to the power supply voltage VDDL. In addition, the drive signal INI2 from the vertical scan circuit 255 is input to the gate of the pMOS transistor 331. The node between the pMOS transistor 332 and the nMOS transistor 333 is connected to the source of the nMOS transistor 327.

[0116] The ground voltage is applied to the source of the nMOS transistor 333, and the drive signal INI1 from the vertical scan circuit 255 is input to the gate of the nMOS transistor 333.

[0117] The pMOS transistors 334 and 335 are connected in series to the power supply voltage VDDL. In addition, the drain of the pMOS transistor 335 is connected to the gate of the pMOS transistor 332 and the drains of the nMOS transistors 336 and 337. The control signal TESTVCO from the vertical scan circuit 255 is input to the gates of the pMOS transistor 335 and the nMOS transistor 337. In addition, the gates of the pMOS transistor 334 and the nMOS transistor 336 are connected to the node between the pMOS transistor 332 and the nMOS transistor 333.

[0118] The output signal VCO is output from the node between the pMOS transistor 335 and the nMOS transistor 337. In addition, the ground voltage is applied to the sources of the nMOS transistors 336 and 337.

[0119] Note that as long as each has the respective functions described in Figure 7 the pixel circuit 220, the differential input circuit 320, and the positive feedback circuit 330 are not limited to the respective circuits exemplified in Figure 8 ​

[0120] "Exemplary Configuration of Signal Processing Circuit"

[0121] Figure 9 is a block diagram of an exemplary configuration of a signal processing circuit 400 in a first embodiment of the present technology. The signal processing circuit 400 includes a plurality of selectors 405, a plurality of arithmetic circuits 410, a CDS frame memory 440, and a TDI frame memory 450.

[0122] The selectors 405 are arranged one-to-one with the columns of the cluster 300, that is, one-to-one with the repeater units 360. When two columns of ADCs 310 are arranged in each cluster 300, one selector 405 is arranged for every two columns. In addition, the arithmetic circuits 410 are arranged one-to-one with the columns of the ADCs 310. When M columns of ADCs 310 are provided, M / 2 selectors 405 and M arithmetic circuits 410 are arranged.

[0123] As described above, each repeater unit 360 sequentially outputs digital signals in odd-numbered columns and digital signals in even-numbered columns.

[0124] The selector 405 selects the output destination of each digital signal according to the control of the control circuit 256. When each repeater unit 360 outputs a digital signal in an odd-numbered column, the selector 405 outputs the digital signal to the arithmetic circuit 410 corresponding to the odd-numbered column. At the same time, when each repeater unit 360 outputs a digital signal in an even-numbered column, the selector 405 outputs the digital signal to the arithmetic circuit 410 corresponding to the even-numbered column.

[0125] Each arithmetic circuit 410 performs CDS processing and TDI processing on the digital signal from the selector 405.

[0126] Here, the digital signal includes a P-phase level and a D-phase level. The P-phase level represents the level when the pixel circuit 220 is initialized due to the reset signal RST. At the same time, the D-phase level represents the level corresponding to the exposure amount when charge is transferred due to the transmission signal TX. The P-phase level is also referred to as the reset level, and the D-phase level is also a signal level.

[0127] In the CDS processing, the M arithmetic circuits 410 store the P-phase frames in which the P-phase levels are arranged in the CDS frame memory 440. Then, the M arithmetic circuits 410 obtain the difference between the P-phase level and the D-phase level of each pixel, thereby generating a CDS frame in which difference data is arranged.

[0128] Then, in the TDI process, M arithmetic circuits 410 retain the first CDS frame in the TDI frame memory 450. Next, the M arithmetic circuits 410 add a line having a predetermined address in the CDS frame of the second frame after the CDS process and a line having an address at a certain distance from the predetermined address in the frame of the first frame. As the moving speed of the object increases, the value set for the distance between the addresses for addition also increases. For example, the distance between the addresses for addition is set to "1". In this case, adjacent lines are added together. For the second frame and subsequent frames, for the Kth CDS frame (K is an integer), the (K - 1)th CDS frame generated before this frame is retained in the TDI frame memory 450.

[0129] In addition, the M arithmetic circuits 410 supply the CDS frame and the TDI frame after the TDI process to the image processing circuit 260.

[0130] "Exemplary Configuration of the Arithmetic Circuit"

[0131] Figure 10 is a circuit diagram of an exemplary configuration of the arithmetic circuit 410 in the first embodiment of the present technology. The arithmetic circuit 410 includes a TDI circuit 420 and a CDS circuit 430. The TDI circuit 420 includes a buffer 421, a selector 422, an adder 423, and a switch 424. The CDS circuit 430 includes a selector 431, a buffer 432, a selector 433, a subtractor 434, and a switch 435. For example, the operations of the selectors 422, 431, and 433 and the switches 424 and 435 are each controlled by the control circuit 256.

[0132] The selector 431 selectively outputs a digital signal from the selector 405 or a digital signal from the TDI frame memory 450 to the buffer 421.

[0133] The buffer 421 delays the signal output from the selector 431. Note that the buffer 421 is an exemplary second buffer in the claims.

[0134] The selector 422 selectively outputs a digital signal from the buffer 421 or a digital signal with a decimal value of "0" to the adder 423.

[0135] The adder 423 adds the digital signal from the selector 422 and the digital signal from the buffer 432. The adder 423 supplies the digital signal indicating the added value as summation data to the switch 424.

[0136] The switch 424 disconnects and closes the path between the adder 423 and the TDI frame memory 450.

[0137] Buffer 432 delays the signal output from the CDS frame memory 440. Note that buffer 432 is an exemplary first buffer in the claims.

[0138] Selector 433 selectively outputs the digital signal from buffer 432 or the digital signal with a decimal value of "0" to subtractor 434.

[0139] Subtractor 434 calculates the difference between the digital signal from buffer 421 and the digital signal from selector 433. Subtractor 434 supplies the digital signal indicating the difference as difference data to switch 435.

[0140] Switch 435 disconnects and closes the path between subtractor 434 and the CDS frame memory 440.

[0141] Next, a method for controlling the circuits in the arithmetic circuit 410 will be described.

[0142] "Exemplary Operations of the Arithmetic Circuit"

[0143] Figure 11 Illustrated is an exemplary state of the arithmetic circuit 410 in the first embodiment of the present technology when maintaining the P-phase level of the first frame.

[0144] The control circuit 256 initializes the CDS frame memory 440 and the TDI frame memory 450. After initialization, the pixel AD conversion unit 254 generates the P-phase level of the first frame.

[0145] Multiple P-phase levels in the corresponding columns of the first frame are sequentially input into selector 431. Selector 431 selectively outputs the P-phase level to buffer 421. Selector 433 outputs the digital signal "0" to subtractor 434. Subtractor 434 subtracts "0" from the P-phase level and outputs the subtraction result to switch 435. In addition, switch 424 is controlled in the off state, and switch 435 is controlled in the on state.

[0146] Due to this control, M arithmetic circuits 410 retain the P-phase frame of the first frame with the P-phase levels arranged in the CDS frame memory 440.

[0147] Figure 12 Illustrated is an exemplary state of the arithmetic circuit during CDS processing of the first frame in the first embodiment of the present technology.

[0148] The pixel AD conversion unit 254 generates the D-phase level of the first frame. Multiple D-phase levels in the corresponding columns of the first frame are sequentially input into selector 431. Selector 431 selectively outputs the D-phase level to buffer 421.

[0149] In addition, the buffer 432 sequentially reads a plurality of P-phase levels in the corresponding columns from the CDS frame memory 440 and outputs them to the selector 433. The selector 433 selectively outputs the P-phase levels to the subtractor 434.

[0150] The subtractor 434 subtracts the P-phase level selected by the selector 433 from the D-phase level output from the buffer 421 and outputs the subtraction result as differential data to the switch 435. In addition, the switch 424 is controlled to be in the off state and the switch 435 is controlled to be in the on state.

[0151] Due to this control, the M arithmetic circuits 410 perform CDS processing on the first frame and retain the CDS frame in which the differential data is arranged in the CDS frame memory 440. In addition, the CDS frame is also supplied to the image processing circuit 260.

[0152] Figure 13 An exemplary state of the arithmetic circuit when retaining a frame in the first embodiment of the present technology is illustrated.

[0153] The pixel AD conversion unit 254 generates P-phase levels of the second frame. A plurality of P-phase levels in the corresponding columns of the second frame are sequentially input to the selector 431. The selector 431 selectively outputs the P-phase levels to the buffer 421. The buffer 421 delays the P-phase levels.

[0154] The buffer 432 sequentially reads a plurality of differential data in the corresponding columns from the CDS frame memory 440 and outputs them to the adder 423. The selector 422 selectively outputs the digital signal "0" to the adder 423. The adder 423 adds "0" to the differential data and outputs the addition result to the switch 424. In addition, the switch 424 is controlled to be in the on state and the switch 435 is controlled to be in the off state.

[0155] Due to this control, the M arithmetic circuits 410 retain the current CDS frame in which different data is arranged in the TDI frame memory 450.

[0156] Figure 14 An exemplary state of the arithmetic circuit 410 when retaining the P-phase levels of the second frame in the first embodiment of the present technology is illustrated.

[0157] The buffer 421 outputs the P-phase levels to the subtractor 434. The selector 433 outputs the digital signal "0" to the subtractor 434. The subtractor 434 subtracts "0" from the P-phase levels and outputs the subtraction result to the switch 435. In addition, the switch 424 is controlled to be in the off state and the switch 435 is controlled to be in the on state.

[0158] Due to this control, the M arithmetic circuits 410 retain the P-phase frame of the second frame arranged with P-phase levels in the CDS frame memory 440.

[0159] Figure 15 FIG. illustrates an exemplary state of the arithmetic circuits during CDS processing of the second frame in the first embodiment of the present technology.

[0160] The pixel AD conversion unit 254 generates the D-phase levels of the second frame. A plurality of D-phase levels in the corresponding columns of the second frame are sequentially input to the selector 431. The selector 431 selectively outputs the D-phase levels to the buffer 421.

[0161] In addition, the buffer 432 sequentially reads a plurality of P-phase levels in the corresponding columns from the CDS frame memory 440 to output to the selector 433. The selector 433 selectively outputs the P-phase levels to the subtractor 434.

[0162] The subtractor 434 subtracts the P-phase level from the D-phase level and outputs the subtraction result as difference data to the switch 435. In addition, the switch 424 is controlled in the off state and the switch 435 is controlled in the on state.

[0163] Due to this control, the M arithmetic circuits 410 perform CDS processing on the second frame, retain the CDS frame arranged with the difference data in the CDS frame memory 440. In addition, the CDS frame is also supplied to the image processing circuit 260.

[0164] Figure 16 FIG. illustrates an exemplary state of the arithmetic circuits during TDI processing of the second frame in the first embodiment of the present technology.

[0165] The selector 431 sequentially reads and selects the difference data in the corresponding columns from the TDI frame memory 450 to output to the buffer 421. In addition, the buffer 432 reads the difference data in the corresponding columns from the CDS frame memory 440 to output to the adder 423. In the case where the row address of the difference data read from the TDI frame memory 450 is defined as a predetermined address, the row address of the difference data read from the CDS frame memory 440 is at a certain distance from the predetermined address. For example, the row address of the difference data read from the CDS frame memory 440 is adjacent to the predetermined address.

[0166] The selector 422 selectively outputs the difference data from the buffer 421 to the adder 423. The adder 423 adds the difference data in the first frame and the difference data in the second frame to output to the switch 424. In addition, the switch 424 is controlled in the on state and the switch 435 is controlled in the off state.

[0167] Due to this control, the M arithmetic circuits 410 add the line with a predetermined address in the current second frame and the line with an adjacent address in the past first frame. The processing for the second frame is repeated for the third frame and subsequent frames.

[0168] Figure 17 An exemplary TDI process in the first embodiment of the present technology is illustrated. For example, after initializing the CDS frame memory 440 and the TDI frame memory 450, frame F1 is first captured. Then, frames F2, F3, F4, and F5 are captured in sequence. The arrows in the figure indicate the moving direction of the object. As illustrated in the figure, the object moves line by line in the vertical direction along the direction of increasing row address.

[0169] The signal processing circuit 400 first performs CDS processing on frame F1, retains the processed frame F1 in the CDS frame memory 440, and retains frame F1 in the TDI frame memory 450.

[0170] Then, the signal processing circuit 400 performs CDS processing on frame F2, and adds the line L2 in the current frame F2 and the line L1 adjacent to line L2 in the past frame F1.

[0171] Next, the signal processing circuit 400 performs CDS processing on frame F3, and adds the line L3 in the current frame F3 and the line L2 adjacent to line L3 in the past frame F2.

[0172] Subsequently, the signal processing circuit 400 performs CDS processing on frame F4, and adds the line L4 in the current frame F4 and the line L3 adjacent to line L4 in the past frame F3.

[0173] Due to this calculation, the lines L1 in frame F1, L2 in frame F2, L3 in frame F3, and L4 in frame F4 are summed. As described above, because the object moves line by line, the pattern of each line to be summed is the same. The signal processing circuit 400 outputs the summed line as the last line of the TDI frame. As described above, the process of integrating the exposure amount with a time offset is called TDI processing.

[0174] The second-to-last line in the TDI frame is generated by summing the lines L1 in frame F2, L2 in frame F3, L3 in frame F4, and L4 in frame F5. Similarly, each of the remaining lines is generated by summing four lines from frame F3 and subsequent frames.

[0175] When the moving speed of the object is relatively fast, it is necessary to shorten the exposure time to prevent blurring. Shortening the exposure time may cause the image to become darker. However, through TDI processing, it is possible to use the summation of multiple lines of the same pattern to increase the brightness. In addition, as the number of lines to be summed increases, due to the smoothing effect, the noise will decrease. Compared with the case where TDI processing is not performed, the increase in brightness and the reduction in noise can improve the image quality of the frame (i.e., image data).

[0176] Note that although the signal processing circuit 400 sums four lines, the number of lines to be summed is not limited to four, as long as it is two or more. In addition, for the first four frames, the signal processing circuit 400 integrates the first four lines starting from the top, but the configuration is not limited to this. For example, in the case where the moving direction of the object is reversed, for the first four frames, the signal processing circuit 400 needs to integrate at least the first four lines starting from the end.

[0177] "Exemplary Operations of the Solid-State Imaging Element"

[0178] Figure 18 is a timing diagram of the exemplary operations of the solid-state imaging element 200 in the first embodiment of the present technology. The pixel AD conversion unit 254 generates frame F1 during the period from timing T1 to timing T2, and generates frame F2 during the period from timing T2 to timing T3. In addition, the pixel AD conversion unit 254 generates frame F3 during the period from timing T3 to timing T4, and generates frame F4 starting from timing T4.

[0179] In addition, during the period from timing T1 to timing T2, each ADC 310 sequentially generates the P-phase level and D-phase level of the first frame. At the same time, each arithmetic circuit 410 performs CDS processing when generating the D-phase.

[0180] In addition, during the period from timing T2 to timing T3, each ADC 310 sequentially generates the P-phase level and D-phase level of the second frame. At the same time, each arithmetic circuit 410 performs TDI processing when generating the P-phase, and performs CDS processing when generating the D-phase.

[0181] For the third frame and subsequent frames, similarly, the P-phase level and D-phase level are generated, and TDI processing and CDS processing are performed.

[0182] Figure 19 Illustratively shows the calculation of the signal processing circuit 400 in the first embodiment of the present technology.

[0183] Multiple pixel circuits 220 each generate an analog pixel signal through photoelectric conversion and supply the analog pixel signal to the pixel AD conversion unit 254. The pixel AD conversion unit 254 includes a plurality of ADCs 310 arranged in a two-dimensional grid pattern. Each ADC 310 converts the analog pixel signal into a digital signal and transmits the digital signal to the arithmetic circuit 410 through the repeater unit 360. The digital signal includes a reset level and a signal level corresponding to the exposure amount. Each ADC 310 outputs the signal level after the reset level. Note that the pixel AD conversion unit 254 is an exemplary analog-to-digital conversion unit in the claims.

[0184] The CDS circuit 430 retains the first P-phase frame in which the P-phase levels are arranged in the CDS frame memory 440. When the D-phase level is input, the CDS circuit 430 reads the P-phase frame from the CDS frame memory 440 and performs a CDS process of obtaining the difference between the P-phase level and the D-phase level. Then, the CDS circuit 430 updates the CDS frame memory 440 with the first CDS frame after the CDS process and retains the CDS frame in the TDI frame memory 450.

[0185] Then, the CDS circuit 430 retains the P-phase frame of the second frame in the CDS frame memory 440. When the D-phase level is input, the CDS circuit 430 reads the P-phase frame from the CDS frame memory 440 and performs a second CDS process of obtaining the difference between the P-phase level and the D-phase level. Then, the CDS circuit 430 updates the CDS frame memory 440 with the CDS frame of the second frame after the CDS process.

[0186] Subsequently, the TDI circuit 420 reads the line having a predetermined address in the (K-1)th CDS frame from the TDI frame memory 450 and reads the line having an address (e.g., an adjacent address) at a certain distance from the predetermined address in the Kth frame from the CDS frame memory 440. Then, the TDI circuit 420 adds the two lines and updates the TDI frame memory 450 with the added lines.

[0187] For the third frame and subsequent frames, a process similar to that of the second frame is repeated. Note that for the third frame and subsequent frames, the number of lines to be summed increases one by one. The number of summation times increases to a certain number (e.g., four times). Due to this process, a TDI frame in which the summation data is arranged is generated.

[0188] Here, as a comparative example, consider the following solid-state imaging device: It includes a charge-coupled device (CCD) that transfers charges with time offset and a circuit that accumulates the amount of its charges in a floating diffusion layer to generate an integration signal. According to the comparative example, as the number of pixels at the charge transfer source increases, it is necessary to increase the capacity of the floating diffusion layer at the charge transfer destination. The increase in capacity leads to deterioration of pixel sensitivity, and further leads to deterioration of the image quality of image data due to the deterioration of pixel sensitivity. As described above, the comparative example has the problem of deterioration of image quality.

[0189] In contrast, according to the configuration in which the TDI process is performed after the CDS process outside the pixel circuit 220, the capacity of the floating diffusion layer in the pixel circuit 220 does not need to be increased according to the number of addition times. Therefore, the capacity of the floating diffusion layer can be made smaller than that of the floating diffusion layer in the comparative example. Therefore, the pixel sensitivity can be made higher than that in the comparative example, thereby improving the image quality of image data.

[0190] Next, a method of controlling the circuit in the solid-state imaging device 200 will be described.

[0191] "Exemplary Operations of the Solid-State Imaging Device"

[0192] Figure 20 FIG. illustrates an exemplary state of the solid-state imaging device 200 at the time of retaining the P-phase level in the first embodiment of the present technology. In the figure, the selector 405 is not illustrated for ease of explanation.

[0193] Whenever the pixel AD conversion unit 254 outputs the P-phase level in each line, the plurality of arithmetic circuits 410 retain the P-phase level in the CDS frame memory 440. Therefore, the P-phase frame in which a plurality of P-phase levels are arranged is retained in the CDS frame memory 440.

[0194] Figure 21 FIG. illustrates an exemplary state of the solid-state imaging device 200 at the time of performing the CDS process in the first embodiment of the present technology. In the figure, the selector 405 is not illustrated.

[0195] Whenever the pixel AD conversion unit 254 outputs the D-phase level in each line, the plurality of arithmetic circuits 410 obtain the difference between the D-phase level and the corresponding P-phase level in the CDS frame memory 440. Then, the arithmetic circuit 410 updates the CDS frame memory 440 with the CDS frame in which the difference data is arranged.

[0196] Figure 22FIG. illustrates an exemplary state of the solid-state imaging element 200 during image processing after CDS processing in the first embodiment of the present technology. In the figure, the selector 405 is not illustrated. The image processing circuit 260 performs predetermined image processing on the frame after CDS processing.

[0197] Figure 23 FIG. illustrates an exemplary state of the solid-state imaging element during TDI processing in the first embodiment of the present technology. In the figure, the selector 405 is not illustrated.

[0198] A plurality of arithmetic circuits 410 add a line having a predetermined address in the CDS frame memory 440 and a line adjacent to the predetermined address in the TDI frame memory 450. Then, the arithmetic circuit 410 updates the TDI frame memory 450 using the summation data indicating the addition of values.

[0199] Figure 24 FIG. illustrates an exemplary state of the solid-state imaging element 200 during image processing after TDI processing in the first embodiment of the present technology. In the figure, the selector 405 is not illustrated. The image processing circuit 260 performs image processing such as black level correction processing on the frame after TDI processing.

[0200] Figure 25 FIG. illustrates an exemplary state of the solid-state imaging element when outputting a frame. In the figure, the selector 405 is not illustrated. The output circuit 257 outputs the result of the image processing to, for example, the storage unit 120.

[0201] Figure 26 is a flowchart of an exemplary operation of the solid-state imaging element in the first embodiment of the present technology. For example, when a predetermined application for frame shooting is executed, the operation starts.

[0202] The pixel drive circuit 252 in the solid-state imaging element 200 drives all the pixels so that simultaneous exposure of all the pixels starts (step S901). The control of simultaneous exposure of all the pixels as described above is called the global shutter technique.

[0203] Just before the exposure is completed, the AD converters 310 each perform AD conversion on the P-phase level (step S902). Then, when the exposure is completed, the AD converters 310 each perform AD conversion on the D-phase level, and the arithmetic circuits 410 each perform CDS processing (step S903).

[0204] The image processing circuit 260 performs predetermined image processing on the frame after CDS processing (step S904), and the arithmetic circuits 410 each perform TDI processing (step S905). The image processing circuit 260 performs predetermined image processing on the frame after TDI processing (step S906), and the output circuit 257 outputs the processing result (step S907). After step S907, the solid-state imaging device 200 completes the processing of capturing one frame. When continuously capturing two or more frames, the processing of steps S901 to S907 is repeated synchronously with the vertical synchronization signal VSYNC.

[0205] As described above, in the first embodiment of the present technology, the arithmetic circuit 410 adds a predetermined line in the K-th frame after CDS processing and an adjacent line in the (K-1)-th frame. Therefore, the capacity of the floating diffusion layer in each pixel circuit 220 does not need to be increased according to the number of additions. Therefore, compared with the case of transferring the charge amounts of multiple pixels to the floating diffusion layer, a floating diffusion layer with a small capacity can be used to improve the pixel sensitivity. The improvement of the pixel sensitivity can improve the image quality of the image data.

[0206] <2. Second Embodiment>

[0207] In the first embodiment, both the TDI circuit 420 and the CDS circuit 430 are arranged between the pixel AD conversion unit 254 and the CDS frame memory 440. However, any one of the circuits (for example, the TDI circuit 420) does not necessarily have to be arranged between the pixel AD conversion unit 254 and the CDS frame memory 440. The solid-state imaging device 200 in the second embodiment is different from the solid-state imaging device in the first embodiment in that the arrangement of the TDI circuit 420 is changed.

[0208] Figure 27 is a block diagram of an exemplary configuration of the circuit chip 202 in the second embodiment of the present technology. In the second embodiment, instead of a plurality of arithmetic circuits 410, a column CDS processing unit 460 and a column TDI arithmetic unit 470 are arranged on the circuit chip 202.

[0209] The column CDS processing unit 460 is arranged between the pixel AD conversion unit 254 and the CDS frame memory 440, and the column TDI arithmetic unit 470 is arranged between the CDS frame memory 440 and the TDI frame memory 450. Note that in the figure, the selector 405 is not shown for the sake of simplicity of illustration.

[0210] Figure 28It is a block diagram of an exemplary configuration of a column CDS processing unit 460 and a column TDI arithmetic unit 470 in a second embodiment of the present technology. As illustrated, a plurality of CDS circuits 430 are arranged in the column CDS processing unit 460. For example, each CDS circuit 430 is arranged for each column of the ADC 310.

[0211] In addition, a plurality of TDI circuits 420 are arranged in the column TDI arithmetic unit 470. For example, each TDI circuit 420 is arranged for each column of the ADC 310.

[0212] As illustrated, since the arrangement positions of the CDS circuit 430 and the TDI circuit 420 are different, the degree of freedom in layout design of the circuit chip 202 can be improved.

[0213] Figure 29 It is a timing diagram of an exemplary operation of the solid-state imaging device 200 in a second embodiment of the present technology. The pixel AD conversion unit 254 sequentially generates frame F1 in the period from timing T1 to timing T2, generates frame F2 in the period from timing T2 to timing T3, generates frame F3 in the period from timing T3 to timing T4, and generates frame F4 from timing T4.

[0214] In addition, in the period from timing T1 to timing T2, each ADC 310 sequentially generates a P-phase level and a D-phase level. At the same time, the column CDS processing unit 460 performs CDS processing when generating the D-phase.

[0215] In addition, in the period from timing T2 to timing T3, each ADC 310 sequentially generates a P-phase level and a D-phase level of a second frame. At the same time, the column TDI arithmetic unit 470 performs TDI processing when generating the P-phase. The column CDS processing unit 460 performs CDS processing when generating the D-phase.

[0216] For the third frame and subsequent frames, similarly, a P-phase level and a D-phase level are generated, and TDI processing and CDS processing are performed.

[0217] As described above, in the second embodiment of the present technology, since the arrangement positions of the TDI circuit 420 and the CDS circuit 430 are different, the degree of freedom in layout design can be improved.

[0218] <3. Third Embodiment>

[0219] In the second embodiment, no buffer is inserted between selector 405 and selector 431. The output timing of the digital signal varies between odd-numbered columns and even-numbered columns. Therefore, desirably, a buffer is inserted for timing adjustment. The solid-state imaging device 200 in the third embodiment is different from the solid-state imaging device in the second embodiment in that a buffer is added to the CDS circuit 430.

[0220] Figure 30 FIG. is a circuit diagram of an exemplary configuration of the CDS circuit 430 and the TDI circuit 420 in the third embodiment of the present technology. The CDS circuit 430 in the third embodiment is different from the CDS circuit in the second embodiment in that a buffer 481 is further provided.

[0221] The buffer 481 is arranged between selector 405 and selector 431. Note that the buffer 481 is the exemplary third buffer in the claims.

[0222] Figure 31 FIG. is a block diagram of an exemplary configuration of the signal processing circuit 400 in the third embodiment of the present technology. As illustrated, the buffer 481, the buffer 432, and the processing circuit 480 are arranged in each CDS circuit 430. Figure 30 The selectors 431 and 433, the subtracter 434, and the switch 435 in FIG. are arranged in the processing circuit 480.

[0223] Each selector 405 outputs the digital signal in the even-numbered column and the digital signal in the odd-numbered column at different timings. The buffer 481 added to the subsequent stage of each selector 405 can adjust the start timing of the CDS process between the odd-numbered column and the even-numbered column.

[0224] As described above, in the third embodiment of the present technology, the buffer 481 inserted between each selector 405 and selector 431 can adjust the start timing of the CDS process between the odd-numbered column and the even-numbered column.

[0225] <4. Fourth Embodiment>

[0226] In the third embodiment, the processing circuit 480 is arranged for each column. As the number of columns increases, the circuit scale of the signal processing circuit 400 increases. The solid-state imaging device 200 in the fourth embodiment is different from the solid-state imaging device in the third embodiment in that the processing circuit 480 is shared between two adjacent columns.

[0227] Figure 32 FIG. is a circuit diagram of an exemplary configuration of the CDS circuit 430 and the TDI circuit 420 in the fourth embodiment of the present technology. The CDS circuit 430 in the fourth embodiment is different from the CDS circuit in the third embodiment in that a buffer 482 and a selector 483 are further provided.

[0228] The buffer 482 reads the digital signals in the even columns from the CDS frame memory 440 and delays the digital signals. In addition, the buffer 432 in the fourth embodiment reads the digital signals in the odd columns from the CDS frame memory 440 and delays the digital signals.

[0229] Under the control of the control circuit 256, the selector 483 selectively outputs the output of the buffer 482 or the output of the buffer 432 to the TDI circuit 420 and the selector 433.

[0230] Figure 33 is a block diagram of an exemplary configuration of the signal processing circuit 400 in the fourth embodiment of the present technology. In the signal processing circuit 400 of the fourth embodiment, the CDS circuit 430 and the TDI circuit 420 are arranged for every two adjacent columns. Note that in the figure, the selector 405 and the TDI circuit 420 are not illustrated.

[0231] The buffers 432, 481 and 482, the selector 483, and the processing circuit 480 are arranged in the CDS circuit 430. As illustrated in the figure, in the fourth embodiment, the processing circuit 480 is shared between two columns. Therefore, compared with the third embodiment in which the processing circuit 480 is provided for each column, the circuit scale of the signal processing circuit 400 can be reduced.

[0232] As described above, in the fourth embodiment of the present technology, the processing circuit 480 is shared between two adjacent columns, so that the circuit scale of the signal processing circuit 400 can be reduced compared with the case where the processing circuit 480 is arranged for each column.

[0233] <5. Fifth Embodiment>

[0234] In the third embodiment, the processing circuit 480 is arranged for each column. As the number of columns increases, the circuit scale of the signal processing circuit 400 increases. The solid-state imaging element 200 in the fifth embodiment is different from the solid-state imaging element in the third embodiment in that the processing circuit 490 is shared among four columns.

[0235] Figure 34 is a circuit diagram of an exemplary configuration of the CDS circuit 430 in the fifth embodiment of the present technology. The CDS circuit 430 in the fifth embodiment includes buffers 491 to 494, a selector 495, buffers 496 to 499, a selector 500, a selector 433, a subtractor 434, and a switch 435.

[0236] Buffers 491 to 494 delay respective digital signals in adjacent four columns from selectors 405 and 406. For example, selector 405 outputs a digital signal in the 4m-th column (m is an integer) or a digital signal in the (4m + 1)-th column, and selector 406 outputs a digital signal in the (4m + 2)-th column or a digital signal in the (4m + 3)-th column. Buffer 491 delays the digital signal in the 4m-th column, and buffer 492 delays the digital signal in the (4m + 1)-th column. Buffer 493 delays the digital signal in the (4m + 2)-th column, and buffer 494 delays the digital signal in the (4m + 3)-th column.

[0237] According to control circuit 256, selector 495 selectively outputs any one of the respective outputs of buffers 491 to 494 and TDI frame memory 450 to TDI circuit 420.

[0238] Buffers 496 to 499 delay respective digital signals in adjacent four columns in CDS frame memory 440. Buffer 496 delays the digital signal in the 4m-th column, and buffer 497 delays the digital signal in the (4m + 1)-th column. Buffer 498 delays the digital signal in the (4m + 2)-th column, and buffer 499 delays the digital signal in the (4m + 3)-th column.

[0239] According to control circuit 256, selector 500 selectively outputs any one of the respective outputs of buffers 496 to 499 to TDI circuit 420 and selector 433.

[0240] Figure 35 is a block diagram of an exemplary configuration of signal processing circuit 400 in the fifth embodiment of the present technology. In signal processing circuit 400 of the fifth embodiment, CDS circuit 430 and TDI circuit 420 are arranged for every four columns. Note that in the figure, TDI circuit 420 is not illustrated.

[0241] Buffers 491 to 494, buffers 496 to 499, and processing circuit 490 are arranged in CDS circuit 430. Figure 34 Selector 495, selector 500, selector 433, subtractor 434, and switch 435 in are arranged in processing circuit 490. As illustrated in the figure, in the fifth embodiment, processing circuit 490 is shared among four columns. Therefore, compared with the third embodiment in which processing circuit 480 is provided for each column, the circuit scale of signal processing circuit 400 can be reduced.

[0242] As described above, in the fifth embodiment of the present technology, processing circuit 490 is shared among four columns, so that the circuit scale of signal processing circuit 400 can be reduced compared with the case where processing circuit 480 is arranged for each column.

[0243] Note that the embodiments are illustrated to embody the present technology, and there is a corresponding relationship between the matters in the embodiments and the specific matters related to the present invention in the claims. Similarly, there is also a corresponding relationship between the specific matters related to the present invention in the claims and the matters represented by the same name as the specific matters in the embodiments of the present technology. Note that the present technology is not limited to these embodiments, and thus various modifications can be made to the embodiments without departing from the substantial scope, so as to be able to embody the present technology.

[0244] Note that the effects in this specification are merely exemplary and not restrictive, and thus other effects can be provided.

[0245] Note that the present technology can also have the following configuration.

[0246] (1) A solid-state imaging element, comprising:

[0247] A correlated double sampling circuit that generates a frame in which a predetermined number of lines are arranged, each of the lines including a plurality of digital signals;

[0248] A time delay integration (TDI) frame memory that retains the (K - 1)th frame generated before the Kth frame, where K is an integer; and

[0249] A time delay integration circuit that performs a time delay integration process of adding the line having a predetermined address in the Kth frame and the line having an address at a certain distance from the predetermined address in the (K - 1)th frame.

[0250] (2) The solid-state imaging element according to (1) above, further comprising:

[0251] A correlated double sampling (CDS) frame memory that retains a frame in which a predetermined reset level is arranged as a reset frame, where

[0252] each of the plurality of digital signals includes the reset level and a signal level corresponding to an exposure amount, and

[0253] the correlated double sampling circuit generates the frame by using a correlated double sampling process of obtaining a difference between the retained reset level and the signal level.

[0254] (3) The solid-state imaging element according to (2) above, further comprising:

[0255] An analog-to-digital conversion unit, in which a plurality of analog-to-digital converters are arranged in a two-dimensional grid pattern, and each of the plurality of analog-to-digital converters converts an analog signal into a digital signal.

[0256] (4) The solid-state imaging element according to (3) above, wherein

[0257] The related double sampling circuit is arranged between the analog-to-digital conversion unit and the CDS frame memory, and

[0258] The time delay integration circuit is arranged between the CDS frame memory and the TDI frame memory.

[0259] (5) The solid-state imaging device according to (4) above, wherein

[0260] The related double sampling circuit is provided for each column in the analog-to-digital conversion unit, and

[0261] Each of the related double sampling circuits performs the related double sampling process on the digital signals from the corresponding column.

[0262] (6) The solid-state imaging device according to (4) above, wherein

[0263] The related double sampling circuits are shared among a plurality of columns in the analog-to-digital conversion unit.

[0264] (7) The solid-state imaging device according to any one of (4) to (6) above, further comprising:

[0265] A plurality of pixel circuits, each of which generates an analog signal and supplies the analog signal to the analog-to-digital conversion unit, wherein

[0266] The plurality of pixel circuits are arranged on a predetermined light receiving chip, and

[0267] The TDI frame memory, the related double sampling circuit, and the time delay integration circuit are arranged on a predetermined circuit chip stacked with the light receiving chip.

[0268] (8) The solid-state imaging device according to any one of (4) to (7) above, wherein

[0269] The related double sampling circuit includes:

[0270] A selector that selects a digital signal generated by the analog-to-digital conversion unit or a digital signal output from the TDI frame memory;

[0271] A subtractor that obtains the difference between the reset level and the signal level; and

[0272] A first buffer inserted between the TDI frame memory and the subtractor, and

[0273] The time delay integration circuit includes:

[0274] An adder that adds a line having the predetermined address and a line having an address that is the certain distance from the predetermined address; and

[0275] A second buffer inserted between the selector and the adder.

[0276] (9) The solid-state imaging device according to (8) above, further comprising:

[0277] A third buffer inserted between the selector and the analog-to-digital conversion unit.

[0278] (10) An imaging device, comprising:

[0279] A correlated double sampling circuit that generates a frame in which a predetermined number of lines are arranged, each of the lines including a plurality of digital signals;

[0280] A TDI frame memory that stores the (K - 1)th frame generated before the Kth frame;

[0281] An arithmetic circuit that adds a line having a predetermined address in the Kth frame and a line having an address that is a certain distance from the predetermined address in the (K - 1)th frame, and outputs the result of the addition as integration data; and

[0282] An image processing circuit that processes the integration data.

[0283] (11) A method of controlling a solid-state imaging device, the method including:

[0284] Performing correlated double sampling to generate a frame in which a predetermined number of lines are arranged, each of the lines including a plurality of digital signals;

[0285] Storing the (K - 1)th frame generated before the Kth frame in a TDI frame memory; and

[0286] Performing time-delay integration processing of adding a line having a predetermined address in the Kth frame and a line having an address that is a certain distance from the predetermined address in the (K - 1)th frame.

[0287] Additionally or alternatively, the present technology can also have the following configurations.

[0288] (1') An imaging device, comprising:

[0289] A first substrate including a plurality of pixels arranged in a matrix, each of the plurality of pixels being configured to output a pixel signal; and

[0290] A second substrate stacked with the first substrate, the second substrate including:

[0291] At least a part of an analog-to-digital circuit, the analog-to-digital circuit being configured to output a digital signal based on the pixel signal,

[0292] An arithmetic circuit, which is configured to receive the digital signal,

[0293] A first storage circuit, which is connected to the arithmetic circuit,

[0294] A second storage circuit, which is connected to the arithmetic circuit, and

[0295] An image processing circuit, which is connected to the second storage circuit.

[0296] (2') The imaging device according to (1'), wherein the arithmetic circuit includes a column CDS processing circuit and a column TDI arithmetic circuit.

[0297] (3') The imaging device according to (1') or (2'), wherein a frame of the digital signal includes a first phase level and a second phase level, and the first storage circuit is configured to store the first phase level.

[0298] (4') The imaging device according to (3'), wherein the arithmetic circuit is configured to obtain a difference between the second phase level and the first phase level, and is configured to store the difference in the first storage circuit.

[0299] (5') The imaging device according to (4'), wherein the image processing circuit is configured to perform a predetermined first image processing on the difference.

[0300] (6') The imaging device according to (5'), wherein the first image processing is at least one of an image recognition process, a black level correction process, an image correction process, and a demosaicing process.

[0301] (7') The imaging device according to (5') or (6'), wherein the arithmetic circuit is configured to: after the image processing circuit performs the predetermined first image processing, obtain a sum of a predetermined first line of the frame and a second line of the frame adjacent to the first line of the frame, and store the sum in the second storage circuit.

[0302] (8') The imaging device according to (7'), wherein the image processing circuit is configured to perform a second image processing on the sum.

[0303] (9') The imaging device according to (8'), wherein the second substrate includes an output circuit configured to output a result of the second image processing.

[0304] (10') The imaging device according to any one of (1') to (9'), wherein each of the pixels includes a floating diffusion portion.

[0305] (11') A method in an imaging device, the method comprising:

[0306] outputting a pixel signal from each of a plurality of pixels arranged in a matrix;

[0307] outputting a digital signal based on the pixel signal from an analog-to-digital circuit; and

[0308] receiving the digital signal by an arithmetic circuit,

[0309] wherein the imaging device includes: a first substrate including the plurality of pixels; and a second substrate stacked with the first substrate and including at least a part of the analog-to-digital circuit, the arithmetic circuit, a first storage circuit, a second storage circuit, and an image processing circuit.

[0310] (12') The method according to (11'), wherein

[0311] a frame of the digital signal includes a first phase level and a second phase level, and

[0312] the method includes storing the first phase level in the first storage circuit.

[0313] (13') The method according to (12'), further comprising:

[0314] obtaining, by the arithmetic circuit, a difference between the second phase level and the first phase level; and

[0315] storing the difference in the first storage circuit.

[0316] (14') The method according to (13'), further comprising: performing a predetermined first image processing on the difference by the image processing circuit.

[0317] (15') The method according to (14'), wherein the first image processing is at least one of an image recognition process, a black level correction process, an image correction process, and a demosaicing process.

[0318] (16') The method according to (14') or (15'), further comprising:

[0319] after performing the predetermined first image processing, obtaining, by the arithmetic circuit, a sum of a predetermined first line of the frame and a second line adjacent to the first line of the frame; and

[0320] The arithmetic circuit stores the sum in the second storage circuit.

[0321] (17') The method according to (16'), further comprising: performing a second image processing on the sum by the image processing circuit.

[0322] (18') The method according to (17'), further comprising: outputting a result of the second image processing by an output circuit included in the second substrate.

[0323] (19') The method according to any one of (11') to (18'), wherein each of the pixels includes a floating diffusion portion.

[0324] (20') An electronic device, comprising:

[0325] An optical component configured to converge and guide incident light; and

[0326] An imaging device configured to receive the incident light, the imaging device including:

[0327] A first substrate including a plurality of pixels arranged in a matrix, each of the plurality of pixels being configured to output a pixel signal in response to the incident light, and

[0328] A second substrate stacked with the first substrate, the second substrate including:

[0329] At least a part of an analog-to-digital circuit configured to output a digital signal based on the pixel signal,

[0330] An arithmetic circuit configured to receive the digital signal,

[0331] A first storage circuit connected to the arithmetic circuit,

[0332] A second storage circuit connected to the arithmetic circuit, and

[0333] An image processing circuit connected to the second storage circuit.

[0334] Those skilled in the art should understand that various modifications, combinations, sub-combinations and changes can be made according to design requirements and other factors within the scope of the appended claims or their equivalents.

[0335] List of reference numerals

[0336] 100 Camera device

[0337] 110 Optical unit

[0338] 120 Storage unit

[0339] 130 Control Unit

[0340] 140 Communication Unit

[0341] 200 Solid-State Imaging Element

[0342] 201 Optical Receiving Chip

[0343] 202 Circuit Chip

[0344] 210 Pixel Array Unit

[0345] 211 Pixel Block

[0346] 212 Peripheral Circuit

[0347] 220 Pixel Circuit

[0348] 221 Reset Transistor

[0349] 222 Floating Diffusion Layer

[0350] 223 Transfer Transistor

[0351] 224 Photoelectric Diode

[0352] 225 Drain Transistor

[0353] 251 DAC

[0354] 252 Pixel Driving Circuit

[0355] 253 Time Code Generation Unit

[0356] 254 Pixel AD Conversion Unit

[0357] 255 Vertical Scanning Circuit

[0358] 256 Control Circuit

[0359] 257 Output Circuit

[0360] 260 Image Processing Circuit

[0361] 300 Cluster

[0362] 310 ADC

[0363] 320 Differential Input Circuit

[0364] 321, 324, 326, 331, 332, 334, 335 pMOS Transistors

[0365] 322, 323, 325, 327, 333, 336, 337 nMOS Transistors

[0366] 330 Positive feedback circuit

[0367] 340 Latch control circuit

[0368] 350 Latch circuit

[0369] 360 Repeater unit

[0370] 400 Signal processing circuit

[0371] 405, 406, 422, 431, 433, 483, 495, 500 Selector

[0372] 410 Arithmetic circuit

[0373] 420 TDI circuit

[0374] 421, 432, 481, 482, 491 to 494, 496 to 499 Buffer

[0375] 423 Adder

[0376] 424, 435 Switch

[0377] 430 CDS circuit

[0378] 434 Subtractor

[0379] 440 CDS frame memory

[0380] 450 TDI frame memory

[0381] 460 Column CDS processing unit

[0382] 470 Column TDI arithmetic unit

[0383] 480, 490 Processing circuit

Claims

1. An imaging device, comprising: A first substrate including a plurality of pixels arranged in a matrix, each of the plurality of pixels being configured to output a pixel signal; And A second substrate stacked with the first substrate, the second substrate including: At least a part of an analog-to-digital circuit configured to output a digital signal based on the pixel signal, An arithmetic circuit configured to receive the digital signal and including a column CDS processing circuit and a column TDI arithmetic circuit, A first storage circuit connected to the arithmetic circuit, A second storage circuit connected to the arithmetic circuit, and An image processing circuit connected to the second storage circuit, Wherein the column CDS processing circuit is arranged between the analog-to-digital circuit and the first storage circuit, and the column TDI arithmetic circuit is arranged between the first storage circuit and the second storage circuit.

2. The imaging device according to claim 1, wherein, A frame of the digital signal includes a first phase level and a second phase level, and the first storage circuit is configured to store the first phase level.

3. The imaging device according to claim 2, wherein, The arithmetic circuit is configured to obtain a difference between the second phase level and the first phase level and is configured to store the difference in the first storage circuit.

4. The imaging device according to claim 3, wherein, The image processing circuit is configured to perform a predetermined first image processing on the difference.

5. The imaging device according to claim 4, wherein, The first image processing is at least one of an image recognition process, a black level correction process, an image correction process, and a demosaicing process.

6. The imaging device according to claim 4, wherein, The arithmetic circuit is configured to: after the image processing circuit performs the predetermined first image processing, obtain a sum of a predetermined first line of the frame and a second line of the frame adjacent to the first line of the frame, and store the sum in the second storage circuit.

7. The imaging device according to claim 6, wherein, The image processing circuit is configured to perform a second image processing on the sum.

8. The imaging device according to claim 7, wherein, The second substrate includes an output circuit configured to output a result of the second image processing.

9. The imaging device according to any one of claims 1 to 8, wherein, Each of the pixels includes a floating diffusion portion.

10. A method in an imaging device, the method comprising: Outputting a pixel signal from each of a plurality of pixels arranged in a matrix; Outputting a digital signal based on the pixel signal from an analog-to-digital circuit; And Receiving the digital signal by an arithmetic circuit, Wherein the imaging device includes: a first substrate including the plurality of pixels; and a second substrate stacked with the first substrate and including at least a part of the analog-to-digital circuit, the arithmetic circuit, a first storage circuit, a second storage circuit, and an image processing circuit, Wherein the arithmetic circuit includes a column CDS processing circuit and a column TDI arithmetic circuit, the column CDS processing circuit is arranged between the analog-to-digital circuit and the first storage circuit, and the column TDI arithmetic circuit is arranged between the first storage circuit and the second storage circuit.

11. The method according to claim 10, wherein A frame of the digital signal includes a first phase level and a second phase level, and The method includes storing the first phase level in the first storage circuit.

12. The method according to claim 11, further comprising: Obtain the difference between the second phase level and the first phase level by the arithmetic circuit; And Store the difference in the first storage circuit.

13. The method according to claim 12, further comprising: Perform a predetermined first image processing on the difference by the image processing circuit.

14. The method according to claim 13, wherein, The first image processing is at least one of image recognition processing, black level correction processing, image correction processing, and demosaicing processing.

15. The method according to claim 13, further comprising: After performing the predetermined first image processing, obtain the sum of a predetermined first line of the frame and a second line adjacent to the first line of the frame by the arithmetic circuit, and Store the sum in the second storage circuit by the arithmetic circuit.

16. The method according to claim 15, further comprising: Perform a second image processing on the sum by the image processing circuit.

17. The method according to claim 16, further comprising: Output the result of the second image processing by the output circuit included in the second substrate.

18. The method according to any one of claims 10 to 17, wherein Each of the pixels includes a floating diffusion portion.

19. An electronic device, comprising: An optical component configured to converge and guide incident light; And An imaging device configured to receive the incident light, the imaging device including: A first substrate including a plurality of pixels arranged in a matrix, each of the plurality of pixels being configured to output a pixel signal in response to the incident light, and A second substrate stacked with the first substrate, the second substrate including: At least a part of an analog-to-digital circuit configured to output a digital signal based on the pixel signal, An arithmetic circuit configured to receive the digital signal, A first storage circuit connected to the arithmetic circuit, A second storage circuit connected to the arithmetic circuit, and An image processing circuit connected to the second storage circuit, Wherein, the arithmetic circuit includes a column CDS processing circuit and a column TDI arithmetic circuit, the column CDS processing circuit is arranged between the analog-to-digital circuit and the first storage circuit, and the column TDI arithmetic circuit is arranged between the first storage circuit and the second storage circuit.

Images