A message processing method, device, electronic device and storage medium

Abstract

The present application provides a message processing method, device, electronic device and storage medium. Applicable to an electronic device equipped with an FPGA chip, the FPGA includes cascade-connected first-in first-out memory FIFOs at various levels, the method comprising: obtaining a set of message bodies to be processed and a macro definition file pre-generated according to a configuration file, the configuration file including the read-write status and bit width corresponding to each message body in each level of FIFO; allocating the required processing resources to each level of FIFO according to the read-write status and bit width corresponding to the message body in each level of FIFO; controlling each level of FIFO to use the allocated processing resources to process the message body in the set of message bodies to be processed. By obtaining the set of message bodies to be processed and the macro definition file, and then allocating the processing resources required for each level of FIFO according to the macro definition file, the full utilization of resources in the FPGA is achieved and the waste of resources is avoided.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a message processing method, device, electronic device and storage medium. Background Art

[0002] As FPGA chips are increasingly used in application technology scenarios involving message processing, such as virtualization scenarios, network application processing scenarios, data center heterogeneous design, etc., FPGA chips play an important role.

[0003] Currently, there are two mainstream FPGA message processing methods: the first is based on the implementation of open-address random access memory RAM, where each message body independently occupies an address, and all message bodies share an address bus. Address line preemption will occur between multiple users, and a unified controller is required for scheduling, and the message processing speed needs to be improved; the other is based on the implementation of first-in-first-out memory FIFO, which merges all message bodies processed by each level of FIFO into a message body set, and uses multi-level FIFO to implement the pipeline design in FPGA to achieve line-speed processing of message processing, but the processing resources required for the message body set are too large, which consumes resources. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a message processing method, device, electronic device and storage medium to reduce the waste of resources in FPGA.

[0005] In a first aspect, an embodiment of the present application provides a message processing method, which is applied to an electronic device equipped with a field programmable gate array FPGA, wherein the FPGA includes various levels of first-in-first-out memory FIFOs connected in cascade, and the method includes: obtaining a set of message bodies to be processed and a macro definition file pre-generated according to a configuration file, wherein the set of message bodies to be processed includes multiple message bodies, and the configuration file includes the read-write status and bit width corresponding to each of the message bodies in each level of FIFO; allocating required processing resources to each level of FIFO according to the read-write status and bit width corresponding to the message body in each level of FIFO; and controlling each level of FIFO to respectively use the allocated processing resources to process the message bodies in the set of message bodies to be processed.

[0006] In the embodiment of the present application, by obtaining a set of message bodies to be processed and a macro definition file generated according to a configuration file, the set of message bodies to be processed includes multiple message bodies, and the configuration file includes the read-write status and bit width corresponding to each message body in each level of FIFO, the required processing resources can be allocated to each level of FIFO according to the read-write status and bit width corresponding to the message body in each level of FIFO, and then the FIFO at each level is controlled to use the allocated processing resources to process the message bodies in the set of message bodies to be processed. The configuration file is set to achieve flexible allocation of processing resources in each level of FIFO, avoiding waste of FIFO resources at each level.

[0007] Furthermore, the method of allocating required processing resources to FIFOs at each level according to the read-write status and bit width corresponding to the message bodies in the FIFOs at each level includes: dynamically adjusting the message bodies included in the set of message bodies to be processed according to the read-write status corresponding to the message bodies in the FIFOs at each level, to obtain the target set of message bodies to be processed corresponding to the FIFOs at each level; determining the total bit width of the target set of message bodies to be processed corresponding to the FIFOs at each level according to the bit width corresponding to the message bodies included in the target set of message bodies to be processed corresponding to the FIFOs at each level; and allocating processing resources to the corresponding FIFOs according to the total bit width of the target set of message bodies to be processed corresponding to the FIFOs at each level.

[0008] In the embodiment of the present application, the message bodies included in the set of to-be-processed message bodies are dynamically adjusted according to the read-write status corresponding to the message bodies in the FIFOs at various levels, and the target to-be-processed message body sets corresponding to the FIFOs at various levels are obtained, and then the total bit width of the target to-be-processed message body sets corresponding to the FIFOs at various levels is determined according to the bit width corresponding to the message bodies included in the target to-be-processed message body sets corresponding to the FIFOs at various levels, and processing resources can be allocated to the corresponding FIFOs according to the total bit width of the target to-be-processed message body sets. The processing resources required for the FIFOs at various levels can be calculated by the read-write status and bit width of each message body configured in the configuration file in the FIFOs at various levels, thereby realizing the reasonable allocation of resources and avoiding waste of resources.

[0009] Furthermore, the read-write status includes one of read-write, read-only, write-only and transparent transmission, and the message bodies included in the set of message bodies to be processed are dynamically adjusted according to the read-write status corresponding to the message bodies in the FIFOs at each level, including: removing the message bodies in the FIFOs at each level whose read-write status is transparent transmission from the set of message bodies to be processed.

[0010] In an embodiment of the present application, the read and write status of the message body may include read and write, read-only, write-only and transparent transmission. By removing the message body with a read and write status of transparent transmission in each level of FIFO from the set of message bodies to be processed, the target set of message bodies to be processed corresponding to each level of FIFO is obtained, and the compression of the structure of the message body set to be processed by each level of FIFO is achieved, thereby reducing the processing resources required by each level of FIFO and avoiding the waste of empty resources.

[0011] Furthermore, the control of each level of FIFO uses the allocated processing resources to process the message bodies in the set of message bodies to be processed, including: determining the survival interval corresponding to each of the message bodies, the survival interval being the cascaded FIFOs at each level including the interval start point and the interval end point; according to the survival interval, the message body processed by the upper level FIFO is used as the input of the lower level FIFO until the processing of the message body by the corresponding FIFOs at each level within the survival interval is completed using the processing resources corresponding to the FIFOs at each level.

[0012] In the embodiment of the present application, by determining the survival interval corresponding to each message body, the survival interval is the FIFO of each level including the interval start point and the interval end point, and according to the survival interval, the message body processed by the upper FIFO can be used as the input of the lower FIFO, until the processing resources corresponding to each FIFO are used to complete the processing of the message body by each FIFO in the survival space. Thus, the processing of each message body by each FIFO is realized, and the processing resources are fully utilized.

[0013] Furthermore, the obtaining of the macro definition file pre-generated according to the configuration file includes: obtaining a pre-written configuration file; translating the configuration file to generate a macro definition file executable on the FPGA chip carried by the electronic device.

[0014] In the embodiment of the present application, a pre-written configuration file is obtained and translated to generate a macro definition file executable on the FPGA chip carried by the electronic device. By translating the configuration file, the flexible arrangement of the macro definition file is realized, which is conducive to adjusting the corresponding message body set in the FIFO at each level and the change of processing resources, and improves the development efficiency of developers.

[0015] Furthermore, the method also includes: modifying the read / write status or bit width corresponding to the message body included in the configuration file in each level of FIFO; or, defining a new message body in the configuration file, and increasing the corresponding read / write status and bit width of the new message body in each level of FIFO.

[0016] In an embodiment of the present application, the read and write status or bit width corresponding to the message body in each level of FIFO can also be modified in the configuration file. A new message body can also be defined in the configuration file, and the read and write status and bit width corresponding to the message body in each level of FIFO can be added, thereby realizing the modification of the configuration file on the FPGA, which is conducive to adjusting the message processing design of each level of FIFO on the FPGA and improving the flexibility and configurability of the FPGA design.

[0017] Furthermore, the method further includes: defining a new FIFO and a corresponding cascade position in the configuration file, and defining the read / write status and bit width of each message body in the new FIFO.

[0018] In an embodiment of the present application, by defining a new FIFO and the cascade position of the FIFO in a configuration file, and then defining the read and write status and bit width of each message body in the FIFO, the processing logic design of the FIFO is quickly implemented, thereby further improving the message processing efficiency of the FPGA.

[0019] In a second aspect, an embodiment of the present application provides a message processing device, comprising: an acquisition module, used to acquire a set of message bodies to be processed and a macro definition file pre-generated according to a configuration file, wherein the set of message bodies to be processed includes multiple message bodies, and the configuration file includes the read-write status and bit width corresponding to each of the message bodies in each level of FIFO; an allocation module, used to allocate required processing resources to each level of FIFO according to the read-write status and bit width corresponding to the message bodies in each level of FIFO; and a control module, used to control the FIFOs at each level to respectively use the allocated processing resources to process the message bodies in the set of message bodies to be processed.

[0020] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a memory, and a bus, wherein the processor and the memory interact with each other through the bus;

[0021] The memory stores program instructions that can be executed by the processor, and the processor can execute the method of the first aspect by calling the program instructions.

[0022] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including:

[0023] The computer-readable storage medium stores computer instructions, which cause the computer to execute the method of the first aspect.

[0024] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the embodiments of the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of a message processing method provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of a specific processing process of a single FIFO provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of a single FIFO message body change provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of the structure of a message processing device provided in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] Before introducing a message processing method provided in an embodiment of the present application, some concepts involved in the embodiment of the present application are first introduced:

[0032] FPGA (Field Programmable Gate Array, also known as large-scale programmable logic circuit): a product further developed on the basis of programmable devices. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0033] FIFO (First Input First Output): It is a first-in-first-out dual-port buffer, that is, the first data that enters it is the first to be removed. One port is the input port of the memory, and the other port is the output port of the memory. With its flexible, convenient and efficient characteristics, it is gradually being used more and more widely in high-speed data acquisition, high-speed data processing, high-speed data transmission and multi-machine processing systems.

[0034] Pipeline streamlined design: a method of systematically dividing the combinational logic, inserting registers between each part (level), and temporarily storing intermediate data. The purpose is to decompose a large operation into several small operations. Each small operation takes a short time, so the frequency can be increased. Each small operation can be executed in parallel, so the data throughput can be increased, and the line speed processing of each level of FIFO can be achieved.

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0036] Figure 1 A flow chart of a message processing method provided in an embodiment of the present application is as follows: Figure 1 As shown, the method can be applied to an electronic device equipped with a field programmable gate array FPGA, wherein the FPGA includes cascade-connected first-in first-out memory FIFOs of various levels, and the FPGA uses a multi-level cascade-connected FIFO, and adopts a pipeline streamlined design, so as to achieve line-speed processing of the message body; wherein the electronic device can specifically be a smart phone, a tablet computer, a computer, a personal digital assistant (PDA), a server, etc.; the server can specifically be an application server or a Web server. The method includes:

[0037] Step 101: Obtain a set of message bodies to be processed and a macro definition file pre-generated according to a configuration file, wherein the set of message bodies to be processed includes multiple message bodies, and the configuration file includes the read / write status and bit width corresponding to each of the message bodies in each level of FIFO.

[0038] In the specific implementation process, the set of message bodies to be processed can be a set of message bodies processed in FIFOs at all levels in the FPGA. There can be multiple message bodies in the set of message bodies to be processed, and each message body can be processed by different FIFOs. The configuration file can be a mapping file written in some high-level programming languages ​​such as Python and Java. The configuration file can define the corresponding read and write status and bit width of each message body in FIFOs at all levels. The read and write status can be the read and write processing of the message body by FIFO, such as read and write, read-only, write-only, etc. The bit width can be the data size occupied by the message body, such as 4bit, 8bit, which is related to the size of the message body. The configuration file can be used to achieve flexible conversion with the macro definition file. The macro definition file can be a file with system verilog attributes that can be executed on the FPGA. System verilog is a low-level hardware description and verification language, which is mainly positioned in the chip implementation and verification process, and provides powerful connection capabilities for the system-level design process. The flexible design of the message body can be achieved by pre-generating the configuration file.

[0039] Step 102: Allocate required processing resources to each level of FIFO according to the read / write status and bit width corresponding to the message body in each level of FIFO.

[0040] In the specific implementation process, in order to ensure that the processing resource size of each level of FIFO can accommodate the set of pending message bodies corresponding to the FIFO, the processing resources required for each level of FIFO can be allocated according to the read and write status and bit width of each message body configured in the configuration file in the FIFO at each level. The processing resources can be the random storage RAM resources required for the FIFO at each level. The electronic device can allocate the RAM resources required for the FIFO at each level according to the writing and reading of the set of pending message bodies by the FIFO at each level, thereby maximizing the utilization of processing resources.

[0041] Step 103: Controlling each level of FIFO to process the message bodies in the set of to-be-processed message bodies using the allocated processing resources respectively.

[0042] In the specific implementation process, after the above-mentioned electronic device has allocated the processing resources required for each level of FIFO, the FIFOs at each level are controlled to use the allocated processing resources to process the message bodies in the message body set to be processed. The read and write status of each message body in the FIFO at each level has been defined in the previous configuration file. According to the read and write status of these message bodies, the message bodies in the message body set to be processed can be processed to complete the overall processing process of the entire FPGA on the message body to be processed, thereby realizing the maximum utilization of resources based on FIFO, and being able to maintain the original FPGA architecture design, and using the configuration file to flexibly adjust the processing resources required for each level of FIFO, thereby improving configurability and maintainability.

[0043] On the basis of the above embodiment, the method of allocating required processing resources to FIFOs at each level according to the read / write status and bit width corresponding to the message body in the FIFOs at each level includes:

[0044] Dynamically adjusting the message bodies included in the to-be-processed message body set according to the read and write states corresponding to the message bodies in the FIFOs at each level, and obtaining the target to-be-processed message body set corresponding to the FIFOs at each level;

[0045] Determine the total bit width of the target to-be-processed message body set corresponding to each level of FIFO according to the bit width corresponding to the message body included in the target to-be-processed message body set corresponding to each level of FIFO;

[0046] Processing resources are allocated to the corresponding FIFOs according to the total bit width of the target to-be-processed message body set corresponding to the FIFOs at each level.

[0047] In a specific implementation, the set of to-be-processed message bodies processed by each level of FIFO can be dynamically adjusted through the read-write status corresponding to the message bodies in each level of FIFO, and the target to-be-processed message body set corresponding to each level of FIFO can be obtained. The dynamic adjustment can be to streamline the set of to-be-processed message bodies. For example, for a message body that is neither read nor written in the read-write status, the message body can be removed from the set of to-be-processed message bodies, thereby streamlining the message body set and avoiding wasting processing resources. The total bit width of each level of FIFO is determined based on the bit width of the message body included in the target to-be-processed message body set, and corresponding processing resources are allocated to each level of FIFO based on the total bit width, thereby achieving full utilization of resources.

[0048] On the basis of the above embodiment, the read / write state includes one of read / write, read-only, write-only and transparent transmission, and the message bodies included in the set of to-be-processed message bodies are dynamically adjusted according to the read / write states corresponding to the message bodies in the FIFOs at each level, including:

[0049] The message bodies in the FIFO at each level whose read / write status is transparent transmission are removed from the set of message bodies to be processed.

[0050] In the specific implementation process, the read-write status can include read-write, read-only, write-only and transparent transmission. The read-write status of each message body in each level of FIFO can be pre-defined in the configuration file. For example, if the read-write status of message body A in FIFO1 is read-write, then FIFO1 needs to allocate corresponding read-write resources for the message body, and the read-write status of message body B in FIFO1 is transparent transmission, then the message body does not occupy the processing resources of FIFO1, and the message body can be transmitted through the universal address in FPGA. Therefore, it is necessary to remove the message body with transparent transmission in each level of FIFO from the set of message bodies to be processed to save processing resources. Each FIFO is equivalent to a message processing module in the pipeline, including a read interface and a write interface. The user can obtain the message body from the read interface in the message processing module, and then write the message body into the FIFO through the write interface, and merge these message bodies in the message processing module to generate the target set of message bodies to be processed corresponding to the FIFO as a factor for processing resource allocation. It is understandable that for some user reading technical scenarios, that is, the process in which an external device needs to read a message body from the electronic device, it is not the reading process of the lower-level FIFO, and the complete set of message bodies to be processed needs to be mapped and output.

[0051] Figure 2 A schematic diagram of a specific processing process of a single FIFO provided for an embodiment of the present application. The change process of obtaining a target message body set to be processed after the message body set to be processed in each FIFO is specifically introduced. It can be seen from the figure that each FIFO may include a read interface FIFO (rd) and a write interface FIFO (wr), and the message body content in the read interface and the write interface may be determined according to the read and write status of each message body in the message body set to be processed, respectively. The message body included in the read interface may be Field A and Field E, and the message body included in the write interface may be Field A and Field C, while Field B and Field D do not need to be processed in the FIFO, and there is no need to allocate processing resources. As for the transmission process of the message body included in the corresponding message body set in each FIFO on the address bus, the complete message body set will be transmitted on the address bus on the FPGA.

[0052] Figure 3 A schematic diagram of a single FIFO message body change provided in an embodiment of the present application mainly explains the change of the target to-be-processed message body set in a single FIFO through a schematic diagram of a specific message body change introduced by an example FIFO. Figure 3As shown, the left half of the figure shows the state of the message body set in the FIFO before processing, including 5 message bodies as described in the following Table 1. Table 1 shows the state of the message body set in the FIFO before processing.

[0053] Table 1 The state of the message body collection in FIFO before processing

[0054] Message body name Read and write status Field A wr / rd (read and write) Field B no used (transparent transmission) Field C wr (write only) Field D no used (transparent transmission) Field E rd (read-only)

[0055] The right half of the figure shows the state of the message body set after processing in the FIFO. Since the read and write states corresponding to Field B and Field D are transparent transmission, the FIFO removes the two transparent message bodies to obtain a compact target message body set to be processed. Therefore, the target message body set to be processed includes 3 message bodies, as described in Table 2 below. Table 2 shows the state of the message body set in the FIFO after processing. According to the processed target message body set to be processed, the corresponding processing resources can be allocated to the FIFO.

[0056] Table 2 The status of the message body collection after processing in FIFO

[0057] Message body name Read and write status Field A wr / rd (read and write) Field C wr (write only) Field E rd (read-only)

[0058] On the basis of the above embodiment, the controlling each level of FIFO uses the allocated processing resources to process the message bodies in the set of to-be-processed message bodies respectively, including:

[0059] Determine a survival interval corresponding to each of the message bodies, wherein the survival interval is a cascade connection of FIFOs at all levels including a start point and an end point of the interval;

[0060] According to the survival interval, the message body processed by the upper FIFO is used as the input of the lower FIFO until the processing of the message body by the corresponding FIFOs at each level within the survival interval is completed by using the processing resources corresponding to the FIFOs at each level.

[0061] In the specific implementation process, the living space corresponding to each message body can be determined according to the corresponding read-write processing status of each message body in each FIFO in the configuration file. The living space can be a continuous FIFO with operation authority for the message body, including the interval start point and the interval end point. The interval start point can be the first FIFO to write the message body, that is, the FIFO to write the message body, and the interval end point can be the last FIFO to read the message body. The processing of each message body by each FIFO at each level is determined according to the living space of each message body. For example, three FIFOs connected in cascade, FIFO1, FIFO2, and FIFO3, when the message body is defined as read-write or read-only attribute in FIFO2, the entire message body to be processed can be compressed to obtain the target message body set to be processed for reading the message body. It should be noted that the message body read in FIFO3 comes from the input of FIFO2 or the input of other addresses. Here, the empty signal of FIFO can be used to merge the operation, and the written message body can be operated or operated, so that the FIFO3 synchronizes the message bodies to be read to the timing of the last arrival, and realizes the message synchronization operation of FIFO3.

[0062] It also includes that if multiple message bodies are defined as read-write or write-only status, FIFO will reorganize these message bodies into a target set of message bodies to be processed and allocate corresponding processing resources. After processing is completed, they are replaced in the reading of the lower-level FIFO, and the processing operations of each level of FIFO are performed in turn until the processing of the message body by each level of FIFO is completed.

[0063] Based on the above embodiment, the step of obtaining a macro definition file pre-generated according to the configuration file includes:

[0064] Get a pre-written configuration file;

[0065] The configuration file is translated to generate a macro definition file executable on the FPGA chip carried by the electronic device.

[0066] In the specific implementation process, first obtain the pre-written configuration file, which can use Python to write a mapping file as the top-level configuration file to implement the read and write status and bit width configuration of each message body. Then translate the configuration file, and the translation method can be written into a specified file according to the code rules instantiated by the Verilog template, so as to obtain a macro definition file, which simplifies the writing of FPGA design files by not directly modifying the macro definition file.

[0067] Based on the above embodiment, the method further includes:

[0068] Modify the read / write status or bit width corresponding to the message body included in the configuration file in each level of FIFO; or,

[0069] A new message body is defined in the configuration file, and the corresponding read / write status and bit width of the new message body in each level of FIFO are increased.

[0070] In the specific implementation process, in the pre-written configuration file, the corresponding read / write status or bit width of the message body included in the to-be-processed message body set in each FIFO can also be modified, and then the macro definition file of the system verilog attribute is generated by the translation tool to realize the editability of the macro definition file. It is also possible to define a new message body, insert the new message body into the to-be-processed message body set, and configure the read / write status and bit width through the configuration file, thereby realizing the flexible change of the configuration file.

[0071] Based on the above embodiment, the method further includes:

[0072] A new FIFO and a corresponding cascade position are defined in the configuration file, and the read / write status and bit width of each message body are defined in the new FIFO.

[0073] In the specific implementation process, the cascade position can be the specific position relationship of the new FIFO defined in the configuration file in the FIFOs of each level cascaded in the above FPGA. By defining the new FIFO, the FIFO can be configured, and the cascade order of the original FIFO can be adjusted to obtain the optimal configuration. Then, the read and write status and bit width of the message body are added to the new FIFO to realize the processing of the message body by the FIFO, thereby improving the maintainability of the FPGA.

[0074] Figure 4 This is a schematic diagram of the structure of a message processing device provided in an embodiment of the present application. The device may be a module, program segment or code on an electronic device. It should be understood that the device is similar to the above-mentioned Figure 1 The method embodiment corresponds to and can be executed Figure 1 The various steps involved in the method embodiment and the specific functions of the device can be found in the above description. To avoid repetition, detailed description is appropriately omitted here. The embodiment of the present application provides a message processing device, which includes:

[0075] An acquisition module 401 is used to acquire a message body set to be processed and a macro definition file pre-generated according to a configuration file, wherein the message body set to be processed includes multiple message bodies, and the configuration file includes a read / write status and a bit width corresponding to each of the message bodies in each level of FIFO;

[0076] An allocation module 402 is used to allocate required processing resources to each level of FIFO according to the read / write status and bit width corresponding to the message body in each level of FIFO;

[0077] The control module 403 is used to control the FIFOs at each level to process the message bodies in the set of to-be-processed message bodies using the allocated processing resources.

[0078] Based on the above embodiment, the allocation module 402 is specifically used for:

[0079] Dynamically adjusting the message bodies included in the to-be-processed message body set according to the read and write states corresponding to the message bodies in the FIFOs at each level, and obtaining the target to-be-processed message body set corresponding to the FIFOs at each level;

[0080] Determine the total bit width of the target to-be-processed message body set corresponding to each level of FIFO according to the bit width corresponding to the message body included in the target to-be-processed message body set corresponding to each level of FIFO;

[0081] Processing resources are allocated to the corresponding FIFOs according to the total bit width of the target to-be-processed message body set corresponding to the FIFOs at each level.

[0082] Based on the above embodiment, the read-write state includes one of read-write, read-only, write-only and transparent transmission.

[0083] Based on the above embodiment, the allocation module 402 is specifically used for:

[0084] The message bodies in the FIFO at each level whose read / write status is transparent transmission are removed from the set of message bodies to be processed.

[0085] Based on the above embodiment, the control module 403 is specifically used for:

[0086] Determine a survival interval corresponding to each of the message bodies, wherein the survival interval is a cascade connection of FIFOs at all levels including a start point and an end point of the interval;

[0087] According to the survival interval, the message body processed by the upper FIFO is used as the input of the lower FIFO until the processing of the message body by the corresponding FIFOs at each level within the survival interval is completed by using the processing resources corresponding to the FIFOs at each level.

[0088] Based on the above embodiment, the device further includes a message body configuration module, which is used to:

[0089] Modify the read / write status or bit width corresponding to the message body included in the configuration file in each level of FIFO; or,

[0090] A new message body is defined in the configuration file, and the corresponding read / write status and bit width of the new message body in each level of FIFO are increased.

[0091] Based on the above embodiment, the device further includes a FIFO configuration module, which is used to:

[0092] A new FIFO and a corresponding cascade position are defined in the configuration file, and the read / write status and bit width of each message body are defined in the new FIFO.

[0093] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Figure 5 As shown, the electronic device includes: a processor (processor) 501, a memory (memory) 502 and a bus 503; wherein,

[0094] The processor 501 and the memory 502 interact with each other via the bus 503;

[0095] The processor 501 is used to call the program instructions in the memory 502 to execute the message processing methods provided by the above-mentioned method embodiments.

[0096] The processor 501 can be an integrated circuit chip with signal processing capabilities. The above-mentioned processor 501 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. It can implement or execute various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0097] The memory 502 may include, but is not limited to, random access memory (RAM), read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), etc.

[0098] This embodiment discloses a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the message processing methods provided by the above-mentioned method embodiments.

[0099] This embodiment provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the message processing methods provided by the above-mentioned method embodiments.

[0100] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or interactive connection shown or discussed can be through some interactive interfaces, and the indirect coupling or interactive connection of devices or units can be electrical, mechanical or other forms.

[0101] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0103] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0104] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A message processing method, characterized in that: The invention is applied to an electronic device equipped with a field programmable gate array (FPGA), wherein the FPGA includes various levels of first-in first-out memory (FIFO) connected in cascade, including: Obtain a message body set to be processed and a macro definition file pre-generated according to a configuration file, wherein the message body set to be processed includes multiple message bodies, and the configuration file includes the read / write status and bit width corresponding to each of the message bodies in each level of FIFO; Allocate required processing resources to each level of FIFO according to the read / write status and bit width corresponding to the message body in each level of FIFO; Controlling each level of FIFO to respectively use the allocated processing resources to process the message bodies in the set of to-be-processed message bodies; The allocating required processing resources to each level of FIFO according to the read / write status and bit width corresponding to the message body in each level of FIFO includes: Dynamically adjusting the message bodies included in the to-be-processed message body set according to the read and write states corresponding to the message bodies in the FIFOs at each level, and obtaining the target to-be-processed message body set corresponding to the FIFOs at each level; Determine the total bit width of the target to-be-processed message body set corresponding to each level of FIFO according to the bit width corresponding to the message body included in the target to-be-processed message body set corresponding to each level of FIFO; Processing resources are allocated to the corresponding FIFOs according to the total bit width of the target to-be-processed message body set corresponding to the FIFOs at each level.

2. The method according to claim 1, characterized in that The read / write state includes one of read / write, read-only, write-only and transparent transmission, and the message bodies included in the set of to-be-processed message bodies are dynamically adjusted according to the read / write states corresponding to the message bodies in the FIFOs at each level, including: The message bodies in the FIFO at each level whose read / write status is transparent transmission are removed from the set of message bodies to be processed.

3. The method according to claim 1, characterized in that The controlling each level of FIFO to respectively process the message bodies in the set of to-be-processed message bodies using the allocated processing resources includes: Determine a survival interval corresponding to each of the message bodies, wherein the survival interval is a cascade connection of FIFOs at all levels including a start point and an end point of the interval; According to the survival interval, the message body processed by the upper FIFO is used as the input of the lower FIFO until the processing of the message body by the corresponding FIFOs at each level within the survival interval is completed by using the processing resources corresponding to the FIFOs at each level.

4. The method according to claim 1, characterized in that: The step of obtaining a macro definition file pre-generated according to the configuration file includes: Get a pre-written configuration file; The configuration file is translated to generate a macro definition file executable on the FPGA chip carried by the electronic device.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: Modify the read / write status or bit width corresponding to the message body included in the configuration file in each level of FIFO; or, A new message body is defined in the configuration file, and the corresponding read / write status and bit width of the new message body in each level of FIFO are increased.

6. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: A new FIFO and a corresponding cascade position are defined in the configuration file, and the read / write status and bit width of each message body are defined in the new FIFO.

7. A message processing device, characterized in that: The invention is applied to an electronic device equipped with a field programmable gate array (FPGA), wherein the FPGA includes various levels of first-in first-out memory (FIFO) connected in cascade, including: An acquisition module, used to acquire a message body set to be processed and a macro definition file pre-generated according to a configuration file, wherein the message body set to be processed includes multiple message bodies, and the configuration file includes the read / write status and bit width corresponding to each of the message bodies in each level of FIFO; An allocation module, used for allocating required processing resources to each level of FIFO according to the read / write status and bit width corresponding to the message body in each level of FIFO; A control module, used for controlling each level of FIFO to respectively process the message bodies in the set of to-be-processed message bodies using the allocated processing resources; The allocation module is specifically used to dynamically adjust the message bodies included in the to-be-processed message body set according to the read and write states corresponding to the message bodies in the FIFOs at each level, and obtain the target to-be-processed message body set corresponding to the FIFOs at each level; Determine the total bit width of the target to-be-processed message body set corresponding to each level of FIFO according to the bit width corresponding to the message body included in the target to-be-processed message body set corresponding to each level of FIFO; Processing resources are allocated to the corresponding FIFOs according to the total bit width of the target to-be-processed message body set corresponding to the FIFOs at each level.

8. An electronic device, characterized in that: include: processor, memory and bus, wherein, The processor and the memory communicate with each other via the bus; The memory stores program instructions executable by the processor, and the processor can execute the method according to any one of claims 1 to 6 by calling the program instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a computer, the computer is caused to perform the method according to any one of claims 1 to 6.

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