A clock frequency testing method, device, electronic equipment and storage medium

Abstract

The invention relates to the field of chip technology, and specifically discloses a clock frequency testing method, device, electronic equipment and storage medium, wherein the method comprises the following steps: setting a linearly varying system clock frequency Fsys, the system clock frequency Fsys satisfies: Fsys=Fs*(PLLn / (PLLm*PLLp)); setting a QSPI clock frequency Freq, the QSPI clock frequency Freq satisfies: Freq=Fsys / div; adjusting the size of div according to the linearly varying system clock frequency Fsys to obtain QSPI clock frequencies Freq with different variation ranges; testing and obtaining the clock frequency of SPI FLASH data reading according to the QSPI clock frequencies Freq with different variation ranges; the method obtains Freq with different variation ranges by adjusting div, thereby achieving full frequency coverage of Freq, so as to accurately obtain the clock frequency of SPI FLASH data reading.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a clock frequency testing method, device, electronic device and storage medium. Background Art

[0002] The main control chip usually uses the QSPI (Qual SPI) bus to communicate with the SPI FLASH (serial memory chip).

[0003] QSPI is a hardware communication interface specifically for SPI FLASH, used to connect single, dual or quad data line SPI Flash storage media.

[0004] The frequency of the QSPI clock signal CLK is controlled by the main control chip. The frequency of CLK determines the speed at which the main control chip reads Flash data. The clock signal frequency set by the main control chip varies according to different application scenarios. The lowest frequency is only a few megahertz and the highest is up to hundreds of megahertz. Therefore, a scan test is required before using SPI FLASH to obtain the clock frequency for data reading.

[0005] The existing SPI FLASH data reading clock full frequency test method can generally only measure limited frequency points and cannot achieve full frequency coverage. For clock frequencies that are not at the frequency point, only approximate values ​​can be matched, which has the problem of insufficient accuracy.

[0006] There is currently no effective technical solution to the above problems. Summary of the invention

[0007] The purpose of the present application is to provide a clock frequency testing method, device, electronic device and storage medium to achieve full frequency coverage of Freq so as to accurately obtain the clock frequency for reading SPI FLASH data.

[0008] In a first aspect, the present application provides a clock frequency testing method for scanning and testing the clock frequency of SPI FLASH data reading, the method comprising the following steps:

[0009] Set a linearly varying system clock frequency Fsys, which satisfies:

[0010] Fsys = Fs*(PLLn / (PLLm*PLLp));

[0011] Among them, Fs is the internal crystal oscillator, PLLn is the main phase-locked loop frequency multiplication coefficient, PLLm is the main phase-locked loop frequency division coefficient, and PLLp is the system clock frequency division coefficient;

[0012] Set the QSPI clock frequency Freq, where the QSPI clock frequency Freq satisfies:

[0013] Freq = Fsys / div;

[0014] Where, div is the clock division factor of QSPI;

[0015] According to the linearly varying system clock frequency Fsys, the size of the div is adjusted to obtain the QSPI clock frequency Freq in different varying ranges;

[0016] The clock frequency for reading the SPI FLASH data is obtained by testing the QSPI clock frequency Freq in different variation ranges.

[0017] A clock frequency testing method of the present application can obtain the corresponding Freq according to the linearly changing Fsys, so that Freq can change linearly following the linear change of Fsys, and obtain Freq in different change ranges by adjusting div, thereby achieving full frequency coverage of Freq, so as to accurately obtain the clock frequency of SPI FLASH data reading, and avoid setting the system clock frequency Fsys too low to cause the test to be too slow.

[0018] The clock frequency testing method described above, wherein the PLLm and the PLLp are preset positive constant values.

[0019] In the clock frequency testing method of this example, PLLm and PLLp are preset to positive constant values, which effectively reduces system variables, so that the system clock frequency Fsys can be accurately adjusted according to the change amount of PLLn.

[0020] The clock frequency testing method, wherein the PLLm and the PLLp are selected according to the Fs, satisfying:

[0021] PLLm*PLLp / Fs=1MHz -1 , making PLLn=Freq*div*1MHz -1 .

[0022] In the clock frequency testing method of this example, the value of PLLn is equal to the frequency value of the system clock frequency Fsys, so the system clock frequency Fsys can be adjusted conveniently and accurately according to PLLn.

[0023] A clock frequency testing method, wherein the div=1,2,4,8,20,50,100.

[0024] In the clock frequency testing method, the system clock frequency Fsys varies in the range of 50 MHz to 216 MHz.

[0025] In the clock frequency testing method, the div is adjusted from small to large or from large to small.

[0026] In the clock frequency test method of this example, the increasing or decreasing adjustment mode of div can make the acquisition process of the clock frequency of SPI FLASH data reading proceed in an orderly manner.

[0027] In the clock frequency testing method, the system clock frequency Fsys changes linearly. When the system clock frequency Fsys changes to the boundary value of the variation range, the div size is adjusted and the linear variation direction of the system clock frequency Fsys is changed.

[0028] In a second aspect, the present application further provides a clock frequency testing device for scanning and testing the clock frequency of SPI FLASH data reading, the device comprising:

[0029] The setting module is used to set the linearly changing system clock frequency Fsys and QSPI clock frequency Freq, wherein the system clock frequency Fsys satisfies:

[0030] Fsys = Fs*(PLLn / (PLLm*PLLp));

[0031] Among them, Fs is the internal crystal oscillator, PLLn is the main phase-locked loop frequency multiplication coefficient, PLLm is the main phase-locked loop frequency division coefficient, and PLLp is the system clock frequency division coefficient;

[0032] The QSPI clock frequency Freq satisfies:

[0033] Freq = Fsys / div;

[0034] Where, div is the clock division factor of QSPI;

[0035] An adjusting module, used for adjusting the size of the div according to the linearly changing system clock frequency Fsys to obtain the QSPI clock frequency Freq in different changing ranges;

[0036] The test module is used to obtain the clock frequency of the SPI FLASH data reading according to the QSPI clock frequency Freq test with different variation ranges.

[0037] A clock frequency testing device of the present application can obtain the corresponding Freq according to the linearly changing Fsys, so that Freq can change linearly following the linear change of Fsys, and obtain Freq with different change ranges by adjusting div through an adjustment module, thereby achieving full frequency coverage of Freq, so that the test module can accurately obtain the clock frequency for reading SPI FLASH data, and avoid setting the system clock frequency Fsys too low, resulting in slow testing.

[0038] In a third aspect, the present application further provides an electronic device, comprising a processor and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method provided in the first aspect are executed.

[0039] In a fourth aspect, the present application further provides a storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps in the method provided in the first aspect are executed.

[0040] From the above, it can be seen that the present application provides a clock frequency testing method, device, electronic device and storage medium, wherein the method can obtain the corresponding Freq according to the linearly changing Fsys, so that Freq can change linearly following the linear change of Fsys, and obtain Freq with different change ranges by adjusting div, thereby achieving full frequency coverage of Freq, so as to accurately obtain the clock frequency of SPIFLASH data reading, and avoid the system clock frequency Fsys being set too low, resulting in slow testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A flowchart of a clock frequency testing method provided in an embodiment of the present application.

[0042] Figure 2 A schematic diagram of the structure of a clock frequency testing device provided in an embodiment of the present application.

[0043] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0045] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0046] The scan test of the clock frequency of SPI FLASH data reading is generally performed based on MCU. The system clock of the traditional MCU-based SPI FLASH data reading clock frequency test method is fixed, and the clock frequency of SPI FLASH data reading can only be tested by frequency division to obtain the characteristic frequency point. Most of the time, the accurate SPI FLASH data reading clock frequency cannot be obtained and can only be replaced by an approximate value, which affects the data transmission capability to a certain extent.

[0047] First, please refer to Figure 1 , Figure 1 A clock frequency test method in some embodiments of the present application is used to scan and test the clock frequency of SPI FLASH data reading, and the method includes the following steps:

[0048] S1. Set the linearly changing system clock frequency Fsys. The system clock frequency Fsys satisfies:

[0049] Fsys = Fs*(PLLn / (PLLm*PLLp)) (1)

[0050] Among them, Fs is the internal crystal oscillator, PLLn is the main phase-locked loop frequency multiplication coefficient, PLLm is the main phase-locked loop frequency division coefficient, and PLLp is the system clock frequency division coefficient;

[0051] Specifically, the method of the embodiment of the present application is improved based on the MCU testing method, and is implemented by setting the system clock frequency Fsys in the MCU to be dynamically changed.

[0052] More specifically, the linearly changing system clock frequency Fsys may be a straight line change or a curve change.

[0053] More specifically, the linearly changing system clock frequency Fsys changes incrementally or incrementally during a change process, that is, it changes incrementally or incrementally from one boundary value within the change range to another boundary value, so that the change process of the system clock frequency Fsys traverses all frequency values ​​within its change range.

[0054] More specifically, PLLm is used to divide the frequency of the main PLL, and PLLp is used for the main PLL to divide the frequency of the system clock. PLL is a phase locked loop (Phase Locked Loop).

[0055] S2. Set the QSPI clock frequency Freq. The QSPI clock frequency Freq satisfies:

[0056] Freq = Fsys / div (2)

[0057] Where, div is the clock division factor of QSPI;

[0058] S3, adjusting the size of div according to the linearly changing system clock frequency Fsys to obtain Freq with different changing ranges;

[0059] S4. The clock frequency for reading SPI FLASH data is obtained by testing the QSPI clock frequency Freq in different variation ranges.

[0060] Specifically, it can be seen from formula (2) that the system clock frequency Fsys is div times the QSPI clock frequency Freq. Therefore, when the linear variation range of the system clock frequency Fsys is determined, the QSPI clock frequency Freq in different ranges can be obtained by changing the value of div. In other words, if it is necessary to obtain QSPI clock frequencies Freq in different ranges, it is not necessary to change the linear variation range of the system clock frequency Fsys, but only to change the value of div, so that the system clock frequency Fsys can be maintained within a suitable variation range, avoiding the problem of too slow execution speed of the system test program during the test due to the system clock frequency Fsys being set too low, and ensuring that the method of the embodiment of the present application can efficiently obtain the clock frequency for reading SPI FLASH data.

[0061] More specifically, the size of div in step S3 needs to be set so that the corresponding acquired variation range of Freq is superimposed to achieve full frequency coverage, so as to ensure that the method of the present application can accurately obtain the clock frequency of SPI FLASH data reading.

[0062] More specifically, full frequency coverage refers to the entire variation range obtained after superimposing the frequency variation range of Freq, which can fully cover all different SPI FLASH data reading clock frequencies. For example, the maximum value of the SPI FLASH data reading clock frequency is 216MHz and the minimum value is 1MHz. Then, the entire variation range obtained after superimposing the frequency variation range of Freq is 1MHz-216MHz, which can achieve full frequency coverage.

[0063] More specifically, in step S4, when Freq is adjusted to be able to communicate with SPI FLASH, the frequency value of Freq at this time is the clock frequency for reading SPI FLASH data.

[0064] A clock frequency testing method in an embodiment of the present application can obtain the corresponding Freq according to the linearly changing Fsys, so that Freq can change linearly following the linear change of Fsys, and obtain Freq in different change ranges by adjusting div, thereby achieving full frequency coverage of Freq, so as to accurately obtain the clock frequency for reading SPI FLASH data and avoid setting the system clock frequency Fsys too low, resulting in slow testing.

[0065] In some preferred implementations, PLLm and PLLp are preset positive constant values.

[0066] Specifically, the method of the embodiment of the present application is improved based on the MCU testing method, and mainly uses PLL (Phase Locked Loop) to unify and integrate clock signals to enable high-frequency devices to work normally; among them, PLLn, PLLm and PLLp are all adjustment parameters of PLL, which can be adjusted according to usage requirements.

[0067] Specifically, PLLm and PLLp are pre-set positive constants and will not change during the entire test process, while Fs is generally a fixed value. It can be seen from formula (1) that the frequency value of the system clock frequency Fsys ultimately depends on PLLn. In the embodiment of the present application, PLLn is a dynamic value and changes linearly, which is used to make the system clock frequency Fsys produce the required linear change and to limit the change range of the system clock frequency Fsys.

[0068] More specifically, PLLm and PLLp are preset to positive constant values, which effectively reduces system variables. When PLLm and PLLp are determined, according to formula (1), the system clock frequency Fsys is determined by Fs and PLLn, and Fs is a constant, which makes the system clock frequency Fsys proportional to PLLn, so that the system clock frequency Fsys can be accurately adjusted according to the change of PLLn.

[0069] In some preferred embodiments, PLLm and PLLp are selected according to Fs to satisfy:

[0070] PLLm*PLLp / Fs=1MHz -1 , making PLLn=Freq*div*1MHz -1 ; If the internal crystal oscillator Fs = 16MHz, preset PLLm to 8, PLLp to 2, then PLLn = Freq*div*1MHz -1 .

[0071] Specifically, according to PLLm*PLLp / Fs=1MHz -1 By conditionally setting PLLm and PLLp, the value of PLLn can be made equal to the frequency value of the system clock frequency Fsys, thereby conveniently and accurately adjusting the system clock frequency Fsys according to PLLn.

[0072] Specifically, since PLLn=Freq*div*1MHz -1 And the value of PLLn is equal to the frequency value of the system clock frequency Fsys, so the value of Freq can be directly obtained by dividing PLLn by div.

[0073] More specifically, the optional value of div is determined based on the variation range of the system clock frequency Fsys and the condition of satisfying the full frequency coverage of Freq.

[0074] In some preferred embodiments, div=1, 2, 4, 8, 20, 50, 100.

[0075] In some preferred implementations, the system clock frequency Fsys varies in the range of 50 MHz to 216 MHz.

[0076] Specifically, the minimum setting value of div is 1, and the maximum value of the clock frequency for reading SPI FLASH data is 216 MHz. Therefore, in the embodiment of the present application, the upper limit value of Fsys is set to 216 MHz, and in order to avoid the system clock frequency Fsys being set too low and causing the test to be too slow, the lower limit value of Fsys is set to 50 MHz; setting the variation range of Fsys to 50 MHz-216 MHz can ensure that the method of the embodiment of the present application can smoothly, efficiently and accurately obtain the clock frequency for reading SPI FLASH data.

[0077] In some preferred embodiments, the maximum value of the clock frequency for reading SPI FLASH data is 216 MHz, and the minimum value is 1 MHz. The method of the embodiment of the present application sets the variation range of Fsys to 80 MHz-216 MHz; accordingly, when div is 1, 2, 4, 8, 20, 50, and 100, respectively, the variation range of the obtained Freq is 80 MHz-216 MHz, 40 MHz-108 MHz, 20 MHz-54 MHz, 10 MHz-27 MHz, 4 MHz-10.8 MHz, 1.6 MHz-4.32 MHz, and 0.8 MHz-2.16 MHz, respectively, so that the variation range of Freq is 0.8 MHz-216 MHz after superposition, which includes the frequency range of 1 MHz -216 MHz, thereby achieving full frequency coverage.

[0078] In some preferred embodiments, the maximum value of the clock frequency for reading SPI FLASH data is 216 MHz, and the minimum value is 1 MHz. The method of the embodiment of the present application sets the variation range of Fsys to 88 MHz-216 MHz; accordingly, when div is 1, 2, 4, 8, 20, 50, and 100, respectively, the variation range of Freq obtained is 88 MHz-216 MHz, 44 MHz-108 MHz, 22 MHz-54 MHz, 11 MHz-27 MHz, 4.4 MHz-10.8 MHz, 1.76 MHz-4.32 MHz, and 0.88 MHz-2.16 MHz, respectively, so that the variation range of Freq is 0.88 MHz-216 MHz after superposition, which includes the frequency range of 1 MHz -216 MHz, thereby achieving full frequency coverage.

[0079] In some preferred embodiments, the maximum value of the clock frequency for reading SPI FLASH data is 216 MHz, and the minimum value is 1 MHz. The method of the embodiment of the present application sets the variation range of Fsys to 100 MHz-250 MHz; accordingly, when div is 1, 2, 4, 8, 20, 50, and 100, respectively, the variation range of Freq obtained is 100 MHz-250 MHz, 50 MHz-125 MHz, 20 MHz-62.5 MHz, 10 MHz-31.25 MHz, 5 MHz-12.5 MHz, 2 MHz-5 MHz, and 1 MHz-2.5 MHz, respectively, so that the variation range of Freq is 0.88 MHz-250 MHz after superposition, which includes the frequency range of 1 MHz -216 MHz, thereby achieving full frequency coverage.

[0080] In some preferred embodiments, the maximum value of the clock frequency for reading SPI FLASH data is 216 MHz, and the minimum value is 1 MHz. The method of the embodiment of the present application sets the range of Fsys to 80 MHz-216 MHz when div=1, and sets the range of Fsys to 80 MHz-200 MHz when div≠1; accordingly, when div is 1, 2, 4, 8, 20, 50, and 100, respectively, the obtained range of Freq is 80 MHz-216 MHz, 40 MHz-100 MHz, 20 MHz-50 MHz, 10 MHz-25 MHz, 4 MHz-10 MHz, 1.6 MHz-4 MHz, and 0.8 MHz-2 MHz, respectively, so that the range of Freq is superimposed to 0.8 MHz-216 MHz, including the frequency range of 1 MHz -216 MHz, thereby achieving full frequency coverage.

[0081] In some preferred implementations, div is adjusted from small to large or from large to small.

[0082] Specifically, div is adjusted from small to large, which can gradually change the range of Freq from a high frequency range to a low frequency range. For example, when the range of Fsys is 80MHz-216MHz, div is adjusted from 1 to 2, which can adjust the range of Freq from 80MHz-216MHz to 40MHz-108MHz. Similarly, div is adjusted from large to small, which can gradually change the range of Freq from a low frequency range to a high frequency range. The increasing or decreasing adjustment method of div can make the acquisition process of the clock frequency of SPI FLASH data reading proceed in an orderly manner.

[0083] In some preferred implementations, the system clock frequency Fsys changes linearly. When the system clock frequency Fsys changes to a boundary value of a variation range, the div size is adjusted and the linear variation direction of the system clock frequency Fsys is changed.

[0084] Specifically, Fsys changes in a straight line, that is, it changes along a certain increasing or decreasing rate; when Fsys changes from one boundary value to another boundary value, it indicates that the frequency values ​​within the current variation range of Freq determined based on Fsys and div have been tested, and the clock frequency for obtaining SPI FLASH data reading cannot be matched within the Freq variation range, so the size of div is adjusted to perform the Freq adjustment test within the next variation range.

[0085] More specifically, since Fsys is at a boundary value when the div adjustment changes, in order to avoid the instantaneous jump of Fsys affecting the test process, the linear change direction of Fsys is changed, and reverse adjustment is performed from the boundary value to ensure the stability of the test process. For example, Fsys is adjusted from 216MHz to 80MHz in a decreasing manner, and the div changes from 1 to 2 at this time. Then, in order to avoid the instantaneous jump of Fsys to 216MHz affecting the test process, Fsys is changed to an increasing adjustment, starting from 80MHz and gradually increasing to 216MHz to allow Freq to be gradually adjusted from 40MHz to 108MHz.

[0086] In some preferred implementations, the system clock frequency Fsys changes linearly. When the system clock frequency Fsys changes to a boundary value of a variation range, the div size is adjusted to return the system clock frequency Fsys to a boundary value within another variation range.

[0087] More specifically, this adjustment method can ensure that Fsys changes in a single direction during the entire test process, and can test and obtain the clock frequency for reading SPI FLASH data in a more orderly manner.

[0088] Example 1

[0089] A clock frequency test method of an embodiment of the present application is based on the measurement of the clock frequency of SPI FLASH data reading by MCU, wherein the internal crystal oscillator Fs of the MCU is 16MHz, the PLLm in the PLL is preset to 8, and the PLLp is preset to 2, so that PLLn=Freq*div*1MHz -1 .

[0090] Set the PLLn variation range to 80-216, and set div=1,2,4,8,20,50,100.

[0091] At the beginning, div is set to 1, and PLLn is adjusted from one boundary value of the variation range to another boundary value. During the adjustment process, whether Freq communicates with SPI FLASH is detected in real time. If it communicates, it is determined that the Freq at that moment is the clock frequency for reading SPI FLASH data. If Freq does not communicate with SPI FLASH during the entire process when PLLn changes to another boundary value of the variation range, div is incremented to the next value, and PLLn is adjusted again. This is repeated until the clock frequency for reading SPI FLASH data is obtained.

[0092] Example 2

[0093] A clock frequency test method of an embodiment of the present application is based on the measurement of the clock frequency of SPI FLASH data reading by MCU, wherein the internal crystal oscillator Fs of the MCU is 16MHz, the PLLm in the PLL is preset to 8, and the PLLp is preset to 2, so that PLLn=Freq*div*1MHz -1 .

[0094] Set the PLLn variation range to 50-216, set div=1,4,16,50.

[0095] At the beginning, div is set to 1, and PLLn is adjusted from one boundary value of the variation range to another boundary value. During the adjustment process, whether Freq communicates with SPI FLASH is detected in real time. If it communicates, it is determined that the Freq at that moment is the clock frequency for reading SPI FLASH data. If Freq does not communicate with SPI FLASH during the entire process when PLLn changes to another boundary value of the variation range, div is incremented to the next value, and PLLn is adjusted again. This is repeated until the clock frequency for reading SPI FLASH data is obtained.

[0096] Example 3

[0097] A clock frequency test method of an embodiment of the present application is based on the measurement of the clock frequency of SPI FLASH data reading by MCU, wherein the internal crystal oscillator Fs of the MCU is 16MHz, the PLLm in the PLL is preset to 8, and the PLLp is preset to 2, so that PLLn=Freq*div*1MHz -1 .

[0098] Set the PLLn variation range to 88-216, and set div=1,2,4,8,20,50,100.

[0099] At the beginning, div is set to 100, and PLLn is adjusted from one boundary value of the variation range to another boundary value. During the adjustment process, whether Freq communicates with SPI FLASH is detected in real time. If it communicates, it is determined that the Freq at that moment is the clock frequency for reading SPI FLASH data. If Freq does not communicate with SPIFLASH during the entire process when PLLn changes to another boundary value of the variation range, div is decreased to the next value, and PLLn is adjusted again. This is repeated until the clock frequency for reading SPI FLASH data is obtained.

[0100] Example 4

[0101] A clock frequency test method of an embodiment of the present application is based on the measurement of the clock frequency of SPI FLASH data reading by MCU, wherein the internal crystal oscillator Fs of the MCU is 16MHz, the PLLm in the PLL is preset to 8, and the PLLp is preset to 2, so that PLLn=Freq*div*1MHz -1 .

[0102] Set the PLLn variation range to 80-216, and set div=1,2,4,8,20,50,100.

[0103] At the beginning, div is set to 100, and PLLn is adjusted from one boundary value of the variation range to another boundary value. During the adjustment process, whether Freq communicates with SPI FLASH is detected in real time. If it communicates, it is determined that the Freq at that moment is the clock frequency for reading SPI FLASH data. If Freq does not communicate with SPIFLASH during the entire process of PLLn changing to another boundary value of the variation range, div is incremented to the next value, and the variation range of PLLn is set to 80-200, and PLLn is adjusted again, and this is repeated until the clock frequency for reading SPI FLASH data is obtained.

[0104] Second, please refer to Figure 2 , Figure 2 A clock frequency test device provided in some embodiments of the present application is used to scan and test the clock frequency of SPI FLASH data reading, and the device includes:

[0105] The setting module 201 is used to set the linearly changing system clock frequency Fsys and the QSPI clock frequency Freq. The system clock frequency Fsys satisfies:

[0106] Fsys = Fs*(PLLn / (PLLm*PLLp));

[0107] Among them, Fs is the internal crystal oscillator, PLLn is the main phase-locked loop frequency multiplication coefficient, PLLm is the main phase-locked loop frequency division coefficient, and PLLp is the system clock frequency division coefficient;

[0108] The QSPI clock frequency Freq satisfies:

[0109] Freq = Fsys / div;

[0110] Where, div is the clock division factor of QSPI;

[0111] An adjustment module 202, used for adjusting the size of div according to the linearly changing Fsys to obtain Freq with different changing ranges;

[0112] The testing module 203 is used to test and obtain the clock frequency for reading SPI FLASH data according to the QSPI clock frequency Freq in different variation ranges.

[0113] A clock frequency testing device according to an embodiment of the present application can obtain a corresponding Freq according to a linearly changing Fsys, so that Freq can change linearly following the linear change of Fsys, and obtain Freq with different change ranges by adjusting div through the adjustment module 202, thereby achieving full frequency coverage of Freq, so that the test module 203 can accurately obtain the clock frequency for reading SPI FLASH data, and avoid setting the system clock frequency Fsys too low to cause the test to be too slow.

[0114] In some preferred implementations, the clock frequency testing device is used to execute the clock frequency testing method of the first aspect.

[0115] Third, please refer to Figure 3 , Figure 3 This is a structural diagram of an electronic device provided in an embodiment of the present application. The present application provides an electronic device 3, including: a processor 301 and a memory 302. The processor 301 and the memory 302 are interconnected and communicate with each other via a communication bus 303 and / or other forms of connection mechanisms (not shown). The memory 302 stores a computer program executable by the processor 301. When the computing device is running, the processor 301 executes the computer program to execute the method in any optional implementation of the above-mentioned embodiment.

[0116] In a fourth aspect, an embodiment of the present application provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the method in any optional implementation of the above embodiment is executed. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, disk or optical disk.

[0117] In summary, the embodiments of the present application provide a clock frequency testing method, device, electronic device and storage medium, wherein the method can obtain the corresponding Freq according to the linearly changing Fsys, so that Freq can change linearly following the linear change of Fsys, and obtain Freq in different change ranges by adjusting div, thereby achieving full frequency coverage of Freq, so as to accurately obtain the clock frequency of SPI FLASH data reading, and avoid the system clock frequency Fsys being set too low, resulting in slow testing.

[0118] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0119] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0121] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0122] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A clock frequency testing method for scanning and testing the clock frequency of SPI FLASH data reading, characterized in that: The method comprises the following steps: Set a linearly varying system clock frequency Fsys, which satisfies: Fsys = Fs*(PLLn / (PLLm*PLLp)); Among them, Fs is the internal crystal oscillator, PLLn is the main phase-locked loop frequency multiplication coefficient, PLLm is the main phase-locked loop frequency division coefficient, and PLLp is the system clock frequency division coefficient; Set the QSPI clock frequency Freq, where the QSPI clock frequency Freq satisfies: Freq = Fsys / div; Where, div is the clock division factor of QSPI; According to the linearly varying system clock frequency Fsys, the size of the div is adjusted to obtain the QSPI clock frequency Freq in different varying ranges; The clock frequency for reading the SPI FLASH data is obtained by testing the QSPI clock frequency Freq in different variation ranges.

2. A clock frequency testing method according to claim 1, characterized in that: The PLLm and the PLLp are preset positive constant values.

3. A clock frequency testing method according to claim 1, characterized in that: The PLLm and the PLLp are selected according to the Fs, satisfying: PLLm*PLLp / Fs=1MHz -1 , making PLLn=Freq*div*1MHz -1 .

4. A clock frequency testing method according to claim 3, characterized in that: The div=1,2,4,8,20,50,100.

5. A clock frequency testing method according to claim 1, characterized in that: The system clock frequency Fsys varies in the range of 50 MHz to 216 MHz.

6. A clock frequency testing method according to claim 1, characterized in that: The div is adjusted from small to large or from large to small.

7. A clock frequency testing method according to claim 1, characterized in that: The system clock frequency Fsys changes in a straight line. When the system clock frequency Fsys changes to a boundary value of a change range, the size of the div is adjusted, and the linear change direction of the system clock frequency Fsys is changed.

8. A clock frequency test device for scanning and testing the clock frequency of SPI FLASH data reading, characterized in that: The device comprises: The setting module is used to set the linearly changing system clock frequency Fsys and QSPI clock frequency Freq, wherein the system clock frequency Fsys satisfies: Fsys = Fs*(PLLn / (PLLm*PLLp)); Among them, Fs is the internal crystal oscillator, PLLn is the main phase-locked loop frequency multiplication coefficient, PLLm is the main phase-locked loop frequency division coefficient, and PLLp is the system clock frequency division coefficient; The QSPI clock frequency Freq satisfies: Freq = Fsys / div; Where, div is the clock division factor of QSPI; An adjusting module, used for adjusting the size of the div according to the linearly changing system clock frequency Fsys to obtain the QSPI clock frequency Freq in different changing ranges; The test module is used to obtain the clock frequency of the SPI FLASH data reading according to the QSPI clock frequency Freq test with different variation ranges.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the steps in the method according to any one of claims 1 to 7 are executed.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are executed.

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