A data processing apparatus, integrated circuit chip, device, and method implemented therefor

Abstract

The present disclosure relates to a data processing apparatus, method, integrated circuit chip, electronic device and board card, wherein the data processing apparatus is included in a computing apparatus, which can be included in a combined processing apparatus, which can further include a general-purpose interconnection interface and other processing apparatuses. The computing apparatus interacts with the other processing apparatuses to jointly complete a user-specified computing operation. The combined processing apparatus can further include a storage apparatus connected with the computing apparatus and the other processing apparatuses respectively, for storing data of the computing apparatus and the other processing apparatuses. The scheme of the present disclosure can be widely applied in various conversions of multi-dimensional data, and improves the efficiency of data conversion.

Description

Technical Field

[0001] This disclosure generally relates to the field of data processing. More specifically, this disclosure relates to a data processing apparatus, an integrated circuit chip, an electronic device, a circuit board, and a method for implementing the data processing apparatus. Background Technology

[0002] Computational work in the field of artificial intelligence often involves processing multi-dimensional data (such as two-dimensional matrices or three-dimensional arrays). Taking the processing of two-dimensional matrices as an example, transformation operations can include transpose, rotation, or mirroring. Currently, such transformation operations are generally implemented using dedicated custom-designed matrix operation circuits. However, these matrix operation circuits are relatively complex in design, and their interfaces and functions are relatively fixed. Furthermore, a single type of matrix operation circuit can only handle matrix transformations of its corresponding type, and cannot perform multiple matrix transformation operations as needed. Therefore, how to obtain a data processing device capable of performing transformation operations on multi-dimensional data has become a problem that needs to be solved in the existing technology.

[0003] Furthermore, in computing systems, an instruction set is a collection of instructions used to perform calculations and control the computing system, playing a crucial role in improving the performance of computing chips (such as processors). Current computing chips (especially those in the field of artificial intelligence) utilize associated instruction sets to perform various general or specific control and data processing operations. However, current instruction sets still have several shortcomings. For example, existing instruction sets are limited by hardware architecture, resulting in poor flexibility. Furthermore, current instructions need improvement in handling the conversion between various data types, particularly in processing multi-dimensional data. Summary of the Invention

[0004] In order to at least address the technical problems mentioned in the background section above and provide a computing architecture and instruction system for efficiently processing multi-dimensional data, the solutions disclosed herein will be described in several aspects below.

[0005] In a first aspect, this disclosure provides a data processing apparatus including a data caching circuit and a data conversion circuit, wherein the data caching circuit is configured to perform data caching, and the data conversion circuit is configured to perform storage and retrieval operations on data to be converted in the data caching circuit according to a data conversion instruction, so as to realize the data conversion of the data to be converted.

[0006] In a second aspect, this disclosure provides an integrated circuit chip that includes the data processing apparatus as described in the first aspect above.

[0007] In a third aspect, this disclosure provides an electronic device that includes an integrated circuit chip as described in the second aspect above.

[0008] In a fourth aspect, this disclosure provides a board that includes an integrated circuit chip as described in the third aspect above.

[0009] In a fifth aspect, this disclosure provides a method implemented by a data processing apparatus, wherein the data processing apparatus includes a data caching circuit and a data conversion circuit, the method comprising: using the data caching circuit to perform data caching; and using the data conversion circuit to perform storage and retrieval operations on data to be converted in the data caching circuit according to a data conversion instruction, so as to realize data conversion of the data to be converted.

[0010] Through the data processing apparatus, integrated circuit chip, electronic device, board, and method provided in the aforementioned aspects, the solution disclosed herein can realize data transformation, such as multi-dimensional data, using data transformation instructions. Specifically, by using data transformation instructions to perform storage and retrieval operations on the data to be transformed in a data buffer circuit, the solution disclosed herein can realize various operations on multi-dimensional data, such as addressing, moving, and transforming. Furthermore, since the aforementioned data transformation operations are implemented using instructions, the solution disclosed herein reduces modifications to the hardware architecture and improves the efficiency of data transformation. Attached Figure Description

[0011] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0012] Figure 1 This is a schematic diagram illustrating a data processing apparatus according to an embodiment of the present disclosure;

[0013] Figure 2 This is a schematic diagram illustrating a computing device according to an embodiment of the present disclosure;

[0014] Figures 3-8 These are flowcharts illustrating various operations of the data conversion circuit according to embodiments of the present disclosure;

[0015] Figure 9 This is a flowchart illustrating a method implemented by a data processing apparatus according to an embodiment of the present disclosure;

[0016] Figure 10 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and

[0017] Figure 11 This is a schematic diagram illustrating the structure of a circuit board according to an embodiment of the present disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0019] It should be understood that the terms "first," "second," "third," and "fourth," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0020] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0021] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0022] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram illustrating a data processing apparatus 100 according to an embodiment of the present disclosure. Figure 1As shown, the data processing apparatus 100 includes a data caching circuit 102 and a data conversion circuit 104. In one embodiment, the data caching circuit can be configured to perform data caching. In an exemplary application scenario, the data suitable for caching by the data caching circuit of this disclosure can be multi-dimensional data, including, for example, tensor data. In one embodiment, the data conversion circuit can be configured to perform storage and retrieval operations on the data to be converted (e.g., multi-dimensional data) in the aforementioned data caching circuit according to data conversion instructions, so as to realize the data conversion of the data to be converted. For example, by performing storage and retrieval operations on the data to be converted in different ways, the solution of this disclosure can perform various spatial transformation operations on the data to be converted to obtain deformed data. Taking three-dimensional data as an example, the solution of this disclosure can realize transpose, mirror, or multi-angle (e.g., 90° or 180°) rotation operations on three-dimensional data. In one application scenario, when the data to be converted is a matrix (i.e., a two-dimensional data), the data caching circuit may include a cache storage array for caching the matrix data written or transformed by the data conversion circuit during the write operation, or for passing the matrix data to the data conversion circuit during the read operation, so that the data conversion circuit can perform appropriate conversion when passing the matrix data to an external memory or computing unit.

[0024] In one embodiment, when the data to be converted is multi-dimensional data, the data conversion instruction may include data volume information and inter-dimensional offset information regarding the amount of data to be stored and retrieved for each dimension of the multi-dimensional data. In one example scenario, the data volume information may include the number of data items to be stored and retrieved in each dimension, while the inter-dimensional offset information includes the address interval to be traversed from the current dimension to the next dimension. In another example scenario, the address interval is determined based on the number of data items within the current dimension and the space occupied by each data item.

[0025] As an example, when multi-dimensional data has three dimensions—length, width, and height—the data volume information for the length or width direction (i.e., one dimension) can be information such as the number of data items, their size, and / or the space occupied by each data item. Furthermore, the inter-dimensional offset information can be the offset from one-dimensional data consisting of length or width to two-dimensional data consisting of length and width, or the offset from two-dimensional data consisting of length and width to three-dimensional data consisting of length, width, and height. For example, the inter-dimensional offset information can be the number of data items and / or the address space offset traversed from the previous lower dimension to the next higher dimension.

[0026] To facilitate the reading and writing of multi-dimensional data, this disclosure proposes defining an M-dimensional counter, i.e., having M one-dimensional counters named N_1, N_2, N_3, ..., N_M. During counting, when the nth counter has completed one cycle N_n (e.g., from 0 to N_n), the nth counter can be reset to zero, while the (n+1)th counter is incremented by 1. Based on the definition of this M-dimensional counter, this disclosure proposes maintaining an M-dimensional read counter and a read pointer, as well as maintaining an M-dimensional write counter and a write pointer. The M-dimensional read counter can be represented as: R_cnt(i_1,i_2,i_3…i_M), and the corresponding read pointer can be represented as: R_p = R_addr + i_1*s_0 + i_2*s_1 + ... + s_M-1*n_M, where R_addr is the read base address. During the reading process, the M-dimensional counter R_cnt is incremented by one after each R_n0 elements are read. Similarly, for an M-dimensional write counter, it can be represented as: W_cnt(i_1,i_2,i_3…i_M), and the corresponding write pointer can be represented as: W_p=W_addr+i_1*s_0+i_2*s_1+…+s_M-1*n_M, where W_addr is the write base address.

[0027] Based on the aforementioned M-dimensional read and write counters, the scheme disclosed herein can achieve data transformation of the data to be transformed by storing R_n0 elements into a data buffer circuit via a data conversion circuit, and then reading W_n0 elements from the data buffer circuit via the data conversion circuit. For example, the data conversion circuit can, according to data conversion instructions, utilize the aforementioned data storage and retrieval operations to perform selective output of partial data from multi-dimensional data, rotate data at a certain angle, mirror or transpose data, etc.

[0028] The above combination Figure 1 The composition and operation of the data processing apparatus of this disclosure have been described. Based on the above description, those skilled in the art will understand that the data processing apparatus of this disclosure utilizes data conversion instructions to transform multi-dimensional data, thereby improving the execution efficiency of multi-dimensional data conversion. Furthermore, by utilizing data conversion circuits to perform various storage and retrieval operations on multi-dimensional data to convert the data, the solution of this disclosure simplifies the complexity of multi-dimensional data conversion operations and accelerates the progress of multi-dimensional data conversion. Therefore, the solution of this disclosure also reduces data processing overhead and, in computational scenarios requiring data conversion, improves computational efficiency and reduces computational overhead.

[0029] Figure 2 This is a schematic diagram illustrating a computing device 200 according to an embodiment of the present disclosure. Figure 2 As shown, the computing device 200 may include the above-described combination. Figure 1The described data processing apparatus 100 includes the data buffer circuit 102 and the data conversion circuit 104 shown in the figure. As already described above... Figure 1 The data processing apparatus of this disclosure has been described in detail, and the specific description of the data buffer circuit 102 and the data conversion circuit 104 also applies to the computing device 200, so the same content will not be repeated.

[0030] As shown in the figure, the computing device of this disclosure also includes computing circuitry 204 and storage circuitry 202. Depending on the application scenario, the computing circuitry and storage circuitry can be implemented in different ways. In one embodiment, the storage circuitry can take the form of memory, such as dynamic random access memory (“DRAM”) or double-data-rate synchronous dynamic random access memory (“DDR SDRAM”), which can be used to store computational data required for the computing circuitry to perform operations, or data to be exchanged with external memory. When the computing device of this disclosure is applied to the field of artificial intelligence, the aforementioned computational data or data to be exchanged can be data from various related fields, such as various training data, network model data and parameters in machine learning, and various types of data to be detected (e.g., image data).

[0031] In another embodiment, the computing circuit may take the form of a general-purpose or special-purpose processor and a general-purpose or special-purpose processor core, which may include various types of arithmetic units and buses (e.g., data buses, control buses, or broadcast buses). When the solutions of this disclosure are applied to the field of artificial intelligence, the computing circuit can be implemented or included in a single-core or multi-core deep learning processor to perform various computational operations. In one application scenario, when the computing circuit is implemented as a processor core, it can be packaged together with a data cache circuit and a data conversion circuit to form a processor. In this case, the data cache circuit can be implemented as a cache of the computing device to store the data and instructions most frequently accessed by the computing circuit in memory (e.g., storage circuit 202), so that the computing circuit does not need to read the required data and instructions from the relatively slow-running memory.

[0032] Figures 3-8 This is a flowchart illustrating various operations of the data conversion circuit according to embodiments of the present disclosure. As described above, the data conversion circuit of the present disclosure obtains data volume information and / or inter-dimensional offset information of multi-dimensional data according to data conversion instructions, and cooperates with the data caching circuit to realize different methods of storing and reading multi-dimensional data, thereby realizing data conversion of multi-dimensional data. The following will combine... Figures 3-8 This will provide a detailed explanation of various exemplary operations.

[0033] Figure 3The following exemplifies the process 300 performed by the data conversion circuit of this disclosure during storage and retrieval operations. Specifically, in step S302, the data conversion circuit can be configured to perform storage and retrieval operations on a corresponding number of data within the dimension of the data to be converted in the data cache circuit based on the data volume information of the dimension. In other words, the data conversion circuit of this disclosure can perform write-to-data cache circuit or read-from-data cache circuit operations on one or more data within the same dimension, thereby realizing the processing of data in a specific dimension of multi-dimensional data. Further, in step S304, the data conversion circuit can be configured to address the next dimension based on the inter-dimensional offset information, so as to perform storage and retrieval operations on a corresponding number of data within the next dimension in the data cache circuit. It can be seen that in this case, after performing storage and retrieval operations on the current dimension data, the data conversion circuit can use the inter-dimensional offset information to perform storage and retrieval operations on data in one dimension, thereby realizing the conversion operation on multiple consecutive dimension data. Furthermore, by utilizing the inter-dimensional offset information, cross-dimensional data conversion operations are also realized.

[0034] Based on the above Figure 3 In one embodiment, the data conversion instruction shown in the diagram may further include the aforementioned storage base address information (“W_addr”) and read base address information (“R_addr”). During the write and read operations, the data conversion circuit is further configured to address the next dimension based on the storage base address information and the inter-dimensional offset information to perform the storage operation, and to address the next dimension based on the read base address information and the inter-dimensional offset information to perform the read operation. It can be seen that by utilizing the base address information, the data conversion circuit can more accurately and efficiently locate the multi-dimensional data requiring storage and read operations. Furthermore, by introducing the base address information, the methods for locating multi-dimensional data are expanded, and the addressing space is broadened. Additionally, by introducing the base address information and the inter-dimensional offset information, the data processing apparatus of this disclosure can implement various operations on multi-dimensional data based on the data conversion instruction, such as one or more operations among multi-dimensional data bypass operations, multi-angle rotation operations, mirror operations, or sequential transformation operations.

[0035] As mentioned earlier, in one implementation scenario, when multi-dimensional data is implemented as a two-dimensional matrix, the data caching circuit of this disclosure may include a cache storage array. In one embodiment, the size of the cache storage array can be determined based on the number of rows X, the number of columns Y, and the storage space K occupied by the basic elements of the matrix to be converted. Specifically, based on the number of rows X, the number of columns Y, and the storage space K occupied by the basic elements of the matrix to be converted, the data processing device of this disclosure can set a cache storage array that matches the size of the matrix to be converted, wherein the storage space occupied by the basic elements of the cache storage array is greater than or equal to K, and the number of rows of the cache storage array is greater than or equal to the larger of X and Y, and the number of columns of the cache storage array is greater than or equal to the larger of X and Y. The aforementioned setting of the size of the cache storage array is to ensure that the matrix to be converted can be stored in the cache storage array according to a preset access method. For example, when X is not equal to Y, under the transpose operation, the number of rows and columns are interchanged, and the number of rows and columns of the cache storage array formed by the above setting can support such changes in the number of rows and columns during the matrix conversion process. Of course, when X equals Y, the above operation can be achieved if the number of rows of the cache storage array is greater than or equal to either X or Y and the number of columns of the cache storage array is greater than or equal to either X or Y.

[0036] In different scenarios, the data conversion circuit of this disclosure can work in conjunction with a cache storage array to perform corresponding write and read operations on a two-dimensional matrix, thereby realizing various operations on the two-dimensional matrix. According to this disclosure, the aforementioned various operations can be, for example, Figure 4 The transpose operation shown Figure 5 The 270° rotation operation shown Figure 6 The 90° rotation operation shown Figure 7 The 180° rotation operation shown and Figure 8 The mirroring operation is shown below. This will be combined with... Figures 4-8 These operations will be described in detail.

[0037] Figure 4 This illustrates the matrix transpose process 400 executed by the data conversion circuit of this disclosure according to data conversion instructions. For example... Figure 4 As shown, in step S402, the data conversion circuit can store each row of the matrix to be converted into the corresponding row in the cache storage array according to the data conversion instruction, forming an intermediate matrix. Then, in step S404, the data conversion circuit can read each column of the intermediate matrix in the cache storage array in the order from the first column to the last column and in column order, outputting each column as the first row to the last row of the matrix, thereby converting the matrix to be converted into the corresponding transpose matrix.

[0038] Specifically, assuming the matrix to be converted is an X*Y matrix, where X may or may not be equal to Y. The data conversion circuit can store the first row of the X*Y matrix in the order from the first element to the Yth element in the first row of the cache storage array, respectively. This process is repeated from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the first element to the Yth element in the Xth row of the cache storage array, forming an intermediate (X*Y) matrix. This intermediate matrix can be understood as the matrix to be converted being copied into the cache storage array. Then, the data conversion circuit reads the first basic element from row 1 to row X of the (X*Y) intermediate matrix in sequence, and concatenates the read X basic elements into a row to form the first row of the transposed matrix. This process is repeated from the first basic element to the Yth basic element until the Yth basic element from row 1 to row X of the X*Y intermediate matrix is ​​read in sequence, and the read X basic elements are concatenated into a row to form the Yth row of the transposed matrix, thus forming the transposed matrix.

[0039] Figure 5 This is flowchart 500 illustrating a matrix rotation 270° operation performed by the data conversion circuit of this disclosure according to a data conversion instruction. For example... Figure 5 As shown, in step S502, the data conversion circuit can store each row of the matrix to be converted into the corresponding row of the cache storage array in reverse row order according to the data conversion instruction to form an intermediate matrix. Then, in step S504, the data conversion circuit can read each column of the intermediate matrix in the cache storage array in the order from the first column to the last column and in column order, outputting each column as the first row to the last row of the matrix, thereby converting the matrix to be converted into a corresponding matrix rotated 270°.

[0040] Specifically, assuming the matrix to be converted is an X*Y matrix, where X may or may not be equal to Y. The data conversion circuit can store the first row of the X*Y matrix in the order from the Yth element to the first element in the first row of the cache array, from the first element to the Yth element. This process is repeated from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth element to the first element in the first row of the cache array, forming an intermediate X*Y matrix. This intermediate matrix can be understood as being formed by mirroring each row of the matrix to be converted within each row. Then, the data conversion circuit can sequentially read the first basic element from row 1 to row X of the X*Y intermediate matrix, and concatenate the X basic elements read in this order into a row to serve as the first row of the rotated matrix. This process is repeated from the first basic element to the Yth basic element until the Yth basic element from row 1 to row X of the X*Y intermediate matrix is ​​read in this order, and the X basic elements read in this order are concatenated into a row to serve as the Yth row of the rotated matrix, thus forming a matrix rotated by 270°.

[0041] Figure 6 This is flowchart 600 illustrating a matrix rotation 90° operation performed by the data conversion circuit of this disclosure according to a data conversion instruction. For example... Figure 6 As shown, in step S602, the data conversion circuit can store each row of the matrix to be converted into the corresponding row in the cache storage array in in-row order to form an intermediate matrix. Then, in step S604, the data conversion circuit can read each column of the intermediate matrix in the cache storage array in reverse in-column order from the first column to the last column, outputting each column as the first row to the last row of the matrix, thereby converting the matrix to be converted into a corresponding matrix rotated by 90°.

[0042] Specifically, assuming the matrix to be converted is an X*Y matrix, where X may or may not be equal to Y. The data conversion circuit can store the first row of the X*Y matrix in the order from the first element to the Yth element in the first row of the cache storage array, respectively. This process is repeated from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the first element to the Yth element in the Xth row of the cache storage array, forming an intermediate X*Y matrix. This intermediate matrix can be understood as the matrix to be converted being copied into the cache storage array. Then, the data conversion circuit can read the first row of the X*Y intermediate matrix in the order from the Yth basic element to the first basic element as the first row of the rotated matrix, and repeat this operation in the order from the first row to the Xth row of the X*Y intermediate matrix until the Xth row of the X*Y intermediate matrix is ​​read in the order from the Yth basic element to the first basic element as the Xth row of the rotated matrix, thus forming a matrix rotated by 90°.

[0043] Figure 7 This is flowchart 700 illustrating a matrix rotation 180° operation performed by the data conversion circuit of this disclosure according to a data conversion instruction. For example... Figure 7 As shown, in step S702, the data conversion circuit can store each row of the matrix to be converted into the corresponding row in the cache storage array in reverse row order to form an intermediate matrix. Then, in step S704, the data conversion circuit can read each row of the intermediate matrix in the cache storage array in the order from the last row to the first row and in row order, outputting each row as the first row to the last row of the matrix, thereby converting the matrix to be converted into a corresponding matrix rotated 180°.

[0044] Specifically, assuming the matrix to be converted is an X*Y matrix, where X may or may not be equal to Y. The data conversion circuit can store the first row of the X*Y matrix in the order from the Yth element to the first element in the first row of the cache array, from the first element to the Yth element. This process is repeated from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth element to the first element in the first row of the cache array, forming an intermediate X*Y matrix. This intermediate matrix can be understood as being formed by mirroring each row of the matrix to be converted within each row. Next, the data conversion circuit can read the Xth row of the X*Y intermediate matrix in the order from the first basic element to the Yth basic element as the first row of the rotated matrix. This process is repeated until the first row of the X*Y intermediate matrix is ​​read in the order from the first basic element to the Yth basic element as the Xth row of the rotated matrix, thus forming a matrix rotated by 180°.

[0045] Figure 8 This is flowchart 800 illustrating the matrix mirroring operation performed by the data conversion circuit of this disclosure according to data conversion instructions. For example... Figure 8 As shown, in step S802, the data conversion circuit can store each row of the matrix to be converted into the corresponding row in the cache storage array in reverse row order to form an intermediate matrix. Then, in step S804, each row of the intermediate matrix is ​​read from the last row to the first row and in reverse row order in the cache storage array and output as the first row to the last row of the matrix, thereby converting the matrix to be converted into a corresponding mirror matrix.

[0046] Specifically, assuming the matrix to be converted is an X*Y matrix, where X may or may not be equal to Y. The conversion processing circuit can store the first row of the X*Y matrix in the order from the Yth element to the first element in the first row of the cache storage array, from the first element to the Yth element. This process is repeated from the first row to the Xth row of the X*Y matrix until the Xth row of the X*Y matrix is ​​stored in the order from the Yth element to the first element in the first row of the cache storage array, forming an intermediate X*Y matrix. This intermediate matrix can be understood as being formed by mirroring each row of the matrix to be converted within each row. Then, the data conversion circuit can read the Xth row of the X*Y intermediate matrix in the order from the Yth basic element to the 1st basic element as the first row of the mirrored matrix, and repeat this operation in the order from the Xth row to the 1st row of the intermediate matrix until the first row of the X*Y intermediate matrix is ​​read in the order from the Yth basic element to the 1st basic element as the Xth row of the mirrored matrix, thus forming a mirrored matrix.

[0047] The above combination Figures 4-8 The description describes storing the matrix to be transformed into a cache storage array in a preset manner to form an intermediate matrix, and then performing a read operation on this intermediate matrix to obtain the transformed matrix. It is understood that when the space occupied by the cache storage array is larger than the matrix to be transformed (the intermediate matrix), operations on the intermediate matrix can also be regarded as operations on the valid basic elements in the cache storage array. Furthermore, it should be noted that the above description of five matrix transformation operations implemented by the data transformation circuit is for illustrative purposes only and not for limiting purposes. The data transformation circuit of this disclosure can also implement other matrix transformations according to data transformation instructions.

[0048] Figure 9 This is a flowchart illustrating a method 900 implemented by a data processing apparatus according to an embodiment of the present disclosure. It is understood that the data processing apparatus here refers to the aforementioned combination... Figures 1-8 The data processing apparatus under discussion. Therefore, the description of the data processing apparatus above also applies to the data processing apparatus. Figure 9 The scheme shown will be repeated hereafter, and the same content will not be elaborated upon again.

[0049] like Figure 9As shown, in step S902, method 900 uses a data caching circuit to perform data caching. According to different embodiments of this disclosure, the data here can be multi-dimensional data, such as a two-dimensional matrix or a three-dimensional array. In step S904, method 900 uses the data conversion circuit to perform storage and retrieval operations on the data to be converted in the data caching circuit according to data conversion instructions, thereby realizing the data conversion of the data to be converted. Although in Figure 9 Not shown, but those skilled in the art will understand that method 900 can perform a combination Figures 1-8 The various operations of the described data processing device.

[0050] Figure 10 This is a structural diagram illustrating a combined processing apparatus 1000 according to an embodiment of the present disclosure. Figure 10 As shown, the combined processing device 1000 includes a computing processing device 1002, an interface device 1004, other processing devices 1006, and a storage device 1008. Depending on the application scenario, the computing processing device may include one or more computing devices 1010, which may include the data processing device of this disclosure and can be configured to perform the functions described herein. Figure 1-9 The described operation.

[0051] In different embodiments, the computing processing apparatus of this disclosure can be configured to perform user-specified operations. In exemplary applications, the computing processing apparatus can be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within the computing processing apparatus can be implemented as an artificial intelligence processor core or a portion of the hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or a portion of the hardware structure of an artificial intelligence processor core, the computing processing apparatus of this disclosure can be considered to have a single-core structure or a homogeneous multi-core structure.

[0052] In exemplary operation, the computing processing device of this disclosure can interact with other processing devices through interface devices to jointly complete user-specified operations. Depending on the implementation, other processing devices of this disclosure may include one or more types of processors such as a central processing unit (CPU), a graphics processing unit (GPU), and an artificial intelligence processor, both general-purpose and / or special-purpose processors. These processors may include, but are not limited to, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing processing device of this disclosure can be considered to have a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, they can be considered to form a heterogeneous multi-core structure.

[0053] In one or more embodiments, the other processing device may serve as an interface between the computing processing device of this disclosure and external data and control, performing basic controls including but not limited to data transfer, starting and / or stopping the computing device. In another embodiment, the other processing device may also cooperate with the computing processing device to jointly complete computational tasks.

[0054] In one or more embodiments, the interface device can be used to transfer data and control commands between a computing processing device and other processing devices. For example, the computing processing device can obtain input data from other processing devices via the interface device and write it to on-chip storage (or memory) of the computing processing device. Further, the computing processing device can obtain control commands from other processing devices via the interface device and write them to on-chip control cache of the computing processing device. Alternatively or optionally, the interface device can also read data from the storage device of the computing processing device and transmit it to other processing devices.

[0055] Additionally or optionally, the combined processing apparatus of this disclosure may further include a storage device. As shown in the figures, the storage device is connected to both the computing processing device and the other processing device. In one or more embodiments, the storage device may be used to store data from the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage of the computing processing device or other processing device.

[0056] In some embodiments, this disclosure also discloses a chip (e.g. Figure 11 The chip shown is 1102. In one implementation, the chip is a system-on-chip (SoC) and integrates one or more such... Figure 10 The combined processing unit shown is illustrated. This chip can be connected to external interface devices (such as...). Figure 11 The external interface device 1106 shown is connected to other related components. These related components may be, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. In some applications, the chip may integrate other processing units (e.g., video codecs) and / or interface modules (e.g., DRAM interfaces). In some embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip. In some embodiments, this disclosure also discloses a board that includes the aforementioned chip package structure. The following will be combined with... Figure 11 This board is described in detail.

[0057] Figure 11 This is a schematic diagram illustrating the structure of a board 1100 according to an embodiment of the present disclosure. For example... Figure 11 As shown, the board includes a storage device 1104 for storing data, which includes one or more storage cells 1110. This storage device can be connected and transmit data with the controller 1108 and the aforementioned chip 1102 via, for example, a bus. Furthermore, the board also includes an external interface device 1106, configured for data relay or switching between the chip (or a chip in a chip package) and an external device 1112 (e.g., a server or computer). For example, data to be processed can be transferred from the external device to the chip via the external interface device. Alternatively, the calculation results of the chip can be transmitted back to the external device via the external interface device. Depending on the application scenario, the external interface device can have different interface forms; for example, it can adopt a standard PCIe interface.

[0058] In one or more embodiments, the controller in the board disclosed herein can be configured to regulate the state of the chip. Therefore, in one application scenario, the controller may include a microcontroller (MCU) for regulating the operating state of the chip.

[0059] Based on the above combination Figure 10 and Figure 11Based on the description, those skilled in the art will understand that this disclosure also discloses an electronic device or apparatus that may include one or more of the aforementioned boards, one or more of the aforementioned chips, and / or one or more of the aforementioned combined processing apparatus.

[0060] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound scanners, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of the end-to-cloud or cloud-edge-end integration.

[0061] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions of this disclosure are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this disclosure, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this disclosure. In addition, depending on the solution, the description of some embodiments in this disclosure also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0062] In terms of specific implementation, based on the disclosure and teachings of this disclosure, those skilled in the art will understand that the several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document divides them based on logical functions, but in actual implementation, there may be other division methods. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0063] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0064] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the solution of this disclosure is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0065] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0066] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of those claims.

[0067] The foregoing can be better understood in accordance with the following terms:

[0068] Clause 1. A data processing apparatus, comprising a data buffer circuit and a data conversion circuit, wherein:

[0069] The data caching circuit is configured to perform data caching; and

[0070] The data conversion circuit is configured to perform storage and retrieval operations on the data to be converted in the data cache circuit according to the data conversion instruction, so as to realize the data conversion of the data to be converted.

[0071] Clause 2. The data processing apparatus according to Clause 1, wherein the data to be converted is multi-dimensional data, and the data conversion instruction includes data volume information and inter-dimensional offset information regarding the storage and retrieval operations to be performed on each dimension of the multi-dimensional data.

[0072] Clause 3. The data processing apparatus according to Clause 2, wherein the data volume information includes the number of data to be stored and retrieved in each dimension, and the inter-dimensional offset information includes the address interval to be traversed from the current dimension to the next dimension.

[0073] Clause 4. The data processing apparatus according to Clause 3, wherein the address interval is determined based on the number of data in the current dimension and the space occupied by each data.

[0074] Clause 5. The data processing apparatus according to Clause 3, wherein during the execution of the storage and retrieval operations, the data conversion circuit is configured to perform the following operations:

[0075] Based on the data volume information of the dimension of the data to be transformed, the corresponding number of data within that dimension are stored and retrieved in the data cache circuit; and

[0076] The next dimension is addressed based on the inter-dimensional offset information so that the corresponding number of data in the next dimension can be stored and retrieved in the data cache circuit.

[0077] Clause 6. The data processing apparatus according to Clause 5, wherein the data conversion instruction further includes storing base address information and reading base address information, wherein in performing the write and read operations, the data conversion circuit is configured to perform the following operations:

[0078] The storage operation is performed by addressing the next dimension based on the storage base address information and the inter-dimensional offset information; and

[0079] The next dimension is addressed based on the base address information and the inter-dimensional offset information to perform the read operation.

[0080] Clause 7. The data processing apparatus according to any one of Clauses 1-6, wherein the data transformation includes one or more operations performed on the multidimensional data, such as bypass operation, multi-angle rotation operation, mirror operation, or sequential transformation operation.

[0081] Clause 8. The data processing apparatus according to Clause 1, wherein the data to be converted is a matrix to be converted, and the data caching circuit includes a cache storage array.

[0082] Clause 9. The data processing apparatus according to Clause 8, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions:

[0083] Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and

[0084] In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding transpose matrix.

[0085] Clause 10. The data processing apparatus according to Clause 8, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions:

[0086] Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and

[0087] In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 270°.

[0088] Clause 11. The data processing apparatus according to Clause 8, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions:

[0089] Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and

[0090] In the cache storage array, each column of the intermediate matrix is ​​read in reverse order from the first column to the last column and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated by 90°.

[0091] Clause 12. The data processing apparatus according to Clause 8, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions:

[0092] Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and

[0093] In the cache storage array, each row of the intermediate matrix is ​​read in the order from the last row to the first row and in the order within the row, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 180°.

[0094] Clause 13. The data processing apparatus according to Clause 8, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions:

[0095] Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and

[0096] In the cache storage array, each row of the intermediate matrix is ​​read in reverse order from the last row to the first row and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding mirror matrix.

[0097] Clause 14. An integrated circuit chip comprising a data processing apparatus according to any one of Clauses 1-13.

[0098] Clause 15. An electronic device comprising an integrated circuit chip as described in Clause 14.

[0099] Clause 16. A board including an integrated circuit chip as described in Clause 14.

[0100] Clause 17. A method implemented by a data processing apparatus, wherein the data processing apparatus includes a data buffer circuit and a data conversion circuit, the method comprising:

[0101] The data caching circuitry is used to perform data caching; and

[0102] The data conversion circuit is used to perform storage and retrieval operations on the data to be converted in the data cache circuit according to the data conversion instructions, so as to realize the data conversion of the data to be converted.

[0103] Clause 18. The method according to Clause 17, wherein the data to be converted is multi-dimensional data, and the data conversion instruction includes data volume information and inter-dimensional offset information regarding the storage and retrieval operations to be performed on each dimension of the multi-dimensional data.

[0104] Clause 19. The method according to Clause 18, wherein the data volume information includes the number of data to be stored and retrieved in each dimension, and the inter-dimensional offset information includes the address interval to be traversed from the current dimension to the next dimension.

[0105] Clause 20, the method according to Clause 19, wherein the address interval is determined based on the number of data within the current dimension and the space occupied by each data.

[0106] Clause 21. The method according to Clause 19, wherein in performing the write and read operations, the method includes performing the following operations using the data conversion circuit:

[0107] Based on the data volume information of the dimension of the data to be transformed, the corresponding number of data within that dimension are stored and retrieved in the data cache circuit; and

[0108] The next dimension is addressed based on the inter-dimensional offset information so that the corresponding number of data in the next dimension can be stored and retrieved in the data cache circuit.

[0109] Clause 22. The method according to Clause 21, wherein the data conversion instruction further includes storing base address information and reading base address information, wherein in performing the write and read operations, the method includes performing the following operations using a data conversion circuit:

[0110] The storage operation is performed by addressing the next dimension based on the storage base address information and the inter-dimensional offset information; and

[0111] The next dimension is addressed based on the base address information and the inter-dimensional offset information to perform the read operation.

[0112] Clause 23. The method according to any one of Clauses 17-22, wherein the data transformation includes performing one or more of the following operations on the multidimensional data: bypass operation, multi-angle rotation operation, mirror operation, or sequential transformation operation.

[0113] Clause 24. The method according to Clause 17, wherein the data to be transformed is a matrix to be transformed, and the data caching circuit includes a cache storage array.

[0114] Clause 25. The method according to Clause 24, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions:

[0115] Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and

[0116] In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding transpose matrix.

[0117] Clause 26. The method according to Clause 24, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions:

[0118] Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and

[0119] In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 270°.

[0120] Clause 27. The method according to Clause 24, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions:

[0121] Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and

[0122] In the cache storage array, each column of the intermediate matrix is ​​read in reverse order from the first column to the last column and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated by 90°.

[0123] Clause 28. The method according to Clause 24, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions:

[0124] Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and

[0125] In the cache storage array, each row of the intermediate matrix is ​​read in the order from the last row to the first row and in the order within the row, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 180°.

[0126] Clause 29. The method according to Clause 24, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions:

[0127] Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and

[0128] In the cache storage array, each row of the intermediate matrix is ​​read in reverse order from the last row to the first row and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding mirror matrix.

[0129] In the above embodiments of this disclosure, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

Claims

1. A data processing apparatus, comprising a data buffer circuit and a data conversion circuit, wherein: The data caching circuit is configured to perform data caching; as well as The data conversion circuit is configured to perform storage and retrieval operations on the data to be converted in the data cache circuit according to the data conversion instruction. By performing storage and retrieval operations on the data to be converted in different ways, and performing spatial transformation operations on the data to be converted, the data conversion of the data to be converted can be achieved. The data to be converted is multi-dimensional data, and the data conversion instruction includes data volume information and inter-dimensional offset information regarding the storage and retrieval operations to be performed on each dimension of the multi-dimensional data.

2. The data processing apparatus according to claim 1, wherein the data volume information includes the number of data to be stored and retrieved in each dimension, and the inter-dimensional offset information includes the address interval to be traversed from the current dimension to the next dimension.

3. The data processing apparatus according to claim 2, wherein the address interval is determined based on the number of data in the current dimension and the space occupied by each data.

4. The data processing apparatus of claim 2, wherein during the execution of the storage and retrieval operations, the data conversion circuit is configured to perform the following operations: Based on the data volume information of the dimension of the data to be transformed, the corresponding number of data within that dimension are stored and retrieved in the data cache circuit; and The next dimension is addressed based on the inter-dimensional offset information so that the corresponding number of data in the next dimension can be stored and retrieved in the data cache circuit.

5. The data processing apparatus according to claim 4, wherein the data conversion instruction further includes storing base address information and reading base address information, wherein in performing the storage and reading operations, the data conversion circuit is configured to perform the following operations: The storage operation is performed by addressing the next dimension based on the storage base address information and the inter-dimensional offset information; and The next dimension is addressed based on the base address information and the inter-dimensional offset information to perform the read operation.

6. The data processing apparatus according to any one of claims 1-5, wherein the data transformation includes performing one or more operations on the multidimensional data, such as bypass operation, multi-angle rotation operation, mirror operation, or sequential transformation operation.

7. The data processing apparatus according to claim 1, wherein the data to be converted is a matrix to be converted, and the data caching circuit includes a cache storage array.

8. The data processing apparatus of claim 7, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instruction: Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding transpose matrix.

9. The data processing apparatus of claim 7, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instruction: Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 270°.

10. The data processing apparatus of claim 7, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and In the cache storage array, each column of the intermediate matrix is ​​read in reverse order from the first column to the last column and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated by 90°.

11. The data processing apparatus of claim 7, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and In the cache storage array, each row of the intermediate matrix is ​​read in the order from the last row to the first row and in the order within the row, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 180°.

12. The data processing apparatus of claim 7, wherein the data conversion circuit is configured to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and In the cache storage array, each row of the intermediate matrix is ​​read in reverse order from the last row to the first row and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding mirror matrix.

13. An integrated circuit chip comprising a data processing device according to any one of claims 1-12.

14. An electronic device comprising the integrated circuit chip according to claim 13.

15. A board comprising the integrated circuit chip according to claim 13.

16. A method implemented by a data processing apparatus, wherein the data processing apparatus includes a data buffer circuit and a data conversion circuit, the method comprising: Use the aforementioned data caching circuit to perform data caching; as well as The data conversion circuit is used to perform storage and retrieval operations on the data to be converted in the data cache circuit according to the data conversion instructions. By performing storage and retrieval operations on the data to be converted in different ways, and performing spatial transformation operations on the data to be converted, the data conversion of the data to be converted is achieved. The data to be converted is multi-dimensional data, and the data conversion instruction includes data volume information and inter-dimensional offset information regarding the storage and retrieval operations to be performed on each dimension of the multi-dimensional data.

17. The method of claim 16, wherein the data volume information includes the number of data to be stored and retrieved in each dimension, and the inter-dimensional offset information includes the address interval to be traversed from the current dimension to the next dimension.

18. The method of claim 17, wherein the address interval is determined based on the number of data in the current dimension and the space occupied by each data.

19. The method of claim 17, wherein in performing the write and read operations, the method includes performing the following operations using the data conversion circuit: Based on the data volume information of the dimension of the data to be transformed, the corresponding number of data within that dimension are stored and retrieved in the data cache circuit; and The next dimension is addressed based on the inter-dimensional offset information so that the corresponding number of data in the next dimension can be stored and retrieved in the data cache circuit.

20. The method of claim 19, wherein the data conversion instruction further includes storing base address information and reading base address information, wherein in performing the storage and reading operations, the method includes performing the following operations using a data conversion circuit: The storage operation is performed by addressing the next dimension based on the storage base address information and the inter-dimensional offset information; and The next dimension is addressed based on the base address information and the inter-dimensional offset information to perform the read operation.

21. The method according to any one of claims 16-20, wherein the data transformation includes performing one or more operations on the multidimensional data, such as bypass operation, multi-angle rotation operation, mirror operation, or sequential transformation operation.

22. The method of claim 16, wherein the data to be converted is a matrix to be converted, and the data caching circuit includes a cache storage array.

23. The method of claim 22, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding transpose matrix.

24. The method of claim 22, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and In the cache storage array, each column of the intermediate matrix is ​​read in the order from the first column to the last column and in the order within the column, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 270°.

25. The method of claim 22, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in the corresponding row of the cache storage array in in-row order to form an intermediate matrix; and In the cache storage array, each column of the intermediate matrix is ​​read in reverse order from the first column to the last column and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated by 90°.

26. The method of claim 22, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and In the cache storage array, each row of the intermediate matrix is ​​read in the order from the last row to the first row and in the order within the row, and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding matrix rotated 180°.

27. The method of claim 22, wherein the data conversion circuit is used to perform the following operations according to the data conversion instructions: Each row of the matrix to be transformed is stored in reverse order within the corresponding row in the cache storage array to form an intermediate matrix; and In the cache storage array, each row of the intermediate matrix is ​​read in reverse order from the last row to the first row and output as the first row to the last row of the matrix, so as to convert the matrix to be converted into the corresponding mirror matrix.

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