A large-scale schematic diagram inspection method and system

Abstract

The present invention discloses a large-scale schematic diagram inspection method and system, belonging to the technical field of automated testing. It includes obtaining an engineering schematic diagram, extracting each data object in the engineering schematic diagram, and parsing the attributes contained in each data object; the data objects include each lead, endpoint, pin, device, and module; the data objects include each lead, endpoint, pin, device, and module; constructing a point matrix according to each data object extracted from the engineering schematic diagram; and respectively inspecting the paths between devices, the paths between a device and a module, and the paths between modules according to the constructed point matrix. By parsing the circuit diagram file and according to the specific information of the circuit schematic diagram, the present invention can quickly and efficiently inspect whether the design rules in the schematic diagram comply with the regulations.

Description

Technical Field

[0001] The present invention belongs to the technical field of automated testing, and more specifically, relates to a method and system for large-scale schematic diagram inspection. Background Art

[0002] For large-scale schematic diagram design, it is necessary to check whether the design violates the rules. For example, whether there are duplicate series-connected capacitors or resistors between chips, capacitor withstand voltage derating inspection, pin transceiver direction inspection between modules, pull-up and pull-down inspection of reset signals, resistance inspection of clock networks, pin floating inspection, etc. It is almost impossible to achieve pure manual inspection.

[0003] In response to the above problems, there are also corresponding improvements in the prior art. For example, the Chinese patent application with the application number CN202010878879.5 and the publication date of December 08, 2020 discloses a method and system for circuit schematic diagram inspection. The method includes the following steps: obtaining a circuit diagram file, and parsing to obtain each circuit network, each chip, and each circuit element; for each circuit network, according to the pin connection relationship between the corresponding chips and circuit elements, performing pin-to-end queries step by step to obtain each pin number in each circuit network and the corresponding end-pin number; among them, the circuit diagram file includes circuit information of circuit networks, chips, and circuit elements, and the circuit elements include resistors, capacitors, and inductors. This invention parses the circuit diagram file, and according to the specific information of the circuit schematic diagram, queries the connection relationship of the pins step by step, so as to realize the inspection of the circuit schematic diagram with a complex topological structure; the Chinese patent application with the application number CN201310539174.0 and the publication date of May 13, 2015 discloses a method for extracting and verifying drawing content. The method includes the following steps: a classification extraction algorithm based on prior knowledge, according to the respective extraction methods, storing each graphic element, cable, single machine, and annotation name according to geometric features, so that the position coordinates are used as the calculation reference to match the graphic with its annotation name; determining the connection relationship between the cable and the single machine; verifying the correctness of the relevant information about the design drawing. The method proposed by this invention has a high degree of generalization. According to the geometric features of the electronic drawings of the communication satellite payload subsystem, an automated method for extracting and verifying drawing content is proposed. When using it, only the characteristic names of the single machine and the cable need to be determined, and no additional configuration is required. The idea of classification and screening is also used. During the graphic extraction process, the influence of other graphic elements on name matching is isolated, and the graphic element content can be accurately extracted; although the above methods can all realize the inspection of the circuit schematic diagram with a complex topological structure, they all require a large amount of time cost and the circuit diagram review efficiency is low. Summary of the Invention

[0004] 1. Problems to be Solved

[0005] In view of the defects existing in the prior art, the purpose of the present invention is to provide a large-scale schematic diagram inspection method and system, which can parse circuit diagram files and quickly and efficiently check whether the design rules in the schematic diagram meet the requirements according to the specific information of the circuit schematic diagram.

[0006] 2. Technical solution

[0007] To solve the above problems, the present invention adopts the following technical solutions.

[0008] As one aspect of the present application, a large-scale schematic diagram inspection method is provided, including the following steps:

[0009] Step S100: Obtain the engineering schematic diagram, extract each data object in the engineering schematic diagram, and parse the attributes included in each data object; the data objects include each lead, endpoint, pin, device, and module;

[0010] Step S200: Construct a point matrix according to each data object extracted from the engineering schematic diagram;

[0011] Step S300: According to the constructed point matrix, check the paths between devices and between devices, the paths between devices and modules, and the paths between modules and modules respectively.

[0012] Its preferred technical solution is:

[0013] For the large-scale schematic diagram inspection method as described above, in step S100, the extraction of each data object in the engineering schematic diagram specifically includes:

[0014] Step S110: First extract each lead in the engineering schematic diagram to create a lead data object; then, according to the lead data object, extract the two endpoints of the lead to create an endpoint data object;

[0015] Step S120: Then extract each chip and module in the engineering schematic diagram to create a device data object; further extract the pins of each chip and module to create a pin data object.

[0016] For the large-scale schematic diagram inspection method as described above, in step S100, the extraction of each data object in the engineering schematic diagram further includes: step S130: Create a data object for the module; step S130 specifically includes:

[0017] Step S131: Obtain the names of all modules in the engineering schematic diagram;

[0018] Step S132: According to the module names, obtain the pins outside each module, as well as the pins, leads, endpoints, and devices inside.

[0019] Step S133: Create data objects for the modules based on the pins outside and inside each module, as well as leads, endpoints, and devices.

[0020] In a large-scale schematic diagram inspection method as described above, in step S200, constructing a point matrix based on the data objects extracted from the engineering schematic diagram specifically includes:

[0021] Step S210: Extract endpoint data objects. Among them, two endpoint objects are created for each lead, multiple endpoint objects are created for each device, multiple endpoint objects are created for each chip, multiple endpoint objects are created for each module, and multiple endpoint objects are created inside each module.

[0022] Step S220: Form an array with the multiple extracted endpoint data objects, and characterize whether there is a connection between endpoints in the form of the endpoint number attribute.

[0023] In a large-scale schematic diagram inspection method as described above, in step S300, inspecting the paths between devices, between a device and a module, and between modules based on the constructed point matrix specifically includes:

[0024] Step S310: Based on the constructed point matrix, obtain the paths between devices, between a device and a module, and between modules.

[0025] Step S320: Filter all the found lines and determine whether they are paths. If so, proceed to the next step.

[0026] Step S330: Check the types of leads in the paths that meet the conditions, and filter out and display the paths of multiple capacitors or resistors.

[0027] In a large-scale schematic diagram inspection method as described above, in step S310, obtaining the paths between devices, between a device and a module, and between modules based on the constructed point matrix specifically includes:

[0028] Step S311: Based on the constructed point matrix, determine all the pins of one of the devices or modules.

[0029] Step S312: Based on the pins of the device or module, determine its corresponding endpoints, and perform a push operation on the endpoints in sequence.

[0030] Step S313: In the constructed point matrix, check whether there is a connected endpoint for the most recently pushed endpoint. If so, execute step S314; otherwise, execute step S315.

[0031] Step S314: Perform a stack push operation on the unmarked connected endpoints in sequence, and mark each endpoint after the stack push; return to Step S313;

[0032] Step S315: By default, the path between the endpoint corresponding to the device or module pin and the most recently pushed endpoint is a conductive path, and pop the most recently pushed endpoint from the stack;

[0033] In a large-scale schematic diagram checking method as described above, in Step S315, it further includes: determining whether there is an endpoint in the stack; if so, return to Step S313 to continue judging the next endpoint; if not, return to Step S311 to perform the judgment on the next device or module.

[0034] As another aspect of the present application, there is also provided a large-scale schematic diagram checking system, including:

[0035] An extraction module, configured to obtain an engineering schematic diagram, extract each data object in the engineering schematic diagram, and parse the attributes included in each data object; the data objects include each lead, endpoint, pin, device, and module;

[0036] A construction module, configured to construct a point matrix according to each data object in the engineering schematic diagram extracted by the extraction module;

[0037] And an inspection module, configured to inspect the conductive paths between devices and between devices and modules, and between modules according to the point matrix constructed by the construction module.

[0038] 3. Beneficial effects

[0039] Compared with the prior art, the beneficial effects of the present invention are:

[0040] When checking whether there are duplicate series-connected capacitors or resistors between devices and between devices and modules, and between modules, it is only necessary to find the conductive paths starting from the pins of all devices or modules, filter out those where both ends of the path are devices or modules, and check whether there are multiple capacitors or resistors in the path, so as to realize the review of the functional design rules of the schematic diagram of the target circuit module. Compared with the prior art method of manual review, the review efficiency and reliability can be improved. Description of the drawings

[0041] Figure 1 It is a flowchart of a large-scale schematic diagram checking method of the present invention. Detailed implementation manners

[0042] As described above, the existing circuit schematic review methods usually adopt the method of manual drawing review, that is, the hardware designers check the circuit schematic diagrams, and the reliability of the manual review method is poor and the efficiency is low. In addition, the circuit schematic diagrams can also be checked by DRC check tools, but this tool can only check according to the general design rules. In the prior art, in one way, the rules of various mode circuits are stored in a rule database, and the matching method of the mode circuits is used to match the corresponding mode circuits in the circuit schematic diagram to be reviewed, and the circuit schematic diagram to be reviewed is reviewed according to the rules of the mode circuits stored in the rule database. In another way, a preset circuit electrical constraint condition library is adopted to check the information of the components in the circuit schematic diagram and the electrical network information between the chip connection pins, and a check report is output according to the check result. However, the existing check schemes in the prior art can only check simple common sense errors such as whether there are short circuits, open circuits, and the connection modes of devices. When large-scale schematic design is adopted, in the process of module migration and final schematic diagram inspection and proofreading, the functional design rules still need to rely on manual inspection, and there are a large number of repetitive tasks in manual inspection, which requires a large amount of time cost and the efficiency of circuit schematic diagram review is low. There are also problems of poor reliability and low efficiency.

[0043] The present invention will be further described below in conjunction with specific embodiments and drawings.

[0044] Embodiment 1

[0045] As Figure 1 shown, this embodiment provides a large-scale schematic diagram inspection method, including the following steps:

[0046] Step S100, obtain an engineering schematic diagram, extract each data object in the engineering schematic diagram, and parse the attributes included in each data object; the data objects include each lead, endpoint, pin, device, and module;

[0047] The schematic diagram of an engineering project contains from several pages to hundreds of pages, with individual devices (such as resistors, capacitors, inductors, etc.), chips, fixed modules (reusable circuit combinations packaged into a block, which can be directly referenced by the design), and the leads between them. The above objects constitute the circuit information of the engineering schematic diagram. According to the structure of the schematic diagram, to obtain a complete circuit connection diagram, the following aspects can be considered:

[0048] Based on the connection relationships at both ends of the leads, the preliminary connection relationships between the lines and the pins of the devices, between the lines and the pins of the chips, and between the lines and the pins of the modules can be obtained. This result serves as the primary connection relationship. The connection relationships within the modules can be processed in the same way as in the first point above, and this result serves as the secondary connection relationship. Based on the above first and second points, a tertiary connection relationship can be formed, which is also the highest-level connection relationship. Note that there is a situation of module reuse in the entire circuit diagram, so the reused modules as the secondary connection relationship are not unique.

[0049] Based on the above three points, the attributes of the above data objects can be expressed as:

[0050] The attribute information of the lead (line) includes but is not limited to the number, start-end coordinates, end-end coordinates, type, page number, and whether it has been accessed, etc.

[0051] The attribute information of the endpoint (vertex) includes but is not limited to the number, coordinates, Line number, page number, and whether it has been accessed, etc.

[0052] The attribute information of the pin includes but is not limited to the coordinates, name, module name it belongs to, page number, pin number, etc.

[0053] The attribute information of the device (symbol) includes but is not limited to the coordinates, page number, pins, etc.

[0054] The information of the module (model) includes but is not limited to pins, leads, devices, endpoints, etc.

[0055] It should be noted that the relationship between points can be connected or not connected. However, in the actual schematic diagram inspection, a point may be connected to a device, a module, or connected to another page. Therefore, the attributes of the above data objects should also include the page number, etc. In addition, for the attribute information of the device or module, the attribute information of the device or module is related to the type of the device or module. When the type of the device or module is different, the corresponding attribute information is different.

[0056] Step S200: Construct a point matrix based on the data objects extracted from the engineering schematic diagram; Exemplarily:

[0057] pConnect[2, 3] = 1; / / 2 and 3 represent the numbers of the endpoints, 1 represents connected;

[0058] pConnect[2, 5] = 0; / / 2 and 5 represent the numbers of the endpoints, 0 represents not connected.

[0059] In this embodiment, by pre - establishing matrix data (pConnect), it is convenient to provide a basis for continuously extracting endpoints in the subsequent inspection of the paths in the engineering schematic diagram, ensuring the stability and rationality of the scheme implementation.

[0060] Step S300: According to the constructed point matrix, check the paths between devices and devices, between devices and modules, and between modules and modules respectively.

[0061] Its preferred technical solution is:

[0062] In a large - scale schematic diagram inspection method as described above, in step S100, extracting each data object in the engineering schematic diagram specifically includes:

[0063] Step S110: First, extract each lead in the engineering schematic diagram to create a lead data object; then, according to the lead data object, extract the two endpoints of the lead to create an endpoint data object.

[0064] Step S120: Then, extract each chip and module in the engineering schematic diagram to create a device data object; further extract the pins of each chip and module to create a pin data object.

[0065] In a large - scale schematic diagram inspection method as described above, in step S100, extracting each data object in the engineering schematic diagram further includes: Step S130: Create a data object for the module; step S130 specifically includes:

[0066] Step S131: Obtain the names of all modules in the engineering schematic diagram.

[0067] Step S132: According to the module names, obtain the pins outside each module, as well as the pins, leads, endpoints, and devices inside.

[0068] Step S133: Create a data object for the module according to the pins outside each module, as well as the pins, leads, endpoints, and devices inside.

[0069] In a large - scale schematic diagram inspection method as described above, in step S200, constructing a point matrix according to each data object extracted from the engineering schematic diagram specifically includes:

[0070] Step S210: Extract the endpoint data objects. Among them, two endpoint objects are created for each lead, multiple endpoint objects are created for each device, multiple endpoint objects are created for each chip, multiple endpoint objects are created for each module, and multiple endpoint objects are created inside each module.

[0071] Step S220: Combine the multiple extracted endpoint data objects into an array, and characterize whether endpoints are connected in the form of the endpoint number attribute.

[0072] As described above, in a large-scale schematic diagram inspection method, in step S300, according to the constructed dot matrix, the inspection of the paths between devices, between a device and a module, and between modules specifically includes:

[0073] Step S310: Obtain the paths between devices, between a device and a module, and between modules according to the constructed dot matrix;

[0074] Step S320: Filter all the found lines and determine whether they are paths. If so, proceed to the next step;

[0075] Step S330: Check the types of leads in the paths that meet the conditions, and filter out and display the paths of multiple capacitors or resistors.

[0076] As described above, in a large-scale schematic diagram inspection method, in step S310, according to the constructed dot matrix, the obtaining of the paths between devices, between a device and a module, and between modules specifically includes:

[0077] Step S311: Determine all the pins of one of the devices or modules based on the constructed dot matrix;

[0078] Step S312: Determine the corresponding endpoints according to the pins of the device or module, and perform a push operation on the endpoints in sequence;

[0079] Step S313: Check whether there are connected endpoints for the most recently pushed endpoint in the constructed dot matrix. If so, execute step S314; otherwise, execute step S315;

[0080] Step S314: Perform a push operation on the unmarked connected endpoints in sequence, and mark each pushed endpoint, for example, mark it as visited; return to step S313;

[0081] Step S315: By default, the path between the endpoint corresponding to the pin of the device or module and the most recently pushed endpoint is a path, and pop the most recently pushed endpoint.

[0082] After finding a path, since the pin endpoints of a device or module or chip may be connected to a device, a module, or connected to another page, there will be some one-to-many point connection relationships. Therefore, it is still necessary to continue to check whether other connected endpoints can form a path. Therefore, further, in step S315, it also includes:

[0083] Determine whether there is an endpoint in the stack; if so, return to step S313 to continue judging the next endpoint; if not, return to step S311 to judge the next device or module.

[0084] In this embodiment, through data push and pop, in a data loop nesting manner, starting from a certain device pin endpoint, a matrix of points constructed by the above technical solution is used to find the endpoints connected to it, and search sequentially until there are no connected endpoints, which is a path. Then repeat the search from the next pin to obtain all paths, and query the connection relationship of the endpoint pins step by step, so as to realize the inspection of complex large-scale circuit schematic diagrams.

[0085] Embodiment 2

[0086] This embodiment provides a large-scale schematic diagram inspection system, including:

[0087] An extraction module for obtaining an engineering schematic diagram and extracting each data object in the engineering schematic diagram, and parsing the attributes included in each data object; the data objects include each lead, endpoint, pin, device, and module;

[0088] A construction module for constructing a point matrix according to each data object in the engineering schematic diagram extracted by the extraction module;

[0089] And an inspection module for inspecting the paths between devices and devices, the paths between devices and modules, and the paths between modules according to the point matrix constructed by the construction module.

[0090] In this embodiment, when inspecting whether there are duplicate series-connected capacitors or resistors between devices and devices, between devices and modules, and between modules, only the paths starting from the pins of all devices or modules need to be found, filter out those where both ends of the path are devices or modules, and check whether there are multiple capacitors or resistors in the path, so as to realize the review of the functional design rules of the target circuit module schematic diagram. Compared with the prior art method of manual review, the review efficiency and reliability can be improved.

[0091] The embodiments described in the present invention are only descriptions of the preferred embodiments of the present invention, and do not limit the concept and scope of the present invention. Without departing from the design idea of the present invention, various deformations and improvements made by those skilled in the art to the technical solutions of the present invention should fall within the protection scope of the present invention.

Claims

1. A large-scale schematic diagram inspection method, characterized in that: It includes the following steps: Step S100: Obtain the engineering schematic diagram, extract each data object in the engineering schematic diagram, and parse the attributes contained in each data object; the data objects include each lead, endpoint, pin, device, and module; Step S200: Construct a point matrix according to each data object in the extracted engineering schematic diagram; in step S200, constructing a point matrix according to each data object in the extracted engineering schematic diagram specifically includes: Step S210: Extract the endpoint data objects. Among them, two endpoint objects are created for each lead, multiple endpoint objects are created for each device, multiple endpoint objects are created for each chip, multiple endpoint objects are created for each module, and multiple endpoint objects are created inside each module; Step S220: Compose the extracted multiple endpoint data objects into an array, and characterize whether there is a connection between endpoints in the way of the endpoint number attribute; Step S300: Inspect the paths between devices and devices, between devices and modules, and between modules and modules according to the constructed point matrix; in step S300, inspecting the paths between devices and devices, between devices and modules, and between modules and modules according to the constructed point matrix specifically includes: Step S310: Obtain the paths between devices and devices, between devices and modules, and between modules and modules according to the constructed point matrix; Step S320: Filter all the found lines and judge whether they are paths. If so, proceed to the next step; Step S330: Check the types of leads in the paths that meet the conditions, and filter out and display the paths of multiple capacitors or resistors.

2. A large-scale schematic diagram inspection method according to claim 1, characterized in that: In step S100, extracting each data object in the engineering schematic diagram specifically includes: Step S110: First extract each lead in the engineering schematic diagram and create a lead data object; then, according to the lead data object, extract the two endpoints of the lead and create an endpoint data object; Step S120: Then extract each chip and module in the engineering schematic diagram and create a device data object; further extract the pins of each chip and module and create a pin data object.

3. A large-scale schematic diagram inspection method according to claim 2, characterized in that: In step S100, extracting each data object in the engineering schematic diagram further includes: step S130: Create a data object for the module; step S130 specifically includes: Step S131: Obtain the names of all modules in the engineering schematic diagram; Step S132: According to the module names, respectively obtain the pins outside each module, as well as the pins, leads, endpoints, and devices inside; Step S133: Create a data object for the module according to the pins outside each module, as well as the pins, leads, endpoints, and devices inside.

4. A large-scale schematic diagram inspection method according to claim 1, characterized in that: In step S310, obtaining the paths between devices, the paths between a device and a module, and the paths between modules according to the constructed point matrix specifically includes: Step S311: Determine all the pins of one of the devices or modules according to the constructed point matrix; Step S312: Determine the corresponding endpoints according to the pins of the device or module, and perform a push operation on the endpoints in sequence; Step S313: Search in the constructed point matrix to see if there are any connected endpoints for the most recently pushed endpoint; if so, execute step S314, otherwise execute step S315; Step S314: Perform a push operation on the unmarked connected endpoints in sequence, and mark each pushed endpoint; return to step S313; Step S315: By default, the path between the endpoint corresponding to the pin of the device or module and the most recently pushed endpoint is a path, and pop the most recently pushed endpoint from the stack.

5. A large-scale schematic diagram checking method according to claim 4, characterized in that: In step S315, it further includes: judging whether there are endpoints in the stack; if so, return to step S313 to continue judging the next endpoint; if not, return to step S311 to perform the judgment on the next device or module.

6. A large-scale schematic diagram checking system, characterized in that: It includes: An extraction module, configured to obtain an engineering schematic diagram, extract each data object in the engineering schematic diagram, and parse the attributes included in each data object; the data objects include each lead, endpoint, pin, device, and module; A construction module, configured to construct a point matrix according to each data object in the engineering schematic diagram extracted by the extraction module; specifically, it includes extracting endpoint data objects, where two endpoint objects are created for each lead, multiple endpoint objects are created for each device, multiple endpoint objects are created for each chip, multiple endpoint objects are created for each module, and multiple endpoint objects are created inside each module; forming an array of the multiple extracted endpoint data objects, and characterizing whether there is a connection between endpoints in the form of an endpoint number attribute; And an inspection module, configured to inspect the paths between devices, the paths between a device and a module, and the paths between modules respectively according to the point matrix constructed by the construction module; specifically, it includes obtaining the paths between devices, the paths between a device and a module, and the paths between modules according to the constructed point matrix; filtering all the found lines and judging whether they are paths, if so, proceed to the next step; checking the types of leads in the paths that meet the conditions, and filtering out the paths of multiple capacitors or resistors for display.

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