Data Processing Method, Apparatus, and Storage Medium

Abstract

The present disclosure relates to a data processing method, apparatus, and storage medium. The board card disclosed therein includes: a storage device, an interface device, a control device, and a chip provided with a data processing device; wherein the data processing device is respectively connected to the storage device, the control device, and the interface device; the storage device is used for storing data; the interface device is used for realizing data transmission between the data processing device and an external device; the control device is used for monitoring the state of the data processing device. The data processing method, apparatus, and storage medium provided by the embodiments of the present disclosure reduce the amount of data read, shorten the data reading time, improve the efficiency and speed of data reading, reduce power consumption, and significantly improve the efficiency of subsequent units performing operations, storage, and other processes, thereby enhancing the performance of the apparatus in data processing.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, apparatus, and storage medium. Background Art

[0002] In related technologies, the process for a device to implement arithmetic processing using an arithmetic unit is as follows: loading data from a memory, the arithmetic unit completing calculations, and outputting results to the memory. However, algorithms usually have the characteristics of large amounts of data and large amounts of calculations. Moreover, due to the existence of the memory wall, data loading and storage often consume a large amount of time, resulting in the inability to effectively improve the efficiency of the arithmetic unit. In neural network algorithms, in order to meet the arithmetic requirements of different operators, it is necessary to fill data before performing specific arithmetic operations, which further increases the memory access power consumption. Summary of the Invention

[0003] In view of this, the present disclosure provides a data processing method, apparatus, and storage medium.

[0004] According to one aspect of the present disclosure, a data processing apparatus is provided. The apparatus includes: a read descriptor parsing unit and a data reading unit.

[0005] The read descriptor parsing unit is configured to parse the received first description information for first data, optimize and modify the parsed first read padding descriptor for the first data to obtain a second read padding descriptor, send the read padding data generated according to the second read padding descriptor to a subsequent unit, and send the second read padding descriptor to the data reading unit;

[0006] The data reading unit is configured to receive a read request for the first data and the second read padding descriptor, modify the read request according to the second read padding descriptor to obtain a modified read request, read a part of the first data as second data according to the modified read request, and send the second data to the subsequent unit.

[0007] The second data is the data in the first data other than the read padding data.

[0008] According to another aspect of the present disclosure, a data processing method is provided, which is applied to a data processing apparatus. The data processing apparatus includes a read descriptor parsing unit and a data reading unit. The method includes:

[0009] Control the read descriptor parsing unit to parse the first description information received for the first data, optimize and modify the parsed first read padding descriptor for the first data to obtain a second read padding descriptor, and send the read padding data generated according to the second read padding descriptor to a subsequent unit, and send the second read padding descriptor to the data reading unit;

[0010] Control the data reading unit to receive a read request and a second read padding descriptor for the first data, modify the read request according to the second read padding descriptor to obtain a modified read request, read a part of the first data as the second data according to the modified read request, and send the second data to the subsequent unit,

[0011] The second data is the data in the first data other than the read padding data.

[0012] According to another aspect of the present disclosure, there is provided a machine learning operation device, the device includes:

[0013] One or more of the above data processing devices, configured to obtain data to be operated and control information from other processing devices, perform specified machine learning operations, and transfer the execution results to other processing devices through an I / O interface;

[0014] When the machine learning operation device includes a plurality of the data processing devices, the plurality of data processing devices can be connected through a specific structure and transmit data;

[0015] Wherein, the plurality of data processing devices are interconnected and transmit data through a Peripheral Component Interconnect Express (PCIE) bus to support larger-scale machine learning operations; the plurality of data processing devices share the same control system or have their own control systems; the plurality of data processing devices share memory or have their own memories; the interconnection mode of the plurality of data processing devices is an arbitrary interconnection topology.

[0016] According to another aspect of the present disclosure, there is provided a combined processing device, the combined processing device includes:

[0017] Such as the above machine learning operation device, a general interconnection interface, and other processing devices;

[0018] The machine learning operation device interacts with the other processing devices to jointly complete a user-specified computing operation,

[0019] Wherein, the combined processing device further includes: a storage device, which is respectively connected to the machine learning operation device and the other processing devices, and is used to store the data of the machine learning operation device and the other processing devices.

[0020] According to another aspect of the present disclosure, a chip is provided, and the chip includes the above-mentioned combined processing device.

[0021] According to another aspect of the present disclosure, a board is provided, and the board includes: a storage device, an interface device, a control device, and the above-mentioned chip;

[0022] wherein the data processing device is respectively connected to the storage device, the control device, and the interface device;

[0023] The storage device is used for storing data;

[0024] The interface device is used for realizing data transmission between the data processing device and an external device;

[0025] The control device is used for monitoring the state of the data processing device,

[0026] wherein the storage device includes: multiple groups of storage units, each group of the storage units is connected to the data processing device through a bus, and the storage unit is: DDR SDRAM;

[0027] The data processing device includes: a DDR controller, which is used for controlling data transmission and data storage of each storage unit;

[0028] The interface device is: a standard PCIE interface.

[0029] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, and characterized in that when the computer program instructions are executed by a processor, the above-mentioned data processing method is realized.

[0030] The data processing method, apparatus, and storage medium provided by the embodiments of the present disclosure. The apparatus includes: a read descriptor parsing unit, configured to parse the received first description information for the first data, optimize and modify the parsed first read padding descriptor for the first data to obtain a second read padding descriptor, send the read padding data generated according to the second read padding descriptor to a subsequent unit, and send the second read padding descriptor to a data reading unit; a data reading unit, configured to receive a read request for the first data and the second read padding descriptor, modify the read request according to the second read padding descriptor to obtain a modified read request, read a first data portion as a second data according to the modified read request, and send the second data to a subsequent unit, where the second data is the data in the first data other than the read padding data. During the process of reading the first data, only the second data in the first data can be read and sent to a subsequent unit, reducing the amount of data read, shortening the data reading time, improving the data reading efficiency and speed, reducing power consumption, and significantly improving the efficiency of subsequent units performing operations, storage, and other processing, and enhancing the data processing performance of the apparatus.

[0031] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings included in and constituting a part of this specification, together with the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and are used to explain the principles of the present disclosure.

[0033] Figure 1 A block diagram showing a data processing apparatus according to an embodiment of the present disclosure.

[0034] Figure 2 A block diagram showing a data processing apparatus according to an embodiment of the present disclosure.

[0035] Figure 3 A block diagram showing a data processing apparatus according to an embodiment of the present disclosure.

[0036] Figure 4 A block diagram showing a data processing apparatus according to an embodiment of the present disclosure.

[0037] Figure 5 A flowchart showing a data processing method according to an embodiment of the present disclosure.

[0038] Figure 6 A structural diagram showing a combined processing apparatus 1200 according to an embodiment of the present disclosure.

[0039] Figure 7 A schematic structural diagram showing a board 1300 according to an embodiment of the present disclosure. Detailed implementation manners

[0040] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Like reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0041] The term "exemplary" used herein means "serving as an example, embodiment, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

[0042] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following detailed implementation manners. Those skilled in the art should understand that the present disclosure can also be implemented without some of these specific details. In some instances, methods, means, elements and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0043] Figure 1 The block diagram of a data processing device according to an embodiment of the present disclosure is shown. As Figure 1 shown, the device includes: a read descriptor parsing unit 41 and a data reading unit 42.

[0044] The read descriptor parsing unit 41 is configured to parse the first description information received for the first data, optimize and modify the parsed first read padding descriptor for the first data to obtain a second read padding descriptor, send the second read padding descriptor to the data reading unit 42, and send the read padding data generated according to the second read padding descriptor to a subsequent unit 43. The data processing device may include the subsequent unit 43, or the subsequent unit 43 may also be another device (which may also be a component unit of another device).

[0045] The data reading unit 42 is configured to receive a read request for the first data and the second read padding descriptor, modify the read request according to the second read padding descriptor to obtain a modified read request, read a part of the first data as the second data according to the modified read request, and send the second data to the subsequent unit 43, where the second data is the data in the first data other than the read padding data.

[0046] Among them, the second data is the data in the first data that has no pattern and can only be obtained by reading from the memory. The read padding data is any one or more data in the first data that has a pattern and can be determined without reading from the memory. For example, assume that the first data is [1, 0, 4, 1, 0, 0, 0, 0], and the last four bits are all zero, but there is no definite pattern in the first four bits. Then, the last four bits can be implemented by padding. When using the above device to read the first data, the data reading unit of the device can use the second description information to describe that "the last four bits of the first data do not need to be read". Finally, only the "second data [1, 0, 4, 1]" is read from the "first data [1, 0, 4, 1, 0, 0, 0, 0]", and the "read padding data [0, 0, 0, 0]" is generated by the read descriptor parsing unit. The subsequent unit can generate the complete first data [1, 0, 4, 1, 0, 0, 0, 0] according to the "second data [1, 0, 4, 1]" and the "read padding data [0, 0, 0, 0]". In this way, the reading of the first data is completed, and at the same time, the data volume of data reading can be reduced, the reading time of the first data can be shortened, the efficiency and speed of the first data reading can be improved, the power consumption can be reduced, and thus the processing efficiency of the subsequent unit can be improved.

[0047] In this embodiment, after the read padding descriptor parsing unit parses the first read padding descriptor, it first determines whether the first read padding descriptor can be optimized. If it cannot be optimized, the processing procedure of "first read padding descriptor → read padding data → sending the first read padding descriptor as the second read padding descriptor and sending the read padding data" is executed. If it can be optimized, the processing procedure of "first read padding descriptor → second read padding descriptor → read padding data → sending the second read padding descriptor and the read padding data" is executed. Among them, whether it can be optimized may refer to whether there is a possibility of modifying the padding position, the padded number, and the data volume of the padding.

[0048] In this embodiment, the difference between the second read padding descriptor and the first read padding descriptor can be described based on the difference in the read padding data generated by the two and / or based on the difference in the second data read by the two. Taking the difference in the read padding data as an example, the influence of the difference between the second read padding descriptor and the first read padding descriptor on the read padding data includes at least one of the following: the data volume of the read padding data becomes larger, the padding position of the read padding data increases (expands), the padded number changes, etc. In this way, it can be ensured that the determined second data is more accurate, and the data volume of the second data can be further reduced, and the storage efficiency, speed, and power consumption can be further reduced.

[0049] In this embodiment, the first data may be data participating in neural network operations, such as input neurons, output neurons, input weights, biases, constant neurons, etc. The first description information may be user input or determined based on other information input by the user. The first description information records information describing the characteristics of the read padding data in the first data, such as the position, size, padding value, data volume, data format, etc. of the read padding data in the first data. The read descriptor parsing unit can parse the first description information, and then generate a first read padding descriptor that can be directly recognized by the device in combination with the information of the first data (such as data volume, data dimension order, etc., which are information characterizing the characteristics of the first data).

[0050] In a possible implementation manner, the second read padding descriptor includes at least one of the following: the padding position of the read padding data in the first data, the data volume of the read padding data, and the data format of the read padding data. The data format may include data dimension order, dimension, data type, and padding number.

[0051] Among them, the padding position may indicate the specific position of the read padding data in the first data, and the padding position can be described by the start position and end position of the read padding data in the first data, or can be represented by the offset of the read padding data relative to the first data. The data volume of the read padding data may indicate the data size of the read padding data, such as 2 bytes. The data format may characterize the format of the read padding data. The dimension may represent the dimensions included in the read padding data, such as channel dimension, height dimension, width dimension, quantity dimension, depth dimension, and time dimension, etc. The data dimension order may indicate the dimension order for reading and / or writing the read padding data, that is, the reading and / or writing order of the above dimensions. For example, if the read padding data includes a width dimension and a height dimension, the data dimension order for reading and / or writing it may be that the width dimension precedes the height dimension. The data type may represent the type and number of bits of the read padding data. For example, the data type of a certain read padding data is 16-bit floating point number. The padding number may be a specific value such as 0 or 1.

[0052] In this embodiment, the read request may be a conventional request for data reading. According to the read request, data can be read from a specified storage location. For example, the first data can be directly read from the storage location of the first data according to the read request for the first data. The data reading unit is also used to directly read the data to be read from the corresponding storage location according to the received read request for the data to be read.

[0053] In this embodiment, the modified read request includes information required to read the second data, such as the position of the second data in the first data, the data volume of the second data, and the data format of the second data. Among them, the data format may include the data dimension order, dimensions, and data type.

[0054] In a possible implementation, the data reading unit may include: a request receiving subunit, a reading subunit, and a first data transmission subunit.

[0055] The request receiving subunit is configured to receive a read request for the first data and a second read padding descriptor, modify the read request according to the second read padding descriptor to obtain a modified read request, and send the modified read request to the reading subunit. The request receiving subunit may receive the read request through a set read request interface and receive the second read padding descriptor through a set read descriptor interface.

[0056] The reading subunit is configured to read a part of the first data from the memory as the second data according to the modified read request, and send the second data to the first data transmission subunit.

[0057] The first data transmission subunit is configured to send the received second data to a subsequent unit. The data transmission subunit may send the second data to the subsequent unit through a set interface.

[0058] In the data processing device provided by the embodiments of the present disclosure, during the process of obtaining the first data, only the second data in the first data may be read and sent to a subsequent unit, reducing the data volume of data reading, shortening the data reading time, improving the efficiency and speed of data reading, reducing power consumption, and significantly improving the efficiency of subsequent units performing operations, storage, and other processing, thereby enhancing the performance of the device for data processing.

[0059] Figure 2 The block diagram of a data processing device according to an embodiment of the present disclosure is shown. In a possible implementation, as Figure 2 shown, the subsequent unit 43 may include an arithmetic unit 431.

[0060] The arithmetic unit 431 is configured to generate the first data according to the received second data and the read padding data, and perform arithmetic processing on the first data to obtain an arithmetic result corresponding to the first data.

[0061] In this implementation, the arithmetic unit may include arithmetic units required to implement arithmetic processing for the first data. The arithmetic processing may include arithmetic operations and / or logical operations. For example, the arithmetic units may include adders, multipliers, comparators, selectors, etc. The arithmetic processing performed on the first data may be operations involved in neural network operations.

[0062] In this implementation, the operation unit receives the second data and the read padding data. Compared with directly receiving the first data, the data input efficiency is significantly improved. Moreover, the first data can be generated based on the read padding data and the second data, without affecting the normal subsequent operation and processing of the first data.

[0063] In a possible implementation, as Figure 2 shown, the subsequent unit 43 may include an operation unit 431, and the read descriptor parsing unit may include a read controller. The read controller is configured to generate read control information according to the second read padding descriptor and send the read control information to the operation unit.

[0064] Wherein, the operation unit 431 performs operations on the second data and / or the read padding data under the control of the read control information. The operation unit 431 may use a selector to select the second data and the read padding data under the control of the read control information, and then perform corresponding operations, so as to obtain an intermediate result corresponding to the read padding data and an intermediate result corresponding to the second data, and finally obtain an operation result corresponding to the first data according to the intermediate result corresponding to the read padding data and the intermediate result corresponding to the second data. Or the operation unit 431 may use a selector to select the second data and the read padding data under the control of the read control information, and then perform corresponding operations to directly obtain an operation result corresponding to the first data.

[0065] Alternatively, the operation unit 431 generates the first data according to the second data and the read padding data under the control of the read control information and then performs operations. The operation unit 431 may use a selector to perform selection processing on the read padding data and the second data under the control of the read control information to obtain the first data, and then perform operations on the obtained first data to obtain an operation result.

[0066] For example, assume that the first data is What is read by using the device of the present disclosure according to the modified read request is the second data and the read padding data [1 1 1] is generated. The operation unit may generate according to and [1 1 1] under the control of the read control information, and then perform operations to obtain an operation result.

[0067] In a possible implementation, the read descriptor parsing unit may further include a read padding data generation subunit. The read controller is further configured to parse the first description information to obtain a first read padding descriptor, optimize and modify the first read padding descriptor to obtain a second read padding descriptor, and send read control information to the read padding data generation subunit. The read padding data generation subunit is configured to receive the read control information and generate read padding data according to the read control information.

[0068] In a possible implementation, the read controller may receive the first description information through a description information receiving interface set in the read descriptor parsing unit, and send the second padding descriptor to the data reading unit through a descriptor sending interface set in the read descriptor parsing unit. The read descriptor parsing unit may further include a second data transmission subunit, and the second data transmission subunit is configured to send the read padding data and the read control information to the arithmetic unit.

[0069] In a possible implementation, the subsequent unit 43 may include a subsequent read descriptor parsing unit and a subsequent data reading unit. The read descriptor parsing unit is further configured to send the second read padding descriptor to the subsequent read descriptor parsing unit; the subsequent read descriptor parsing unit is configured to send the second read padding descriptor to the subsequent data reading unit.

[0070] The subsequent read descriptor parsing unit further generates read padding data according to the second read padding descriptor and sends it to other subsequent units (such as an arithmetic unit, excluding the subsequent data reading unit). The subsequent data reading unit receives a read request for the first data and the second read padding descriptor, modifies the read request according to the second read padding descriptor to obtain a modified read request, reads a part of the first data as the second data according to the modified read request, and sends the second data to the other subsequent units (such as an arithmetic unit, excluding the subsequent data reading unit), and the second data is the data in the first data other than the read padding data.

[0071] The data reading unit may also directly forward the read request to the subsequent data reading unit.

[0072] In this implementation manner, the subsequent units may include a plurality of subsequent read descriptor parsing units and a plurality of subsequent data reading units. Through the above manner, by only inputting the second description information to the read descriptor parsing unit and inputting a read request to the data reading unit, the data reading unit and the subsequent data reading units can respectively read the second data, and the read descriptor parsing unit and the subsequent read descriptor parsing units can also generate read padding data. Each data reading unit and the corresponding read descriptor parsing unit (or subsequent data reading unit and the corresponding subsequent read descriptor parsing unit) can respectively send the second data and the read padding data to different arithmetic units to implement different arithmetic processes and obtain arithmetic results.

[0073] Figure 3 The block diagram of a data processing device according to an embodiment of the present disclosure is shown. In a possible implementation manner, as Figure 3 shown, the subsequent unit 43 may further include a write descriptor parsing unit 432 and a first data writing unit 433.

[0074] The arithmetic unit 431 is further configured to send the arithmetic result to the first data writing unit 433.

[0075] The write descriptor parsing unit 432 is configured to parse the received second description information for the arithmetic result to obtain a first write padding descriptor, generate write padding data according to the first write padding descriptor, and send the first write padding descriptor and the write padding data to the first data writing unit 433.

[0076] The first data writing unit 433 is configured to receive a first write request for the arithmetic result, the first write padding descriptor, and the write padding data, modify the first write request according to the first write padding descriptor to obtain a modified first write request, and store the data to be written in the arithmetic result and the write padding data according to the modified first write request. The data to be written is the data in the arithmetic result other than the write padding data.

[0077] In this implementation manner, since the state of the first data (such as information about the position of the read padding data in the first data) is known in advance, and the arithmetic method, operator, etc. adopted in the arithmetic result corresponding to the first data obtained by the arithmetic unit are also known in advance, therefore, the write padding data in the arithmetic result can be determined based on this. In this way, for the arithmetic result, the first data writing unit only stores the data to be written therein (partial data of the arithmetic result), which can improve the storage efficiency, speed of the arithmetic result, and reduce the power consumption of storing the arithmetic result. The setting of the write padding data ensures that the stored data to be written and the write padding data can finally generate the arithmetic result. Ensure the integrity of the data.

[0078] For example, assume that the operation result is What is written according to the first write request after modification is the part to be written in the operation result And write the write padding data [0 0 0] generated according to the first write padding descriptor.

[0079] In another possible implementation, the write descriptor parsing unit 432 is configured to parse the received second description information for the operation result to obtain a first write padding descriptor, and send the first write padding descriptor to the first data writing unit 433. The first data writing unit 433 is configured to receive the first write request, the first write padding descriptor, and the write padding data for the operation result, modify the first write request according to the first write padding descriptor to obtain a modified first write request, and store the data to be written and the first write padding descriptor in the operation result according to the modified first write request, that is, store the data to be written and the first write padding descriptor as the "operation result". During the subsequent process of reading the "operation result", the data to be written and the first write padding descriptor can be read, and then the write padding data can be generated according to the first write padding descriptor, so as to generate an operation result including all data according to the data to be written and the write padding data. Then, the data to be written is the data in the operation result other than the write padding data. In this way, the data storage process for the operation result can be further simplified, and the storage efficiency, speed can be further improved, and the power consumption of storing the operation result can be reduced.

[0080] In a possible implementation, the first write padding descriptor may include at least one of the following: the padding position of the write padding data in the operation result, the data amount of the write padding data, and the data format of the write padding data. The data format further includes at least one of the following: data dimension order, dimension, data type, and filled number. The definition of the information included in the first write padding descriptor is the same as that of the second read padding descriptor. For the relevant description of the second read padding descriptor, please refer to the above text and will not be elaborated here.

[0081] In a possible implementation, the first data writing unit is further configured to receive a third write request for the operation result, and store the operation result according to the third write request. That is, the first data writing unit can directly store the operation result.

[0082] In a possible implementation, the write descriptor parsing unit is further configured to optimize the first write padding descriptor to obtain an optimized write padding descriptor when determining that the first write padding descriptor meets the optimization condition, generate the write padding data according to the optimized write padding descriptor, and send the optimized write padding descriptor to the first data writing unit as the first write padding descriptor.

[0083] In this implementation, after the write descriptor parsing unit parses the first write padding descriptor, it first determines whether it is possible to optimize it. If optimization is not possible, it executes the processing procedure of "first write padding descriptor → write padding data → send the first write padding descriptor and write padding data". If optimization is possible, it executes the processing procedure of "first write padding descriptor → optimized write padding descriptor → write padding data → send the first write padding descriptor (i.e., the optimized write padding descriptor) and write padding data". Among them, whether it is possible to optimize may refer to whether there is a possibility of modifying the filling position, the filled number, and the filled data volume. In this way, it can be ensured that the determined data to be written is more accurate, and the data volume of the data to be written can be further reduced, further improving the storage efficiency and speed and reducing the power consumption of the stored operation result. The difference between the first write padding descriptor and the optimized write padding descriptor can be referred to the difference between the first read padding descriptor and the second read padding descriptor above, which will not be elaborated here.

[0084] Figure 4 The block diagram of a data processing device according to an embodiment of the present disclosure is shown. In a possible implementation, as Figure 4 shown, the subsequent unit 43 includes a second data writing unit 434.

[0085] The read descriptor parsing unit is further configured to send the first read padding descriptor to the second data writing unit 434 as the second write padding descriptor.

[0086] The second data writing unit 434 is further configured to receive the second data, the read padding data, the second write request for the second data, and the second write padding descriptor, modify the second write request according to the second write padding descriptor to obtain a modified second write request, and store the second data and the read padding data according to the modified second write request, or store the first data generated according to the second data and the read padding data according to the modified second write request.

[0087] In the above manner, the process of transferring and storing the first data is actually implemented. Since only a part of the first data (i.e., the second data) is read during the reading process, and the storage of the first data in the storage also performs the storage process of storing a part of the first data (i.e., the second data), the access amount during the data transfer and storage process is greatly reduced, the efficiency and speed of the transfer and storage are improved, and the power consumption of the transfer and storage is reduced.

[0088] Alternatively, the second data writing unit 434 may also store only the second data and the second write padding descriptor, and store them as the "first data". During the subsequent process of reading the "first data", the second data and the second write padding descriptor can be read, and then the read padding data can be generated according to the second write padding descriptor. Finally, the first data including all the data can be generated according to the second data and the read padding data. In this way, the process of transferring and storing the first data can be further simplified, the efficiency and speed of the transfer and storage can be further improved, and the power consumption of the transfer and storage can be reduced.

[0089] In a possible implementation manner, the device includes a data processing module, and the data processing module includes at least one of the data reading unit, the read descriptor parsing unit, and the subsequent unit. One or more of the data reading unit, the read descriptor parsing unit, and the subsequent unit can be integrated into the same data processing module according to needs, so as to simplify the structure of the device.

[0090] In a possible implementation manner, the second read padding descriptor, the first write padding descriptor, and the second write padding descriptor can set the same padding descriptor format, and distinguish whether the padding descriptor is a read padding descriptor or a write padding descriptor through write and read identifiers. For example, the padding descriptor format can be:

[0091]

[0092] Among them, pattern represents the data format, order represents the data dimension order, dims represents the dimension, Data type represents the data type, data represents the filled number, reserved represents the reserved field or redundant field, Addr represents the filling position, Size represents the data volume, and Attribute represents whether the padding descriptor is the second read padding descriptor for a read request or the first write padding descriptor or the second write padding descriptor for a write request. Different codes can be set for Attribute, such as 01 representing the second read padding descriptor, and 00 representing the first write padding descriptor or the second write padding descriptor.

[0093] Figure 5 Shows a flowchart of a data processing method according to an embodiment of the present disclosure. As Figure 5As shown, this method is applied to the above data processing device, and this method includes step S11 and step S12.

[0094] Step S11: Control the read descriptor parsing unit to parse the first description information received for the first data, optimize and modify the parsed first read padding descriptor for the first data to obtain a second read padding descriptor, send the read padding data generated according to the second read padding descriptor to a subsequent unit, and send the second read padding descriptor to the data reading unit.

[0095] Step S12: Control the data reading unit to receive a read request for the first data and the second read padding descriptor, modify the read request according to the second read padding descriptor to obtain a modified read request, read a part of the first data as the second data according to the modified read request, and send the second data to the subsequent unit.

[0096] The second data is the data in the first data other than the read padding data.

[0097] In a possible implementation, the subsequent unit may include an arithmetic unit. The method may further include:

[0098] Control the arithmetic unit to generate the first data according to the received second data and the read padding data, and perform arithmetic processing on the first data to obtain an arithmetic result corresponding to the first data.

[0099] In a possible implementation, the subsequent unit may include an arithmetic unit, and the read descriptor parsing unit may include a read controller. The method further includes: Control the read controller to generate read control information according to the second read padding descriptor, and send the read control information to the arithmetic unit.

[0100] Wherein, the method further includes: Control the arithmetic unit to perform arithmetic on the second data and / or the read padding data under the control of the read control information; or

[0101] Control the arithmetic unit to perform arithmetic after generating the first data according to the second data and the read padding data under the control of the read control information.

[0102] In a possible implementation, the subsequent unit may include a subsequent read descriptor parsing unit and a subsequent data reading unit. The method further includes:

[0103] Control the read descriptor parsing unit to send the first read padding descriptor to the subsequent read descriptor parsing unit;

[0104] Control the subsequent read descriptor parsing unit to send the first read padding descriptor to the subsequent data reading unit.

[0105] In a possible implementation, the subsequent unit may further include a write descriptor parsing unit and a first data writing unit. The method further includes:

[0106] Control the arithmetic unit to send the arithmetic result to the first data writing unit;

[0107] Control the write descriptor parsing unit to parse the received second description information for the arithmetic result to obtain a first write padding descriptor, generate write padding data according to the first write padding descriptor, and send the write padding data and the first write padding descriptor to the first data writing unit;

[0108] Control the first data writing unit to receive a first write request for the arithmetic result, the write padding data, and the first write padding descriptor, modify the first write request according to the first write padding descriptor to obtain a modified first write request, and store the data to be written in the arithmetic result and the write padding data according to the modified first write request,

[0109] The data to be written is the data in the arithmetic result other than the write padding data.

[0110] In a possible implementation, the subsequent unit may include a second data writing unit. The method further includes:

[0111] Control the read descriptor parsing unit to send the first read padding descriptor as a second write padding descriptor to the second data writing unit;

[0112] Control the second data writing unit to receive the second data, the read padding data, a second write request for the second data, and the second write padding descriptor, modify the second write request according to the second write padding descriptor to obtain a modified second write request, and store the second data and the read padding data according to the modified second write request, or store the first data generated according to the second data and the read padding data according to the modified second write request.

[0113] In a possible implementation, the subsequent unit further includes a first data writing unit. The method further includes:

[0114] Control the first data writing unit to receive a third write request for the arithmetic result and store the arithmetic result according to the third write request.

[0115] In a possible implementation, the method further includes: controlling the write descriptor parsing unit to optimize the first write padding descriptor to obtain an optimized write padding descriptor when it is determined that the first write padding descriptor meets the optimization condition, generating the write padding data according to the optimized write padding descriptor, and sending the optimized write padding descriptor to the first data writing unit as the first write padding descriptor.

[0116] In a possible implementation, the second read padding descriptor includes at least one of the following: the padding position of the read padding data in the first data, the data volume of the read padding data, the data format of the read padding data.

[0117] The first write padding descriptor includes at least one of the following: the padding position of the write padding data in the operation result, the data volume of the write padding data, the data format of the write padding data.

[0118] The data format further includes at least one of the following: data dimension order, dimension, data type, filled numbers.

[0119] The data processing method provided by the embodiments of the present disclosure can, during the process of reading the first data, only read the second data in the first data and send it to the subsequent unit, reducing the data volume of data reading, shortening the data reading time, improving the efficiency and speed of data reading, reducing power consumption, and significantly improving the efficiency of subsequent units performing operations, storage, and other processes, thereby enhancing the performance of the device for data processing.

[0120] It should be noted that although the above embodiments are used as examples to introduce the data processing method and device as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly set each step and unit according to personal preferences and / or actual application scenarios as long as they conform to the technical solution of the present disclosure.

[0121] The present disclosure provides a machine learning operation device, which may include one or more of the above data processing devices, and is configured to obtain data to be operated and control information from other processing devices and execute specified machine learning operations. The machine learning operation device may obtain neural network computing macro instructions or neural network computing instructions to be executed from other machine learning operation devices or non-machine learning operation devices, and transmit the execution results to peripheral devices (which may also be referred to as other processing devices) through an I / O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, Wi-Fi interfaces, and servers. When there are more than one data processing device, the data processing devices may be linked and data may be transmitted through a specific structure. For example, they may be interconnected and data may be transmitted through a PCIE bus to support the operation of larger-scale neural networks. At this time, the same control system may be shared, or there may be independent control systems for each; the memory may be shared, or each accelerator may have its own memory. In addition, the interconnection method may be any interconnection topology.

[0122] The machine learning operation device has high compatibility and can be connected to various types of servers through a PCIE interface.

[0123] Figure 6 FIG. is a structural diagram showing a combined processing device 1200 according to an embodiment of the present disclosure. As Figure 6 shown in the figure, the combined processing device 1200 includes a computing processing device 1202, an interface device 1204, other processing devices 1206, and a storage device 1208. According to different application scenarios, the computing processing device may include one or more computing devices 1210. The computing processing device 1202 may be the above-mentioned machine learning operation device or the above-mentioned data processing device.

[0124] In different embodiments, the computing processing device of the present disclosure may be configured to execute operations specified by a user. In an exemplary application, the computing processing device may be implemented as a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing processing device may be implemented as artificial intelligence processor cores (i.e., the computing cores described above) or partial hardware structures of artificial intelligence processor cores.

[0125] In an exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through an interface device to jointly complete operations specified by a user. Depending on the implementation, the other processing devices of the present disclosure can include one or more types of general-purpose and / or special-purpose processors such as a central processing unit (CPU), a graphics processing unit (GPU), and an artificial intelligence processor. These processors can include, but are not limited to, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and the number thereof can be determined according to actual needs. As mentioned above, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when considering the computing processing device and other processing devices together, the two can be regarded as forming a heterogeneous multi-core structure.

[0126] In one or more embodiments, the other processing device can serve as an interface for external data and control for the computing processing device of the present disclosure (which can be specifically implemented as a related computing device for artificial intelligence such as neural network operations), and perform basic controls including but not limited to data transfer, turning on and / or off the computing device. In other embodiments, the other processing device can also cooperate with the computing processing device to jointly complete computing tasks.

[0127] In one or more embodiments, the interface device can be used to transfer data and control instructions between the computing processing device and other processing devices. For example, the computing processing device can obtain input data from other processing devices via the interface device and write it into the storage device (or memory) on the chip of the computing processing device. Further, the computing processing device can obtain control instructions from other processing devices via the interface device and write them into the control cache on the chip of the computing processing device. Alternatively or optionally, the interface device can also read the data in the storage device of the computing processing device and transfer it to other processing devices.

[0128] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is respectively connected to the computing processing device and the other processing device. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, this data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0129] In some embodiments, the present disclosure also discloses a chip (such as Figure 7 the chip 1302 shown in Figure 6 ). In one implementation, the chip is a system-on-chip (SoC) and integrates one or more combined processing devices as shown in Figure 7 . The chip can be connected to other related components through an external interface device (such as the external interface device 1306 shown in Figure 7 ). The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. In some application scenarios, other processing units (such as a video codec) and / or interface modules (such as a DRAM interface) etc. may be integrated on the chip. In some embodiments, the present disclosure also discloses a chip package structure including the above chip. In some embodiments, the present disclosure also discloses a board including the above chip package structure. The following will describe the board in detail in conjunction with

[0130] Figure 7 is a schematic structural diagram of a board 1300 according to an embodiment of the present disclosure. As shown in Figure 7 , the board includes a storage device 1304 for storing data, which includes one or more storage units 1310. The storage device can be connected and data-transferred to the control device 1308 and the above-mentioned chip 1302 through, for example, a bus. Further, the board also includes an external interface device 1306, which is configured to perform data relaying or switching functions between the chip (or the chip in the chip package structure) and an external device 1312 (such as a server or a computer, etc.). For example, the data to be processed can be transmitted from the external device to the chip through the external interface device. Again, for example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device may have different interface forms. For example, it may adopt a standard PCIE interface, etc.

[0131] In one or more embodiments, the control device in the disclosed board can be configured to regulate the state of the chip. For this purpose, in one application scenario, the control device can include a microcontroller unit (MCU) for regulating the operating state of the chip.

[0132] According to the above combination Figure 6 and Figure 7 the description of, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which can include one or more of the above-mentioned boards, one or more of the above-mentioned chips, and / or one or more of the above-mentioned combined processing devices.

[0133] According to different application scenarios, the electronic device or apparatus of the present disclosure can include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, Internet of Things terminals, mobile terminals, mobile phones, dash cams, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, vision terminals, autonomous driving terminals, transportation means, household appliances, and / or medical devices. The transportation means includes airplanes, ships, and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, range hoods; the medical devices include nuclear magnetic resonance imagers, B-ultrasound devices, and / or electrocardiographs. The electronic device or apparatus of the present disclosure can also be applied to fields such as the Internet, Internet of Things, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and medical. Further, the electronic device or apparatus of the present disclosure can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing such as the cloud, edge, and terminal. In one or more embodiments, the electronic device or apparatus with high computing power according to the present disclosure solution can be applied to cloud devices (such as cloud servers), while the electronic device or apparatus with low power consumption can be applied to terminal devices and / or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of cloud devices is compatible with the hardware information of terminal devices and / or edge devices, so that appropriate hardware resources can be matched from the hardware resources of cloud devices according to the hardware information of terminal devices and / or edge devices to simulate the hardware resources of terminal devices and / or edge devices, so as to complete the unified management, scheduling, and collaborative work of end-cloud integration or cloud-edge-end integration.

[0134] It should be noted that, for the purpose of simplicity, some methods and their embodiments in the present disclosure are expressed as a series of actions and their combinations. However, those skilled in the art can understand that the solutions of the present disclosure are not limited by the order of the described actions. Therefore, according to the disclosure or teachings of the present disclosure, those skilled in the art can understand that some of the steps can be executed in other orders or simultaneously. Further, those skilled in the art can understand that the embodiments described in the present disclosure can be regarded as optional embodiments, that is, the actions or modules involved are not necessarily required for the implementation of certain solutions of the present disclosure. In addition, according to different solutions, the descriptions of some embodiments in the present disclosure also have different focuses. In view of this, those skilled in the art can understand that for the parts not detailed in a certain embodiment of the present disclosure, they can also refer to the relevant descriptions of other embodiments.

[0135] In terms of specific implementation, based on the disclosure and teachings of the present disclosure, those skilled in the art can understand that several embodiments disclosed in the present disclosure can also be implemented by other means not disclosed herein. For example, for each unit in the foregoing embodiments of the electronic device or apparatus, a division is made herein based on the consideration of logical functions, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions of the units or components can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed in conjunction with the accompanying drawings herein can be direct or indirect couplings between units or components. In some scenarios, the foregoing direct or indirect couplings involve communication connections using interfaces, where the communication interfaces can support signal transmissions in electrical, optical, acoustic, magnetic, or other forms.

[0136] In the present disclosure, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The foregoing components or units may be located at the same position or distributed over multiple network units. In addition, according to actual needs, some or all of the units can be selected to achieve the purpose of the solutions described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure can be integrated into one unit or each unit physically exists separately.

[0137] In some implementation scenarios, the above-integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as an independent product, the above-integrated units may be stored in a computer-readable memory. Based on this, when the solution of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product may be stored in a memory, and it may include several instructions for causing a computer device (such as a personal computer, a server, or a network device, etc.) to execute some or all of the steps of the method described in the embodiments of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as USB flash drives, flash memory drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs.

[0138] In some other implementation scenarios, the above-integrated units may also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, and the physical devices may include, but are not limited to, devices such as transistors or memristors. In view of this, various devices described herein (such as computing devices or other processing devices) may be implemented by appropriate hardware processors, such as CPU, GPU, FPGA, DSP, and ASIC, etc. Further, the aforementioned storage unit or storage device may be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which may be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM, etc.

[0139] The embodiments of the present disclosure have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the technical improvements to the technology in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A data processing device, characterized in that, the device includes: a read descriptor parsing unit and a data reading unit, the read descriptor parsing unit is configured to parse the received first description information for the first data, optimize and modify the parsed first read padding descriptor for the first data to obtain a second read padding descriptor, and send the read padding data generated according to the second read padding descriptor to a subsequent unit, and send the second read padding descriptor to the data reading unit; the data reading unit is configured to receive a read request for the first data and the second read padding descriptor, modify the read request according to the second read padding descriptor to obtain a modified read request, read a part of the first data as the second data according to the modified read request, and send the second data to the subsequent unit, wherein the second data is the data in the first data other than the read padding data; the read padding data is any one or more regular data in the first data that can be determined without reading from the memory.

2. The device according to claim 1, characterized in that, the subsequent unit includes an arithmetic unit, the arithmetic unit is configured to generate the first data according to the received second data and the read padding data, and perform arithmetic processing on the first data to obtain an arithmetic result corresponding to the first data.

3. The device according to claim 1 or 2, characterized in that, the subsequent unit includes an arithmetic unit, and the read descriptor parsing unit includes a read controller, the read controller is configured to generate read control information according to the second read padding descriptor, and send the read control information to the arithmetic unit; wherein, the arithmetic unit performs arithmetic on the second data and / or the read padding data under the control of the read control information; or the arithmetic unit generates the first data according to the second data and the read padding data under the control of the read control information and then performs arithmetic.

4. The device according to claim 1, characterized in that, the subsequent unit includes a subsequent read descriptor parsing unit and a subsequent data reading unit, wherein, the read descriptor parsing unit is further configured to send the first read padding descriptor to the subsequent read descriptor parsing unit; the subsequent read descriptor parsing unit is configured to send the first read padding descriptor to the subsequent data reading unit.

5. The device according to claim 2, characterized in that, the subsequent unit further includes a write descriptor parsing unit and a first data writing unit, the arithmetic unit is further configured to send the arithmetic result to the first data writing unit; the write descriptor parsing unit is configured to parse the received second description information for the arithmetic result to obtain a first write padding descriptor, generate write padding data according to the first write padding descriptor, and send the write padding data and the first write padding descriptor to the first data writing unit; The first data writing unit is configured to receive a first write request for the operation result, the write padding data, and the first write padding descriptor, modify the first write request according to the first write padding descriptor to obtain a modified first write request, and store the data to be written in the operation result and the write padding data according to the modified first write request. The data to be written is the data in the operation result other than the write padding data.

6. The apparatus according to claim 1, wherein, the subsequent unit includes a second data writing unit, the read descriptor parsing unit is further configured to send the first read padding descriptor to the second data writing unit as a second write padding descriptor; the second data writing unit is further configured to receive the second data, the read padding data, a second write request for the second data, and the second write padding descriptor, modify the second write request according to the second write padding descriptor to obtain a modified second write request, and store the second data and the read padding data according to the modified second write request, or store the first data generated according to the second data and the read padding data according to the modified second write request.

7. The apparatus according to claim 2, wherein, the subsequent unit further includes a first data writing unit, the first data writing unit is further configured to receive a third write request for the operation result and store the operation result according to the third write request.

8. The apparatus according to claim 5, wherein, the write descriptor parsing unit is further configured to optimize the first write padding descriptor to obtain an optimized write padding descriptor when determining that the first write padding descriptor meets the optimization condition, generate the write padding data according to the optimized write padding descriptor, and send the optimized write padding descriptor to the first data writing unit as the first write padding descriptor.

9. The apparatus according to claim 1, wherein, the apparatus includes a data storage module, and the data storage module includes at least one of the data reading unit, the read descriptor parsing unit, and the subsequent unit.

10. The apparatus according to claim 5, wherein, the second read padding descriptor includes at least one of the following: the padding position of the read padding data in the first data, the data amount of the read padding data, the data format of the read padding data, the first write padding descriptor includes at least one of the following: the padding position of the write padding data in the operation result, the data amount of the write padding data, the data format of the write padding data, the data format further includes at least one of the following: data dimension order, dimension, data type, filled number.

11. A data processing method, wherein, applied to a data processing apparatus, the data processing apparatus includes a read descriptor parsing unit and a data reading unit, and the method includes: Control the read descriptor parsing unit to parse the first description information received for the first data, optimize and modify the parsed first read padding descriptor for the first data to obtain a second read padding descriptor, send the read padding data generated according to the second read padding descriptor to the subsequent unit, and send the second read padding descriptor to the data reading unit; Control the data reading unit to receive a read request and a second read padding descriptor for the first data, modify the read request according to the second read padding descriptor to obtain a modified read request, read a part of the first data as the second data according to the modified read request, and send the second data to the subsequent unit, The second data is the data in the first data other than the read padding data; The read padding data is any one or more regular data in the first data that can be determined without reading from the memory.

12. A non-volatile computer-readable storage medium, Characterized in that, It stores computer program instructions, and characterized in that when the computer program instructions are executed by a processor, the data processing method described in claim 11 is implemented.

13. A data processing device, Characterized in that, The device includes a processor and a memory, the memory stores a computer program, and when the processor executes the computer program, the data processing method described in claim 11 is implemented.

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