Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched; forming an initial sacrificial layer on the layer to be etched; forming a modified layer within the initial sacrificial layer, wherein the modified layer has a thickness less than that of the initial sacrificial layer and has a different etching rate than the initial sacrificial layer; using a first etch to remove a portion of the initial sacrificial layer to form a groove between the modified layers, wherein the depth of the groove is less than the thickness of the initial sacrificial layer; and using the modified layer as a mask, using a second etch to remove the initial sacrificial layer exposed at the bottom of the groove, thereby forming a sacrificial layer and a modified layer located on the sacrificial layer. The semiconductor structure formed by this method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the continuous improvement of the performance of very large-scale integrated circuits (VLSI), the gradual reduction of device size and the continuous increase in device density, the process nodes continue to shrink. Due to the insufficient light source power of the next-generation lithography technology, extreme ultraviolet lithography (EUV), its time to enter mass production has been delayed, so 193 nanometer (nm) deep ultraviolet (DUV) immersion lithography technology will inevitably continue to be used for a long time. However, the resolution of a single exposure of deep ultraviolet immersion lithography technology is approximately 38 nanometers (nm). To further reduce the process node, new process methods must be used. Therefore, a variety of pattern-forming materials have been introduced. The materials can be modified under appropriate conditions. Under certain conditions, the modified materials have a larger etching selectivity ratio with the original materials, thereby being able to form an ordered pattern of nanometer-sized structural units, forming the pattern of the semiconductor structure to be formed.

[0003] However, as semiconductor technology nodes are further reduced, existing methods of using material modification as a method for patterning semiconductor structures need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the pattern of the semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming an initial sacrificial layer on the layer to be etched; forming a modified layer in the initial sacrificial layer, the thickness of the modified layer is less than the thickness of the initial sacrificial layer, and the etching rate of the modified layer is different from that of the initial sacrificial layer; using a first etch to remove part of the initial sacrificial layer, forming a groove between the modified layers, the depth of the groove is less than the thickness of the initial sacrificial layer; using the modified layer as a mask, using a second etch to remove the initial sacrificial layer exposed at the bottom of the groove, to form a sacrificial layer and a modified layer located on the sacrificial layer.

[0006] Optionally, the thickness of the modified layer is one third to two thirds of the thickness of the initial sacrificial layer.

[0007] Optionally, the bottom of the groove is flush with the bottom plane of the modified layer.

[0008] Optionally, the first etching process includes a wet etching process.

[0009] Optionally, the second etching process includes a dry etching process.

[0010] Optionally, the method further includes: etching the layer to be etched using the sacrificial layer and the modified layer located on the sacrificial layer as masks.

[0011] Optionally, the method for forming the modified layer includes: forming a first mask structure on the initial sacrificial layer, the first mask structure exposing a portion of the top surface of the initial sacrificial layer; and performing ion implantation on the initial sacrificial layer using the first mask structure as a mask to form the modified layer.

[0012] Optionally, the ions implanted into the initial sacrificial layer include carbon ions, fluorine ions or nitrogen ions.

[0013] Optionally, after forming the modified layer and before removing part of the initial sacrificial layer, the method further includes: forming a second mask structure on the initial sacrificial layer and the modified layer, the second mask structure exposing part of the surface of the initial sacrificial layer and part of the surface of the modified layer; etching the exposed initial sacrificial layer and the modified layer using the second mask structure as a mask until the surface of the layer to be etched is exposed, and forming a composite structure on the layer to be etched, the composite structure including the transition sacrificial layer and part of the modified layer located in the transition sacrificial layer.

[0014] Optionally, after the composite structure is formed, a sidewall structure is formed on the sidewall of the composite structure; a portion of the transition sacrificial layer is removed to form the groove, and a portion of the groove exposes the sidewall of the sidewall structure.

[0015] Optionally, after forming the sacrificial layer and the modified layer located on the sacrificial layer, the method further includes: etching the layer to be etched using the sidewall structure, the sacrificial layer and the modified layer located on the sacrificial layer as a mask.

[0016] Optionally, the method for forming the sidewall structure includes: forming a sidewall material layer on the top surface and sidewall surface of the composite structure and the surface of the layer to be etched; and etching back the sidewall material layer until the top surface of the composite structure is exposed to form the sidewall structure.

[0017] Optionally, the material of the sidewall structure and the material of the transition sacrificial layer have different etching rates; the material of the sidewall structure and the material of the modified layer have different etching rates; the material of the sidewall structure and the material of the surface of the layer to be etched have different etching rates.

[0018] Optionally, the material of the sidewall structure includes titanium oxide, silicon oxide or silicon nitride.

[0019] Optionally, the layer to be etched includes a substrate, a transition layer located on the substrate, and a stop layer located on the transition layer; the substrate includes a base and a device layer located on the base, the device layer includes an isolation layer and a device structure located in the isolation layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0020] Optionally, the material of the stop layer includes silicon oxide or silicon nitride.

[0021] Optionally, the material of the transition layer includes titanium nitride, titanium oxide or silicon nitride.

[0022] Optionally, the etching rate of the material of the initial sacrificial layer is different from that of the surface material of the layer to be etched.

[0023] Optionally, the material of the initial sacrificial layer includes a material of a fourth main group element, and the material of the fourth main group element includes silicon, germanium or carbon.

[0024] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0025] The method for forming a semiconductor structure according to the technical solution of the present invention comprises first performing ion implantation on the initial sacrificial layer to form a modified layer, wherein the thickness of the modified layer is less than that of the initial sacrificial layer, then removing a portion of the initial sacrificial layer to form a groove, and then removing the initial sacrificial layer at the bottom of the groove. The modified layer formed after the modification of the initial sacrificial layer has a different etching rate than the initial sacrificial layer. Since the thickness of the modified layer is less than that of the initial sacrificial layer, the morphology of the doped region of the modified layer is controllable, and the dimensional uniformity of the formed modified layer is good. A first etching step is first performed to remove a portion of the initial sacrificial layer. The first etching step has a large etching selectivity for the materials of the modified layer and the initial sacrificial layer. The morphology of the sidewalls of the groove formed is controlled by the doped region of the modified layer, and a groove with relatively straight and smooth sidewalls is formed. Then, a second etching step is performed to remove the initial sacrificial layer at the bottom of the groove. The second etching step has a high degree of directionality, thereby making the sidewalls of the formed sacrificial layer relatively straight and smooth, and the morphology of the sidewalls of the sacrificial layer can also be controlled. In summary, the first etching and the second etching make the formed sacrificial layer and the modified layer located on the sacrificial layer have better morphology and uniform size. When the graphic transfer is subsequently continued using the sacrificial layer and the modified layer located on the sacrificial layer as masks, the size uniformity of the formed semiconductor structure is better, which is beneficial to improving the uniformity of the performance of the semiconductor structure.

[0026] Furthermore, the modified layer and the initial sacrificial layer have different etching rates, and the first etching process includes a wet etching process, which has a larger etching selectivity ratio for the modified layer and the initial sacrificial layer, so the first etching can obtain a groove with better sidewall morphology.

[0027] Furthermore, the second etching process includes a dry etching process. The dry etching process is anisotropic, and thus can perform highly directional etching on the initial sacrificial layer at the bottom of the groove to obtain a sacrificial layer with a better sidewall morphology.

[0028] Furthermore, after forming the modified layer and before removing part of the initial sacrificial layer, the method further includes: forming a composite structure on the layer to be etched, the composite structure including a transition sacrificial layer and a portion of the modified layer located within the transition sacrificial layer, and then forming a sidewall structure on the sidewall of the composite structure. After removing the exposed transition sacrificial layer, the formed sacrificial layer and the modified layer located on the sacrificial layer and the sidewall structure together serve as a mask pattern for subsequent pattern transfer. Because the etching rates of the modified layer and the transition sacrificial layer are different, the required mask patterns of different sizes and different spacings can be obtained by adjusting the sizes of the modified layer and the transition sacrificial layer within the composite structure, so as to subsequently form semiconductor structures with diverse sizes. The method is highly flexible, has a simple process, and has good dimensional accuracy, which is conducive to improving production efficiency and saving production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 and Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0030] Figures 3 to 8 is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0031] Figures 9 to 14 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the existing method of using material modification as a method for pattern formation in semiconductor structures needs to be improved.

[0033] Figure 1 and Figure 2 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0034] Please refer to Figure 1 , providing a layer to be etched 100; forming a sacrificial layer 101 on the layer to be etched 100; forming a mask structure 102 on the sacrificial layer 101, wherein the mask structure 102 exposes a portion of the top surface of the sacrificial layer 101; ion implantation is performed on the sacrificial layer 101 using the mask structure 102 as a mask to form a modified layer 103.

[0035] Please refer to Figure 2After forming the modified layer 103 , the mask structure 102 and the sacrificial layer 101 are removed.

[0036] During the formation of the semiconductor structure, the pattern of the modified layer 103 is subsequently used as a mask to transfer the pattern to the layer to be etched to form the semiconductor structure. The modified layer 103 needs to meet certain thickness requirements to compensate for the natural loss that occurs during the subsequent pattern transfer. Therefore, the thickness of the sacrificial layer 101 cannot be too thin.

[0037] However, the modified layer 103 is obtained by ion implantation into the sacrificial layer 101. The sacrificial layer 101 is relatively thick, so the energy of the implanted ions is weakened when they enter the bottom of the sacrificial layer 101. The implanted ions undergo some free diffusion, resulting in an uneven distribution of the implanted ions at the bottom of the sacrificial layer 101. This makes it difficult to control the morphology of the implanted ions in the implanted area at the bottom of the sacrificial layer 101. Therefore, after the sacrificial layer 101 is removed by a wet etching process, the bottom and top dimensions of the modified layer 103 formed are quite different, and the morphology of the modified layer 103 is poor. After the modified layer 103 is subsequently used as a mask to further etch the layer to be etched, the morphology of the semiconductor structure formed is also poor, affecting the dimensional uniformity of the semiconductor structure, and further affecting the performance uniformity of the semiconductor structure.

[0038] To address the above-mentioned problems, the technical solution of the present invention provides a method for forming a semiconductor structure, wherein ion implantation is first performed on an initial sacrificial layer to form a modified layer, wherein the modified layer has a thickness less than that of the initial sacrificial layer; then, a portion of the initial sacrificial layer is removed to form a groove; and then, the initial sacrificial layer at the bottom of the groove is removed. The modified layer formed after the modification of the initial sacrificial layer has a different etching rate than the initial sacrificial layer. Because the thickness of the modified layer is less than that of the initial sacrificial layer, the morphology of the doped region of the modified layer is controllable, and the dimensional uniformity of the formed modified layer is good. A first etching step is first performed to remove a portion of the initial sacrificial layer. The first etching step has a large etching selectivity for the materials of the modified layer and the initial sacrificial layer. The morphology of the sidewalls of the groove formed is controlled by the doped region of the modified layer, and a groove with relatively straight and smooth sidewalls is formed. Then, a second etching step is performed to remove the initial sacrificial layer at the bottom of the groove. The second etching step has a high degree of directionality, thereby making the sidewalls of the sacrificial layer relatively straight and smooth, and the morphology of the sidewalls of the sacrificial layer can also be controlled. In summary, the first etching and the second etching make the formed sacrificial layer and the modified layer located on the sacrificial layer have better morphology and uniform size. When the graphic transfer is subsequently continued using the sacrificial layer and the modified layer located on the sacrificial layer as masks, the size uniformity of the formed semiconductor structure is better, which is beneficial to improving the uniformity of the performance of the semiconductor structure.

[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 3 to 8 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0041] Please refer to Figure 3 , providing a layer to be etched.

[0042] In this embodiment, the layer to be etched includes a substrate 200 , a transition layer 201 located on the substrate 200 , and a stop layer 202 located on the transition layer 201 .

[0043] The stop layer 202 is used as an etching stop layer for subsequently etching the initial sacrificial layer 203 , and the transition layer 201 is used to transfer the pattern to the substrate 200 .

[0044] The material of the stop layer 202 includes silicon oxide or silicon nitride. The material of the transition layer 201 includes titanium nitride, titanium oxide or silicon nitride.

[0045] In this embodiment, the material of the stop layer 202 includes silicon oxide; the material of the transition layer 201 includes titanium nitride.

[0046] The substrate 200 includes a base (not shown) and a device layer (not shown) located on the base, the device layer includes an isolation layer and a device structure located in the isolation layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0047] In this embodiment, the substrate is made of silicon.

[0048] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0049] Please continue to refer to Figure 3 , forming an initial sacrificial layer 203 on the layer to be etched.

[0050] The material of the initial sacrificial layer 203 has a different etching rate than the surface material of the etched layer, that is, the material of the initial sacrificial layer 203 is different from that of the stop layer 202. Therefore, when the initial sacrificial layer 203 is subsequently etched, the etching process can stop at the surface of the stop layer 202.

[0051] In this embodiment, the material of the initial sacrificial layer 203 includes a material of the fourth main group element, which includes silicon, germanium, or carbon. The initial sacrificial layer 203 of the fourth main group element material is easy to perform ion implantation to form a modified layer in the initial sacrificial layer 203.

[0052] Next, a modified layer 205 is formed in the initial sacrificial layer 203. The thickness of the modified layer 205 is smaller than that of the initial sacrificial layer 203. The modified layer 205 and the initial sacrificial layer 203 have different etching rates. Figure 4 and Figure 5 .

[0053] Please refer to Figure 4 , a first mask structure 204 is formed on the initial sacrificial layer 203 , wherein the first mask structure 204 exposes a portion of the top surface of the initial sacrificial layer 203 .

[0054] The first mask structure 204 includes a liner layer (not shown), an anti-reflection layer (not shown) on the liner layer, and a photoresist layer (not shown) on the anti-reflection layer.

[0055] The material of the liner layer includes an amorphous material, and the amorphous material includes amorphous silicon or amorphous carbon; the anti-reflection layer includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC) or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0056] In this embodiment, the material of the liner layer includes amorphous carbon; and the anti-reflection layer includes a thin silicon anti-reflection layer (Si-ARC).

[0057] Please refer to Figure 5 , ion implantation is performed on the initial sacrificial layer 203 using the first mask structure 204 as a mask to form the modified layer 205 .

[0058] The ions implanted into the initial sacrificial layer 203 include carbon ions, fluorine ions, or nitrogen ions. The carbon ions, fluorine ions, or nitrogen ions implanted into the initial sacrificial layer 203 form a modified layer 205. The modified layer 205 has a large etching selectivity with respect to the material of the initial sacrificial layer 203, thereby minimizing damage to the modified layer 205 when a portion of the initial sacrificial layer 203 is subsequently removed.

[0059] Since the thickness of the modified layer 205 is less than the thickness of the initial sacrificial layer 203, the thickness of the modified layer 205 is relatively small, so the morphology of the doped region of the modified layer 205 is controllable, and the size uniformity of the formed modified layer 205 is good. Subsequently, the first etching is used to remove part of the initial sacrificial layer 203. The first etching has a large etching selectivity ratio for the materials of the modified layer 205 and the initial sacrificial layer 203, so that the morphology of the sidewall of the formed groove is controlled by the doped region of the modified layer 205, and a groove with relatively straight and smooth sidewalls can be formed.

[0060] In this embodiment, the thickness of the modified layer 205 is one-third to two-thirds of the thickness of the initial sacrificial layer 203 .

[0061] If the thickness of the modified layer 205 is less than one-third of the thickness of the initial sacrificial layer 203, the thickness of the modified layer 205 is too thin. When the initial sacrificial layer 203 is subsequently etched using the modified layer 205 as a mask, the modified layer 205 is insufficient to serve as a mask for etching the initial sacrificial layer 203, making it difficult to control the morphology of the formed sacrificial layer; if the thickness of the modified layer 205 is greater than two-thirds of the thickness of the initial sacrificial layer 203, the thickness of the modified layer 205 is too thick. When ions are implanted to form the modified layer 205, the depth of the ion implantation is deeper, making it difficult to control the morphology of the doped region of the modified layer 205.

[0062] In this embodiment, after forming the modified layer 205 , the step further includes: removing the first mask structure 204 .

[0063] In other embodiments, the first mask structure is naturally consumed during the subsequent process of removing a portion of the initial sacrificial layer.

[0064] Please refer to Figure 6 A first etching process is used to remove a portion of the initial sacrificial layer 203 , forming a groove 206 between the modified layers 205 . The depth of the groove 206 is less than the thickness of the initial sacrificial layer 203 .

[0065] In this embodiment, the bottom of the groove 206 is flush with the bottom plane of the modified layer 205 .

[0066] In this embodiment, the first etching process includes a wet etching process, wherein the etching solution of the wet etching process includes a mixed solution of ammonia water and hydrofluoric acid.

[0067] The modified layer 205 has a different etching rate from the initial sacrificial layer 203. The first etching process includes a wet etching process, which has a larger etching selectivity ratio for the modified layer 205 and the initial sacrificial layer 203. The sidewall morphology of the formed groove 206 is controlled by the doping area of the modified layer 205. Therefore, the first etching can obtain a groove 206 with better sidewall morphology.

[0068] Please refer to Figure 7 Using the modified layer 205 as a mask, a second etching process is performed to remove the initial sacrificial layer 203 exposed at the bottom of the groove 206 , thereby forming a sacrificial layer 207 and a modified layer 205 located on the sacrificial layer 207 .

[0069] The second etching has a high directionality, so that the sidewalls of the formed sacrificial layer 207 are relatively straight and smooth, and the morphology of the sidewalls of the sacrificial layer 207 can also be controlled.

[0070] In this embodiment, the second etching process includes a dry etching process, and the etching gas of the dry etching process includes a mixture of tetrafluoromethane and chlorine.

[0071] The second etching process includes a dry etching process. The dry etching process is anisotropic, and thus can perform highly directional etching on the initial sacrificial layer 203 at the bottom of the groove 206 to obtain a sacrificial layer 207 with a better sidewall morphology.

[0072] In summary, the first etching and the second etching make the formed sacrificial layer 207 and the modified layer 205 located on the sacrificial layer 207 have good morphology and uniform size. When the graphic transfer is subsequently continued using the sacrificial layer 207 and the modified layer 205 located on the sacrificial layer 207 as masks, the size uniformity of the formed semiconductor structure is good, which is beneficial to improving the uniformity of the performance of the semiconductor structure.

[0073] Please refer to Figure 8 The stop layer 202 and the transition layer 201 are etched using the sacrificial layer 207 and the modified layer 205 located on the sacrificial layer 207 as masks to form a transition structure 208 .

[0074] The process of etching the stop layer 202 and the transition layer 201 includes a dry etching process. The dry etching process has high directionality and can obtain a transition structure 208 with good sidewall morphology and high dimensional accuracy, which is beneficial to the stability of pattern transfer.

[0075] In this embodiment, the modified layer 205 , the sacrificial layer 207 and the stop layer 202 are naturally consumed during the pattern transfer process, and there is no need to add a removal process.

[0076] The transition structure 208 continues to transfer the pattern to the substrate 200 to form a semiconductor structure. This process is a common technical means in the art and will not be described in detail here.

[0077] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 5 ,include:

[0078] layer to be etched;

[0079] an initial sacrificial layer 203 located on the layer to be etched;

[0080] The modified layer 205 is located in the initial sacrificial layer 203 . The modified layer 205 contains ions. The thickness of the modified layer 205 is smaller than that of the initial sacrificial layer 203 . The modified layer 205 and the initial sacrificial layer 203 have different etching rates.

[0081] In this embodiment, the thickness of the modified layer is one-third to two-thirds of the thickness of the initial sacrificial layer.

[0082] In this embodiment, the layer to be etched includes a substrate 200, a transition layer 201 located on the substrate 200, and a stop layer 202 located on the transition layer 201; the substrate 200 includes a base (not shown) and a device layer (not shown) located on the base, the device layer includes an isolation layer and a device structure located in the isolation layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc.

[0083] In this embodiment, the etching rates of the material of the initial sacrificial layer 203 and the surface material of the layer to be etched are different.

[0084] In this embodiment, the material of the initial sacrificial layer 203 includes a material of a fourth main group element, and the material of the fourth main group element includes silicon, germanium, or carbon.

[0085] In this embodiment, the ions in the modified layer 205 include carbon ions, fluorine ions, or nitrogen ions.

[0086] In this embodiment, the material of the transition layer 201 includes titanium nitride, titanium oxide or silicon nitride.

[0087] In this embodiment, the material of the stop layer 202 includes silicon oxide or silicon nitride.

[0088] In the semiconductor structure, the initial sacrificial layer 203 includes a modified layer 205, and the thickness of the modified layer 205 is less than that of the initial sacrificial layer 203. Since the thickness of the modified layer 205 is less than that of the initial sacrificial layer 203, a wet etching process can be subsequently used to remove a portion of the initial sacrificial layer 203 to form a groove, and then a dry etching process can be used to remove the initial sacrificial layer 203 at the bottom of the groove. The formed sacrificial layer and the modified layer located on the sacrificial layer have good morphology and uniform size. When pattern transfer is subsequently performed using the sacrificial layer and the modified layer located on the sacrificial layer as masks, the size uniformity of the formed semiconductor structure is good, which is conducive to improving the uniformity of the performance of the semiconductor structure.

[0089] Figures 9 to 14 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0090] Please refer to Figure 9 , Figure 9 For Figure 5 Based on the structural diagram, a second mask structure 304 is formed on the initial sacrificial layer 203 and the modified layer 205, and the second mask structure 304 exposes part of the surface of the initial sacrificial layer 203 and part of the surface of the modified layer 205.

[0091] The second mask structure 304 includes a liner layer (not shown), an anti-reflection layer (not shown) on the liner layer, and a photoresist layer (not shown) on the anti-reflection layer.

[0092] The material of the liner layer includes an amorphous material, and the amorphous material includes amorphous silicon or amorphous carbon; the anti-reflection layer includes a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC) or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0093] In this embodiment, the material of the liner layer includes amorphous carbon; and the anti-reflection layer includes a thin silicon anti-reflection layer (Si-ARC).

[0094] Please refer to Figure 10 , using the second mask structure 304 as a mask to etch the exposed initial sacrificial layer 203 and modified layer 205 until the surface of the layer to be etched is exposed, forming a composite structure on the layer to be etched, the composite structure including the transition sacrificial layer 306 and a portion of the modified layer 205 located in the transition sacrificial layer 306.

[0095] The process of etching the exposed initial sacrificial layer 203 and modified layer 205 includes a dry etching process. The dry etching process has high directionality and can obtain a composite structure with good sidewall morphology and high dimensional accuracy, which is beneficial to the stability of pattern transfer.

[0096] Please refer to Figure 11 After the composite structure is formed, a sidewall structure 307 is formed on the sidewall of the composite structure.

[0097] The method for forming the sidewall structure includes: forming a sidewall material layer (not shown) on the top surface and sidewall surface of the composite structure and the surface of the layer to be etched; and etching back the sidewall material layer until the top surface of the composite structure is exposed to form the sidewall structure 307 .

[0098] The material of the spacer structure 307 and the material of the transition sacrificial layer 306 have different etching rates; the material of the spacer structure 307 and the material of the modified layer 205 have different etching rates; the material of the spacer structure 307 and the material of the surface of the layer to be etched have different etching rates, that is, the material of the spacer structure 307 and the material of the stop layer 202 have different etching rates. Therefore, when the spacer material layer is etched back to form the spacer structure 307, the etch-back process causes minimal damage to the transition sacrificial layer 306, the modified layer 205, and the stop layer 202.

[0099] The material of the spacer structure 307 includes titanium oxide, silicon oxide or silicon nitride. The process of forming the spacer material layer includes atomic layer deposition process or chemical vapor deposition process.

[0100] In this embodiment, the material of the spacer structure 307 includes silicon nitride; the process of forming the spacer material layer includes an atomic layer deposition process, and the atomic layer deposition process can form a spacer material layer with a dense structure and a relatively thin thickness.

[0101] In this embodiment, before forming the spacer structure 307 on the sidewall of the composite structure, the method further includes: removing the second mask structure 304 .

[0102] In other embodiments, the second mask structure is naturally consumed during the process of forming the composite structure.

[0103] Please refer to Figure 12 A first etching step is used to remove a portion of the transition sacrificial layer 306 to form a groove 308 . Part of the groove 308 exposes the sidewall of the sidewall structure 307 . The depth of the groove 308 is lower than the thickness of the transition sacrificial layer 306 .

[0104] In this embodiment, the bottom plane of the groove 308 is flush with the top plane of the modified layer 205 .

[0105] In this embodiment, the first etching process includes a wet etching process, wherein the etching solution of the wet etching process includes a mixed solution of ammonia water and hydrofluoric acid.

[0106] The material of the transition sacrificial layer 306 has a different etching rate from the material of the modified layer 205, the material of the transition sacrificial layer 306 has a different etching rate from the side wall structure 307, and the material of the transition sacrificial layer 306 has a different etching rate from the surface of the layer to be etched. Therefore, the process of removing part of the transition sacrificial layer 306 causes less damage to the modified layer 205, the side wall structure 307 and the stop layer 202.

[0107] Please refer to Figure 13 Using the modified layer 205 as a mask, a second etching process is performed to remove the transition sacrificial layer 306 exposed at the bottom of the groove 308 to form a sacrificial layer 309 and the modified layer 205 located on the sacrificial layer 309 .

[0108] The second etching has a high directionality, so that the sidewalls of the formed sacrificial layer 309 are relatively straight and smooth, and the morphology of the sidewalls of the sacrificial layer 309 can also be controlled.

[0109] In this embodiment, the second etching process includes a dry etching process.

[0110] The second etching process includes a dry etching process. The dry etching process is anisotropic, and thus can perform highly directional etching on the transition sacrificial layer 306 at the bottom of the groove 308 to obtain a sacrificial layer 309 with a better sidewall morphology.

[0111] In summary, the first etching and the second etching make the formed sacrificial layer 309 and the modified layer 205 located on the sacrificial layer 309 have good morphology and uniform size. When the graphic transfer is subsequently continued using the sacrificial layer 309 and the modified layer 205 located on the sacrificial layer 309 as masks, the size uniformity of the formed semiconductor structure is good, which is beneficial to improving the uniformity of the performance of the semiconductor structure.

[0112] Please refer to Figure 14 After forming the sacrificial layer 309 and the modified layer 205 located on the sacrificial layer 309, the method further includes: etching the stop layer 202 and the transition layer 201 using the sidewall structure 307, the sacrificial layer 309 and the modified layer 205 located on the sacrificial layer 309 as masks to form a transition structure 310.

[0113] The process of etching the stop layer 202 and the transition layer 201 includes a dry etching process. The dry etching process has high directionality and can obtain a transition structure 310 with good sidewall morphology and high dimensional accuracy, which is beneficial to the stability of pattern transfer.

[0114] In this embodiment, the modified layer 205 , the sacrificial layer 309 and the stop layer 202 are naturally consumed during the pattern transfer process, and there is no need to add a removal process.

[0115] The transition structure 310 continues to transfer the pattern to the substrate 200 to form a semiconductor structure. This process is a common technical means in the art and will not be described in detail here.

[0116] The sacrificial layer 309, the modified layer 205 located on the sacrificial layer 309, and the sidewall structure 307 together serve as a mask pattern for subsequent pattern transfer. Because the modified layer 206 and the transition sacrificial layer 306 have different etch rates, mask patterns of varying sizes and spacings can be obtained by adjusting the dimensions of the modified layer 205 and the transition sacrificial layer 306 within the composite structure, allowing for the subsequent formation of semiconductor structures with diverse sizes. This method offers high flexibility, simple process flow, and excellent dimensional accuracy, which helps improve production efficiency and reduce production costs.

[0117] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 11 ,include:

[0118] layer to be etched;

[0119] A composite structure located on the layer to be etched, the composite structure comprising a transition sacrificial layer 306 and a modified layer 205 located within the transition sacrificial layer 306, the modified layer 205 having ions therein, the thickness of the modified layer 205 being less than the thickness of the transition sacrificial layer 306, and the etching rates of the modified layer 205 and the transition sacrificial layer 306 being different.

[0120] In this embodiment, the thickness of the modified layer 205 is one-third to two-thirds of the thickness of the transition sacrificial layer 306 .

[0121] In this embodiment, the layer to be etched includes a substrate 200, a transition layer 201 located on the substrate 200, and a stop layer 202 located on the transition layer 201; the substrate 200 includes a base (not shown) and a device layer (not shown) located on the base, the device layer includes an isolation layer and a device structure located in the isolation layer, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0122] In this embodiment, the etching rates of the material of the transition sacrificial layer 306 and the surface material of the layer to be etched are different.

[0123] In this embodiment, the material of the transition sacrificial layer 306 includes a material of the fourth main group element, and the material of the fourth main group element includes silicon, germanium or carbon.

[0124] In this embodiment, the ions in the modified layer 205 include carbon ions, fluorine ions, or nitrogen ions.

[0125] In this embodiment, it further includes: a sidewall structure 307 located on the side wall of the composite structure.

[0126] In this embodiment, the material of the sidewall structure 307 and the material of the transition sacrificial layer 306 have different etching rates; the material of the sidewall structure 307 and the material of the modified layer 205 have different etching rates; the material of the sidewall structure 307 and the material of the surface of the layer to be etched have different etching rates.

[0127] In this embodiment, the material of the spacer structure 307 includes titanium oxide, silicon oxide or silicon nitride.

[0128] In this embodiment, the material of the transition layer 201 includes titanium nitride, titanium oxide or silicon nitride.

[0129] In this embodiment, the material of the stop layer 202 includes silicon oxide or silicon nitride.

[0130] The semiconductor structure has a composite structure on the layer to be etched, and the composite structure includes a transition sacrificial layer 306 and a partially modified layer 205 located within the transition sacrificial layer 306. Since the etching rates of the modified layer 205 and the transition sacrificial layer 306 are different, the required mask patterns of different sizes and different spacings can be obtained by adjusting the sizes of the modified layer 205 and the transition sacrificial layer 306 within the composite structure, so as to subsequently form a semiconductor structure with diverse sizes.

[0131] Furthermore, the composite structure sidewalls include a sidewall structure 307. After the exposed transition sacrificial layer 306 is removed, the resulting sacrificial layer, the modified layer located thereon, and the sidewall structure together serve as a mask pattern for subsequent pattern transfer. The mask pattern is adjustable in size, offering high flexibility, a simple process, and excellent dimensional accuracy, thereby improving production efficiency and reducing production costs.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a layer to be etched; forming an initial sacrificial layer on the layer to be etched; forming a modified layer in the initial sacrificial layer, wherein the thickness of the modified layer is smaller than that of the initial sacrificial layer, and the etching rate of the modified layer is different from that of the initial sacrificial layer; Using a first etching process to remove a portion of the initial sacrificial layer to form a groove between the modified layers, wherein the depth of the groove is less than the thickness of the initial sacrificial layer; The modified layer is used as a mask and a second etching process is performed to remove the initial sacrificial layer exposed at the bottom of the groove, thereby forming a sacrificial layer and a modified layer located on the sacrificial layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the modified layer is one third to two thirds of the thickness of the initial sacrificial layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The bottom of the groove is flush with the bottom plane of the modified layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process includes a wet etching process.

5. The method for forming a semiconductor structure according to claim 1, wherein: The second etching process includes a dry etching process.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: The layer to be etched is etched using the sacrificial layer and the modified layer located on the sacrificial layer as masks.

7. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the modified layer includes: forming a first mask structure on the initial sacrificial layer, wherein the first mask structure exposes a portion of the top surface of the initial sacrificial layer; and performing ion implantation on the initial sacrificial layer using the first mask structure as a mask to form the modified layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The ions implanted into the initial sacrificial layer include carbon ions, fluorine ions or nitrogen ions.

9. The method for forming a semiconductor structure according to claim 1, wherein: After forming the modified layer and before removing part of the initial sacrificial layer, the method also includes: forming a second mask structure on the initial sacrificial layer and the modified layer, wherein the second mask structure exposes part of the surface of the initial sacrificial layer and part of the surface of the modified layer; etching the exposed initial sacrificial layer and the modified layer using the second mask structure as a mask until the surface of the layer to be etched is exposed, and forming a composite structure on the layer to be etched, wherein the composite structure includes a transition sacrificial layer and part of the modified layer located in the transition sacrificial layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: After the composite structure is formed, a sidewall structure is formed on the sidewall of the composite structure; a portion of the transition sacrificial layer is removed to form the groove, and a portion of the groove exposes the sidewall of the sidewall structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: After forming the sacrificial layer and the modified layer located on the sacrificial layer, the method further includes: etching the layer to be etched using the sidewall structure, the sacrificial layer and the modified layer located on the sacrificial layer as masks.

12. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the sidewall structure includes: forming a sidewall material layer on the top surface and sidewall surface of the composite structure and the surface of the layer to be etched; and etching back the sidewall material layer until the top surface of the composite structure is exposed to form the sidewall structure.

13. The method for forming a semiconductor structure according to claim 10, wherein: The material of the sidewall structure and the material of the transition sacrificial layer have different etching rates; the material of the sidewall structure and the material of the modified layer have different etching rates; the material of the sidewall structure and the material of the surface of the layer to be etched have different etching rates.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the sidewall structure includes titanium oxide, silicon oxide or silicon nitride.

15. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes a substrate, a transition layer located on the substrate, and a stop layer located on the transition layer; the substrate includes a base and a device layer located on the base, the device layer includes an isolation layer and a device structure located in the isolation layer, and the device structure includes a transistor, a diode, a triode, a capacitor or an inductor.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the stop layer includes silicon oxide or silicon nitride.

17. The method for forming a semiconductor structure according to claim 15, wherein: The material of the transition layer includes titanium nitride, titanium oxide or silicon nitride.

18. The method for forming a semiconductor structure according to claim 14, wherein: The material of the initial sacrificial layer and the surface material of the layer to be etched have different etching rates.

19. The method for forming a semiconductor structure according to claim 18, wherein: The material of the initial sacrificial layer includes a material of the fourth main group element, and the material of the fourth main group element includes silicon, germanium or carbon.

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