Semiconductor structure and method of making the same, three-dimensional memory, storage system

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, a three-dimensional memory, and a storage system, and relates to the technical field of semiconductor chips, and aims to solve the problems of stress unevenness and cracks caused when filling the oxide of the step part in the three-dimensional memory when the number of stacked layers of the three-dimensional memory is large. A semiconductor structure is provided, comprising a first storage stack structure and a second storage stack structure. The first storage stack structure comprises a first connecting wall and a first step part, the first connecting wall being in contact with the first step part, and the first connecting wall extending to a first core area and a second core area. The second storage stack structure comprises a second step part, the second step part comprising a first step group and a second step group, the first step group extending to the first core area and having a step surface descending in a direction close to the second core area, and the second step group extending to the second core area and having a step surface descending in a direction close to the first core area.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor structure and a manufacturing method thereof, a three-dimensional memory, and a storage system. BACKGROUND

[0002] As the feature size of the storage unit approaches the lower limit of the process, the planar process and manufacturing technology become challenging and costly, which causes the storage density of the 2D or planar NAND flash memory to approach the upper limit.

[0003] To overcome the limitations of the 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to improve the storage density by arranging the storage units three-dimensionally on the substrate.

[0004] To achieve higher storage density, the number of stacked layers in the three-dimensional memory has also increased significantly, for example, from 32 layers to 64 layers, 96 layers, 128 layers, and even to 150 layers or more. However, as the number of stacked layers in the three-dimensional memory increases, higher requirements are placed on the manufacturing process. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a three-dimensional memory, and a storage system, aiming to solve the problem of stress unevenness and cracks caused when filling the oxide of the step part in the three-dimensional memory when the number of stacked layers of the three-dimensional memory is large.

[0006] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a semiconductor structure is provided. The semiconductor structure has a first core region, a step region, and a second core region arranged in sequence. The semiconductor structure includes a first memory stack structure and a second memory stack structure. The first memory stack structure includes first dielectric layers and first conductive layers arranged in an alternating stack; a portion of the first memory stack structure located in the step region is a first connection structure; the first connection structure includes first connection walls distributed along a first direction and first step portions, the first connection walls are in contact with the first step portions, the first connection walls extend to the first core region and the second core region along a second direction; the first direction is a thickness direction of the first connection walls. The second memory stack structure is arranged at one side of the first memory stack structure. The second memory stack structure includes second dielectric layers and second conductive layers arranged in an alternating stack, a portion of the second memory stack structure located in the step region is a second connection structure; the second connection structure includes second step portions, the second step portions include a first step group and a second step group, the first step group extends to the first core region and has a step surface descending in a direction approaching the second core region, the second step group extends to the second core region and has a step surface descending in a direction approaching the first core region.

[0008] In some embodiments, along a thickness direction of the semiconductor structure, in the first step portions, a step is located at a different level than other steps.

[0009] In some embodiments, each first conductive layer extends in the first core region, the step region, and the second core region.

[0010] In some embodiments, the first step portions include a third step group and a fourth step group, along a direction of the first core region pointing to the second core region, a step surface of the third step group and a step surface of the fourth step group are arranged in sequence and are adjacent in position. The step surface of the third step group rises in a direction approaching the second core region, and the step surface of the fourth step group descends in a direction approaching the second core region.

[0011] In some embodiments, the first connection structure further includes first support walls extending along the first direction, the first support walls and the first step portions are located at the same side of the first connection walls, and the first support walls are located between the step surface of the third step group and the step surface of the fourth step group.

[0012] In some embodiments, along the thickness direction of the semiconductor structure, a step in the first step group is located at the same level as a step in the second step group.

[0013] In some embodiments, in the second storage stack structure, each second conductive layer is discontinuous in the second direction in the portion of the step region.

[0014] In some embodiments, the second connection structure further comprises a second support wall extending along the first direction; the second step portion comprises a plurality of first step groups and a plurality of second step groups, the second support wall is located between the step surfaces of two adjacent first step groups, or is located between the step surfaces of two adjacent second step groups.

[0015] In some embodiments, the second connection structure further comprises a second connection wall, the second connection wall and the second step portion are distributed along the first direction, the second connection wall is in contact with the second step portion, and the second connection wall extends to the first core region and the second core region along the second direction.

[0016] In some embodiments, the first step portion has N sub-regions along the first direction; N first layer groups continuously distributed along the thickness direction of the semiconductor structure in the first step portion have a stepped shape along the first direction; and / or, the second step portion has N sub-regions along the first direction; N second layer groups continuously distributed along the thickness direction of the semiconductor structure in the second step portion have a stepped shape along the first direction; wherein N≥2, and N is an integer; a first layer group consists of a first dielectric layer and a first conductive layer, and a second layer group consists of a second dielectric layer and a second conductive layer.

[0017] In some embodiments, the first storage stack structure further comprises a plurality of first channel structures penetrating through the first dielectric layers and the first conductive layers arranged in the alternating layer stack; the second storage stack structure further comprises a plurality of second channel structures penetrating through the second dielectric layers and the second conductive layers arranged in the alternating layer stack; a first channel structure located in the first core region is located opposite to and coupled with a second channel structure located in the first core region; a first channel structure located in the second core region is located opposite to and coupled with a second channel structure located in the second core region.

[0018] In another aspect, a three-dimensional memory is provided, comprising the semiconductor structure provided in any of the above embodiments.

[0019] In some embodiments, the three-dimensional memory further comprises a source layer and a peripheral circuit, the source layer, the semiconductor structure and the peripheral circuit are sequentially arranged along the thickness direction of the semiconductor structure and along the step rising direction of the step region of the semiconductor structure.

[0020] In yet another aspect, a storage system is provided, including a controller and a three-dimensional memory provided by any of the above embodiments. The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0021] In yet another aspect, a method for manufacturing a semiconductor structure having a first core region, a step region and a second core region sequentially arranged is provided. The method includes: manufacturing a first original memory stack structure on a substrate, the first original memory stack structure including first material layers and second material layers alternately and sequentially arranged, a portion of the first original memory stack structure located at the step region being a first original connection structure; wherein the first original connection structure includes a first original connection wall distributed along a first direction and a first original step portion, the first original step portion being in contact with the first original connection wall, the first original connection wall extending to the first core region and the second core region along a second direction, the first direction being a thickness direction of the first original connection wall; and manufacturing a second original memory stack structure on the substrate before or after the step of manufacturing the first original memory stack structure on the substrate, the second original memory stack structure including third material layers and fourth material layers alternately and sequentially arranged, a portion of the second original memory stack structure located at the step region being a second original connection structure.

[0022] In some embodiments, the step region includes a third protection region and a third etching region distributed along the first direction. The step of manufacturing the first original memory stack structure on the substrate includes: forming a first stack structure on the substrate, the first stack structure including the first material layers and the second material layers alternately and sequentially arranged. The portion of the first stack structure located at the third protection region is protected, and the portion of the first stack structure located at the third etching region is etched to form the first original step portion located at the third etching region and the first original connection wall located at the third protection region. The first original step portion includes a third original step group and a fourth original step group located at different levels, and the step surface of the third original step group and the step surface of the fourth original step group are sequentially arranged and adjacent in a direction from the first core region to the second core region. The step surface of the third original step group rises in a direction approaching the second core region, and the step surface of the fourth original step group descends in the direction approaching the second core region.

[0023] In some embodiments, etching the portion of the first stack structure located in the third etching region to form the first original step portion located in the third etching region comprises: trimming etching the portion of the first stack structure located in the third etching region to form a first preliminary step portion. The first preliminary step portion comprises: a third preliminary step group and a fourth preliminary step group located at the same level, and the step surface of the third preliminary step group and the step surface of the fourth preliminary step group are sequentially arranged and located adjacent to each other in a direction from the first core region to the second core region; the step surface of the third preliminary step group rises in a direction approaching the second core region, and the step surface of the fourth preliminary step group descends in a direction approaching the second core region. The first preliminary step portion is subjected to a preset etching to form the first original step portion.

[0024] In some embodiments, fabricating the first original storage stack structure on the substrate further comprises: after the steps of forming the first original connection wall and the first original step portion, forming a plurality of first trench structures in the portions of the first stack structure located in the first core region and the second core region.

[0025] In some embodiments, fabricating the second original storage stack structure on the substrate comprises: forming a second stack structure on the substrate, the second stack structure comprising third material layers and fourth material layers alternately stacked. Etching the second stack structure to form the second original connection structure; wherein the second original connection structure comprises a second original step portion, the second original step portion comprising a first original step group and a second original step group, the first original step group extending to the first core region and having a step surface descending in a direction approaching the second core region, and the second original step group extending to the second core region and having a step surface descending in a direction approaching the first core region.

[0026] In some embodiments, the step of forming the second original connection structure includes: protecting portions of the second stack structure located in the first protection regions and the second protection regions, and etching portions of the second stack structure located in the first etching regions, to form a plurality of first preliminary step groups located at a same horizontal level; etching portions of the second stack structure located in the second etching regions, to form a plurality of second preliminary step groups located at a same horizontal level; wherein a step surface of each first preliminary step group descends in a direction approaching the second core region, and a step surface of each second preliminary step group descends in a direction approaching the first core region. The step of forming the second original connection structure further includes: protecting the portions of the second stack structure located in the first protection regions and the second protection regions, and etching at least one first preliminary step group and at least one second preliminary step group, to form the plurality of first original step groups, the plurality of second original step groups, and a plurality of second original support walls, a second original support wall being located in a first protection region or a second protection region.

[0027] In some embodiments, the step of forming the first original memory stack structure is performed before the step of forming the second original memory stack structure; and the first original memory stack structure includes a plurality of first channel structures. The step of forming the second original memory stack structure on the substrate further includes: forming a plurality of second channel structures in portions of the second stack structure located in the first core region and the second core region, such that a second channel structure located in the first core region is directly opposite and coupled to a first channel structure located in the first core region, and a second channel structure located in the second core region is directly opposite and coupled to a first channel structure located in the second core region.

[0028] In some embodiments, the step of forming the plurality of second channel structures is performed before the step of forming the second original connection structure.

[0029] In some embodiments, the method of fabricating the semiconductor structure further includes: replacing the second material layer with a first conductive layer after the step of forming the first original memory stack structure; and replacing the fourth material layer with a second conductive layer after the step of forming the second original memory stack structure.

[0030] In some embodiments, the method of fabricating the semiconductor structure further includes removing the substrate.

[0031] In the semiconductor structure provided in the embodiments of this disclosure, the first memory stack structure and the second memory stack structure can be fabricated separately. Thus, when the number of stacked layers in the semiconductor structure is large, the semiconductor structure can be divided into a first memory stack structure and a second memory stack structure with fewer layers, which can be fabricated separately. Compared to fabricating the semiconductor structure in one step, dividing the semiconductor structure into two parts and fabricating it in two steps simplifies the fabrication process. Furthermore, when filling the step portion with oxide, the fewer stacked layers improve the stress unevenness and cracking problems caused by oxide filling.

[0032] It is understood that the three-dimensional memory and storage system provided in the above embodiments of this disclosure include the semiconductor structure. The method for fabricating the semiconductor structure provided in the above embodiments of this disclosure can be used to fabricate the semiconductor structure. The beneficial effects that can be achieved can be referred to the beneficial effects of the semiconductor structure in the above text, and will not be repeated here. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0034] Figure 1 This is a structural diagram of a three-dimensional memory according to some embodiments;

[0035] Figure 2A This is a three-dimensional structural diagram of a three-dimensional memory according to some embodiments;

[0036] Figure 2B for Figure 1 The equivalent circuit diagram of a storage cell block in the three-dimensional memory is shown.

[0037] Figure 3 This is a structural diagram of a semiconductor structure according to some embodiments;

[0038] Figure 4A This is a structural diagram of a first memory stack structure in a semiconductor structure according to some embodiments;

[0039] Figure 4B for Figure 4A A partial enlarged view of the first storage stack structure in the image;

[0040] Figure 5 for Figure 4A A structural diagram of the first connection structure of the first storage stack structure in the middle;

[0041] Figure 6 for Figure 4A structure diagram of a first connection structure of a first memory stack structure in the semiconductor structure of

[0042] Figure 7A for Figure 4A structure diagram of a multi-level step in the first memory stack structure in the semiconductor structure of

[0043] Figure 7B for Figure 4A structure diagram of a multi-level step in the second memory stack structure in the semiconductor structure of

[0044] Figure 8A structure diagram of a first conductive layer and a contact of a first memory stack structure in a semiconductor structure according to some embodiments;

[0045] Figure 8B structure diagram of a first conductive layer and a contact of a first memory stack structure in a semiconductor structure according to some embodiments;

[0046] Figure 9 structure diagram of a first conductive layer in a semiconductor structure according to some embodiments;

[0047] Figure 10A structure diagram of a second memory stack structure in a semiconductor structure according to some embodiments;

[0048] Figure 10B for Figure 10A partial enlarged view of a second memory stack structure in the semiconductor structure of

[0049] Figure 11 for Figure 10A structure diagram of a second connection structure of a second memory stack structure in the semiconductor structure of

[0050] Figure 12A for Figure 10A structure diagram of a multi-level step in the second memory stack structure in the semiconductor structure of

[0051] Figure 12B for Figure 10A structure diagram of a multi-level step in the second memory stack structure in the semiconductor structure of

[0052] Figure 13 structure diagram of a second conductive layer in a semiconductor structure according to some embodiments;

[0053] Figure 14 for Figure 3 cross-sectional view of the semiconductor structure along the cross-sectional line AA' in the semiconductor structure of

[0054] Figure 15 structure diagram of a memory system according to some embodiments;

[0055] Figure 16 Structure diagram of a memory system according to some embodiments;

[0056] Figure 17 Flow chart of a method of fabricating a semiconductor structure according to some embodiments;

[0057] Figure 18 Structure diagram of a first original memory stack structure according to some embodiments;

[0058] Figure 19 Structure diagram of a second original memory stack structure according to some embodiments; Figure 18 Partial enlarged view of the first original memory stack structure in

[0059] Figure 20 Structure diagram of a second original memory stack structure according to some embodiments;

[0060] Figure 21 Structure diagram of a second original memory stack structure according to some embodiments; Figure 19 Partial enlarged view of the second original memory stack structure in

[0061] Figure 22 Process flow chart of a method of fabricating a semiconductor structure according to some embodiments;

[0062] Figure 23 Process flow chart of a method of fabricating a semiconductor structure according to some embodiments; Figure 22 Partial enlarged view of region U3 in

[0063] Figure 24 Process flow chart of a method of fabricating a semiconductor structure according to some embodiments;

[0064] Figure 25 Process flow chart of a trimming etch process in a method of fabricating a semiconductor structure according to some embodiments;

[0065] Figure 26 Structure diagram of a mask pattern in a method of fabricating a semiconductor structure according to some embodiments;

[0066] Figure 27 Process flow chart of a method of fabricating a semiconductor structure according to some embodiments;

[0067] Figure 28 Process flow chart of a method of fabricating a semiconductor structure according to some embodiments;

[0068] Figure 29 Structure diagram of a mask pattern in a method of fabricating a semiconductor structure according to some embodiments;

[0069] Figure 30 Process flow chart of a method of fabricating a semiconductor structure according to some embodiments;

[0070] Figure 31 Process flow chart for presetting etching process in the method of manufacturing semiconductor structure according to some embodiments;

[0071] Figure 32 Structure diagram of mask pattern in the method of manufacturing semiconductor structure according to some embodiments;

[0072] Figure 33 Process flow chart for the method of manufacturing semiconductor structure according to some embodiments;

[0073] Figure 34 Process flow chart for the method of manufacturing semiconductor structure according to some embodiments;

[0074] Figure 35 Structure diagram of mask pattern in the method of manufacturing semiconductor structure according to some embodiments;

[0075] Figure 36 Process flow chart for the method of manufacturing semiconductor structure according to some embodiments;

[0076] Figure 37 Structure diagram of mask pattern in the method of manufacturing semiconductor structure according to some embodiments;

[0077] Figure 38 Process flow chart for the method of manufacturing semiconductor structure according to some embodiments;

[0078] Figure 39 Process flow chart for the method of manufacturing semiconductor structure according to some embodiments;

[0079] Figure 40 is a partial enlarged view of region U6 in Figure 39

[0080] Figure 41 Structure diagram of mask pattern in the method of manufacturing semiconductor structure according to some embodiments;

[0081] Figure 42 Structure diagram of mask pattern in the method of manufacturing semiconductor structure according to some embodiments;

[0082] Figure 43 Process flow chart for the method of manufacturing semiconductor structure according to some embodiments;

[0083] Figure 44 Process flow chart for the method of manufacturing semiconductor structure according to some embodiments;

[0084] Figure 45 Structure diagram of mask pattern in the method of manufacturing semiconductor structure according to some embodiments;

[0085] ​Figure 46 Structure diagram of a mask pattern in a method of manufacturing a semiconductor structure according to some embodiments;

[0086] Figure 47 Process flow diagram of a method of manufacturing a semiconductor structure according to some embodiments;

[0087] Figure 48 Process flow diagram of a method of manufacturing a semiconductor structure according to some embodiments;

[0088] Figure 49 Structure diagram of a mask pattern in a method of manufacturing a semiconductor structure according to some embodiments;

[0089] Figure 50 Process flow diagram of a method of manufacturing a semiconductor structure according to some embodiments;

[0090] Figure 51 Process flow diagram of a method of manufacturing a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0091] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0092] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship shown in the drawings, and are only intended to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation to the present disclosure.

[0093] Unless otherwise required by context, the term "comprises" in the specification and claims is to be construed as an open, inclusive meaning, i.e., "comprises, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", or "exemplarily" and the like are intended to indicate that the particular feature, structure, material or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0094] The terms "first", "second", etc. are used herein only to describe one feature distinguishable from another feature, and cannot be understood as indicating or implying relative importance or implying a number of the features indicated. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0095] In describing some embodiments, the expressions "coupled" and "connected" and their derivatives can be used. For example, the term "connected" can be used to describe some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term "coupled" can be used to describe some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the context.

[0096] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", both of which include the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0097] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0098] The use of "configured to" herein means open and inclusive language that does not exclude devices suitable for or configured to perform additional tasks or steps.

[0099] In addition, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0100] In the context of the present disclosure, the meanings of "on" and "over" should be interpreted in the broadest possible way, such that "on" means not only "directly on" but also includes the meaning of "on" with intermediate features or layers therebetween, and "over" means not only "above" or "over" but also includes the meaning of "above" or "over" without intermediate features or layers therebetween (i.e., directly on).

[0101] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that would be formed in a device and are not intended to limit the scope of the exemplary embodiments.

[0102] In the drawings of the present disclosure, each two of the x-axis, the y-axis, and the z-axis are perpendicular to each other, and a three-dimensional rectangular coordinate system can be formed.

[0103] As used herein, the term "substrate" refers to a material on which a subsequent layer of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0104] Some embodiments of the present disclosure provide a three-dimensional memory. Figure 1 A structural schematic diagram of a three-dimensional memory according to some embodiments, Figure 2A A perspective structural diagram of a three-dimensional memory according to some embodiments, Figure 2B An equivalent circuit diagram of a memory cell block in a three-dimensional memory according to some embodiments.

[0105] Referring to Figure 1 , Figure 2A and Figure 2B , the three-dimensional memory 10 includes a semiconductor structure 100, a peripheral circuit 200, and a source layer SL.

[0106] In some embodiments, in the three-dimensional memory 10, the source layer SL and the semiconductor structure 100 can be sequentially arranged along a thickness direction of the three-dimensional memory 10. Further, in some possible implementations, the peripheral circuit 200 can be arranged on a side of the semiconductor structure 100 away from the source layer SL, i.e., the source layer SL, the semiconductor structure 100, and the peripheral circuit 200 can be sequentially arranged along the thickness direction of the three-dimensional memory 10.

[0107] Specifically, the semiconductor structure 100 includes a plurality of memory cell blocks BLK, such as memory cell blocks BLK1 to BLKm (m is an integer greater than or equal to 2). Figure 1 Each of the plurality of memory cell blocks BLK in the three-dimensional memory 10 can be as shown inFigure 2B The storage unit block BLK includes at least one (e.g., one; or, alternatively, multiple) string of storage unit transistors (referred to herein as a "storage unit string", such as a NAND storage unit string), such as storage unit strings NS11-NS33. It is noted that, Figure 2B The number of storage unit strings in the illustrated storage unit block is merely illustrative, and embodiments of the present disclosure do not limit the number of storage unit strings in a storage unit block. Each storage unit string NS (e.g., each of the storage unit strings NS) includes a plurality of storage unit transistors MC (referred to herein as storage units MC), which can be connected in series with each other. The storage units MC can be configured to store data. In the semiconductor structure 100, the storage units MC can be distributed in an array, and thus the semiconductor structure 100 can also be referred to as an array device.

[0108] The storage unit strings NS can extend in a direction perpendicular to the source layer SL. That is, each of the storage units MC in the storage unit string NS can be distributed in a direction perpendicular to the source layer SL.

[0109] In some embodiments, the storage unit string NS can further include at least one (e.g., one; or, alternatively, multiple) string selection transistor SST and at least one (e.g., one; or, alternatively, multiple) ground selection transistor GST located on both sides of each of the storage units MC connected in series. The at least one string selection transistor SST and the at least one ground selection transistor GST can be connected in series with each of the storage units MC. Further, one pole (e.g., a drain) of the string selection transistor SST can be coupled to the bit line BL, and one pole (e.g., a source) of the ground selection transistor GST can be coupled to the source layer SL. That is, the storage unit string NS can include the at least one string selection transistor SST, the plurality of storage units MC, and the at least one ground selection transistor GST connected in series, and one pole of the string selection transistor SST is coupled to the bit line BL, and one pole of the ground selection transistor GST is coupled to the source layer SL.

[0110] In some embodiments, at least one (e.g., one; or, alternatively, multiple) dummy cell, which can be a transistor, is included between the string selection transistor SST and the topmost storage unit MC (e.g., the fourth storage unit MC4) and / or between the ground selection transistor GST and the bottommost storage unit MC (e.g., the first storage unit MC1).

[0111] In some embodiments, the channels of the transistors in a memory cell string NS can form a vertical channel structure. It can also be said that a memory cell block BLK can include at least one (e.g., one; or, for example, multiple) vertical channel structure (which can also be referred to as a channel structure herein), which can include the channels of the memory cells MC in a memory cell string NS, and also include the channels of the string selection transistor SST, the ground selection transistor GST, and the dummy cell. A memory cell block BLK (e.g., each memory cell block BLK) can also include at least one (e.g., one; or, for example, multiple) word line WL. A word line WL (e.g., each word line WL) can serve as the gate of the memory cells MC in the same logical page in the memory cell block BLK. The memory cell block BLK can also include at least one (e.g., one; or, for example, multiple) string selection line SSL, which can serve as the gate of one or more string selection transistors SST. The memory cell block BLK can also include at least one (e.g., one; or, for example, multiple) ground selection line GSL, which can serve as the gate of one or more ground selection transistors GST.

[0112] It should be noted that, in Figure 2B In a memory cell block BLK, the string selection lines SSL1 to SSL3 are separated from each other, the ground selection lines GSL are coupled to each other, and the word lines at the same level are coupled to each other. However, embodiments of the present disclosure do not particularly limit the connection relationship of the above-mentioned signal lines. For example, in some embodiments, the ground selection lines GSL can be separated from each other like the string selection lines SSL1 to SSL3.

[0113] The peripheral circuit 200 is coupled to the semiconductor structure 100 and is configured to receive signals from the outside of the three-dimensional memory 10, for example, including address signals ADDR, command signals CMD, control signals CTRL, and data signals DA, and input signals to and / or receive signals from the semiconductor structure 100 in response to the signals, so that the three-dimensional memory 10 can perform a storage operation, for example, a read operation, a program operation, and an erase operation.

[0114] In some embodiments, the peripheral circuit 200 can include a page buffer 210, a row decoder 220, and control logic 230. For example, the peripheral circuit 200 can also include various sub-circuits, for example, an input / output circuit, a voltage generation circuit for generating voltages used for operating the three-dimensional memory 10, and an error correction circuit for correcting errors in data read from the semiconductor structure 100.

[0115] Specifically, in some embodiments, the control logic 230 is coupled with the row decoder 220, and can also be coupled with the voltage generation circuit and the input / output circuit. The control logic 230 can control the operation of the three-dimensional memory 10. Illustratively, the control logic 230 can generate various internal control signals used in the three-dimensional memory 10 in response to a control signal CTRL. For example, when the three-dimensional memory 10 performs a program operation or an erase operation, the control logic 230 can adjust the voltage level provided to the word line WL and the bit line BL.

[0116] In some embodiments, the row decoder 220 selects at least one (e.g., one; or, alternatively, multiple) of the plurality of memory cell blocks BLK in response to the address signal ADDR, and selects at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell block(s) BLK. Illustratively, the row decoder 220 can be configured to send a voltage for performing a memory operation to the word line WL of the selected memory cell block BLK.

[0117] In some embodiments, the page buffer 210 can be configured as a write driver or a sense amplifier. Illustratively, in a program operation, the page buffer 210 can be configured as a write driver, through which a voltage can be applied to the bit line BL so as to store the data DA in the memory cell MC. In a read operation, the page buffer 210 can be configured as a sense amplifier, through which the data DA stored in the memory cell MC can be read out.

[0118] Some embodiments of the present disclosure also provide a semiconductor structure. The semiconductor structure can be used in the three-dimensional memory provided in any of the above embodiments. Of course, the semiconductor structure can also be applied to other three-dimensional memories, which are not limited by the present disclosure.

[0119] Figure 3 A structural diagram of the semiconductor structure according to some embodiments, Figure 3 In the structure of the step region is shown in detail, and other structures are omitted, for example, the channel structure is omitted. And, Figure 3 In the structure of the step region is shown in detail, and other structures are omitted, for example, the channel structure is omitted. And,

[0120] Referring to Figure 3The semiconductor structure 100 has a first core region C1, a step region SSA and a second core region C2 arranged in sequence. Exemplarily, the first core region C1, the step region SSA and the second core region C2 can be arranged in sequence along a direction parallel to the x-axis, and the x-axis direction can be perpendicular to the thickness direction of the semiconductor structure 100. Among the first core region C1 and the second core region C2, a plurality of channel structures of memory cell strings can be arranged. At least one string selection line, a plurality of word lines and at least one ground selection line corresponding to each memory cell string can extend into the step region SSA.

[0121] In some possible implementation manners, in the semiconductor structure 100, the part located in the step region SSA is coupled to each channel structure located in the first core region C1 and each channel structure located in the second core region C2. In this way, each channel structure in the first core region C1 and each channel structure in the second core region C2 can be controlled by the part located in the step region SSA. At this time, it can be said that the semiconductor structure 100 has a word line center-driven structure. Since the semiconductor structure 100 has the word line center-driven structure, compared with a structure in which the first core region C1 and the second core region C2 are located on the same side of the step region SSA, the length of each word line driving a channel structure in the semiconductor structure 100 can be reduced, and thus the driving time delay (RC delay) caused by the resistance-capacitance effect can be reduced.

[0122] As described above, the three-dimensional memory can include at least one memory cell block. Accordingly, the semiconductor structure 100 can include a part located in the at least one memory cell block. Exemplarily, the semiconductor structure 100 has regions B1 to B4, and each of the regions B1 to B4 can be a region corresponding to a memory cell block. In some possible implementation manners, in a direction parallel to the y-axis, the part of the semiconductor structure 100 located in the region B1 and the part located in the region B2 can be separated from each other, for example, in the direction parallel to the y-axis, a gate line slit is arranged between the part of the semiconductor structure 100 located in the region B1 and the part located in the region B2, and the part of the semiconductor structure 100 located in the region B1 and the part located in the region B2 can be separated from each other through the gate line slit. Similarly to the part of the semiconductor structure 100 located in the region B1 and the part located in the region B2, the part located in the region B2 and the part located in the region B3 can be separated from each other, and the part located in the region B3 and the part located in the region B4 can also be separated from each other.

[0123] The semiconductor structure 100 includes a first memory stack structure 110 and a second memory stack structure 120. The first memory stack structure 110 and the second memory stack structure 120 can be disposed on a substrate, which can be removed in a subsequent process of forming a three-dimensional memory from the semiconductor structure 100, and a source layer can be formed at a position corresponding to the substrate. Therefore, it can also be said that, in the three-dimensional memory, the first memory stack structure 110 and the second memory stack structure 120 can be disposed on the source layer.

[0124] The second memory stack structure 120 is disposed on one side of the first memory stack structure 110. Exemplarily, in a thickness direction (for example, parallel to the z-axis direction) of the semiconductor structure 100, the first memory stack structure 110 and the second memory stack structure 120 are sequentially distributed. It should be noted that embodiments of the present disclosure do not limit the relative positions of the first memory stack structure 110 and the second memory stack structure 120 in the semiconductor structure 100 in the direction parallel to the z-axis. Exemplarily, in the semiconductor structure 100, the first memory stack structure 110 and the second memory stack structure 120 can be sequentially distributed along the positive direction of the z-axis, or can be sequentially distributed along the negative direction of the z-axis, wherein the positive direction of the z-axis can be a direction in which the substrate or the source layer points to the semiconductor structure 100, and correspondingly, the negative direction of the z-axis can be a direction in which the semiconductor structure 100 points to the substrate or the source layer.

[0125] Figure 4A A structural view of the first memory stack structure. Figure 4B A partial enlarged view of a region U1 in the first memory stack structure in Figure 4A

[0126] Referring to Figure 4A and Figure 4B The first memory stack structure 110 includes first dielectric layers 111 and first conductive layers 112 which are alternately stacked. Specifically, in the thickness direction of the semiconductor structure, the first dielectric layers 111 and the first conductive layers 112 are stacked. It can also be said that, in the thickness direction (for example, parallel to the z-axis direction) of the first memory stack structure 110, the first dielectric layers 111 and the first conductive layers 112 are stacked. Moreover, the first dielectric layers 111 and the first conductive layers 112 are alternately arranged, that is, one first dielectric layer 111 can be disposed between every two first conductive layers 112, or it can also be said that the plurality of first conductive layers 112 are separated from each other by the plurality of first dielectric layers 111.

[0127] The first conductive layer 112 can be configured as a word line or a string selection line or a ground selection line of at least one memory cell string.

[0128] ​The material of the first dielectric layer 111 can be an insulating material, for example, silicon oxide or silicon nitride. The material of the first conductive layer 112 can be a conductive material, for example, a metal such as tungsten, aluminum, copper or gold, a combination of one or more of doped silicon, metal nitride and metal silicide.

[0129] Since the semiconductor structure has the first core region C1, the step region SSA and the second core region C2 arranged in sequence along the x-axis direction, and the first memory stack structure and the second memory stack structure can be arranged in sequence along the z-axis direction. Therefore, the first memory stack structure 110 can also include portions located in the first core region C1, the step region SSA and the second core region C2 accordingly. And since the semiconductor structure can include portions located in at least one memory cell block, the first memory stack structure 110 can also include portions located in at least one memory cell block accordingly. Exemplarily, the first memory stack structure 110 can have regions B11-B14, each of which can correspond to a memory cell block.

[0130] The portion of the first memory stack structure 110 located in the step region SSA is a first connection structure LP1. Figure 5 The structure of the first connection structure in Figure 6 The structure of the portion of the first connection structure in a memory cell block (for example, the portion located in region B11) is shown. Figure 5 The structure of the portion of the first connection structure in a memory cell block (for example, the portion located in region B11) is shown.

[0131] Referring to Figure 5 and Figure 6 , the first connection structure LP1 includes a first connection wall XW1 and a first step portion SP1 distributed along a first direction. The first connection wall XW1 and the first step portion SP1 can be located in a memory cell block. Wherein, the first direction is the thickness direction of the first connection wall XW1, for example, the direction parallel to the y-axis. And the first connection wall XW1 is in contact with the first step portion SP1. Exemplarily, one side SP1' of the first step portion SP1 along the first direction can be in contact with one side XW1' of the first connection wall XW1 along the first direction.

[0132] Figure 7A and Figure 7B is a partial enlarged view of a step group in Figure 4A , showing the structure of the multi-level steps of a step group in the first memory stack structure. For the convenience of explanation, the structure of each level of steps in the step group of the first memory stack structure is described with Figure 7A as an example. Understandably, Figure 7B the structure of each level of steps in Figure 7A can also refer to the related description of each level of steps in

[0133] Referring to Figure 4A and Figure 7A The first step portion SP1 can include a plurality of step groups SG. A step group SG can include a plurality of steps S.

[0134] First of all, it should be noted that, in this article, A and B are at the same level can mean that, taking a point in the semiconductor structure (for example, the center of the semiconductor structure) as the origin, taking the direction in which the substrate points to the semiconductor structure or the source layer points to the semiconductor structure as the positive direction of the z-axis, the coordinates of the center of A and the center of B along the z-axis direction relative to the origin are equal to each other. Similarly, A is at a higher level than B can mean that, taking a point in the semiconductor structure (for example, the center of the semiconductor structure) as the origin, taking the direction in which the substrate points to the semiconductor structure or the source layer points to the semiconductor structure as the positive direction of the z-axis, the coordinate of the center of A along the z-axis direction relative to the origin is greater than the coordinate of the center of B along the z-axis direction. A is at a lower level than B can mean that, taking a point in the semiconductor structure (for example, the center of the semiconductor structure) as the origin, taking the direction in which the substrate points to the semiconductor structure or the source layer points to the semiconductor structure as the positive direction of the z-axis, the coordinate of the center of A along the z-axis direction relative to the origin is less than the coordinate of the center of B along the z-axis direction.

[0135] In addition, it should be noted that, in this article, a step group SG can include a plurality of steps S, and a step S can be formed by one stack group or by a plurality of stack groups. Among them, the stack group can be a first stack group LTa or a second stack group, and each first stack group LTa consists of a first conductive layer 112 and a first dielectric layer 111 (the structure of the second stack group will be described in detail below).

[0136] In a step group SG, each step S extends laterally (for example, along the x-axis direction) farther than any step S located at a higher level than it, or in other words, each step S laterally protrudes farther than any step S located at a higher level than it, so that the shape of the horizontal cross section (for example, the cross section in the xy plane) of the step group SG changes in the step group SG according to the vertical distance from the top surface of the substrate or the source layer (i.e., the side surface located at a higher level among the two side surfaces opposite along the z-axis direction).

[0137] Based on the above, each level step S in a step group SG can form a step surface SGP. Specifically, a level step S can include at least one horizontal surface LP and at least one vertical surface VP. Wherein the horizontal surface LP can be a surface extending along the xy plane (a plane determined by the x-axis and the y-axis), and the vertical surface VP can be a surface extending along the yz plane (a plane determined by the y-axis and the z-axis) or along the xz plane (a plane determined by the x-axis and the z-axis). Two horizontal surfaces LP located at different levels can be connected together by one or more vertical surfaces, so that each horizontal surface LP and vertical surface VP of each level step S in a step group SG can form a step surface SGP.

[0138] When a step group SG has the above structure, it can also be said that the plurality of layer groups (for example, the first layer group LTa) forming the step group SG have a stepped shape in the second direction.

[0139] Based on the above, in some embodiments, in a step group SG of the first step portion SP1, a level step S is formed by a first layer group LTa. At this time, for each first conductive layer 112 in the step group SG, each first conductive layer 112 can protrude laterally (for example, along the x-axis direction) than any first conductive layer 112 located at a higher level thereof. The portion of a first conductive layer in a step group that protrudes in the x-axis direction can be referred to as a first protruding portion. Based on the above, referring to Figure 8A , the semiconductor structure can further include a plurality of contacts K extending along the thickness direction of the semiconductor structure (for example, parallel to the z-axis direction). A contact K (for example, each contact K) can be configured to transmit an electrical signal to a first conductive layer 112, for example, a contact K can be in contact with a first protruding portion 112-A of a first conductive layer 112, thereby enabling transmission of an electrical signal to a first conductive layer 112 through a contact K. Further, electrical signals can be transmitted to a plurality of first conductive layers 112 through a plurality of contacts K.

[0140] Continuing to refer to Figure 4A , Figure 7A and Figure 8BIn some embodiments, the first step portion SP1 has N (N≥2 and N is an integer) sub-zones DZ in the first direction (e.g., parallel to the y-axis direction). The N sub-zones DZ are arranged in the first direction in a step shape. In other words, the N sub-zones DZ are arranged in the first direction in a step shape. In other embodiments, in a step group SG of the first step portion SP1, a first step S is formed by N (N≥2 and N is an integer) first layer groups LTa. At this time, the first step portion SP1 can have N sub-zones DP in the first direction (e.g., parallel to the y-axis direction). Also, the N first layer groups LTa in the first step S have a step shape in the first direction, and it can also be said that the N first layer groups LTa continuously distributed in the thickness direction of the semiconductor structure (e.g., parallel to the z-axis direction) in the first step portion SP1 have a step shape in the first direction. Referring to the above description, since the N first layer groups LTa have a step shape in the first direction, for each first conductive layer 112 in the N first layer groups LTa, each first conductive layer 112 protrudes laterally (e.g., in the y-axis direction) than any first conductive layer 112 located at a higher level. The portion of a first conductive layer 112 in the first step S that protrudes in the y-axis direction can be referred to as a second protruding portion 112-B. Similarly, an electrical signal can be transmitted to a first conductive layer 112 in the first step S by a contact K, for example, a contact K can be in contact with the second protruding portion 112-B of a first conductive layer 112, and thus an electrical signal can be transmitted to a first conductive layer 112 by a contact K. Further, electrical signals can be transmitted to multiple first conductive layers 112 by multiple contacts K.

[0141] Referring to Figure 6 , Figure 7A and Figure 8A In some embodiments, when the first step portion SP1 has N sub-zones DP in the first direction (e.g., parallel to the y-axis direction), the first step S can include N horizontal surfaces LP arranged in the first direction (e.g., parallel to the y-axis direction) in sequence, and the z-axis coordinates of the N horizontal surfaces LP gradually decrease in the direction (e.g., the positive direction of the y-axis) pointing to the first step portion SP1 along the first connection wall XW1, that is, in any two of the N horizontal surfaces, the horizontal surface closer to the first connection wall XW1 is located at a higher level than the other horizontal surface.

[0142] When the first stepped portion SP1 has no sub-region DP in the first direction, in the second direction (e.g., parallel to the x-axis direction), the N first-tier groups LTa need to form N steps, i.e., each of the first conductive layers 112 in the N first-tier groups LTa needs to protrude in the second direction than other first conductive layers 112 located at a higher level, so as to realize the contact between each of the first conductive layers 112 in the N first-tier groups LTa and the contact K. When the first stepped portion SP1 has N sub-regions DP in the first direction, in the second direction, the N first-tier groups LTa can form one step. Since the N first-tier groups LTa can form a stepped shape in the first direction, the contact between each of the first conductive layers in the N first-tier groups LTa and the contact K can be realized. It can be understood that the size of the one-step S in the second direction can be smaller than the size of the N-step in the second direction. Therefore, when the first stepped portion SP1 has N sub-regions in the first direction, the size of the semiconductor structure in the second direction can be smaller, thereby reducing the size of the three-dimensional memory.

[0143] Continuing to refer to Figure 4A and Figure 6 , the first connection wall XW1 extends to the first core region C1 and the second core region C2 in the second direction. It can be understood that the second direction is the extension direction of the first connection wall XW1, e.g., the direction parallel to the x-axis.

[0144] Since the first connection wall XW1 is in contact with the first stepped portion SP1, and the first connection wall XW1 extends to the first core region C1 and the second core region C2 in the second direction, the first stepped portion SP1 can be coupled to the part of the first storage stack structure 110 located in the first core region C1 and the part located in the second core region C2 through the first connection wall XW1. In this way, the transmission of electrical signals between the first stepped portion SP1 and the channel structure located in the first core region C1 and the second core region C2 can be realized, so that the three-dimensional memory can perform a storage operation.

[0145] Further, referring to Figure 9 , Figure 9 is Figure 4A a structural view of the part of the first conductive layer of the first storage stack structure in a memory cell block, e.g., a structural view of the part of the first conductive layer located in the region B11. It should be noted that Figure 9 omits the specific structure of the corresponding part of the channel structure in the first conductive layer, e.g., omits the channel hole in the channel structure located in the first conductive layer.

[0146] In some embodiments, each first conductive layer 112 extends in the first core region C1, the step region SSA, and the second core region C2. Exemplarily, in a memory cell block, the first conductive layer 112 can include a first continuous pattern 112a located in the first core region C1, a second continuous pattern 112b located in the step region SSA, and a third continuous pattern 112c located in the second core region C2. The first conductive layer 112 extending in the first core region C1, the step region SSA, and the second core region C2 can mean that the first continuous pattern 112a, the second continuous pattern 112b, and the third continuous pattern 112c are located at the same level, and the second continuous pattern 112b is in contact with the first continuous pattern 112a and the third continuous pattern 112c. In some possible implementations, the first continuous pattern 112a, the second continuous pattern 112b, and the third continuous pattern 112c of the first conductive layer form an integral pattern (i.e., a pattern with a closed outer contour).

[0147] Since each first conductive layer 112 extends in the first core region C1, the step region SSA, and the second core region C2, when an electrical signal is written into the first part Q1 in the first step portion SP1 in the second continuous pattern 112b, for example, the electrical signal is written into the second protruding portion 112-B in the first part Q1, the electrical signal can be transmitted to the first continuous pattern 112a and the third continuous pattern 112c through the second part Q2 in the second connecting wall XW1 in the second continuous pattern 112b, thereby the channel structure located in the first core region C1 and the channel structure located in the second core region C2 can be controlled.

[0148] Figure 10A FIG. 4 is a structural diagram of a second memory stack structure, Figure 10B FIG. 5 is a structural diagram of a third memory stack structure, Figure 10A FIG. 6 is a partial enlarged view of a middle region U2 of the third memory stack structure.

[0149] Referring to Figure 10A and Figure 10B The second memory stack structure 120 includes second dielectric layers 121 and second conductive layers 122 arranged in an alternating stack. The positional relationship and materials of the second dielectric layers 121 and the second conductive layers 122 can refer to the description of the first dielectric layers and the first conductive patterns above, and will not be described here again. It should be noted that the material of the second dielectric layers 121 can be the same as or different from the first dielectric layers, and the material of the second conductive layers 122 can also be the same as or different from the first conductive layers, and the embodiments of the present disclosure do not limit this.

[0150] The second conductive layer 122 can be configured as a word line or a string selection line or a ground selection line of at least one (for example, one; or for example, multiple) memory cell string.

[0151] Similarly to the first memory stack structure, since the semiconductor structure has the first core region C1, the step region SSA and the second core region C2 arranged in sequence along the x-axis direction, and the first memory stack structure and the second memory stack structure are arranged in sequence along the z-axis direction, the second memory stack structure can also include portions located in the first core region C1, the step region SSA and the second core region C2 accordingly. And since the semiconductor structure can include portions located in at least one memory cell block, the second memory stack structure 120 can also include portions located in at least one memory cell block. Exemplarily, the second memory stack structure 120 can have regions B21-B24, each of which can correspond to a memory cell block.

[0152] The portion of the second memory stack structure 120 located in the step region SSA is a second connection structure LP2. Figure 11 A structural diagram of the second connection structure. Referring to Figure 11 , the second connection structure LP2 includes a second step portion SP2. The second step portion SP2 can be located in a memory cell block, and exemplarily, the second step portion SP2 can be located in the region B21.

[0153] The second step portion SP2 can include a plurality of step groups SG. Figure 12A and Figure 12B A partial enlarged view of a step group in the second memory stack structure, showing the structure of the multiple levels of steps in a step group in the second memory stack structure. For the convenience of description, the structure of the multiple levels of steps in a step group in the second memory stack structure will be described by taking Figure 12A For example, the structure of the multiple levels of steps in a step group in the second memory stack structure will be described, and it can be understood that Figure 12B the structure of the multiple levels of steps in a step group in the second memory stack structure can also refer to the description of the multiple levels of steps in a step group in the first memory stack structure. Figure 12A

[0154] Referring to Figure 11 and Figure 12A , in the second step portion SP2, a step group SG can include multiple levels of steps S. The structure of a level of steps S in the second step portion SP2 can refer to the structure of a level of steps in the first step portion, which will not be described here. It should be noted that in the second step portion SP2, one or more layer groups that make up a level (e.g. each level) of steps S are second layer groups LTb. A second layer group LTb (e.g. each second layer group LTb) can be composed of a second conductive layer 122 and a second dielectric layer 121.

[0155] ​Further, in some embodiments, similarly to the first stepped portion, the second stepped portion SP2 can have N partitions along the first direction. At this time, the N second layer groups LTb continuously distributed along the thickness direction of the semiconductor structure in the second stepped portion SP2 have a staircase shape in the first direction. The description of the partitions of the second stepped portion SP2 can refer to the description of the partitions of the first stepped portion SP1 above, and will not be repeated here. Exemplarily, as shown in Figure 12A , the second stepped portion SP2 can have three partitions DP along the first direction, for example, partitions DP1-DP3.

[0156] Similarly, in the second stepped portion SP2, a stepped group SG can include a stepped surface SGP. The description of the stepped surface of a stepped group in the second stepped portion can refer to the description of the stepped surface of a stepped group in the first stepped portion above, and will not be repeated here.

[0157] Specifically, referring to Figure 10A and Figure 11 , the second stepped portion SP2 can include one or more first stepped groups SG1 and one or more second stepped groups SG2.

[0158] The first stepped group SG1 extends to the first core region C1, and therefore, the first stepped group SG1 can be coupled with the part of the second storage stack structure located in the first core region C1, for example, the first stepped group SG1 can be coupled with at least one (for example, one; or, for example, multiple) channel structure located in the first core region C1.

[0159] Further, referring to Figure 11 and Figure 12B , the first stepped group SG1 has a stepped surface SGP that descends in the direction (for example, the positive direction of the x-axis) approaching the second core region C2. Exemplarily, the shape of the stepped surface SGP of the first stepped group SG1 can refer to the shape of the stepped surface SGP formed by each level of the stepped group in Figure 12B . The stepped surface SGP of the first stepped group SG1 descending in the direction (for example, along the positive direction of the x-axis) approaching the second core region C2 can mean that, in the first stepped group SG1, the horizontal surface LP of each level of the stepped S is closer to the second core region C2 than the horizontal surface LP of any level of the stepped S located at a higher level thereof.

[0160] Continuing to refer to Figure 10A and Figure 11 , the second stepped group SG2 extends to the second core region C2, and therefore, the second stepped group SG2 can be coupled with the part of the second storage stack structure located in the second core region C2, for example, the second stepped group SG2 can be coupled with at least one (for example, one; or, for example, multiple) channel structure located in the second core region C2.

[0161] And, referring to Figure 11 and Figure 12A , the second step group SG2 has step faces SGP descending in a direction approaching the first core region C1 (e.g. the negative direction of the x-axis). Exemplarily, the shape of the step faces SGP of the second step group SG2 can refer to the shape of the step faces SGP formed by the steps in Figure 12A . The step faces SGP of the second step group SG2 descending in a direction approaching the first core region C1 (e.g. along the negative direction of the x-axis) can mean that, in the second step group SG2, the horizontal surface LP of each step S is closer to the first core region C1 than the horizontal surface LP of any step S located at a higher level thereof.

[0162] When the number of stacked layers of the three-dimensional memory is large, in the formation of the step structure (e.g. including the first step portion and the second step portion), due to the limitation of the photoresist development process, the problem of exposure of the word line located at a lower level can be caused, leading to unstable electrical connection of the step structure. In addition, after the formation of the step structure, the filling of the oxide is required to cover and protect the step portion. When the number of stacked layers of the three-dimensional memory is large, the amount of the filled oxide also increases accordingly, which can cause problems such as stress unevenness and cracking. In the semiconductor structure provided in the embodiments of the present disclosure, the first storage stack structure and the second storage stack structure can be respectively fabricated. In this way, when the number of stacked layers of the semiconductor structure is large, the semiconductor structure can be divided into the first storage stack structure and the second storage stack structure with a smaller number of stacked layers for respective fabrication. Compared with one-step fabrication of the semiconductor structure, the division of the semiconductor structure into two parts and the two-step respective fabrication can simplify the fabrication process, and, in the filling of the oxide for the step portion, due to the smaller number of stacked layers, the above-mentioned problems caused by the filling of the oxide can be improved, thereby improving the stability of the semiconductor structure and the product yield.

[0163] Referring to Figure 6 , in some embodiments, in the first storage stack structure, along the thickness direction of the semiconductor structure, one step (i.e. a first step) in the first step portion SP1 is located at a different level than other steps. Exemplarily, one step (i.e. a first step) in the first step portion SP1 is located at a different level than other steps. Exemplarily, each step in the first step portion SP1 is located at a different level than other steps.

[0164] In some possible implementations, due to the fact that one step (i.e. a first step) in the first step portion SP1 is located at a different level than other steps, at least two step groups SG in the first step portion SP1 can be located at different levels. Exemplarily, each step group SG in the first step portion SP1 is located at a different level.

[0165] In the first storage stack structure, since the steps in the first step portion SP1 (i.e., one level of steps) are located at different levels from the other steps, and the first step portion SP1 includes the first connection wall XW1, when an electrical signal is written to one of the first conductive layers in the one level of steps, the electrical signal can be transmitted to both the first core region C1 and the second core region C2 through the first connection wall XW1 to achieve center driving of the word line. Compared to the structure in which two ends of the first step portion are respectively provided with steps to respectively control the first core region C1 and the second core region C2, the structure of the first step portion provided in the embodiments of the present disclosure can have a smaller size along the second direction (e.g., parallel to the x-axis direction), and can reduce the volume of the three-dimensional memory.

[0166] Continuing to refer to Figure 6 In some embodiments, the first step portion SP1 includes a third step group SG3 and a fourth step group SG4, and the step faces SGP of the third step group SG3 and the step faces SGP of the fourth step group SG4 are sequentially arranged and located adjacent to each other in a direction (e.g., the positive direction of the x-axis) along which the first core region C1 points to the second core region C2. It should be noted that, in this context, two step faces being located adjacent to each other in a certain direction can mean that there is no other step face between the two step faces in the direction.

[0167] Further, the step faces SGP of the third step group SG3 rise in a direction (e.g., the positive direction of the x-axis) approaching the second core region C2, and the step faces SGP of the fourth step group SG4 fall in the direction approaching the second core region C2. For example, the shape of the step faces SGP of the third step group SG3 can refer to the shape of the step faces SGP formed by the steps in the third step group SG3 in the first storage stack structure 1000 in Figure 7A , and the shape of the step faces SGP of the fourth step group SG4 can refer to the shape of the step faces SGP formed by the steps in the fourth step group SG4 in the first storage stack structure 1000 in Figure 7B .

[0168] For example, the step faces SGP of the third step group SG3 rising in the direction approaching the second core region C2 can mean that, in the third step group SG3, the horizontal surface LP of each step S is closer to the second core region C2 than the horizontal surface LP of any step S located at a lower level thereof. The description of the step faces SGP of the fourth step group SG4 falling in the direction approaching the second core region C2 can refer to the description of the step faces of the first step group falling in the direction approaching the second core region C2 in the foregoing, and will not be repeated here. Figure 6 Figure 7A

[0169] ​​In addition, in some possible implementation manners, referring to the above description, since one step in the first step portion SP1 is located at a different level from other steps, the third step group SG3 and the fourth step group SG4 can be located at different levels.

[0170] Since the third step group SG3 and the fourth step group SG4 have the above structure, the stress of the first step portion SP1 can be more uniform, which is beneficial to improving the structural stability of the three-dimensional memory. In addition, the third step group SG3 and the fourth step group SG4 can be formed simultaneously by one mask pattern in one etching process (for example, one trimming etching process), so that the manufacturing process of the three-dimensional memory can be simplified.

[0171] Referring to Figure 11 In some embodiments, in the second memory stack structure, one step (for example, each step) in the first step group SG1 is located at the same level as one step in the second step group SG2. In this way, one step in the first step group SG1 located at a level can be coupled with one step in the second step group SG2 located at the same level to achieve word line center driving. In some possible implementation manners, each step in the first step group SG1 is located at the same level as one step in the second step group SG2. At this time, the first step group SG1 and the second step group SG2 can be located at the same level.

[0172] In some possible implementation manners, the second connection structure LP2 can further include a second connection wall. The structure of the second connection wall can be similar to that of the first connection wall in the first connection structure. Specifically, the second connection wall can be distributed along the first direction with the second step portion SP2, the second connection wall can be in contact with the second step portion SP2, and the second connection wall extends to the first core area C1 and the second core area C2 along the second direction. For the description of the second connection wall, refer to the description of the first connection wall above, which is not repeated here. The first step group SG1 and the second step group SG2 can be coupled by the second connection wall, and word line center driving can be achieved.

[0173] Continuing to refer to Figure 11In some possible implementations, a horizontal surface at a level in the first set of steps SG1 can be coupled with a horizontal surface at the same level in the second set of steps SG2 by a metal connection line Met, so as to realize the coupling of a step at a level in the first set of steps SG1 with a step at the same level in the second set of steps SG2. In this way, the word line center driving structure for simultaneously controlling the first core area C1 and the second core area C2 can be realized without the second connection wall. Since there is no second connection wall, the process of filling the oxide to cover the second step part after the second step part is manufactured is simpler, and the problems of stress unevenness and cracks caused by the connection wall can be reduced.

[0174] Further, Figure 13 The structure of the second conductive layer is shown. Referring to Figure 13 In some embodiments, in the second storage stack structure, the second conductive layer 122 located in the part of the step area SSA is disconnected in the second direction, where the second direction is the direction in which the first connection wall extends, for example, the x-axis direction. Since the second conductive layer 122 located in the part of the step area SSA is disconnected in the second direction in the second storage stack structure, the first set of steps SG1 and the second set of steps SG2 can be separated from each other. In this way, when the first storage stack layer and the second storage stack layer are sequentially arranged along the positive direction of the z-axis, the step surfaces of the first connection structure in the first storage stack structure at a lower level can be exposed, so that the first conductive layers of the first connection structure are coupled with the peripheral circuit.

[0175] Continuing to refer to Figure 11 In some embodiments, the second step part SP2 includes a plurality of first sets of steps SG1 and a plurality of second sets of steps SG2, and the second connection structure LP2 can further include a second support wall YW2 extending in the first direction. A second support wall YW2 can be located in one memory cell block. Specifically, a second support wall YW2 (for example, each second support wall YW2) is located between the step surfaces SGP of the adjacent two first sets of steps SG1, or is located between the step surfaces SGP of the adjacent two second sets of steps SG2.

[0176] It should be noted that in this paper, the adjacent two sets of steps can mean that the two sets of steps are adjacent in the thickness direction of the semiconductor structure (for example, parallel to the z-axis direction), or it can be said that there is no other set of steps between the two sets of steps in the thickness direction of the semiconductor structure.

[0177] Based on the above, the following will be described in detail that “a second support wall YW2 is located between the step surfaces SGP of the adjacent two first step groups SG1 respectively”. It can be understood that “a second support wall YW2 is located between the step surfaces SGP of the adjacent two second step groups SG2 respectively” can also be referred to the following description.

[0178] Continuing to refer to Figure 11 In the second connection structure LP2, the adjacent two first step groups SG1 can include a first step group SG1 located at a higher level (hereinafter referred to as a higher level first step group) and a first step group SG1 located at a lower level (hereinafter referred to as a lower level first step group). The step surfaces SGP of the higher level first step group and the step surfaces SGP of the lower level first step group can be distributed at different levels along the second direction (for example, the direction parallel to the x-axis). The second support wall YW2 can be located between the above two step surfaces SGP, that is, in the second direction, the step surface SGP of the higher level first step group, the second support wall YW2 and the step surface SGP of the lower level first step group can be sequentially arranged. And the second support wall YW2 can be located above the lower level first step group, that is, the second support wall YW2 can be located on the side of the lower level first step group close to the higher level first step group, that is, on the side of the lower level first step group along the positive direction of the z-axis.

[0179] Embodiments of the present disclosure do not limit the height (for example, the size of the second support wall along the z-axis direction) of the second support wall YW2, and the height of the second support wall YW2 can be set according to actual needs. Exemplarily, the second support wall YW2 can be flush with the part of the second storage stack structure located in the first core area C1 or the part located in the second core area C2. Exemplarily, the top surface of the second support wall YW2 (that is, one of the two opposite surfaces of the second support wall YW2 along the z-axis direction located at a higher level) can be located at a higher level or a lower level compared to the top surface of the part of the second storage stack structure located in the first core area C1 or the part located in the second core area C2 (that is, one of the two opposite surfaces of the part of the second storage stack structure located in the first core area C1 or the part located in the second core area C2 along the z-axis direction located at a higher level).

[0180] The second support wall YW2 can play a supporting role and can improve the structural stability of the second storage stack structure. In addition, when the top of the second storage stack structure (that is, one end along the positive direction of the z-axis) is subjected to, for example, a chemical mechanical polishing process (CMP) to planarize the top of the second storage stack structure, the second support wall YW2 can act as a stop layer in the chemical mechanical polishing process, so that the chemical mechanical polishing process stops in time.

[0181] Similarly, in some embodiments, the first connection structure in the first storage stack structure can also include a first support wall, the first support wall and the first step portion are located at the same side (e.g., the same side in the first direction) of the first connection wall. In addition, the first support wall can be located between the step surface of the third step group and the step surface of the fourth step group. The description about the first support wall can refer to the description about the second support wall above, which will not be repeated here. The beneficial effects that the first support wall can achieve are similar to those of the second support wall, and the description about the beneficial effects that the second support wall can achieve above will not be repeated here.

[0182] In some embodiments, referring to Figure 3 , the first storage stack structure 110 and the second storage stack structure 120 are sequentially arranged along the positive direction of the z-axis. At this time, the first storage stack structure 110 can also include a bottom select gate structure BSG. Specifically, the bottom select gate structure BSG can be located in the first connection structure. Illustratively, the bottom select gate structure BSG can include at least one first stack group, which can have a stepped shape in the second direction. For example, the bottom select gate structure BSG can include two step groups located at the same level.

[0183] One or more first conductive layers in the bottom select gate structure BSG can serve as ground select lines.

[0184] Correspondingly, the second storage stack structure 120 can also include a top select gate structure TSG. The top select gate structure TSG can be located in the second connection structure. Illustratively, the top select gate structure TSG can include at least one second stack group, which can have a stepped shape in the second direction. For example, the top select gate structure TSG can include two step groups located at the same level.

[0185] One or more second conductive layers in the top select gate structure TSG can serve as string select lines.

[0186] Figure 14 For Figure 3 , a cross-sectional view of the semiconductor structure along the cross-sectional line AA'. Referring to Figure 14 , the channel structure in the semiconductor structure will be described below taking the channel structure located in the second core region as an example. It can be understood that the channel structure located in the first core region can refer to the description of the channel structure located in the second core region below, which will not be repeated here.

[0187] In some embodiments, the first memory stack structure 110 further comprises a plurality of first channel structures CH1 penetrating through the first dielectric layers 111 and the first conductive layers 112 arranged in an alternating stack. The plurality of first channel structures CH1 can be located in the first core region and the second core region C2. The first channel structure CH1 can serve as a part of a channel of a memory cell string in the semiconductor structure. The second memory stack structure 120 further comprises a plurality of second channel structures CH2 penetrating through the second dielectric layers 121 and the second conductive layers 122 arranged in an alternating stack. The plurality of second channel structures CH2 can be located in the first core region and the second core region C2. The second channel structure CH2 can also serve as a part of a channel of a memory cell string in the semiconductor structure.

[0188] Further, a first channel structure CH1 (e.g. each first channel structure CH1) located in the second core region C2 is located opposite to and coupled with a second channel structure CH2 located in the second core region C2.

[0189] Wherein, the first channel structure CH1 being located opposite to the second channel structure CH2 can mean that, in a direction parallel to the z-axis, at least a part (e.g. a part; or, for example, the whole) of the orthogonal projection of the first channel structure CH1 on the substrate or the source layer overlaps with the orthogonal projection of the second channel structure CH2 on the substrate or the source layer.

[0190] In some possible implementations, the first channel structure CH1 comprises a semiconductor layer, and the second channel structure CH2 can also comprise a semiconductor layer. The material of the semiconductor layer is, for example, silicon. The semiconductor layer in the first channel structure CH1 can be in contact with the semiconductor layer in the second channel structure CH2 to realize the coupling between the first channel structure CH1 and the second channel structure CH2.

[0191] Similarly, a first channel structure CH1 (e.g. each first channel structure CH1) located in the first core region is located opposite to and coupled with a second channel structure CH2 located in the first core region.

[0192] Since the first channel structure located in the first core region is located opposite to and coupled with the second channel structure located in the first core region, and the first channel structure located in the second core region is located opposite to and coupled with the second channel structure located in the second core region, the first channel structure and the second channel structure can extend along the z-axis direction as a whole. And the first channel structure and the second channel structure can form a channel of a memory cell string.

[0193] In some embodiments, based on the above description, in the three-dimensional memory, the peripheral circuit can be located in the step-up direction of the steps in the stepped region of the semiconductor structure. It should be noted that in this paper, the step-up direction can mean that in this direction, the size of each step in the vertical direction gradually decreases. In some possible implementations, in the three-dimensional memory provided by the embodiments of the present disclosure, the step-up directions of the steps in each step group in the stepped region of the semiconductor structure are the same. In this way, each first conductive layer or second conductive layer laterally protruding in each step can be coupled to the peripheral circuit through the contact extending in the step-up direction, which can reduce the size of the three-dimensional memory. At this time, in the three-dimensional memory, the source layer, the semiconductor structure and the peripheral circuit can be sequentially arranged along the step-up direction in the semiconductor structure.

[0194] Some embodiments of the present disclosure also provide a storage system. Figure 15 A block diagram of a storage system according to some embodiments. Figure 16 A block diagram of a storage system according to some other embodiments. Referring to Figure 15 and Figure 16 The storage system 1 includes a three-dimensional memory 10 and a controller 20. The three-dimensional memory 10 can be any of the three-dimensional memories provided by the above embodiments. The controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0195] The storage system 1 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1 can be applied to and packaged into different types of electronic products, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device with a storage.

[0196] In some embodiments, referring to Figure 15 The storage system 1 includes a controller 20 and one three-dimensional memory 10, and the storage system 1 can be integrated into a memory card.

[0197] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), compact flash (Compact Flash, CF for short) card, smart media (Smart Media, SM for short) card, memory stick, multimedia card (Multimedia Card, MMC for short), secure digital memory card (Secure Digital Memory Card, SD for short), and UFS.

[0198] In some embodiments, referring to Figure 16 , the storage system 1 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1 can be integrated into a solid state drive (SSD for short).

[0199] In the storage system 1, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, for example, an SD card, a CF card, a universal serial bus (USB for short) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0200] In some other embodiments, the controller 20 is configured to operate in a high duty cycle environment, such as an SSD or an eMMC, which is used for data storage of mobile devices such as smartphones, tablet computers, laptops, etc. and enterprise storage arrays.

[0201] In some embodiments, the controller 20 can be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (such as a host). In some embodiments, the controller 20 can also be configured to control the operation of the three-dimensional memory 10, such as read, erase and program operations. In some embodiments, the controller 20 can also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes related to data read from or written to the three-dimensional memory 10.

[0202] Of course, the controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10. For example, the controller 20 can communicate with an external device (such as a host) through at least one of various interface protocols.

[0203] It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronic device (IDE) protocol, and a Firewire protocol.

[0204] Some embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure. The semiconductor structure provided by any of the above embodiments can be manufactured by using the method. Based on the above description, the semiconductor structure manufactured by the method for manufacturing a semiconductor structure can have a first core region, a step region, and a second core region arranged in sequence. The description of the first core region, the step region, and the second core region of the semiconductor structure can refer to the description of the semiconductor structure above, and will not be repeated here.

[0205] Figure 17 A flowchart of the method for manufacturing a semiconductor structure according to some embodiments is shown in FIG. Figure 17 The method for manufacturing a semiconductor structure includes the following steps:

[0206] S1, manufacturing a first original memory stack structure on a substrate.

[0207] Referring to Figure 18 and Figure 19 , Figure 19 is a partial enlarged view of the region U3 in Figure 18 The first original memory stack structure 300 can be manufactured on the substrate SUB. The first original memory stack structure 300 includes first material layers 320 and second material layers 310 arranged in an alternating stack. The first material layers 320 can be used to form the first dielectric layers in the first memory stack structure described above, and the structure and material thereof can refer to the related description above, which will not be repeated here. The material of the second material layers 310 can be silicon oxide or silicon nitride, or other possible materials, and the embodiments of the present disclosure do not make any limitation in this regard.

[0208] The positions, materials, and functions of the remaining structures in the first original memory stack structure 300 are the same as those of the corresponding structures in the first memory stack structure, except that the material of the second material layers 310 is different from that of the first conductive layers 112 described above. Therefore, for the remaining structures in the first original memory stack structure 300, the description of the corresponding structures in the first memory stack structure above can be referred to, and will not be repeated here. Specifically, in the following description, each structure in the first original memory stack structure with the name "original" can refer to the description of the corresponding structure in the first memory stack structure above, unless otherwise specified.

[0209] Since the semiconductor structure to be formed has a first core region C1, a step region SSA, and a second core region C2, the first original memory stack structure 300 also has a first core region C1, a step region SSA, and a second core region C2. Based on this, the portion of the first original memory stack structure 300 located in the step region SSA is the first original interconnect structure OLP1.

[0210] The first original connecting structure OLP1 includes a first original connecting wall OXW1 and a first original step portion OSP1 distributed along a first direction. The first direction is the thickness direction of the first original connecting wall OXW1, for example, parallel to the x-axis. The first original step portion OSP1 contacts the first original connecting wall OXW1, and the first original connecting wall OXW1 extends along a second direction to a first core region C1 and a second core region C2.

[0211] S2. Fabricate a second primitive memory stack structure on the substrate.

[0212] Among them, see Figure 20 and Figure 21 ,in, Figure 21 for Figure 20 A partially enlarged view of region U4. A second primitive memory stack structure 400 can be formed on the substrate SUB. The second primitive memory stack structure 400 includes an alternately stacked third material layer 420 and a fourth material layer 410. The third material layer 420 can be used to form the second dielectric layer in the second memory stack structure described above; its structure and material can be found in the relevant description above and will not be repeated here. The material of the fourth material layer 410 can be silicon oxide or silicon nitride, or other possible materials; the embodiments disclosed herein are not limited in this regard.

[0213] Similarly, in the second original memory stack structure 400, except for the fourth material layer 410 which differs from the material of the second conductive layer described above, the positions, materials, and functions of the remaining structures are identical to the corresponding structures in the first memory stack structure. Therefore, unless otherwise specified, the remaining structures in the second original memory stack structure 400 can be referred to the descriptions of the corresponding structures in the second memory stack structure above, and will not be repeated here. Specifically, in the following text, each structure in the second original memory stack structure whose name includes "original" can be referred to the descriptions of the corresponding structures in the second memory stack structure above.

[0214] The portion of the second primitive storage stack structure 400 located in the step region SSA is the second primitive connection structure OLP2.

[0215] It should be noted that step S2 can be performed before or after step S1. In some embodiments, step S2 is performed after step S1, at which time, the second original memory stack structure can be fabricated on the substrate with the first original memory stack structure, for example, the second original memory stack structure can be located on the side of the first original memory stack structure away from the substrate. In other embodiments, step S2 is performed before step S1, at which time, the first original memory stack structure can be fabricated on the substrate with the second original memory stack structure, i.e., the first original memory stack structure can be located on the side of the second original memory stack structure away from the substrate.

[0216] When the number of stacked layers of the three-dimensional memory is large, the exposure of the word line located at a lower level can occur due to the limitation of the photoresist development process when forming the step portion, resulting in unstable electrical connection of the step structure. In addition, after the step portion is formed, oxide filling is required to cover and protect the step portion. When the number of stacked layers of the three-dimensional memory is large, the amount of filled oxide also increases accordingly, which can cause problems such as stress unevenness and cracking. In the method for manufacturing a semiconductor structure provided in the embodiments of the present disclosure, the semiconductor structure can be divided into a first memory stack structure and a second memory stack structure and fabricated separately, for example, the first original memory stack structure and the second original memory stack structure are fabricated separately. Compared with one-step fabrication of the semiconductor structure, two-step fabrication of the semiconductor structure divided into two parts can simplify the fabrication process and improve the above-mentioned problems, thereby improving the stability of the semiconductor structure and improving product yield.

[0217] In some embodiments, step S1 can include the following steps:

[0218] S11, referring to Figure 22 and Figure 23 , wherein Figure 22 is a process flow diagram of the method for manufacturing a semiconductor structure according to some embodiments, Figure 23 is Figure 22 is a partial enlarged view of the region U5 in . The first layer structure 500 is formed on the substrate SUB. The first layer structure 500 includes the first material layer 320 and the second material layer 310 arranged alternately. It should be noted that the substrate can be configured to provide support in the fabrication of the first original memory stack structure, and the first original memory stack structure and the first layer structure do not include the substrate SUB.

[0219] Exemplarily, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, etc. can be used to alternately deposit the first material layer 320 and the second material layer 310 on the substrate.

[0220] In the first stack structure 500, a first material layer 320 and a second material layer 310 located adjacently in the z-axis direction can form a first original stack group OLTa.

[0221] Exemplarily, the first stack structure 500 can include 155 first original stack groups OLTa.

[0222] S12 (optional), referring to Figure 24 , etching the first stack structure 500 to form an original bottom select gate structure OBSG.

[0223] When step S1 is prior to step S2, that is, when the second original memory stack structure is located on the side of the first original memory stack structure away from the substrate, the first stack structure 500 can be etched to form the original bottom select gate structure OBSG when the first original memory stack structure is manufactured. Exemplarily, the first stack structure 500 can be trimmed and etched by a trim and etch process to form the original bottom select gate structure OBSG. For example, the middle part of the first stack structure 500 (for example, the part of the first stack structure 500 located at the middle position along the x-axis direction) can be trimmed and etched.

[0224] It should be noted that, in this article, trimming and etching a structure can mean forming a mask pattern on the structure, and completing the trimming and etching of the structure by performing at least one (for example, one time; for example, multiple times) etching and trimming the mask pattern.

[0225] Exemplarily, Figure 25 The steps of one trimming and one etching in the trim and etch process are shown. Referring to (a)-(d) in FIG. 6, a mask pattern B can be formed on a stack structure A (for example, the first stack structure or the second stack structure, which will be described below). The material of the mask pattern B is, for example, a photoresist material. First, the stack structure A can be etched by the mask pattern B to form a first-level step. Then, the mask pattern B is trimmed so that the size of the mask pattern B in the x-axis direction is reduced. By performing at least one of the above steps of etching the stack structure A and trimming the mask pattern B, and when repeatedly performing the above step of etching the stack structure A, the stack structure A can be etched by the trimmed mask pattern B to form a multi-level step. Figure 25 In some possible implementations, the material of the mask pattern B can be reasonably selected so that the etching rate of the mask pattern B matches the etching rate of the stack structure A, and thus the step of trimming the mask pattern B and the step of etching the stack structure A can be performed simultaneously in the trim and etch process. In this way, the etching process can be further simplified.

[0226]

[0227] ​Based on the above, please refer to [link / reference]. Figure 24 In some embodiments, in step S12, a primary bottom selection gate structure OBSG comprising 7 steps can be formed by etching 7 times and trimming 6 times in one trimming etching process, for example etching a first primary stack.

[0228] S13 (optional), see also Figure 24 , Figure 26 and Figure 27 Through mask pattern M1 Figure 24 The first stacked structure 500 is etched so that the subsequently formed first original step portion can have partitions along the first direction.

[0229] For example, see Figure 26 and Figure 27 ,exist Figure 26 and Figure 27 In this process, position lines with the same name (e.g., position lines L1-L4, position lines V1-V4) correspond to each other. For example, position lines with the same name are located at the same position in the first stacked structure 500. The first original step portion to be formed has two partitions along the first direction. At this time, the portion of the first stacked structure 500 exposed by the mask pattern M1 is etched through the mask pattern M1, for example, at least one (e.g., one; or more) of the first original stacked group can be etched to form Figure 27 The first stacked structure 500 is shown. Following step 13, in the portions of the first stacked structure located in the two partitions DP1 and DP2, the portion located in DP2 is at a lower level in the thickness direction (e.g., parallel to the z-axis) of the first stacked structure compared to the portion located in DP1. This allows the subsequently formed first initial step portion to have partitions along a first direction.

[0230] S14, see also Figure 22 and Figure 18 In some embodiments, the stepped region SSA includes a third protection zone PA3 and a third etched region EA3 distributed along a first direction. A third protection zone PA3 (e.g., each third protection zone PA3) and a third etched region EA3 (e.g., each third etched region EA3) may be located within the stepped region SSA. Furthermore, part or all of a third protection zone PA3 and a third etched region EA3 may be located within a memory cell block; for example, part or all of a third protection zone PA3 and a third etched region EA3 may be located within region B11.

[0231] Based on the above, step S14 includes protecting the portion of the first stacked structure 500 located in the third protected zone PA3, and etching the portion of the first stacked structure 500 located in the third etched zone EA3, to form as shown. Figure 18The first original step portion OSP1 located in the third etching area and the first original connection wall OXW1 located in the third protection area PA3 are shown.

[0232] The first original step portion OSP1 includes a third original step group OSG3 and a fourth original step group OSG4 located at different levels. In a direction from the first core area C1 to the second core area C2 (for example, a positive direction of the x-axis), the step faces SGP of the third original step group OSG3 and the step faces SGP of the fourth original step group OSG4 are sequentially arranged and located adjacent to each other. In addition, the step faces SGP of the third original step group OSG3 rise in a direction approaching the second core area C2 (for example, a positive direction of the x-axis), and the step faces SGP of the fourth original step group OSG4 fall in a direction approaching the second core area C2.

[0233] In some embodiments, the portion of the first stacked structure 500 located in the third protection area PA3 can be protected by forming a hard mask on the surface of the portion of the first stacked structure 500 located in the third protection area PA3. For example, a suitable hard mask material can be selected such that the etching rate of the hard mask is small during etching, thereby protecting the portion covered by the hard mask. In the subsequent etching process, the portion of the first stacked structure 500 covered by the hard mask can not be etched. In this way, the first original connection wall OXW1 located in the third protection area PA3 can be formed.

[0234] Further, in step S14, the step of etching the portion of the first stacked structure 500 located in the third etching area EA3 to form the first original step portion OSP1 located in the third etching area EA3 can include:

[0235] S141, referring to Figure 22 , Figure 27 and Figure 28 trimming and etching the portion of the first stacked structure 500 located in the third etching area EA3 to form the first preliminary step portion ASP1 in Figure 28 .

[0236] The first preliminary step portion ASP1 includes a third preliminary step group ASG3 and a fourth preliminary step group ASG4 located at the same level. In a direction from the first core area C1 to the second core area C2, the step faces SGP of the third preliminary step group ASG3 and the step faces SGP of the fourth preliminary step group ASG4 are sequentially arranged and located adjacent to each other. In addition, the step faces SGP of the third preliminary step group ASG3 rise in a direction approaching the second core area C2, and the step faces SGP of the fourth preliminary step group ASG4 fall in a direction approaching the second core area C2.

[0237] Similarly, the first preliminary step section ASP1 may also include a sixth preliminary step group ASG6 and a seventh preliminary step group ASG7 located at the same level. Along the direction from the first core region C1 to the second core region C2, the step surfaces SGP of the sixth preliminary step group ASG6 and the seventh preliminary step group ASG7 are sequentially arranged and adjacent to each other. Furthermore, the step surface SGP of the sixth preliminary step group ASG6 rises in the direction approaching the second core region C2, while the step surface SGP of the seventh preliminary step group ASG7 descends in the direction approaching the second core region C2.

[0238] Furthermore, the first preliminary step section ASP1 may also include a fifth preliminary step group ASG5, the step surface SGP of which descends in the direction approaching the second core region C2. The first preliminary step section ASP1 may also include an eighth preliminary step group ASG8, the step surface SGP of which ascends in the direction approaching the second core region C2.

[0239] In some possible implementations, the fifth preliminary step group ASG5, the third preliminary step group ASG3, the fourth preliminary step group ASG4, the sixth preliminary step group ASG6, the seventh preliminary step group ASG7, and the eighth preliminary step group ASG8 can be located at the same level, and the step surfaces of the fifth preliminary step group ASG5, the third preliminary step group ASG3, the fourth preliminary step group ASG4, the sixth preliminary step group ASG6, the seventh preliminary step group ASG7, and the eighth preliminary step group ASG8 can be arranged sequentially along a second direction (e.g., parallel to the x-axis direction).

[0240] In some embodiments, see Figure 28 See also Figure 29 and Figure 30 ,exist Figure 29 and Figure 30 In this context, position lines with the same name (e.g., position lines L5 to L10) correspond to each other; for example, position lines with the same name are located at the same position in the first stacked structure 500. In step S141, the mask pattern used in the trimming etching process can be as follows: Figure 29 As shown, a trimming and etching process can be performed using mask pattern M2, for example, trimming 5 times and etching 6 times to form 6 steps. Then, a trimming and etching process can be performed using mask pattern M3, for example, trimming 5 times and etching 6 times to form 6 steps.

[0241] The mask pattern M2 may include mask sub-patterns M21 to M24, and the mask pattern M3 may include mask sub-patterns M31 to M34. The fifth preliminary step group ASG5 can be formed using mask sub-patterns M21 and M31; the third preliminary step group ASG3 and the fourth preliminary step group ASG4 can be formed using mask sub-patterns M22 and M32; the sixth preliminary step group ASG6 and the seventh preliminary step group ASG7 can be formed using mask sub-patterns M23 and M33; and the eighth preliminary step group ASG8 can be formed using mask sub-patterns M24 and M34.

[0242] In trimming etching, since trimming etching can be isotropic, the mask pattern is also etched in the thickness direction (e.g., parallel to the z-direction). Therefore, when the number of steps to be formed in a single trimming etching process is large, the required mask pattern thickness is relatively thick, which is detrimental to process and product shape control. Based on this, in the semiconductor structure fabrication method provided in the embodiments of this disclosure, when the number of steps in a preliminary step group is large, multiple (e.g., two) trimming etching processes can be used, with each trimming etching process forming only a portion of the steps. This allows for better control of the trimming etching process and the product morphology.

[0243] S142. Perform pre-etching on the first preliminary step group ASP1 to form a shape as shown in the figure. Figure 18 The first original step portion OSP1 is shown.

[0244] It should be noted that, in this article, "preset etching of a structure" can mean forming a mask pattern on the structure and etching a preset number of layers into the structure by performing one etching operation.

[0245] For example, Figure 31 The pre-defined etching steps are shown. See also Figure 31 (a) and (b) in the diagram. A mask pattern C can be formed on the stacked structure A (e.g., a first stacked structure and a second stacked structure, the second stacked structure will be described below). The mask pattern C is, for example, photoresist or a hard mask. The stacked structure A in (a) can be etched with a predetermined number of layers using the mask pattern C, such as etching four first original stacked layers, to obtain the stacked structure A shown in (b).

[0246] Based on the above, in step S142, multiple preset etching processes can be performed to form... Figure 18 The first original step portion OSP1 is shown.

[0247] For example, step S142 may include the following sub-steps:

[0248] S142a, see also Figure 32、 Figure 33 and Figure 34 wherein, Figure 32 、 Figure 33 and Figure 34 the position lines with the same name (e.g. position lines L11 and L12, position lines V5-V8) correspond to each other. By preset etching of the first stack structure 500 in Figure 32 with the mask pattern M4, the first stack structure 500 shown in Figure 33 is formed. For example, by etching away a preset number of layers from the portions not covered by the mask pattern M4, e.g. etching away 26 first original stack groups, the first stack structure 500 shown in Figure 34 is formed. For the convenience of illustration, in Figure 34 , the positions of the preliminary step groups are shown by the positions of the step faces of the preliminary step groups. It can be seen that, by step S142a, the third preliminary step group ASG3, the fourth preliminary step group ASG4, the sixth preliminary step group ASG6 and the seventh preliminary step group ASG7 can be located at the same level, and the third preliminary step group ASG3, the fourth preliminary step group ASG4, the sixth preliminary step group ASG6 and the seventh preliminary step group ASG7 can be located at a lower level compared to the fifth preliminary step group ASG5 and the eighth preliminary step group ASG8.

[0249] S142b, referring to Figure 34 、 Figure 35 and Figure 36 wherein, Figure 34 、 Figure 35 and Figure 36 the position lines with the same name (e.g. position lines L13 and L14) correspond to each other. By preset etching of the first stack structure 500 shown in Figure 35 obtained by step S142a with the mask pattern M5, the first stack structure 500 shown in Figure 34 is formed. For example, by etching away a preset number of layers from the portions not covered by the mask pattern M5, e.g. etching away 26 first original stack groups, the first stack structure 500 shown in Figure 36 is formed. For the convenience of illustration, in Figure 36 , the positions of the preliminary step groups are shown by the positions of the step faces of the preliminary step groups. It can be seen that, by step S142b, the fourth preliminary step group ASG4 and the sixth preliminary step group ASG6 can be located at the same level, and the fourth preliminary step group ASG4 and the sixth preliminary step group ASG6 can be located at a lower level compared to the third preliminary step group ASG3 and the seventh preliminary step group ASG7.

[0250] S142c, referring to Figure 36 、 Figure 37 and Figure 38 wherein, Figure 36 、 Figure 37and Figure 38 The position lines with the same name in the middle (for example, the position lines L15 and L16) correspond to each other. The first stack structure 500 obtained in step S142b is pre-etched by the mask pattern M6 shown in Figure 37 . Illustratively, the portions not covered by the mask pattern M6 are removed by a preset number of layers, for example, 26 first original stack groups are etched and removed, and the first stack structure 500 shown in Figure 36 may be formed. For the convenience of illustration, in Figure 38 , the positions of the preliminary step groups are shown by the positions of the step surfaces of the preliminary step groups. It can be seen that, through step S142c, the fifth preliminary step group ASG5, the third preliminary step group ASG3, the fourth preliminary step group ASG4, the sixth preliminary step group ASG6, the seventh preliminary step group ASG7, and the eighth preliminary step group ASG8 can be located at different levels, i.e., the first original step portion OSP1 shown in Figure 38 is formed. Figure 18

[0251] In addition, since the portion of the first stack structure located in the third protection area is protected, in the etching process of step S142, the portion of the first stack structure located in the third protection area is not etched, and a first original connecting wall can be formed, which can be located in the third protection area.

[0252] S15 (optional), after the step of forming the first original connecting wall and the first original step portion, a plurality of first trench structures are formed in the portions of the first stack structure located in the first core area and the second core area.

[0253] Compared with forming the first trench structure first and then forming the first original connecting wall and the first original step portion, forming the first original connecting wall and the first original step portion first and then forming the first trench structure can avoid the damage of the process steps (for example, etching or cleaning steps) for forming the first original connecting wall and the first original step portion to the first trench structure, can improve the structural stability of the semiconductor structure, and can improve the yield of the product.

[0254] In some embodiments, step S2 can include the following steps:

[0255] S21, referring to Figure 39 and Figure 40 , wherein Figure 39 is a process flow diagram of a method for manufacturing a semiconductor structure according to some embodiments, Figure 40 Figure 39 ​​A partially enlarged view of region U6 of the second stacked structure. A second stacked structure 600 is formed on the substrate SUB. The second stacked structure 600 includes alternating layers of a third material layer 420 and a fourth material layer 410. It should be noted that the substrate SUB can be configured to provide support in the fabrication of the first original memory stacked structure, which does not include the substrate SUB.

[0256] For example, a third material layer 420 and a fourth material layer 410 can be alternately deposited on a substrate using methods such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0257] In the second stacked structure 600, a third material layer 420 and a fourth material layer 410 that are adjacent in the z-axis direction can form a second original stack group OLTb. For example, the second stacked structure 600 may include 155 second original stack groups OLTb.

[0258] In some embodiments, before step S2, a second stacked structure 600 may be formed on the side of the first original storage stacked structure away from the substrate. In the accompanying drawings provided below, unless otherwise specified, the first original stacked structure (or first stacked structure) located on the side of the second original stacked structure (or second stacked structure) closer to the substrate will be omitted, and only the substrate and the second original stacked structure (second stacked structure) will be shown.

[0259] S22 (optional), see also Figure 39 , Figure 41 , Figure 42 and Figure 43 The second stacked structure 600 is etched to form the original top selected gate structure OTSG.

[0260] When step S1 is before step S2, it can also be said that when the second original memory stack structure is located on the side of the first original memory stack structure away from the substrate, the second stack structure 600 can be etched during the fabrication of the second original memory stack structure to form the original top select gate structure OTSG.

[0261] For example, step S22 may include the following sub-steps:

[0262] S22a, through Figure 41 The mask pattern M7 shown is used to etch the second stacked structure 600 using a preset etching process. Exemplarily, the mask pattern M7 is a hard mask. Sub-step S22a can be used to open up areas where steps need to be formed subsequently.

[0263] S22b, via Figure 42The mask pattern M8 shown is used to etch the second stack structure 600 using a trimming etching process. For example, by trimming 3 times of etching 4 times, a raw top select gate OTSG structure with 4 levels of steps is formed.

[0264] S23 (optional), etching the second stack structure 600 so that the subsequently formed second raw step portion can have a partition along the first direction. The specific steps can refer to the description of etching the first stack structure to form a partition above, which will not be repeated here.

[0265] In some embodiments, step S23 and step S22 can be performed simultaneously. Exemplarily, by using the mask patterns in step S23 and step S22 in combination, one etching can form a level of step in the raw top select gate structure OTSG, and at the same time, etch one or more second raw stack groups in a partition of the second stack structure. Further, through multiple etchings, the raw top select gate structure OTSG and the partition structure can be formed at the same time.

[0266] S24, etching the second stack structure 600 to form Figure 20 The second raw connection structure OLP2 shown.

[0267] Among them, the second raw connection structure OLP2 includes a second raw step portion OSP2, the second raw step portion OSP2 includes a first raw step group OSG1 and a second raw step group OSG2, the first raw step group OSG1 extends to the first core area C1 and has a step face SGP descending in the direction approaching the second core area C2 (for example, the positive direction of the x-axis). The second raw step group OSG2 extends to the second core area C2 and has a step face SGP descending in the direction approaching the first core area C1 (for example, the negative direction of the x-axis).

[0268] In some embodiments, referring to Figure 39 The step area SSA of the semiconductor structure to be formed can include a plurality of first sub-areas GA1 and a plurality of second sub-areas GA2 distributed in sequence along the second direction, each first sub-area GA1 includes a first protection area PA1 and a first etching area EA1 located on the side of the first protection area PA1 close to the second core area C2. Each second sub-area GA2 includes a second protection area PA2 and a second etching area EA2 located on the side of the second protection area PA2 close to the first core area C1. Correspondingly, the second stack structure 600 can also have the above-mentioned areas.

[0269] Based on this, step S24 can include the following steps:

[0270] S241, referring to Figure 39 and Figure 44The portions of the second stack structure 600 located in the first protection area PA1 and the second protection area PA2 are protected, and the portions of the second stack structure 600 located in the plurality of first etching areas EA1 are etched to form a plurality of first preliminary step groups ASG1 located at the same level. In addition, the portions of the second stack structure 600 located in the plurality of second etching areas EA2 are etched to form a plurality of second preliminary step groups ASG2 located at the same level.

[0271] In some possible implementation manners, in step S241, the step faces SGP of each first preliminary step group ASG1 decline in a direction close to the second core area C2, and the step faces SGP of each second preliminary step group ASG2 decline in a direction close to the first core area C1.

[0272] In some possible implementation manners, after step S241, each first preliminary step group ASG1 and each second preliminary step group ASG2 can be located at the same level. For example, the second stack structure 600 includes three first preliminary step groups ASG1, i.e., the first preliminary step groups ASG11-ASG13, and can also include three second preliminary step groups ASG2, i.e., the second preliminary step groups ASG21-ASG23. The first preliminary step group ASG11, the first preliminary step group ASG12, the first preliminary step group ASG13, the second preliminary step group ASG21, the second preliminary step group ASG22, and the second preliminary step group ASG23 are located at the same level, and can be sequentially distributed along the second direction (for example, parallel to the x-axis direction).

[0273] In some embodiments, the portions of the second stack structure 600 located in the first protection area PA1 and the second protection area PA2 can be protected by forming a hard mask on the surface of the portions of the second stack structure 600 located in the first protection area PA1 and the second protection area PA2. For example, a suitable hard mask material can be selected, so that the etching rate of the hard mask is small in the etching process, and thus the portions covered by the hard mask are protected. In the subsequent etching process, the portions of the second stack structure 600 covered by the hard mask can not be etched.

[0274] In some embodiments, in step S241, the portions of the second stack structure 600 located in the plurality of first etching areas EA1 and the plurality of second etching areas EA2 are etched by one or more times of trimming etching.

[0275] For example, referring to FIG. 6, the first preliminary step group ASG11 and the second preliminary step group ASG21 are located at the same level, the first preliminary step group ASG12 and the second preliminary step group ASG22 are located at the same level, and the first preliminary step group ASG13 and the second preliminary step group ASG23 are located at the same level. Figure 44 and Figure 45 The position lines (for example, the position lines L29-L40) with the same names in Figure 44 and Figure 45 correspond. In step S241, the mask pattern used in the trimming etching process can be as shown in FIG. 6. Figure 45The first preliminary step group ASG1 and the second preliminary step group ASG2 can be formed by one trimming and etching process with the mask pattern Ma, for example, trimming 4 times and etching 5 times. The second preliminary step group ASG2 and the third preliminary step group ASG3 can be formed by one trimming and etching process with the mask pattern Mb, for example, trimming 5 times and etching 6 times. The third preliminary step group ASG3 and the fourth preliminary step group ASG4 can be formed by one trimming and etching process with the mask pattern Mc, for example, trimming 5 times and etching 6 times.

[0276] The mask pattern Ma can include mask sub-patterns Ma1-Ma6, the mask pattern Mb can include mask sub-patterns Mb1-Mb6, and the mask pattern Mc can include mask sub-patterns Mc1-Mc64. The first preliminary step group ASG11 can be formed by the mask sub-pattern Ma1, the mask sub-pattern Mb1, and the mask sub-pattern Mc1. The first preliminary step group ASG12 can be formed by the mask sub-pattern Ma2, the mask sub-pattern Mb2, and the mask sub-pattern Mc2. The first preliminary step group ASG13 can be formed by the mask sub-pattern Ma3, the mask sub-pattern Mb3, and the mask sub-pattern Mc3. The second preliminary step group ASG21 can be formed by the mask sub-pattern Ma4, the mask sub-pattern Mb4, and the mask sub-pattern Mc4. The second preliminary step group ASG22 can be formed by the mask sub-pattern Ma5, the mask sub-pattern Mb5, and the mask sub-pattern Mc5. The second preliminary step group ASG23 can be formed by the mask sub-pattern Ma6, the mask sub-pattern Mb6, and the mask sub-pattern Mc6.

[0277] S242, protecting the portions of the second stack structure 600 located in the first protection area and the second protection area, etching at least one (for example, one; for example, multiple) first preliminary step group ASG1 and etching at least one (for example, one; for example, multiple) second preliminary step group ASG2 to form Figure 20 The plurality of first original step groups OSG1, the plurality of second original step groups OSG2, and the plurality of second original support walls OYW2 shown.

[0278] Each second original support wall OYW2 is located in the first protection area or the second protection area.

[0279] In some embodiments, the at least one first preliminary step group ASG1 and / or the at least one second preliminary step group ASG2 can be etched by a preset etching process to form Figure 20 The plurality of first original step groups OSG1, the plurality of second original step groups OSG2, and the plurality of second original support walls OYW2 shown.

[0280] For example, the step S242 can include the following sub-steps:

[0281] S242a, referring toFigure 46 , Figure 47 and Figure 48 wherein, Figure 46 , Figure 47 and Figure 48 the same named position lines (e.g. position line L41 and position line L42) correspond. By means of the mask pattern Md in Figure 46 , the second stack structure 600 in Figure 47 is etched. Exemplarily, a preset number of layers of the portions not covered by the mask pattern Md are etched away, for example, 51 second original stack groups are etched away, and the second stack structure 600 shown in Figure 48 may be formed. For the convenience of illustration, in Figure 48 , the positions of the preliminary step groups are shown by the positions of the step faces of the preliminary step groups. It can be seen that, by means of step S242a, the first preliminary step group ASG12, the first preliminary step group ASG13, the second preliminary step group ASG21 and the second preliminary step group ASG22 can be located at the same level. And, compared with the first preliminary step group ASG11 and the second preliminary step group ASG23, the first preliminary step group ASG12, the first preliminary step group ASG13, the second preliminary step group ASG21 and the second preliminary step group ASG22 can be located at a lower level.

[0282] S242b, see Figure 48 , Figure 49 and Figure 50 wherein, Figure 48 , Figure 49 and Figure 50 the same named position lines (e.g. position line L43 and position line L44) correspond. By means of the mask pattern Me in Figure 49 , the second stack structure 600 obtained by means of step S242a, as shown in Figure 48 , is etched by a preset number of layers. Exemplarily, a preset number of layers of the portions not covered by the mask pattern Me are etched away, for example, 48 second original stack groups are etched away, and the second stack structure 600 shown in Figure 50 may be formed. For the convenience of illustration, in Figure 50 , the positions of the preliminary step groups are shown by the positions of the step faces of the preliminary step groups. It can be seen that, by means of step S242b, the first preliminary step group ASG13 and the second preliminary step group ASG21 can be located at the same level. And, compared with the first preliminary step group ASG12 and the second preliminary step group ASG22, the first preliminary step group ASG13 and the second preliminary step group ASG21 can be located at a lower level. In this way, the second original step portion OSP2 shown in Figure 20 is formed.

[0283] see Figure 50In some embodiments, the step S1 is prior to the step S2, and the position line L43 and the position line L46 have a certain distance in the second direction. Exemplarily, in the thickness direction (e.g., parallel to the z-axis direction) of the second stack structure 600, the portion of the second stack structure 600 between the position line L43 and the position line L46 can be directly opposite the step faces of the step groups in the first stack structure.

[0284] In some embodiments, the step S1, i.e., the step of manufacturing the first original storage stack structure, is prior to the step S2, i.e., the step of manufacturing the second original storage stack structure. At this time, the step S2 can further include: forming a plurality of second channel structures in the portion of the second stack structure located in the first core region and the second core region, so that a second channel structure located in the first core region is directly opposite and coupled to a first channel structure located in the first core region, and a second channel structure located in the second core region is directly opposite and coupled to a first channel structure located in the first core region.

[0285] In some possible implementations, after the step of manufacturing the first original storage stack structure, i.e., after the first channel structure is manufactured, a stop layer can be formed in each first channel structure of the first original storage stack structure. In this way, in the subsequent process of manufacturing the second channel structure in the second original storage stack structure located away from the substrate side of the first original storage stack structure, the etching of the channel hole of the second channel structure can be stopped in the stop layer of the first channel structure, and the damage of the etching to the first channel structure can be improved.

[0286] In some embodiments, the step of forming the second channel structure is prior to the step of forming the second original connection structure. In this way, the electrical connection stability of the first channel structure and the second channel structure can be improved. In other embodiments, the step of forming the second channel structure can also be after the step of forming the second original connection structure.

[0287] In some embodiments, the method for manufacturing the semiconductor structure can further include the following steps:

[0288] S3, after the step S1, i.e., the step of manufacturing the first original storage stack structure, the second material layer is replaced by the first conductive layer.

[0289] S4, after the step S2, i.e., the step of manufacturing the second original storage stack structure, the fourth material layer is replaced by the second conductive layer.

[0290] In some possible implementations, the step S3 can be performed after the step S1, and then the steps S2 and S4 are performed. In other possible implementations, the steps S1 and S3 can be performed after the steps S2 and S4.

[0291] In yet another possible implementation, steps S3 and S4 can be performed after steps S1 and S2, i.e., after the first original memory stack structure and the second original memory stack structure are formed. Exemplarily, the first original memory stack structure and the second original memory stack structure are sequentially distributed along the thickness direction of the semiconductor structure to be formed. One or more gate line slits extending along the thickness direction of the semiconductor structure to be formed and penetrating the first original memory stack structure and the second original memory stack structure can be formed, and the first original memory stack structure and the second original memory stack structure are exposed through the one or more gate line slits. Then, the second material layers and the fourth material layers can be removed by an etching process (e.g., a wet etching process), and the first conductive layer and the second conductive layer are formed in the formed gaps.

[0292] In some embodiments, referring to Figure 51 wherein, Figure 51 is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments. The method for manufacturing a semiconductor structure can further include step S5: removing the substrate. Exemplarily, step S5 can be performed after steps S3 and S4, i.e., after the semiconductor structure 100 including the first memory stack structure and the second memory stack structure is formed. In this way, the source layer SL can be formed at the position of the original substrate, and the peripheral circuit 200 can be disposed on the side of the semiconductor structure 100 away from the source layer SL to form a three-dimensional memory. In this way, the peripheral circuit 200 and the semiconductor structure 100 can be manufactured separately, the manufacturing process of the three-dimensional memory can be simplified, and the structural stability of the three-dimensional memory can be improved.

[0293] In some embodiments, the semiconductor structure disposed on a substrate (hereinafter referred to as a first substrate) and the peripheral circuit disposed on another substrate (hereinafter referred to as a second substrate) can be bonded, and then the first substrate corresponding to the semiconductor structure can be removed. In this way, the second substrate can play a supporting role in the process of removing the first substrate, the structural stability of the three-dimensional memory can be improved, and the yield of the product can be improved.

[0294] The above only describes specific implementation manners of the present application, but the protection scope of the present application is not limited to this. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, Having: a first core region, a step region and a second core region arranged in sequence; The semiconductor structure comprises: a first storage stack structure comprising first dielectric layers and first conductive layers arranged in an alternating stack; a portion of the first storage stack structure located in the step region is a first connection structure; the first connection structure comprises a first connection wall distributed along a first direction and a first step portion, the first connection wall is in contact with the first step portion, and the first connection wall extends to the first core region and the second core region along a second direction; the first direction is the thickness direction of the first connection wall; the first step portion comprises a third step group and a fourth step group arranged in the second direction, the step surface of the third step group rises in the direction close to the second core region, and the step surface of the fourth step group descends in the direction close to the second core region; a second storage stack structure arranged on one side of the first storage stack structure; the second storage stack structure comprises second dielectric layers and second conductive layers arranged in an alternating stack, and a portion of the second storage stack structure located in the step region is a second connection structure; the second connection structure comprises a second step portion, and the second step portion comprises a first step group and a second step group, the first step group extends to the first core region and has a step surface descending in the direction close to the second core region, and the second step group extends to the second core region and has a step surface descending in the direction close to the first core region.

2. The semiconductor structure of claim 1, wherein in the first step portion, a step is located at a different level from other steps along the thickness direction of the semiconductor structure.

3. The semiconductor structure of claim 1, wherein each first conductive layer extends in the first core region, the step region and the second core region.

4. The semiconductor structure of claim 1, wherein, in the direction of the first core region pointing to the second core region, the step surface of the third step group and the step surface of the fourth step group are arranged in sequence and adjacent in position.

5. The semiconductor structure of claim 4, wherein the first connection structure further comprises a first support wall extending along the first direction, the first support wall and the first step portion are located on the same side of the first connection wall, and the first support wall is located between the step surface of the third step group and the step surface of the fourth step group.

6. The semiconductor structure of any one of claims 1-5, wherein in the first step group, a step is located at the same level as a step in the second step group along the thickness direction of the semiconductor structure.

7. The semiconductor structure of claim 6, wherein in the second storage stack structure, the portion of each second conductive layer located in the step region is disconnected in the second direction.

8. The semiconductor structure of claim 1, wherein the second connection structure further comprises a second support wall extending along the first direction. The second step portion includes a plurality of first step groups and a plurality of second step groups, and the second support wall is located between step surfaces of adjacent two first step groups or between step surfaces of adjacent two second step groups.

9. The semiconductor structure of claim 1, wherein, The second connection structure further includes a second connection wall, the second connection wall and the second step portion are distributed along the first direction, the second connection wall is in contact with the second step portion, and the second connection wall extends to the first core region and the second core region along the second direction.

10. The semiconductor structure of claim 1, wherein, The first step portion has N sub-regions along the first direction; N first stack groups continuously distributed along a thickness direction of the semiconductor structure in the first step portion have a stepped shape along the first direction; and / or The second step portion has N sub-regions along the first direction; N second stack groups continuously distributed along a thickness direction of the semiconductor structure in the second step portion have a stepped shape along the first direction; wherein N≥2 and N is an integer; a first stack group is composed of a first dielectric layer and a first conductive layer, and a second stack group is composed of a second dielectric layer and a second conductive layer.

11. The semiconductor structure of claim 1, wherein, The first storage stack structure further includes a plurality of first channel structures penetrating the first dielectric layer and the first conductive layer arranged in the alternating stack; and the second storage stack structure further includes a plurality of second channel structures penetrating the second dielectric layer and the second conductive layer arranged in the alternating stack; A first channel structure located in the first core region is located opposite to and coupled with a second channel structure located in the first core region; A first channel structure located in the second core region is located opposite to and coupled with a second channel structure located in the second core region.

12. A three-dimensional memory, comprising: The semiconductor structure of any one of claims 1-11.

13. The three-dimensional memory as recited in claim 12, further comprising: Further comprising: a source layer and a peripheral circuit, the source layer, the semiconductor structure and the peripheral circuit are sequentially arranged along a thickness direction of the semiconductor structure and along a step rising direction of a step region of the semiconductor structure.

14. A storage system, characterized by A controller and the three-dimensional memory of claim 12 or 13, the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

15. A method of fabricating a semiconductor structure, the method comprising: The semiconductor structure has a first core region, a step region and a second core region sequentially arranged; The manufacturing method of the semiconductor structure includes: The first original storage stack structure is manufactured on a substrate, and includes first material layers and second material layers arranged in an alternating stack, a part of the first original storage stack structure located at the step region is a first original connection structure; wherein the first original connection structure includes a first original connection wall and a first original step part distributed along a first direction, the first original step part is in contact with the first original connection wall, the first original connection wall extends to the first core region and the second core region along a second direction, the first direction is a thickness direction of the first original connection wall; the first original step part includes a third original step group and a fourth original step group arranged in the second direction, a step surface of the third original step group rises in a direction close to the second core region, and a step surface of the fourth original step group falls in the direction close to the second core region; The second original storage stack structure is manufactured on the substrate before or after the step of manufacturing the first original storage stack structure on the substrate, and includes third material layers and fourth material layers arranged in an alternating stack, a part of the second original storage stack structure located at the step region is a second original connection structure; the second original connection structure includes a second original step part, the second original step part includes a first original step group and a second original step group, the first original step group extends to the first core region and has a step surface falling in a direction close to the second core region, and the second original step group extends to the second core region and has a step surface falling in a direction close to the first core region.

16. The method of fabricating a semiconductor structure of claim 15, wherein, The step region includes a third protection region and a third etching region distributed along the first direction; The first original storage stack structure is manufactured on a substrate, and includes: A first stack structure is formed on a substrate, and includes first material layers and second material layers arranged in an alternating stack; A part of the first stack structure located at the third protection region is protected, and a part of the first stack structure located at the third etching region is etched to form a first original step part located at the third etching region and a first original connection wall located at the third protection region; The first original step part includes: the third original step group and the fourth original step group located at different levels, and step surfaces of the third original step group and the fourth original step group are sequentially arranged and adjacent in a direction from the first core region to the second core region.

17. The method of claim 16, wherein: The part of the first stack structure located at the third etching region is etched to form the first original step part located at the third etching region, including: trimming and etching the first stack structure located in the third etching region to form a first preliminary step portion; the first preliminary step portion comprises: a third preliminary step group and a fourth preliminary step group located at the same level, and the step surface of the third preliminary step group and the step surface of the fourth preliminary step group are sequentially arranged and located adjacent to each other in the direction from the first core region to the second core region; the step surface of the third preliminary step group rises in the direction approaching the second core region, and the step surface of the fourth preliminary step group descends in the direction approaching the second core region; performing a preset etching on the first preliminary step portion to form a first original step portion.

18. The method of claim 16, wherein: forming the first original storage stack structure on the substrate further comprises: forming a plurality of first channel structures in the portions of the first stack structure located in the first core region and the second core region after forming the first original connection wall and the first original step portion.

19. The method according to any one of claims 15 to 18, wherein forming the second original storage stack structure on the substrate comprises: forming a second stack structure on the substrate, the second stack structure comprising third material layers and fourth material layers alternately stacked; etching the second stack structure to form the second original connection structure.

20. The method of fabricating a semiconductor structure of claim 19, wherein, The step region comprises a plurality of first sub-regions and a plurality of second sub-regions sequentially distributed in the second direction, each first sub-region comprising: a first protection region and a first etching region located on the side of the first protection region close to the second core region, and each second sub-region comprising: a second protection region and a second etching region located on the side of the second protection region close to the first core region; etching the second stack structure to form the second original connection structure comprises: protecting the portions of the second stack structure located in the first protection region and the second protection region, and etching the portions of the second stack structure located in the plurality of first etching regions to form a plurality of first preliminary step groups located at the same level; etching the portions of the second stack structure located in the plurality of second etching regions to form a plurality of second preliminary step groups located at the same level; wherein the step surface of each first preliminary step group descends in the direction approaching the second core region, and the step surface of each second preliminary step group descends in the direction approaching the first core region; protecting the portions of the second stack structure located in the first protection region and the second protection region, and etching at least one first preliminary step group and at least one second preliminary step group to form a plurality of the first original step groups, a plurality of the second original step groups, and a plurality of second original support walls, a second original support wall being located in the first protection region or the second protection region.

21. The method of claim 19, wherein: the step of forming the first original storage stack structure is performed before the step of forming the second original storage stack structure; and the first original storage stack structure comprises a plurality of first channel structures. Fabricating the second original memory stack structure on the substrate further comprises: forming a plurality of second trench structures in the second stack structure in the portion of the first core region and the second core region, such that a second trench structure in the first core region is directly opposite and coupled to a first trench structure in the first core region, and a second trench structure in the second core region is directly opposite and coupled to a first trench structure in the second core region.

22. The method of claim 21, wherein: the step of forming a plurality of second trench structures is prior to the step of forming the second original connection structure.

23. The method of fabricating a semiconductor structure of claim 15, wherein, further comprising: replacing the second material layer with a first conductive layer after the step of fabricating the first original memory stack structure; replacing the fourth material layer with a second conductive layer after the step of fabricating the second original memory stack structure.

24. The method of fabricating a semiconductor structure of claim 15, wherein, further comprising: removing the substrate.

Images