Semiconductor structure and preparation method thereof, three-dimensional memory and storage device

Abstract

The present disclosure provides a semiconductor structure and a method for preparing the same, a three-dimensional memory, and a storage device, relating to the field of semiconductor chip technology, and is intended to address the problem of low integration of peripheral circuits in three-dimensional memory. The semiconductor structure can be divided into a high-voltage well region and a low-voltage well region; the semiconductor structure includes: a substrate, including a first groove and at least one second groove, the first groove being located in the high-voltage well region, and the second groove being located in the low-voltage well region; a first isolation structure disposed within the first groove; the thickness of the first isolation structure being greater than the depth of the first groove; a second isolation structure disposed within the second groove; the thickness of the second isolation structure being less than the depth of the second groove; a first gate oxide layer being located in the high-voltage well region; the first gate oxide layer being disposed on the surface of the substrate, and exposing the first isolation structure. The above-mentioned semiconductor structure is applied to a three-dimensional memory to implement data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a three-dimensional memory and a storage device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memories with three-dimensional structures (3D NAND), which increase storage density by arranging memory cells three-dimensionally on a substrate.

[0003] In three-dimensional memories, peripheral circuits are used to perform logical operations and control and detect the switching states of each memory cell string to store and retrieve data. These circuits typically employ planar transistors, such as symmetrical or asymmetrical double-diffused metal oxide semiconductor field effect transistors (MOSFETs), or fin field-effect transistors (Fin-FETs).

[0004] However, this structure of using planar transistors or Fin-FET devices to make peripheral circuits results in a large area of the peripheral circuits and low integration. Summary of the Invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a three-dimensional memory, and a storage device, aiming to solve the problem of low integration of peripheral circuits of the three-dimensional memory.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a semiconductor structure is provided. The semiconductor structure can be divided into a first well region and a second well region. The semiconductor structure includes a substrate, a first isolation structure, a second isolation structure, and a first gate oxide layer. The substrate includes a first groove and at least one second groove, the first groove being located in the first well region and the second groove being located in the second well region. The first isolation structure is disposed within the first groove, and the thickness of the first isolation structure is greater than the depth of the first groove. The second isolation structure is disposed within the second groove, and the thickness of the second isolation structure is less than the depth of the second groove. The first gate oxide layer is located in the first well region; the first gate oxide layer is disposed on the surface of the substrate, exposing the first isolation structure.

[0008] The semiconductor structure provided by the above-described embodiments of the present disclosure, by arranging the first isolation structure higher than the substrate and the second isolation structure lower than the substrate, can achieve the configuration of a planar transistor in the first well region and a Fin-FET device in the second well region. This can improve the integration density of the semiconductor structure and reduce the integration area.

[0009] In some embodiments, the first groove and the second groove have the same depth.

[0010] In some embodiments, the at least one second groove is a plurality of second grooves, and the second isolation structure in each second groove has the same thickness.

[0011] In some embodiments, the first well region is a high-pressure well region; the second well region is a low-pressure well region; the low-pressure well region includes a first low-pressure well region and a second low-pressure well region, and the second low-pressure well region is arranged on the side of the first low-pressure well region away from the high-pressure well region; the first low-pressure well region and the second low-pressure well region are respectively provided with a second isolation structure.

[0012] In some embodiments, a distance between a surface of the second isolation structure and a surface of the substrate is in a range of 75 nm to 85 nm.

[0013] In some embodiments, the distance between the surface of the substrate and the surface of the first isolation structure is in a range of 20 nm to 40 nm.

[0014] In some embodiments, the semiconductor structure further includes an auxiliary layer; the auxiliary layer is located in the first well region; the auxiliary layer is disposed on the surface of the substrate and covers a wall of the second groove away from the second isolation structure.

[0015] In some embodiments, the semiconductor structure further includes a second gate oxide layer and a third gate oxide layer; the second gate oxide layer is located in the first low-voltage well region; the second gate oxide layer is disposed on the substrate and covers the second isolation structure; the third gate oxide layer is located in the second low-voltage well region; the third gate oxide layer is disposed on the substrate and covers the second isolation structure; the thickness of the third gate oxide layer is less than the thickness of the second gate oxide layer.

[0016] In some embodiments, the semiconductor structure further includes a first source, a first drain, and a first gate located in the first well region; the first gate is disposed on the gate oxide layer, the first source and the first drain are located on both sides of the first gate, and extend from the surface of the substrate into the interior; and / or, the semiconductor structure further includes a second source, a second drain, and a second gate located in the second well region; the second source and the second drain extend from the surface of the substrate into the interior of the substrate, and the second gate is disposed across the top surface and two opposite side surfaces of the second source and the second drain.

[0017] On the other hand, a method for preparing a semiconductor structure is provided, wherein the semiconductor structure includes a first well region and a second well region; the method for preparing the semiconductor structure includes: forming a first gate oxide layer on a substrate; the first gate oxide layer is located in the first well region; forming a first isolation structure and a second isolation column; the first isolation structure is located in the first well region, and the second isolation column is located in the second well region; the first isolation structure and the second isolation column are buried from the surface of the substrate into the substrate; forming a protective layer; the protective layer is located in the first well region and is arranged on the side of the first gate oxide layer away from the substrate; etching the second isolation column to form a second isolation structure; the surface of the second isolation structure is lower than the surface of the substrate; and removing the protective layer.

[0018] The method for preparing a semiconductor structure provided by the above-mentioned embodiment of the present disclosure is such that the first isolation structure is set to be higher than the substrate and the height of the second isolation structure is set to be lower than the substrate. It is possible to set a planar transistor in the first well region and a Fin-FET device in the second well region. This can improve the integration of the semiconductor structure and reduce the integration area. Moreover, when forming the second isolation structure on the second well region, the protective layer can effectively protect the first gate oxide layer in the first well region, thereby reducing damage to the first gate oxide layer in the first well region when forming the second isolation structure. During the etching process, the auxiliary layer can effectively protect the substrate and the second isolation structure, thereby reducing damage to the substrate and the second isolation structure caused by the etching process. At the same time, the auxiliary layer can also repair the sidewalls of the second groove, thereby improving the cross-sectional characteristics between the substrate and the second isolation structure and protecting the active area of the substrate when removing the protective layer.

[0019] In some embodiments, the material forming the protection layer includes polysilicon, amorphous silicon, or nitrogen-doped silicon carbide material.

[0020] In some embodiments, before forming the first isolation structure and the second isolation column, the preparation method also includes: forming a first groove and at least one second groove; the first groove is located in the first well region, and the second groove is located in the second well region; the first groove and the second groove extend from the surface of the substrate into the substrate; forming the first isolation structure and the second isolation column, including forming the first isolation structure in the first groove and forming the second isolation column in the second groove.

[0021] In some embodiments, after forming the first gate oxide layer on the substrate, the preparation method further includes: forming a first sacrificial layer and a second sacrificial layer on the substrate; the first sacrificial layer is located in the second well region, and the second sacrificial layer covers the first gate oxide layer and the first sacrificial layer.

[0022] In some embodiments, forming the second isolation structure includes: thinning the second sacrificial layer located in the second well region; and removing the remaining second sacrificial layer, the first sacrificial layer, and a portion of the second isolation pillar to form the second isolation structure.

[0023] In some embodiments, after removing the protection layer, the method further includes: removing the second sacrificial layer located in the first well region.

[0024] In some embodiments, forming a protective layer includes: forming a protective film, the protective film being located on a side of the first gate oxide layer away from the substrate; forming a first mask layer located in the first well region on the protective film; and removing the protective film located in the second well region to form a protective layer.

[0025] In some embodiments, before forming the first mask layer located in the first well region on the protection film, the method further includes: forming a third sacrificial layer on the protection film.

[0026] In some embodiments, removing the protective layer includes: forming a second mask layer; the second mask layer is located in the second well region and covers the second isolation structure and the substrate; and removing the protective layer.

[0027] In some embodiments, before forming the second mask layer, the method further includes: forming an auxiliary film, wherein the auxiliary film covers the protective layer and the substrate; and before removing the protective layer, the method further includes: removing the auxiliary film located in the first well region.

[0028] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor structure provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here.

[0029] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes: an electrically connected memory array and a peripheral device; the memory array includes an array of memory cell strings; the peripheral device includes: a first well region and a second well region, and a first isolation structure extending into a substrate and a second isolation structure located within the substrate; the surface of the first isolation structure is higher than the surface of the substrate, and the surface of the second isolation structure is lower than the surface of the substrate; the first isolation structure is located in the first well region, and the second isolation structure is located in the second well region; the peripheral device also includes a first gate oxide layer, a first source, a first drain, and a first gate located in the first well region; the first gate oxide layer is disposed on the surface of the substrate and exposes the first isolation structure; the first gate is disposed on the first gate oxide layer; and / or the peripheral device also includes a second source, a second drain, and a second gate located in the second well region.

[0030] In some embodiments, the first source and the first drain are located on both sides of the first gate and extend from the surface of the substrate into the substrate; the second source and the second drain extend from the surface of the substrate into the substrate, and the second gate spans the top surface and two opposite side surfaces of the second source and the second drain.

[0031] In another aspect, a storage device is provided, comprising a controller and the above-mentioned three-dimensional memory, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0033] Figure 1 A block diagram of a storage system provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of the structure of a three-dimensional memory provided in an embodiment of the present application;

[0035] Figure 3A A schematic structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0036] Figure 3B A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0037] Figure 4A A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0038] Figure 4B A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0039] Figure 5 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0040] Figure 6 A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0041] Figures 7A-7S A schematic diagram of a semiconductor structure preparation process provided in an embodiment of the present application;

[0042] Figure 8 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0043] Figure 9 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0044] Figure 10 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0045] Figure 11A schematic structural diagram of another semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0047] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0059] The term "three-dimensional memory" refers to a semiconductor device formed by arraying strings of memory cell transistors on a major surface of a substrate (referred to herein as "memory cell strings," such as NAND memory cell strings) and extending perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the major surface (i.e., lateral surface) of the substrate.

[0060] The present application provides an electronic device, which may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. The present application does not impose any specific restrictions on the specific form of the above-mentioned electronic device, and any electronic device having a storage device is sufficient.

[0061] The storage device may be a universal flash storage (UFS) package or an embedded Multi Media Card (eMMC) package, wherein the storage system may be integrated into various types of storage devices.

[0062] An example of a storage system structure is as follows: Figure 1As shown, the storage system 1 mainly includes one or more three-dimensional memories 2 and a controller 3. The controller 3 is coupled to the three-dimensional memories 2 to control the storage data of the three-dimensional memories 2. The storage system 1 can be integrated into various memory cards such as personal computer memory card international association (PCMCIA or PC), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital memory card (SD), universal flash storage (UFS), and solid state drives (SSD).

[0063] The controller 3 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0064] Alternatively, the controller 3 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0065] Alternatively, the controller 3 is configured to manage data stored in the three-dimensional memory 2 and communicate with an external device (e.g., a host) according to a specific communication protocol, wherein the communication protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small drive interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a FireWire protocol.

[0066] The controller 3 may also be configured to control operations of the three-dimensional memory 2, such as read, erase, and program operations. In some embodiments, the controller 3 may also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 2, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 3 may also be configured to process error correction codes for data read from or written to the three-dimensional memory 2. The controller 3 may also perform any other suitable functions, such as formatting the three-dimensional memory 2.

[0067] Regarding the three-dimensional memory 2, as Figure 2 As shown, the three-dimensional memory 2 includes a peripheral device 10 and a memory array device 20. The peripheral device 10 is electrically connected to the memory array device 20 to implement the peripheral device 10's functional support for the memory array device 20, such as reading, writing, and erasing data in memory cells.

[0068] The memory array device 20 includes a memory cell string array 21 and an array interconnect layer 22. The array interconnect layer 22 is disposed on a side of the memory cell string array 21 close to the peripheral device 10, and the memory cell string array 21 and the array interconnect layer 22 are electrically connected.

[0069] The peripheral device 10 includes a peripheral circuit 11 and a peripheral interconnection layer 12. The peripheral interconnection layer 12 is disposed on a side of the peripheral circuit 11 close to the memory array device 20, and the peripheral circuit 11 and the peripheral interconnection layer 12 are electrically connected.

[0070] It is understandable that the memory array device 20 is electrically connected to the peripheral device 10 via the array interconnect layer 22 and the peripheral interconnect layer 12 , thereby electrically connecting the memory cell string array 21 to the peripheral circuit 11 .

[0071] like Figure 2 As shown, the peripheral device 10 includes a semiconductor structure. The peripheral device 10 can be, for example, a peripheral device in the three-dimensional memory 2 for controlling and detecting the switching states of each memory cell string array 21 to store and read data.

[0072] The peripheral device 10 may include peripheral circuits 11 such as a page buffer, a decoder (e.g., a row decoder and a column decoder), a read amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, and at least one of the peripheral circuits 11 includes a semiconductor structure 100 and a transistor arranged on the semiconductor structure 100.

[0073] The peripheral circuit 10 may be a periphery near cell (PNC) architecture, a periphery under cell (PUC) architecture, or an inverted X-tacking architecture, which is not limited in the embodiments of the present application.

[0074] like Figure 3A As shown, the semiconductor structure 100 may be divided into a first well region 101 and a second well region 102 .

[0075] In one embodiment, the first well region 101 is a high voltage (HV) well region 101, and the second well region 102 is a low voltage well region 102. The low voltage well region 102 includes a first low voltage well region 102a and a second low voltage well region 102b. The first low voltage well region 102a is, for example, an LV (low voltage) well region, and the second low voltage well region 102b is, for example, an LLV (low low voltage) well region.

[0076] Regarding the structure of the semiconductor structure 100 in each well region, in some embodiments, a first groove 141 is provided in the substrate 110 of the high-voltage well region 101 , and at least one second groove 142 is provided in the substrate 110 of the low-voltage well region 102 .

[0077] There is no limitation on the number of the first grooves 141 and the second grooves 142 . Only one first groove 141 and two second grooves 142 are used as an example. In a specific structure, multiple first grooves 141 and multiple second grooves 142 can be provided according to actual needs.

[0078] A first isolation structure 151 is disposed in the first groove 141. The thickness h2 of the first isolation structure 151 is greater than the depth h1 of the first groove 141. Here, the depth of the first groove is perpendicular to the substrate 110. In other words, in the direction perpendicular to the substrate 110, the thickness h2 of the first isolation structure 151 is greater than the depth h1 of the first groove 141. Alternatively, the upper surface of the first isolation structure 151 is higher than the upper surface of the substrate 110.

[0079] Similarly, a second isolation structure 152 is disposed in the second groove 142 , and a thickness h4 of the second isolation structure 152 is greater than a depth h3 of the second groove 142 .

[0080] Figure 3AIn the semiconductor structure 100 shown, in subsequent process steps, a plurality of planar transistors are formed on the substrate 110 to prepare the peripheral circuit 11. The first isolation structure 151 and the second isolation structure 152 are used not only to isolate the active area (AA) in the substrate 110, but also to isolate the high-voltage well region 101 from the low-voltage well region 102.

[0081] However, the planar transistors are relatively large in size, which is not conducive to the integration of the semiconductor structure 100 .

[0082] In other embodiments, Figure 3B As shown, in the semiconductor structure 100 , the thickness h2 of the first isolation structure is smaller than the depth h1 of the first groove, and the thickness h4 of the second isolation structure is smaller than the depth h3 of the second groove.

[0083] like Figure 3B In the semiconductor structure 100 shown, a plurality of fin field-effect transistors (Fin-FETs) are formed on the substrate 110 in subsequent process steps to prepare the peripheral circuit 11 .

[0084] Based on this, the embodiment of the present application further provides a semiconductor structure 100, such as Figure 4A As shown, the thickness h2 of the first isolation structure is greater than the depth h1 of the first groove, and the thickness h4 of the second isolation structure is less than the depth h3 of the second groove.

[0085] like Figure 4A In the semiconductor structure 100 shown, in subsequent process steps, a plurality of planar transistors are formed on the substrate 110 in the high-voltage well region 101 , and a plurality of fin field-effect transistors are formed on the substrate 110 in the low-voltage well region 102 .

[0086] Since FinFETs can effectively solve the problems of short channel effect caused by further reduction in the size of silicon-based planar FETs, Figure 4A Planar transistors and fin field effect transistors are formed on the semiconductor structure 100 to form a peripheral circuit 11 , which can improve the integration of the peripheral devices 10 in the three-dimensional memory 2 and reduce the integration area.

[0087] Indicate a Figure 4AThe preparation method of the semiconductor structure 100 shown includes: forming a first gate oxide layer 121 on a substrate 110, and the first gate oxide layer 121 is located in the high-voltage well region 101; then forming a first isolation structure 151 and a second isolation structure 152, wherein the first isolation structure 151 is located in the high-voltage well region 101, and the second isolation column 152' is located in the low-voltage well region 102; then thinning the second isolation 152' to form a second isolation structure 152.

[0088] However, during the preparation process of the semiconductor structure 10, Figure 4B As shown, the gate oxide layer of the high voltage well region 101 will be formed simultaneously, which may easily cause the first gate oxide layer 121 of the high voltage well region 101 to be damaged due to the hard mask integration process (such as Figure 5 shown).

[0089] Based on this, in order to solve the problem of damage to the gate oxide layer in the high-voltage well region, the embodiment of the present application also provides a method for preparing a semiconductor structure, such as Figure 4B As shown, the semiconductor structure 100 manufactured by the semiconductor structure manufacturing method mainly includes a substrate 110 , a first isolation structure 151 , a second isolation structure 152 and a first gate oxide layer 121 .

[0090] like Figure 6 As shown, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0091] S1, such as Figure 7A As shown, a first gate oxide layer 121 , a first sacrificial layer 131 and a second sacrificial layer 132 are formed on a substrate 110 .

[0092] The substrate 110 is used to support the peripheral devices 10 and the memory array device 20 of the three-dimensional memory 2. The peripheral devices 10 are used to form a peripheral circuit 11 to control the memory cell string array 21 of the memory array device 20. In the embodiments of the present application, only the peripheral device 10 portion of the substrate is shown, and the memory array device 20 portion of the substrate is not limited.

[0093] The present embodiment does not limit the material of the substrate 110. For example, the material forming the substrate 110 may be a semiconductor material, such as silicon (single crystal silicon, polycrystalline silicon, or amorphous silicon), germanium (single crystal germanium), silicon germanium, silicon carbide, glass, gallium nitride, gallium arsenide, glass, SOI (silicon on insulator), GOI (germanium on insulator), or other suitable III-V compound substrates. The substrate 110 may also be P-type doped or N-type doped.

[0094] The substrate 110 may be divided into a high-voltage well region 101 and a low-voltage well region 102. The low-voltage well region 102 may further include a first low-voltage well region 102a and a second low-voltage well region 102b.

[0095] Illustratively, the second low-pressure well region 102b is disposed on a side of the first low-pressure well region 102a away from the high-pressure well region 101. The arrangement of the high-pressure well region 101, the first low-pressure well region 102a, and the second low-pressure well region 102b is not limited in this embodiment of the application.

[0096] Exemplarily, the high voltage of the high voltage well region 101 is in the range of 12V to 100V, and the low voltage of the low voltage well region 102 is in the range of 1V to 6V.

[0097] The high-voltage well region 101 and the low-voltage well region 102 may be formed by implanting impurity ions into the substrate 110 .

[0098] A patterned mask layer is formed on the surface of the substrate 110 to expose a predetermined formation area of the high-voltage well region 101. Impurity ions are implanted into the predetermined formation area of the substrate 110 by an ion implantation process to form the high-voltage well region 101.

[0099] Similarly, a patterned mask layer is formed on the surface of the substrate 110 to expose the predetermined formation area of the low voltage well region 102. Impurity ions are implanted into the predetermined formation area of the substrate 110 by an ion implantation process to form the low voltage well region 102.

[0100] The embodiment of the present application does not limit the type of impurity ions injected into the high-voltage well region 101 and the low-voltage well region 102. For example, N-type ions, such as phosphorus ions or arsenic ions, are injected into the predetermined formation region of the high-voltage well region 101 to form the high-voltage well region 101 with an N-type doping type. P-type ions, such as boron ions or gallium ions, are injected into the predetermined formation region of the low-voltage well region 102 to form the low-voltage well region 102 with a P-type doping type.

[0101] There is no limitation on the order of forming the high-pressure well region 101 and the low-pressure well region 102. The high-pressure well region 101 can be formed first, and then the low-pressure well region 102; the low-pressure well region 102 can be formed first, and then the high-pressure well region 101; or the high-pressure well region 101 and the low-pressure well region 102 can be formed at the same time.

[0102] Regarding the first gate oxide layer 121, the first sacrificial layer 131 and the second sacrificial layer 132, as shown in FIG. Figure 7A As shown, the first gate oxide layer 121 is located in the high-voltage well region 101 and covers the substrate 110 of the high-voltage well region 101 , the first sacrificial layer 131 is located in the low-voltage well region 102 and covers the substrate 110 of the low-voltage well region 102 , and the second sacrificial layer 132 covers the first gate oxide layer 121 and the first sacrificial layer 131 .

[0103] Alternatively, it can be understood that the first gate oxide layer 121 is arranged on the side of the substrate 110 of the high-voltage well region 101, the first sacrificial layer 131 is arranged on the side of the substrate 110 of the low-voltage well region 102, and the second sacrificial layer 132 is arranged on the side of the first gate oxide layer 121 and the first sacrificial layer 131 away from the substrate 110.

[0104] Exemplarily, the method of forming the first gate oxide layer 121, the first sacrificial layer 131 and the second sacrificial layer 132 is as follows: Figure 7A As shown, step S1 includes:

[0105] S11 , forming a first gate oxide layer 121 on the substrate 110 .

[0106] A first gate oxide layer 121 is formed in the high voltage well region 101 of the substrate 110. Figure 7A As shown, the first gate oxide layer 121 is disposed on the high-voltage well region 101 of the substrate 110. For example, the first gate oxide layer 121 is disposed on the surface of the substrate 110 and is located in the high-voltage well region 101.

[0107] The first gate oxide layer 121 may be formed by growing a layer of oxide material on the substrate 110 of the high-voltage well region 101 using a mask to form the first gate oxide layer 121. The growth process may be, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or other deposition techniques.

[0108] The material of the first gate oxide layer 121 includes silicon oxide, but is not limited thereto.

[0109] The first gate oxide layer 121 is used to subsequently form a gate layer on the first gate oxide layer 121 . The gate layer can serve as a gate of a planar transistor in the semiconductor structure 100 .

[0110] In some embodiments, the thickness of the first gate oxide layer 121 is in the range of 400 nm to 600 nm. For example, the thickness of the first gate oxide layer 121 is 420 nm, 450 nm, 475 nm, 498 nm, 523 nm, 530 nm, 550 nm, 570 nm, or 590 nm.

[0111] S12 , forming a first sacrificial layer 131 on the substrate 110 .

[0112] A first sacrificial layer 131 is formed in the low voltage well region 102 of the substrate 110. Figure 7A As shown, the first sacrificial layer 131 is disposed in the low-voltage well region 102 of the substrate 110 .

[0113] For example, the first sacrificial layer 131 is disposed on the surface of the substrate 110 and is located in the low-voltage well region 102 .

[0114] The first sacrificial layer 131 may be formed by growing a layer of oxide material on the substrate 110 of the low-voltage well region 102 using a mask to form the first sacrificial layer 131 .

[0115] The material of the first sacrificial layer 131 includes silicon oxide, but is not limited thereto.

[0116] The first sacrificial layer 131 is used to protect the substrate 110 during subsequent process steps.

[0117] It is understandable that the embodiment of the present application does not limit the order of step S11 and step S12, and step S12 can also be performed first and then step S11.

[0118] For example, the thickness of the first sacrificial layer 131 is not greater than the thickness of the first gate oxide layer 121 .

[0119] In some embodiments, the thickness of the first sacrificial layer 131 is the same as the thickness of the first gate oxide layer 121, and the first gate oxide layer 121 and the first sacrificial layer 131 can be made of the same material. In this way, the first gate oxide layer 121 and the first sacrificial layer 131 can be manufactured in the same process, which simplifies the manufacturing process and saves process steps.

[0120] S13 , forming a second sacrificial layer 132 on the first gate oxide layer 121 and the first sacrificial layer 131 .

[0121] Alternatively, it can be understood that the second sacrificial layer 132 is formed on a side of the first gate oxide layer 121 and the first sacrificial layer 131 away from the substrate 110 .

[0122] like Figure 7A As shown, the second sacrificial layer is disposed on the surface of the first gate oxide layer 121 and the first sacrificial layer 131 , and is located in the high-voltage well region 101 and the low-voltage well region 102 .

[0123] The material of the second sacrificial layer 132 may be nitride, such as silicon nitride (SiN).

[0124] The second sacrificial layer 132 serves as a polishing stop layer in subsequent process steps.

[0125] The embodiment of the present application does not limit the thickness of the second sacrificial layer 132 , and the thickness of the second sacrificial layer 132 only needs to be greater than the difference in thickness between the first gate oxide layer 121 and the first sacrificial layer 131 .

[0126] S2, such as Figure 7B As shown, a first groove 141 and at least one second groove 142 are formed. Figure 7B The following description is made by taking the formation of a plurality of second grooves 142 as an example).

[0127] The first groove 141 is located in the high-voltage well region 101 , and the second groove 142 is located in the low-voltage well region 102 . The first groove 141 and the second groove 142 extend from the surface of the second sacrificial layer 132 into the substrate 110 .

[0128] The embodiment of the present application does not limit the number and depth of the first grooves 141 and the second grooves 142 . For example, the depth h1 of the first groove 141 and the depth h3 of the second groove 142 are the same.

[0129] In this way, the first groove 141 and the second groove 142 can be prepared simultaneously, and the preparation process is simple. It should be noted that when forming multiple second grooves 142, the multiple second grooves 142 can be located in the same low-voltage well region 102, or in different low-voltage well regions 102. For example, the multiple second grooves 142 are all located in the LV well region; or the multiple second grooves 142 are all located in the LLV well region; or Figure 7B As shown, part of the second groove 142 is located in the first low-voltage well region 102 a (eg, LV well region), and part of the second groove 142 is located in the second low-voltage well region 102 b (eg, LLV well region).

[0130] S3, such as Figure 7C As shown, a first isolation structure 151 and a second isolation column 152 ′ are formed.

[0131] It is explained here that the second isolation column 152' can be obtained after thinning. Figure 4B The second isolation structure 152 in the semiconductor structure 100 is shown.

[0132] Exemplarily, an isolation material is deposited in the first groove 141 to form a first isolation structure 151 located in the high-voltage well region 101 , and an isolation material is deposited in the second groove 142 to form a second isolation column 152 ′ located in the low-voltage well region 102 .

[0133] The isolation material of the first isolation structure 151 and the second isolation column 152 ′ may be silicon nitride, and the embodiment of the present application does not limit the isolation material.

[0134] like Figure 7CAs shown, the first isolation structure 151 and the second isolation pillar 152 ′ are embedded into the substrate 110 from the surface of the second sacrificial layer 132 . In other words, the surfaces of the first isolation structure 151 and the second isolation pillar 152 ′ are flush with the surface of the second sacrificial layer 132 .

[0135] Regarding the method of forming the first isolation structure 151 and the second isolation column 152 ′, exemplarily, as shown in FIG. Figure 7D , a second sacrificial film of a certain thickness is formed on the side of the first gate oxide layer 121 and the first sacrificial layer 131 away from the substrate 110; then, a first groove 141 is formed on the high-voltage well region 101, and a second groove 142 is formed on the low-voltage well region 102, and an isolation material is deposited in the first groove 141 and the second groove 142 to form an isolation structure; finally, the upper surface of the second sacrificial film and the surface of the isolation structure are ground to obtain the second sacrificial layer 132, the first isolation structure 151 and the second isolation column 152'.

[0136] It is explained here that the second sacrificial film can be obtained after grinding. Figure 7C A second sacrificial layer 132 is shown.

[0137] The second sacrificial film may be polished by, for example, a chemical mechanical polishing (CMP) process.

[0138] Of course, it can also be Figure 7B Based on the structure shown, a first isolation structure 151 is directly formed in the first groove 141, and a second isolation column 152' is formed in the second groove 142. The present embodiment does not limit the method of forming the first isolation structure 151 and the second isolation column 152'.

[0139] It should be noted that the second isolation column 152 ′ formed here is used to form the second isolation structure 152 in a subsequent process.

[0140] In some embodiments, the first isolation structure 151 and the second isolation structure 152 may also be shallow trench isolation (STI) structures.

[0141] S4, such as Figure 7E As shown, a protection film 160 ′ is formed on the second sacrificial layer 132 .

[0142] Alternatively, it can be understood that a protective film 160' is formed on the side of the second sacrificial layer 132 away from the substrate 110. Figure 7E As shown, the protection film 160 ′ is disposed on the surface of the second sacrificial layer 132 and is located in the high-voltage well region 101 and the low-voltage well region 102 .

[0143] The embodiment of the present application does not limit the material for forming the protection film 160 ′. For example, the material for the protection film 160 ′ may be polysilicon.

[0144] Alternatively, the material of the protection film 160 ′ may be, for example, amorphous silicon (a-Si).

[0145] Alternatively, for example, the material of the protection film 160 ′ may be nitrogen-doped silicon carbide (NDC) material.

[0146] Since amorphous silicon (a-Si) or nitrogen-doped silicon carbide (NDC) materials have high selectivity for certas (chemical gas etching) machines, using amorphous silicon (a-Si) or nitrogen-doped silicon carbide (NDC) materials as the material of the protective film 160' can reduce the damage to the protective film 160' caused by the certas machine and effectively protect the first gate oxide layer 121.

[0147] The function of the protection film 160 ′ is to protect the structures in the high-voltage well region 101 , such as the first gate oxide layer 121 , in subsequent process steps.

[0148] S5, such as Figure 7F As shown, a first mask layer 171 is formed on the protection film 160 ′ and located in the high-voltage well region 101 .

[0149] Alternatively, it can be understood that the first mask layer 171 is formed on the side of the protective film 160' away from the substrate 110. Figure 7F As shown, the first mask layer 171 is disposed on the surface of the protection film 160 ′ and is located in the high-voltage well region 101 .

[0150] The first mask layer 171 may be photoresist (PR).

[0151] It is understandable that, due to process requirements, in order to reduce the direct contact between the organic components in the photoresist and the silicon material forming the protective film 160' and thus damage the silicon material, the Figure 7G As shown, before the photoresist is used as the first mask layer 171, a third sacrificial layer 133 needs to be formed on the protective film 160'. Alternatively, it can be understood that the third sacrificial layer 133 is formed on the side of the protective film 160' away from the substrate 110. Figure 7G As shown, the third sacrificial layer 133 is disposed between the protection film 160 ′ and the first mask layer 171 , and the third sacrificial layer 133 is located between the high-voltage well region 101 and the low-voltage well region 102 .

[0152] The material of the third sacrificial layer 133 may be oxide, such as silicon oxide.

[0153] In some embodiments, the thickness of the third sacrificial layer 133 is For example, the thickness of the third sacrificial layer 133 may be or

[0154] If the thickness of the third sacrificial layer 133 is too large, it will cause difficulty in the subsequent etching process, while if the thickness of the third sacrificial layer 133 is too small, it will not be able to effectively isolate the photoresist and the protective film 160'. Therefore, the thickness of the third sacrificial layer 133 in the embodiment of the present application is between Within the range of , the third sacrificial layer 133 can effectively block the protective film 160 ′ to reduce the situation where the silicon material in the protective film 160 ′ is damaged by the photoresist, and reduce the situation where subsequent process preparation is difficult.

[0155] For the sake of convenience, the following Figure 7G As shown, in the subsequent processes, the formation of the third sacrificial layer 133 is taken as an example for illustration.

[0156] S6, such as Figure 7H As shown, the protection film 160 ′ located in the low voltage well region 102 is removed to form a protection layer 160 .

[0157] It should be noted that when removing the protection film 160 ′ located in the low-voltage well region 102 , the third sacrificial layer 133 located in the low-voltage well region 102 also needs to be removed (while retaining the third sacrificial layer 133 ′ located in the high-voltage well region 101 ).

[0158] Or understand it as Figure 7H As shown, the protection layer 160 is located in the high-voltage well region 101 and covers the surface of the second sacrificial layer 132 .

[0159] In some embodiments, dry etching may be used to remove the protective film 160' and the third sacrificial layer 133 of the low-voltage well region 102. The etching gas used in the dry etching may include ammonia, chlorine, or ammonia-hydrogen gas.

[0160] S7, such as Figure 7I As shown, a second isolation structure 152 is formed.

[0161] The surface of the second isolation structure 152 is lower than the surface of the substrate 110. That is, in a direction perpendicular to the substrate 110, the thickness h4 of the second isolation structure 152 is less than the depth h3 of the second groove 142. In other words, the thickness h4 of the second isolation structure 152 is less than the depth h3 of the second groove 142.

[0162] The embodiment of the present application does not limit the thickness of the second isolation structure 152 in each second groove 142 . Exemplarily, the thickness h4 of the second isolation structure 152 in each second groove 142 is the same.

[0163] In some embodiments, the distance between the surface of the second isolation structure 152 and the surface of the substrate 110 is within a range of 75 nm to 85 nm. In other words, the height difference between the surface of the second isolation structure 152 and the surface of the substrate 110 is within a range of 75 nm to 85 nm. The difference between the depth h3 of the second groove 142 and the thickness h4 of the second isolation structure 152 is within a range of 75 nm to 85 nm. For example, the distance between the surface of the second isolation structure 152 and the surface of the substrate 110 can be 76 nm, 77 nm, 78 nm, 79 nm, 80 nm, 81 nm, 82 nm, 83 nm, or 84 nm.

[0164] If the distance between the surface of the second isolation structure 152 and the surface of the substrate 110 is too large, subsequent process steps will be more difficult and difficult to implement. If the distance between the surface of the second isolation structure 152 and the surface of the substrate 110 is too small, it will be difficult to form a Fin-FET device. Therefore, in the embodiment of the present application, the distance between the surface of the second isolation structure 152 and the surface of the substrate 110 is controlled within the range of 75nm to 85nm.

[0165] In some embodiments, regarding the method of forming the second isolation structure 152, as shown in FIG. Figure 7I As shown, S7 includes:

[0166] S71 , thinning the second sacrificial layer 132 and the second isolation pillar 152 ′ located in the low-voltage well region 102 .

[0167] In some embodiments, dry etching can be used to thin the second sacrificial layer 132 and the second isolation pillars 152' located in the low-voltage well region 102. The amount of thinning of the second sacrificial layer 132 and the second isolation pillars 152' can be controlled by controlling the dry etching time. The dry etching gas can include a carbon-based or fluorine-based gas.

[0168] In some embodiments, the remaining thickness of the second sacrificial layer 132 ′ is in the range of 10 nm to 20 nm. For example, the remaining thickness of the second sacrificial layer 132 ′ may be 11 nm, 13 nm, 15 nm, 17 nm, or 19 nm.

[0169] If the remaining second sacrificial layer 132' is too thin, subsequent processes may damage the substrate 110 and the first sacrificial layer 131. Therefore, in the embodiment of the present application, the remaining second sacrificial layer 132' should be no less than 10nm to 20nm thick to protect the substrate 110 and the first sacrificial layer 131.

[0170] S72 , removing the first mask layer 171 .

[0171] In the embodiment of the present application, the process for removing the first mask layer 171 is not limited. For example, the first mask layer 171 can be burned away using oxygen.

[0172] S73 , removing the remaining second sacrificial layer 132 ′, the first sacrificial layer 131 and a portion of the second isolation pillar 152 ′ in the low-voltage well region 102 to form a second isolation structure 152 .

[0173] For example, a certas (chemical gas etching) machine can be used to remove the remaining second sacrificial layer 132, the first sacrificial layer 131, and a portion of the second isolation pillar 152'. The present embodiment does not limit the method for removing the remaining second sacrificial layer 132, the first sacrificial layer 131, and a portion of the second isolation pillar 152' to form the second isolation structure 152. Compared to plasma etching, chemical gas etching does not involve plasma and does not cause charged particles to accumulate in the substrate 110 and the first gate 124, thereby reducing plasma-induced damage (PID) and improving product yield.

[0174] When the remaining second sacrificial layer 132 ′, the first sacrificial layer 131 and a portion of the second isolation pillars 152 ′ are removed, the third sacrificial layer 133 ′ located in the high-voltage well region 101 is also removed.

[0175] It is understandable that if Figure 7I As shown, since a protective layer 160 is provided in the high-voltage well region 101, when the second isolation structure 152 is formed, the structure in the high-voltage well region 101, such as the first gate oxide layer 121, can be effectively protected, thereby reducing damage to the first gate oxide layer 121 located in the high-voltage well region 101 when the second isolation structure 152 is formed.

[0176] In some other embodiments, the method for forming the second isolation structure 152 includes: removing the first mask layer 171 ; and removing the second sacrificial layer 132 , the first sacrificial layer 131 and a portion of the second isolation pillars 152 ′ to form the second isolation structure 152 .

[0177] In this embodiment, there is no need to thin the second sacrificial layer 132 , which can save process steps.

[0178] S8, such as Figure 7J As shown, an auxiliary film 180' is formed.

[0179] The auxiliary film 180 ′ covers the protection layer 160 and the substrate 110 , and covers the wall of the second groove 142 away from the second isolation structure 152 . The auxiliary film 180 ′ is located in the high-voltage well region 101 and the low-voltage well region 102 .

[0180] The material of the auxiliary film 180 ′ may be an oxide, for example, silicon oxide.

[0181] The auxiliary film 180 ′ is used to repair the sidewall of the second groove 142 on the substrate 110 and effectively protect the substrate 110 in the low voltage well region 102 in subsequent process steps.

[0182] S9, such as Figure 7K As shown, a second mask layer 172 is formed.

[0183] The second mask layer 172 is located in the low-voltage well region 102 and covers the second isolation structure 152 and the substrate 110 .

[0184] The second mask layer 172 may be photoresist.

[0185] S10, such as Figure 7L As shown, the protective layer 160 is removed.

[0186] For example, the protective layer 160 located in the high-voltage well region 101 is removed. The method for removing the protective layer 160 is as follows: Figure 7L Shown, including:

[0187] S101 , removing the auxiliary film 180 ′ located in the high-voltage well region 101 to form an auxiliary layer 180 . The auxiliary layer 180 is disposed between the second mask layer 172 , the substrate 110 , and the second isolation structure 152 , and is located in the low-voltage well region 102 .

[0188] In some embodiments, the auxiliary layer 180 can effectively protect the substrate 110 and the second isolation structure 152, thereby reducing damage to the substrate 110 and the second isolation structure 152 caused by the etching process. Furthermore, the auxiliary layer 180 can repair the sidewalls of the second groove 142, thereby improving the cross-sectional characteristics between the substrate 110 and the second isolation structure 152.

[0189] S102 , removing the protective layer 160 .

[0190] The method for removing the protection layer 160 may refer to the method for removing the protection film 160 ′ located in the low-voltage well region 102 in S6 .

[0191] S103 , removing the second mask layer 172 .

[0192] The method for removing the second mask layer 172 may refer to the method for removing the first mask layer 171 in S72 .

[0193] S110, such as Figure 7M As shown, the second sacrificial layer 132" located in the high-voltage well region 101 is removed.

[0194] The second sacrificial layer 132 ″ located in the high-voltage well region 101 may be removed by a wet etching process to expose the first gate oxide layer 121 .

[0195] The surface of the first isolation structure 151 is higher than the surface of the first gate oxide layer 121 .

[0196] In some embodiments, the distance between the surface of the substrate 110 and the surface of the first isolation structure 151 is within a range of 20 nm to 40 nm. In other words, the height difference between the surface of the substrate 110 and the surface of the first isolation structure 151 is within a range of 20 nm to 40 nm. Alternatively, the difference between the depth h1 of the first groove 141 and the thickness h2 of the first isolation structure 151 is within a range of 20 nm to 40 nm.

[0197] For example, the distance between the surface of the substrate 110 and the surface of the first isolation structure 151 may be 21 nm, 23 nm, 25 nm, 27 nm, 29 nm, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, or 39 nm.

[0198] If the distance between the surface of the substrate 110 and the surface of the first isolation structure 151 is too large, the sidewalls of the first isolation structure 151 may be damaged. If the distance between the surface of the substrate 110 and the surface of the first isolation structure 151 is too small, the gate of the planar transistor may be damaged during subsequent processing. Therefore, in the embodiment of the present application, the distance between the surface of the substrate 110 and the surface of the first isolation structure 151 is controlled within the range of 20nm to 40nm.

[0199] S120, such as Figure 7N As shown, a second gate oxide layer 122 and a third gate oxide layer 123 are formed.

[0200] Alternatively, it can be understood that a second gate oxide layer 122 and a third gate oxide layer 123 are formed on the substrate 110, wherein the second gate oxide layer 122 is located in the first low-voltage well region 102a, the second gate oxide layer 122 is disposed on the substrate 110, and covers the second isolation structure 152. The third gate oxide layer 123 is located in the second low-voltage well region 102b, the third gate oxide layer 123 is disposed on the substrate 110, and covers the second isolation structure 152.

[0201] In some embodiments, before forming the second gate oxide layer 122 and the third gate oxide layer 123 , the auxiliary layer 180 needs to be etched away first.

[0202] In some embodiments, a method for forming the second gate oxide layer 122 and the third gate oxide layer 123 includes: forming a second gate oxide film, the second gate oxide film being located in the low-voltage well region 102, and the thickness of the second gate oxide film being less than the thickness of the first gate oxide layer 121; graphically etching the second low-voltage well region 102b, thinning the second gate oxide film in the second low-voltage well region 102b, and forming the second gate oxide layer 122 and the third gate oxide layer 123.

[0203] In other embodiments, the method for forming the second gate oxide layer 122 and the third gate oxide layer 123 includes: forming a third gate oxide film, wherein the third gate oxide film is located in the low-voltage well region 102; then, forming a second gate oxide film, wherein the second gate oxide film is located in the first low-voltage well region 102a, wherein the thickness of the third gate oxide film is less than the thickness of the second gate oxide film, and the sum of the thicknesses of the third gate oxide film and the second gate oxide film is less than the thickness of the first gate oxide layer 121; the second gate oxide film and the third gate oxide film located in the first low-voltage well region 102a constitute the second gate oxide layer 122, and the third gate oxide film located in the second low-voltage well region 102b constitutes the third gate oxide layer 123.

[0204] In the embodiment of the present application, there is no limitation on the formation of the second gate oxide layer 122 and the third gate oxide layer 123 , as long as the thickness of the third gate oxide layer 123 is less than the thickness of the second gate oxide layer 122 , and the thickness of the second gate oxide layer 122 is less than the thickness of the first gate oxide layer 121 .

[0205] S130, such as Figure 7O As shown, a planar transistor 191 and a Fin-FET device 192 are formed.

[0206] The planar transistor 191 is located in the high-voltage well region 101 , and the Fin-FET device 192 is located in the low-voltage well region 102 .

[0207] Regarding the method of forming the planar transistor 191 and the Fin-FET device 192, as shown in FIG. Figure 7P As shown, step S130 includes:

[0208] S131 , forming a first gate 201 and a second gate 202 .

[0209] Regarding the method for forming the first gate 201 and the second gate 202, step S130 includes:

[0210] S1311 , forming a gate layer on a side of the first gate oxide layer 121 , the second gate oxide layer 122 , and the third gate oxide layer 123 away from the substrate 110 .

[0211] The gate layer can be formed by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. For example, plasma chemical vapor deposition is used to form a polysilicon layer on the side of the first gate oxide layer 121, the second gate oxide layer 122, and the third gate oxide layer 123 away from the substrate 110, and the polysilicon layer is doped to form the gate layer.

[0212] S1312 , forming a patterned mask layer on a side of the gate layer away from the substrate 110 .

[0213] S1313 , etching the gate layer to form a first gate 201 and a second gate 202 .

[0214] The first gate 201 is located in the high-voltage well region 101 , and the second gate 202 is located in the low-voltage well region 102 .

[0215] S132, such as Figure 7Q As shown, a first gate spacer 211 covering the side of the first gate 201 and a second gate spacer 212 covering the side of the second gate are formed.

[0216] Exemplarily, silicon nitride is deposited on the side of the first gate oxide layer 121, the second gate oxide layer 122 and the third gate oxide layer 123 away from the substrate 110 by chemical vapor deposition, and then the silicon nitride on the surface of the first gate oxide layer 121, the second gate oxide layer 122 and the third gate oxide layer 123 is removed by dry etching to form a first gate sidewall 211 and a second gate sidewall 212.

[0217] During the process of forming the source and drain of the subsequent transistor, the first gate sidewall 211 can effectively protect the side of the first gate 201, and at the same time alleviate the problem caused by the first source 221 and the first drain 231 being too close to the channel when a large amount of ions are implanted into the substrate 110, resulting in the channel being too short, causing the first source 221 and the first drain 231 to be connected.

[0218] The first gate spacer 211 may be a single-layer structure or a stacked-layer structure. Exemplarily, the first gate spacer 211 is a single-layer structure, and the material of the first gate spacer 211 includes silicon nitride.

[0219] Similarly, the second gate sidewall 212 can also effectively protect the side of the second gate 202, while alleviating the problem that the second source 222 and the second drain 232 are too close to the channel when a large amount of ions are implanted into the substrate 110, resulting in the channel being too short, causing the second source 222 and the second drain 232 to be connected.

[0220] The second gate spacer 212 may be a single-layer structure or a stacked-layer structure. Exemplarily, the second gate spacer 212 is a single-layer structure, and the material of the second gate spacer 212 includes silicon nitride.

[0221] S133, such as Figure 7R As shown, doped regions 241 are formed on both sides of the first gate 201 , and the doped regions 241 extend from the surface of the substrate 110 into the substrate 110 . The doped regions 241 are located in the high-voltage well region 101 .

[0222] Exemplarily, a method for forming the doped region 241 includes forming a mask layer on the surface of the substrate 110, exposing an area for forming the doped region 241, and performing ion implantation in the exposed area to form the doped region 241. The implanted ions may be arsenic ions.

[0223] In the subsequent process, the first source 221 and the first drain 231 are arranged in the doped region 241. In this way, the doped region 241 can withstand part of the voltage, thereby effectively weakening the drain region electric field, thereby reducing the impact of the hot electron degradation effect on the first source 221 and the first drain 231.

[0224] S134, such as Figure 7S As shown, a first source electrode 221 , a first drain electrode 231 , a second source electrode 222 , and a second drain electrode 232 are formed.

[0225] Ion doping is performed on the substrate 110 on both sides of the first gate 201 and the second gate 202 to form a first source 221 and a first drain 231 on both sides of the first gate 201, and a second source 222 and a second drain 232 on both sides of the second gate 202. The ion doping method can be ion implantation or ion diffusion.

[0226] The above preparation method provided in the embodiments of the present application is not limited to any step sequence and can be reasonably adjusted as needed.

[0227] In addition, the steps S1-S130 described above may have some steps removed as needed, and are not limited to including every step. Some steps may also be added as needed, and are not limited to including only the steps described above.

[0228] The preparation method of the semiconductor structure provided in the embodiment of the present application only takes the example of setting the planar transistor 191 in the high-voltage well region 101 and the Fin-FET device 192 in the low-voltage well region 102, and is not limited to the semiconductor structure being limited to the high-voltage well region 101 and the low-voltage well region 102. It can also be applied to other semiconductor structures that require the integration of the planar transistor 191 and the Fin-FET device 192.

[0229] The method for preparing a semiconductor structure provided in an embodiment of the present application is to set the first isolation structure 151 higher than the substrate 110 and the height of the second isolation structure 152 lower than the substrate 110. It is possible to set the planar transistor 191 in the first well region 101 and the Fin-FET device 192 in the second well region 102. This can improve the integration of the semiconductor structure 100 and reduce the integration area. Moreover, when forming the second isolation structure 152 on the second well region 102, the protective layer 160 can effectively protect the first gate oxide layer 121 in the first well region 101, thereby reducing damage to the first gate oxide layer 121 in the first well region 101 when forming the second isolation structure 152. During the etching process, the auxiliary layer 180 can effectively protect the substrate 110 and the second isolation structure 152, thereby reducing damage to the substrate 110 and the second isolation structure 152 caused by the etching process. At the same time, the auxiliary layer 180 can also repair the sidewalls of the second groove 142 , thereby improving the cross-sectional characteristics between the substrate 110 and the second isolation structure 152 and protecting the active area of the substrate 110 when the protection layer 160 is removed.

[0230] The following examples illustrate the semiconductor structure provided in the embodiments of the present application. The semiconductor structure can be obtained by using the above-mentioned method for preparing the semiconductor structure.

[0231] Based on this, Figure 8 As shown, the semiconductor structure 100 includes a substrate 110 , a first isolation structure 151 , a second isolation structure 152 and a first gate oxide layer 121 .

[0232] The semiconductor structure 100 can be divided into a high-voltage well region 101 and a low-voltage well region 102. The low-voltage well region 102 includes a first low-voltage well region 102a and a second low-voltage well region 102b. The second low-voltage well region 102b is located on a side of the first low-voltage well region 102 away from the high-voltage well region 101.

[0233] The substrate 110 is provided with a first isolation structure 151 and a second isolation structure 152. The first isolation structure 151 is located in the high-voltage well region 101, and the second isolation structure 152 is located in the low-voltage well region 102. The second isolation structure 152 is provided in both the first low-voltage well region 102a and the second low-voltage well region 102b.

[0234] Alternatively, the substrate 110 includes a first groove 141 and at least one second groove 142. The first groove 141 is the boundary between the first isolation structure 151 and the substrate 110. Similarly, the second groove 142 is the boundary between the second isolation structure 152 and the substrate 110.

[0235] The first groove 141 is located in the high-pressure well region 101, and the second groove 142 is located in the low-pressure well region 102. In other words, the second groove 142 is provided in both the first low-pressure well region 102a and the second low-pressure well region 102b.

[0236] The present embodiment of the present application does not limit the number and depth of the first groove 141 and the second groove 142. For example, the depth h1 of the first groove 141 and the depth h3 of the second groove 142 are the same. An appropriate number of first grooves 141 and second grooves 142 can be fabricated based on the actual requirements of the three-dimensional memory 100. In the present embodiment of the present application, only one first groove 141 and two second grooves 142 are used as an example.

[0237] Regarding the first isolation structure 151, Figure 8 As shown, the thickness h2 of the first isolation structure 151 is greater than the depth h1 of the first groove 141. The depth direction of the first groove 141 refers to the direction perpendicular to the substrate 110. Alternatively, in the direction perpendicular to the substrate 110, the thickness h2 of the first isolation structure 151 is greater than the depth h1 of the first groove 141. In other words, the surface of the first isolation structure 151 is higher than the surface of the substrate 110, facilitating the subsequent formation of a planar transistor in the high-voltage well region 101.

[0238] In some embodiments, the distance between the surface of substrate 110 and the surface of first isolation structure 151 is in the range of 20 nm to 40 nm. For example, the distance between the surface of substrate 110 and the surface of first isolation structure 151 can be 21 nm, 23 nm, 25 nm, 27 nm, 29 nm, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, or 39 nm.

[0239] Regarding the second isolation structure 152, as shown in FIG. Figure 8 As shown, the thickness h4 of the second isolation structure 152 is less than the depth h3 of the second recess 142. The depth direction of the second recess 142 refers to the direction perpendicular to the substrate 110. Alternatively, in the direction perpendicular to the substrate 110, the thickness h4 of the second isolation structure 152 is less than the depth h3 of the second recess 142. In other words, the surface of the second isolation structure 152 is lower than the surface of the substrate 110, facilitating the subsequent formation of a Fin-FET device in the high-voltage well region 101.

[0240] In some embodiments, the distance between the surface of the second isolation structure 152 and the surface of the substrate 110 is in the range of 75nm to 85nm. For example, the distance between the surface of the second isolation structure 152 and the surface of the substrate 110 can be 76nm, 77nm, 78nm, 79nm, 80nm, 81nm, 82nm, 83nm or 84nm.

[0241] The embodiment of the present application does not limit the thickness of the second isolation structure 152 in each second groove 142 . Exemplarily, the thickness h4 of the second isolation structure 152 in each second groove 142 is the same.

[0242] During the execution of step S7 , the second isolation structures 152 with different thicknesses are obtained by controlling the etching time.

[0243] Regarding the first gate oxide layer 121, Figure 8 As shown, the first gate oxide layer 121 is located in the high-voltage well region 101. The first gate oxide layer 121 is disposed on the surface of the substrate 110 and exposes the first shallow isolation structure 151. Alternatively, the first gate oxide layer 121 has an opening in the middle, and the first shallow isolation structure 151 extends from the opening.

[0244] In some embodiments, the thickness of the first gate oxide layer 121 is in the range of 400 nm to 600 nm. For example, the thickness of the first gate oxide layer 121 is 420 nm, 450 nm, 475 nm, 498 nm, 523 nm, 530 nm, 550 nm, 570 nm, or 590 nm. The material of the first gate oxide layer 121 may include an oxide, such as silicon oxide.

[0245] The semiconductor structure 110 provided in the embodiment of the present application is as follows: Figure 9 As shown, it also includes: an auxiliary layer 180.

[0246] The auxiliary layer 180 is located in the low voltage well region 102 .

[0247] The auxiliary layer 180 is disposed on the surface of the substrate 110 and covers the wall of the second groove 142 away from the second isolation structure 152 .

[0248] The material of the auxiliary layer 180 may be oxide, for example, silicon oxide.

[0249] The auxiliary layer 180 is used to repair the sidewall of the second groove 142 on the substrate 110 and effectively protect the substrate 110 in the low-voltage well region 102 .

[0250] The semiconductor structure 110 provided in the embodiment of the present application is as follows: Figure 10 As shown, the structure further includes: a second gate oxide layer 122 and a third gate oxide layer 123 .

[0251] The second oxide layer 122 and the third oxide layer 123 are located in the low voltage well region 102 .

[0252] The second gate oxide layer 122 is located in the first low-voltage well region 102 a . The second oxide layer 122 is disposed on the substrate 110 and covers the second isolation structure 152 .

[0253] The third gate oxide layer 123 is located in the second low-voltage well region 102 b . The third oxide layer 123 is disposed on the substrate 110 and covers the second isolation structure 152 .

[0254] The thickness of the third gate oxide layer 123 is smaller than that of the second gate oxide layer 122, and the thickness of the second gate oxide layer 122 is smaller than that of the first gate oxide layer 121.

[0255] The semiconductor structure 110 provided in the embodiment of the present application is as follows: Figure 11 As shown, it also includes: a transistor.

[0256] The transistors include: a planar transistor 191 and a Fin-FET device 192 .

[0257] In some embodiments, the planar transistor 191 is disposed on the substrate 110 and located in the high-voltage well region 101 , and the Fin-FET device 192 is disposed on the substrate 110 and located in the low-voltage well region 102 .

[0258] The planar transistor 191 mainly includes a first gate 201 , a first gate spacer 211 , a first source 221 , a first drain 231 and a doped region 241 .

[0259] The first gate spacers 211 are disposed on both sides of the first gate 201 to protect the sides of the first gate 201. The material of the first gate spacers 211 may include silicon nitride.

[0260] The first gate spacer 211 may be a single-layer structure or a stacked-layer structure. Exemplarily, the first gate spacer 211 is a single-layer structure, and the material of the first gate spacer 211 includes silicon nitride.

[0261] The doped regions 241 are disposed on both sides of the first gate 201 and extend from the surface of the substrate 110 into the substrate 110. The doped regions 241 are used to effectively weaken the drain region electric field and prevent hot electron degradation effects.

[0262] The first source 221 and the first drain 231 are respectively disposed inside the doping region 241 and extend from the doping region 241 close to the surface of the first gate oxide layer 151 into the doping region 241 .

[0263] Regarding the Fin-FET device 192, as Figure 11 As shown, the Fin-FET device 192 mainly includes a second gate 202 , a second gate spacer 212 , a second source 222 and a second drain 232 .

[0264] Similarly, the second gate spacers 212 are disposed on both sides of the second gate 202 to protect the side surfaces of the second gate 202. The material of the second gate spacers 212 may include silicon nitride.

[0265] The second gate spacer 212 may be a single-layer structure or a stacked-layer structure. Exemplarily, the second gate spacer 212 is a single-layer structure, and the material of the second gate spacer 212 includes silicon nitride.

[0266] The second source 222 and the second drain 232 are respectively disposed on two sides of the second gate 202 and extend from the surface of the substrate 110 into the substrate 110 .

[0267] In the semiconductor structure provided by the embodiment of the present application, by disposing the first isolation structure 151 higher than the substrate 110 and the second isolation structure 152 lower than the substrate 110, the planar transistor 191 can be disposed in the first well region 101 and the Fin-FET device 192 can be disposed in the second well region 102. This can improve the integration level of the semiconductor structure 100 and reduce the integration area.

[0268] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: a first well region and a second well region; the first well region is a high-pressure well region; the second well region is a low-pressure well region; the low-pressure well region includes a first low-pressure well region and a second low-pressure well region; the second low-pressure well region is arranged on a side of the first low-pressure well region away from the high-pressure well region; A substrate comprising a first groove and at least one second groove, wherein the first groove is located in the first well region and the second groove is located in the second well region; A first isolation structure is disposed in the first groove; the thickness of the first isolation structure is greater than the depth of the first groove; a second isolation structure disposed in the second groove; a thickness of the second isolation structure being less than a depth of the second groove; and the first low-voltage well region and the second low-voltage well region being respectively provided with the second isolation structure; a first gate oxide layer, located in the first well region; The first gate oxide layer is disposed on the surface of the substrate and exposes the first isolation structure; a second gate oxide layer, located in the first low-voltage well region, the second gate oxide layer being disposed on the substrate and covering the second isolation structure; a third gate oxide layer, located in the second low-voltage well region, the third gate oxide layer being disposed on the substrate and covering the second isolation structure; The third gate oxide layer is connected to the second gate oxide layer.

2. The semiconductor structure according to claim 1, wherein: The first groove and the second groove have the same depth.

3. The semiconductor structure according to claim 2, wherein: The at least one second groove comprises a plurality of second grooves, and the second isolation structure in each second groove has the same thickness.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The distance between the surface of the second isolation structure and the surface of the substrate is in the range of 75 nm to 85 nm.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The distance between the surface of the substrate and the surface of the first isolation structure is in the range of 20 nm to 40 nm. The semiconductor structure according to claim 1 , wherein: The thickness of the third gate oxide layer is smaller than that of the second gate oxide layer.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a first source, a first drain, and a first gate located in the first well region; the first gate is disposed on the gate oxide layer, and the first source and the first drain are located on both sides of the first gate and extend from the surface of the substrate into the substrate; and / or, The semiconductor structure also includes a second source, a second drain and a second gate located in the second well region; the second source and the second drain extend from the surface of the substrate into the substrate, and the second gate spans the top surface and two opposite side surfaces of the second source and the second drain.

8. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure includes a first well region and a second well region; the first well region is a high-voltage well region; the second well region is a low-voltage well region; the low-voltage well region includes a first low-voltage well region and a second low-voltage well region; The second low-pressure well region is arranged on a side of the first low-pressure well region away from the high-pressure well region; The method for preparing the semiconductor structure comprises: forming a first gate oxide layer on the substrate; wherein the first gate oxide layer is located in the first well region; forming a first isolation structure and a second isolation column; the first isolation structure is located in the first well region, and the second isolation column is located in the second well region; the first isolation structure and the second isolation column are buried from the surface of the substrate into the substrate; forming a protective layer; the protective layer is located in the first well region and is disposed on a side of the first gate oxide layer away from the substrate; The second isolation column is etched to form a second isolation structure; the surface of the second isolation structure is lower than the surface of the substrate; the first low-voltage well region and the second low-voltage well region are respectively provided with the second isolation structure; removing the protective layer; forming a second gate oxide film, wherein the second gate oxide film is located in the low-voltage well region; The second gate oxide film located in the second low-voltage well region is thinned to form a second gate oxide layer and a third gate oxide layer, wherein the second gate oxide layer is located in the first low-voltage well region, the second gate oxide layer is arranged on the substrate, and covers the second isolation structure; the third gate oxide layer is located in the second low-voltage well region, the third gate oxide layer is arranged on the substrate, and covers the second isolation structure.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The material forming the protective layer includes: polysilicon, amorphous silicon or nitrogen-doped silicon carbide material.

10. The method for preparing a semiconductor structure according to claim 8, wherein: Before forming the first isolation structure and the second isolation column, the preparation method further includes: forming a first groove and at least one second groove; the first groove is located in the first well region, and the second groove is located in the second well region; the first groove and the second groove extend from the surface of the substrate into the substrate; Forming a first isolation structure and a second isolation column includes forming the first isolation structure in the first groove and forming the second isolation column in the second groove.

11. The method for preparing a semiconductor structure according to claim 8, wherein: After forming the first gate oxide layer on the substrate, the preparation method further comprises: A first sacrificial layer and a second sacrificial layer are formed on a substrate; the first sacrificial layer is located in the second well region, and the second sacrificial layer covers the first gate oxide layer and the first sacrificial layer.

12. The method for preparing a semiconductor structure according to claim 11, wherein: forming a second isolation structure, comprising: thinning the second sacrificial layer located in the second well region; The remaining second sacrificial layer, the first sacrificial layer and a portion of the second isolation pillars are removed to form the second isolation structure.

13. The method for preparing a semiconductor structure according to claim 12, wherein: After removing the protective layer, the method further includes: The second sacrificial layer located in the first well region is removed.

14. The method for preparing a semiconductor structure according to claim 8, wherein: Forming a protective layer, including: forming a protective film, wherein the protective film is located on a side of the first gate oxide layer away from the substrate; forming a first mask layer located in the first well region on the protective film; The protection film located in the second well region is removed to form the protection layer.

15. The method for preparing a semiconductor structure according to claim 14, wherein: Before forming a first mask layer located in the first well region on the protective film, the method further includes: A third sacrificial layer is formed on the protection film.

16. The method for preparing a semiconductor structure according to claim 8, wherein: Removing the protective layer comprises: forming a second mask layer; the second mask layer is located in the second well region and covers the second isolation structure and the substrate; The protective layer is removed.

17. The method for preparing a semiconductor structure according to claim 16, wherein: Before forming the second mask layer, the method further includes: forming an auxiliary film, wherein the auxiliary film covers the protective layer and the substrate; Before removing the protective layer, the method further includes: The auxiliary film located in the first well region is removed.

18. A three-dimensional memory, characterized in that: include: electrically connected memory arrays and peripheral devices; The memory array includes an array of memory cell strings; The peripheral device includes: a first well region and a second well region, and a first isolation structure extending into a substrate and a second isolation structure located in the substrate; the first well region is a high-voltage well region; the second well region is a low-voltage well region; the low-voltage well region includes a first low-voltage well region and a second low-voltage well region; the second low-voltage well region is located on a side of the first low-voltage well region away from the high-voltage well region; the surface of the first isolation structure is higher than the surface of the substrate, and the surface of the second isolation structure is lower than the surface of the substrate; the first isolation structure is located in the first well region, and the second isolation structure is located in the second well region; the first low-voltage well region and the second low-voltage well region are respectively provided with the second isolation structure; The peripheral device further includes a first gate oxide layer, a first source electrode, a first drain electrode, and a first gate electrode located in the first well region; the first gate oxide layer is disposed on the surface of the substrate and exposes the first isolation structure; the first gate electrode is disposed on the first gate oxide layer; The peripheral device also includes a second source, a second drain, a second gate oxide layer, a third gate oxide layer and a second gate located in the second well region; the second gate oxide layer is arranged on the substrate and covers the second isolation structure; the third gate oxide layer is arranged on the substrate and covers the second isolation structure; the third gate oxide layer is connected to the second gate oxide layer.

19. The three-dimensional memory according to claim 18, wherein: The first source and the first drain are located on both sides of the first gate and extend from the surface of the substrate into the substrate; the second source and the second drain extend from the surface of the substrate into the substrate, and the second gate spans the top surface and two opposite side surfaces of the second source and the second drain.

20. A storage device, characterized in that: The device comprises a controller and the three-dimensional memory according to claim 18 or 19, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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