Charge pump circuit to reduce noise

Abstract

The present invention discloses a charge pump circuit for reducing noise, comprising a first controlled switch unit connected to the upper plates of a first pump capacitor C1 and a second pump capacitor C2, and a second controlled switch unit connected to the lower plates of the first pump capacitor C1 and the second pump capacitor C2; the first controlled switch unit also comprises a charging current limiting resistor and a discharging current limiting resistor; a non-overlapping clock signal is generated to control the switch to open and close, so that an input power source charges the first pump capacitor and the second pump capacitor respectively, and enables the first pump capacitor C1 and the second pump capacitor C2 to transfer the charged charge to a load capacitor C3 respectively; and the charging current limiting resistor and the discharging current limiting resistor are switched in or out by controlling the switch to open and close.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a charge pump circuit capable of reducing noise. Background Art

[0002] With the development of science and technology, semiconductor devices are increasingly being used due to their own advantages. Among them, the stability and noise of the charge pump that generates negative pressure in analog integrated circuits are particularly important. In actual use, the noise level of the charge pump output voltage will directly affect the reliability of the circuit where the charge pump is located.

[0003] Nowadays, charge pumps use the charging and discharging of capacitors to achieve voltage conversion, with the input circuit and the output circuit being turned on in turn. The internal FET switch array controls the charging and discharging of the fast capacitor in a certain way, so that the input voltage is reduced by a certain factor, thereby obtaining the required output voltage. Since the circuit works as a switch, the charge pump structure will also generate certain output ripple and EMI (electromagnetic interference).

[0004] Figure 3 It is a traditional charge pump circuit, in which Mp1~Mp4 are pmos tubes, Mn1~Mn4 are nmos tubes, they are all used as switches, C1~C3 are capacitors, C1 and C2 are pump capacitors, C3 is the output capacitor, Vin is the input voltage, CLK_A and CLK_A_N are logic control signals.

[0005] CLK_A and CLK_A_N are the clock control signals of the charge pump, and MOS tubes Mp1~ Mp4 and Mn1~ Mn4 form the switch unit. Figure 3 Without too much noise reduction processing, the original circuit is controlled by two control signals CLK_A and CLK_A_N. When CLK_A_N and CLK_A are switched, Mp1 and Mn1, Mp2 and Mn2, Mp3 and Mn3, Mp4 and Mn4, Mn4 and Mn3, Mp3 and Mp4 will be closed at the same time, and current will flow between them, resulting in crosstalk, excessive current and voltage noise and output voltage loss. In addition, the current is limited at the moment of switch closing, resulting in a large current at the moment of switch turning on, resulting in large output ripple and EMI (electromagnetic interference). Summary of the invention

[0006] The present invention provides a charge pump circuit with reduced noise to solve the technical problems of serious crosstalk between MOS tubes in the current charge pump circuit, large instantaneous current when the MOS tube is closed, large output voltage noise, and output voltage loss. The present invention adopts the following technical solutions.

[0007] A charge pump circuit for reducing noise, comprising: a clock unit, a capacitor unit and a switch unit;

[0008] The capacitor unit includes a first pump capacitor C1, a second pump capacitor C2 and a load capacitor C3;

[0009] The switch unit comprises a first controlled switch unit connected to the upper plates of the first pump capacitor C1 and the second pump capacitor C2, and a second controlled switch unit connected to the lower plates of the first pump capacitor C1 and the second pump capacitor C2; the first controlled switch unit and the second controlled switch unit both comprise a plurality of switches, and the first controlled switch unit further comprises a charging current limiting resistor and a discharging current limiting resistor; the switches in the first controlled switch unit and the second controlled switch unit are both opened or closed by the clock unit signal;

[0010] A clock unit is connected to the control ends of the first controlled switch unit and the second controlled switch unit, and is used to generate non-overlapping clock signals to control the opening and closing of switches in the first controlled switch unit and the second controlled switch unit, so that the input power supply charges the first pump capacitor and the second pump capacitor respectively, and enables the first pump capacitor C1 and the second pump capacitor C2 to transfer the charged charge to the load capacitor C3 respectively; and the charging current limiting resistor and the discharging current limiting resistor are switched in or out by controlling the switch to be opened and closed.

[0011] Further, it includes: the first controlled switch unit includes the first to eighth switches, the first ends of the third switch and the fifth switch are connected to the input power supply through the charging current limiting resistor, the second end of the third switch and the first end of the fourth switch are commonly connected to the first node N1, the second end of the fifth switch is connected to the first end of the sixth switch and is commonly connected to the second node N2, the second end of the fourth switch and the second end of the sixth switch are both connected to the ground GND through the discharging current limiting resistor, and the first node N1 and the second node N2 are respectively connected to the upper plate of the first pump capacitor C1 and the upper plate of the second pump capacitor;

[0012] Two ends of the first switch are respectively connected to the input power supply and the first node N1, and two ends of the second switch are respectively connected to the first node N1 and the ground GND;

[0013] Two ends of the seventh switch are connected to the input power supply and the second node N2 respectively, and two ends of the eighth switch are connected to the second node N2 and the ground GND respectively.

[0014] Furthermore, the control ends of the first controlled switch unit are respectively the control ends of the first to eighth switches.

[0015] Further, the first controlled switch unit includes first to eighth switches, the first ends of the third switch and the fifth switch are connected to the input power supply through the charging current limiting resistor, the second end of the third switch and the first end of the fourth switch are commonly connected to the first node N1, the second end of the fifth switch is connected to the first end of the sixth switch and is commonly connected to the second node N2, the second end of the fourth switch and the second end of the sixth switch are both connected to the ground GND through the discharging current limiting resistor, and the first node N1 and the second node N2 are respectively connected to the upper plate of the first pump capacitor C1 and the upper plate of the second pump capacitor C2;

[0016] A first end of the first switch is connected to an input power supply, and a second end is connected to a node between the third switch and a charging current limiting resistor;

[0017] A first end of the second switch is connected to a node between the fourth switch and the discharge current limiting resistor; a second end of the second switch is connected to the ground GND;

[0018] A first end of the seventh switch is connected to the input power supply, and a second end is connected to a node between the sixth switch and the charging current limiting resistor;

[0019] A first end of the eighth switch is connected to a node between the sixth switch and the discharge current limiting resistor; and a second end of the eighth switch is connected to the ground GND.

[0020] Further, the second controlled switch unit includes a ninth to twelfth switch, the first ends of the ninth switch and the eleventh switch are both connected to the ground GND, the second end of the ninth switch and the first end of the tenth switch are commonly connected to the third node N3, the second end of the eleventh switch and the first end of the twelfth switch are commonly connected to the fourth node N4, the second ends of the tenth switch and the twelfth switch are both connected to the lower plate of the load capacitor C3, the upper plate of the load capacitor C3 is connected to the ground GND, the lower plate of the first pump capacitor C1 is connected to the third node N3 and the control end of the twelfth switch, and the lower plate of the second pump capacitor C2 is connected to the fourth node N4 and the control end of the tenth switch.

[0021] Furthermore, the control ends of the second controlled switch unit are respectively the control ends of the ninth switch and the eleventh switch.

[0022] Further, the first switch, the third switch, the fifth switch, the seventh switch, the ninth switch and the eleventh switch are all Mp type switches, and the control end input of the Mp type switch is turned on by a low level input, and is cut off by a low or high level input; the second switch, the fourth switch, the sixth switch, the eighth switch and the tenth switch are all Mn type switches, and the control end input of the Mn type switch is turned on by a high level input, and is cut off by a low level.

[0023] The beneficial technical effects achieved by the present invention are as follows: the noise-reducing charge pump circuit provided by the present invention can solve the crosstalk phenomenon between MOS tubes, reduce the maximum current flowing through the MOS tubes, reduce the noise of the current and output voltage, and has a more obvious current noise suppression effect, thereby improving circuit efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the structure of a charge pump circuit provided in Embodiment 1 of the present invention;

[0025] Figure 2 A schematic diagram of the structure of a charge pump circuit provided in Embodiment 2 of the present invention;

[0026] Figure 3 It is a schematic diagram of the structure of a charge pump circuit in the prior art;

[0027] Figure 4 A comparison diagram of simulation results of the charge pump circuit provided in Example 1 and the charge pump circuit in the prior art;

[0028] Figure 5 A voltage output waveform diagram of the charge pump circuit provided in Example 1 and a simulation result of a charge pump circuit in the prior art;

[0029] Figure 6 A logic schematic diagram of a charge pump circuit provided in Embodiment 1 of the present invention;

[0030] Figure 7 The relationship between the logic timing diagrams of the charge pump circuit CLK_A and CLK_A_N provided in Embodiment 1 of the present invention;

[0031] The reference numerals are: 1-first switch; 2-second switch; 3-third switch; 4-fourth switch; 5-fifth switch; 6-sixth switch; 7-seventh switch; 8-eighth switch; 9-ninth switch; 10-tenth switch; 11-eleventh switch; 12-twelfth switch;

[0032] N1-first node; N2-second node; N3-third node; N4-fourth node. DETAILED DESCRIPTION

[0033] The low noise charge pump circuit and the working method thereof of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0035] Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, when the phrases "in one embodiment" or "in some embodiments" appear in various places throughout the specification, not all references are to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0036] Embodiment 1: A charge pump circuit for reducing noise, comprising: Figure 1 As shown, it includes a clock unit, a capacitor unit and a switch unit, and contains 4 resistors and 12 switches;

[0037] The capacitor unit includes a first pump capacitor C1, a second pump capacitor C2 and a load capacitor C3;

[0038] The switch unit comprises a first controlled switch unit connected to the upper plates of the first pump capacitor C1 and the second pump capacitor C2, and a second controlled switch unit connected to the lower plates of the first pump capacitor C1 and the second pump capacitor C2; the first controlled switch unit and the second controlled switch unit both comprise a plurality of switches, and the first controlled switch unit further comprises a charging current limiting resistor and a discharging current limiting resistor; the switches in the first controlled switch unit and the second controlled switch unit are both opened or closed by the clock unit signal;

[0039] A clock unit is connected to the control ends of the first controlled switch unit and the second controlled switch unit, and is used to generate non-overlapping clock signals to control the opening and closing of switches in the first controlled switch unit and the second controlled switch unit, so that the input power supply charges the first pump capacitor and the second pump capacitor respectively, and enables the first pump capacitor C1 and the second pump capacitor C2 to transfer the charged charge to the load capacitor C3 respectively; and the charging current limiting resistor and the discharging current limiting resistor are switched in or out by controlling the switch to be opened and closed.

[0040] The first controlled switch unit includes first to eighth switches, a first end of the third switch 3 is connected to the input power supply through a charging current limiting resistor R1, and a first end of the fifth switch 5 is connected to the input power supply through a charging current limiting resistor R2; a second end of the third switch 3 and a first end of the fourth switch 4 are commonly connected to a first node N1, a second end of the fifth switch 5 and a first end of the sixth switch 6 are commonly connected to a second node N2, a second end of the fourth switch is connected to the ground GND through a discharging current limiting resistor R3; and a second end of the sixth switch is connected to the ground GND through a discharging current limiting resistor R4;

[0041] The first node N1 and the second node N2 are respectively connected to the upper plate of the first pump capacitor C1;

[0042] Two ends of the first switch 1 are respectively connected to the input power supply Vin and the first node N1, and two ends of the second switch are respectively connected to the first node N1 and the ground GND;

[0043] Two ends of the seventh switch are connected to the input power source Vin and the second node N2 respectively, and two ends of the eighth switch are connected to the second node N2 and the ground GND respectively.

[0044] The control ends of the first controlled switch unit are respectively the control ends of the first to eighth switches.

[0045] The second controlled 2 switch unit includes a ninth to twelfth switch, the first ends of the ninth switch 9 and the eleventh switch 11 are both connected to the ground GND, the second end of the ninth switch 9 and the first end of the tenth switch 10 are commonly connected to the third node N3, the second end of the eleventh switch 11 and the first end of the twelfth switch 12 are commonly connected to the fourth node N4, the second ends of the tenth switch 10 and the twelfth switch 12 are both connected to the lower plate of the load capacitor C3, the upper plate of the load capacitor C3 is connected to the ground GND, the lower plate of the first pump capacitor C1 is connected to the third node N3 and the control end of the twelfth switch 12, and the lower plate of the second pump capacitor C2 is connected to the fourth node N4 and the control end of the tenth switch 10.

[0046] This implementation assumes that the first switch 1, the third switch 3, the fifth switch 5, the seventh switch 7, the ninth switch 9 and the eleventh switch 11 are all switches of the Mp model, see Mp1 to Mp6 in the figure;

[0047] The second switch 2, the fourth switch 4, the sixth switch 6, the eighth switch 8, the tenth switch 10 and the twelfth switch 12 are all switches of the Mn model, see Mn1 to Mn6 in the figure.

[0048] As shown in the figure, the charge pump circuit has eight control signals for controlling switches. Among them, Mp1~Mp6 and Mn1~Mn6 are used as switches, R1~R4 are resistors that limit current, C1~C3 are capacitors, among which C1 and C2 are pump capacitors, C3 is the output load capacitor, Vin is the input voltage, SW_A_A, SW_B_A, CLK_A_RS, CLK_A, SW_A_B, SW_B_B, CLK_A_RS_N, CLK_A_N are logic control signals.

[0049] Mp type is that the control end is off when it is high level, and on when it is low level, Mn is that the control end is on when it is high level, and off when it is low level. That is, when the control end of Mp1~Mp6 is low level, the switch is on, and when the control end is high level, the switch is off and not on. Mn1~Mn6 is opposite to Mp1~Mp6, the control end is on when it is high level, and off when it is low level.

[0050] like Figure 1 As shown, when Mp1 is closed, Mp3 is disconnected, Mn1 is disconnected, and Mp5 is disconnected, the potential of capacitor C1 rises gradually through Mp1 and resistor R1.

[0051] When Mp1 is closed, Mp3 is closed, Mn1 is disconnected, and Mp5 is closed, the input power flows through Mp3, the first pump capacitor C1, and Mp5 via Vin, the capacitor C1 is charged, the current limiting resistor R1 is cut out, and the charging current increases.

[0052] When Mp1 is disconnected, Mn1 is closed, Mn5 is disconnected, and Mp5 is disconnected, the voltage between the upper and lower plates of capacitor C1 decreases slowly through resistors R3 and Mn1.

[0053] When Mp1 is disconnected, Mn1 is closed, Mn3 is closed and Mn5 is closed, Mp5 is disconnected. At this time, the discharge circuit includes Mn3, the first pump capacitor C1, Mn5 and the load capacitor C3. The capacitor C1 discharges to supply energy to C3, the resistor R3 is cut out, and the charging current increases.

[0054] In this embodiment, the circuit is bilaterally symmetrical and the components are the same, so they will not be described in detail.

[0055] The central control signals of the circuits on both sides are CLK_A and CLK_A_N. The remaining control signals SW_A_A, SW_B_A, and CLK_A_RS on the left are converted based on CLK_A, and the remaining control signals SW_A_B, SW_B_B, and CLK_A_RS_N on the right are converted based on CLK_A_N.

[0056] The circuit is improved from a mutually coupled charge pump. C1 and C2 are used as pump capacitors. The circuit first charges C1 and C2 alternately, and then C1 and C2 alternately provide charge to the load capacitor C3. When C1 charges C3, the circuit charges C2; when C2 charges C3, the circuit charges C1. C1 and C2 alternately supply power to C3, so that the power supply time to C3 is increased within one clock cycle signal.

[0057] This embodiment also solves the problem of large instantaneous current when the MOS tube is turned on. First, the circuits Mp1 and Mn1, Mp2 and Mn2 form an inverter. During the switching of the inverter control signal, a large amount of instantaneous current will pass through the middle of the inverter. The resistors R1~R4 are connected at both ends of the inverter to limit the current from Vin on the inverter to the ground.

[0058] Secondly, when CLK_A is at a high level, that is, Mp1 is disconnected and Mn1 is closed (setting 0 potential as a low level and Vin as a high level), the first pump capacitor C1 is grounded through the turned-on Mn1 and the resistor in series therewith. Assuming that C1 is at 0 potential at this time, when CLK_A changes from a high level to a low level, Mp1 is closed and Mn1 is disconnected. CLK_A_RS changes from a high level to a low level earlier than CLK_A, and Mn3 is disconnected, that is, Mn3 is disconnected first and then Mp1 is turned on, to avoid the crosstalk problem that the switches should be in the on state at the same time. At this time, Mp1 is turned on and Mn1 is turned off. At this time, C The voltage difference between 1 and Vin is Vin, and resistor R1 limits the peak current of capacitor charging, which is less than Vin / R1. At the same time, in the process of the potential rising of the upper and lower plates of C1, Mp5 and Mn5 are also in the off state, limiting the charging from the lower plate of C1. In the process of capacitor C1 charging through resistor R1, Mp3 and Mn3 are in the off state. When the potential on C1 rises to a certain level, Mp3 is turned on, and then Mp5 controlled by SW_B_A is turned on. There is no series resistance on Mp3, but C1 reduces the potential difference between the upper plate and Vin, and the lower plate and ground through resistor R1. When Mp3 is turned on, its peak current will be reduced a lot, and the turning on of Mp3 will make the upper plate potential of C1 quickly approach Vin. The turning on of Mp5 makes C1 replenish a large amount of charge, and the lower plate is close to 0V, which reduces voltage loss and current noise (electromagnetic interference).

[0059] After C1 is charged to a certain level, it starts the discharge process (the process of C1 providing charge to C3). The discharge process starts when CLK_A changes from a low level to a high level. CLK_A is a high level, Mp1 is disconnected, and Mn1 is closed. Before CLK_A rises to a high level, SW_A_A must rise to a high level earlier than CLK_A. When SW_A_A is a high level, Mp3 is disconnected, and SW_B_A must also rise to a high level in advance. When SW_B_A is a high level, Mp5 is disconnected. That is, Mp3 and Mp5 must be disconnected before Mp1 is disconnected and Mn1 is closed. The advance time of the two control logics should be as short as possible to reduce crosstalk and voltage loss between MOS tubes. CLK_A rises to a high level and Mn1 is turned on. The current is limited by resistor R3. At this time, Mn3 is in the disconnected state. When the voltage of the upper plate of C1 is pulled down to a certain value, CLK_A_RS changes from a low level to a high level, and Mn3 is turned on, so that the potential of C1 quickly approaches the zero potential. At this time, the lower plate of C1 will stabilize at a negative voltage value. When the voltage of C2 on the right is charged to a certain level, the potential of its lower plate is close to 0V, Mn5 is turned on, and C1 replenishes the charge for C3.

[0060] The logic control signal on the right is the same as the left one in terms of logic timing, except that there is a 180-degree phase difference between the left and right signals. SW_A_A corresponds to SW_A_B, SW_B_A corresponds to SW_B_B, CLK_A_RS corresponds to CLK_A_RS_N, and CLK_A corresponds to CLK_A_N. Because Mn5 and Mn6 are the lower plate voltage control switches of C1 and C2, in order to realize the above logic control function, the duty cycle of CLK_A and CLK_A_N must be greater than 50%.

[0061] This circuit can also use 12 separate control signals to control 12 switches, but in order to improve circuit efficiency and simplify control logic, 8 control signals are used. If each switch is controlled by a separate logic, Mn1 needs to be turned off (i.e., the switch is disconnected) when Mp1 is switched on, and Mp1 needs to be turned off (i.e., the switch is disconnected) when Mn1 is switched on. Mn5 needs to be turned on after the negative voltage of the lower board of C1 is stable (so as to reduce the ripple voltage peak during the charging process of C3 and reduce the output voltage noise), that is, switch Mn5 needs to be turned on after Mn4 is turned on, and Mn5 needs to be turned off before Mn4 is turned off. The control method on the right is the same as that on the left, which will increase the control difficulty and reduce efficiency.

[0062] Embodiment 2: The charge pump circuit provided in this embodiment is as follows Figure 2As shown, the first controlled switch unit includes the first to eighth switches, the first ends of the third switch and the fifth switch are connected to the input power supply through the charging current limiting resistor, the second end of the third switch and the first end of the fourth switch are commonly connected to the first node N1, the second end of the fifth switch is connected to the first end of the sixth switch and is commonly connected to the second node N2, the second end of the fourth switch and the second end of the sixth switch are both connected to the ground GND through the discharging current limiting resistor, and the first node N1 and the second node N2 are respectively connected to the upper plate of the first pump capacitor C1;

[0063] A first end of the first switch is connected to an input power supply, and a second end is connected to a node between the third switch and a charging current limiting resistor;

[0064] A first end of the second switch is connected to a node between the fourth switch and the discharge current limiting resistor; a second end of the second switch is connected to the ground GND;

[0065] A first end of the seventh switch is connected to the input power supply, and a second end is connected to a node between the sixth switch and the charging current limiting resistor;

[0066] A first end of the eighth switch is connected to a node between the sixth switch and the discharge current limiting resistor; and a second end of the eighth switch is connected to the ground GND.

[0067] This embodiment can realize a structure with similar functions as that of embodiment 1, such as Figure 2 As shown, Mp1~Mp6 and Mn1~Mn6 are all used as switches, R1~R4 are resistors that limit the current, C1~C3 are capacitors, among which C1 and C2 are pump capacitors, C3 is the output load capacitor, Vin is the input voltage, SW_A_A, SW_B_A, CLK_A_RS, CLK_A, SW_A_B, SW_B_B, CLK_A_RS_N, CLK_A_N are logic control signals.

[0068] Mp3, Mp4, Mn3, Mn4 and resistors R1, R2, R3, R4 are connected in parallel, and Figure 1 In comparison, the logic SW_A_A, CLK_A_RS, SW_A_B, CLK_A_RS_N that controls the shutdown of Mp3, Mp4, Mn3, and Mn4 does not need to jump to a low level earlier than CLK_A and CLK_A_N, because the logic that controls the start and end of charging and discharging of the pump capacitor is CLK_A and CLK_A_RS, which is more logically implemented. Figure 1 It is easy to implement. Circuit Figure 1 and Figure 2 Under the same switch, capacitance and resistance parameters, Figure 1 The output voltage of the structure is slightly better than Figure 2, because when the switch is turned on, there is a certain impedance in Mp3, Mp4, Mn3, and Mn4, which are not directly connected to capacitors C1 or C2. The resistance from the positive electrode of the capacitor to VDD and VSS is higher. Figure 2 The output voltage of the circuit structure will be higher than Figure 1 There is a lot of voltage loss.

[0069] From the circuit Figure 1~Figure 2 That is, the circuit structures provided in Example 1 and Example 2 have the same effect. Here, Example 1 and the prior art are simulated, and the results are compared. Figure 4 , this simulation data takes the power supply voltage of 2.5V as an example. Figure 4 The following are the output current waveforms of the charge pump circuit power supply of Example 1 and the prior art, wherein the current pulse with the highest value (solid line) is Figure 3 The structure with the smallest current peak (dashed line) is the structure of Example 1, and the peak current is greatly reduced.

[0070] Figure 5 : is a waveform diagram of the simulated voltage output of Example 1 and the prior art, wherein the waveform with the smallest absolute voltage value (solid line) and the largest voltage noise is the top waveform, which corresponds to the prior art, i.e. Figure 3 The circuit structure with the smallest voltage ripple and the largest absolute value (dashed line) is Example 1. Figure 1 The structure shown.

[0071] It can be seen from the voltage and current simulation that the circuit structure provided in the present application effectively reduces the peak current and voltage noise, and also reduces the voltage loss.

[0072] Figure 6 This is a timing diagram for realizing the left half logic control. For easy identification, each logic path is expanded in the vertical direction, while the horizontal direction is the same time coordinate axis. Figure 7 Represents the relationship between the CLK_A and CLK_A_N logic timing diagrams. The left logic is centered on CLK_A, and the right logic is centered on CLK_A_N. CLK_A and CLK_A_N also determine the relationship between the left and right circuits. The right half logic is the same as the left circuit logic, but the phase difference is 180 degrees. Figure 6 and Figure 7 It can be achieved Figure 1 , Figure 2 The logical function of the circuit structure shown.

[0073] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A charge pump circuit for reducing noise, characterized in that include: A clock unit, a capacitor unit and a switch unit; The capacitor unit includes a first pump capacitor, a second pump capacitor and a load capacitor; A switch unit, comprising a first controlled switch unit connected to the upper plates of the first pump capacitor and the second pump capacitor, and a second controlled switch unit connected to the lower plates of the first pump capacitor and the second pump capacitor; the first controlled switch unit and the second controlled switch unit both comprise a plurality of switches, and the first controlled switch unit further comprises a charging current limiting resistor and a discharging current limiting resistor; the switches in the first controlled switch unit and the second controlled switch unit are both opened or closed by the clock unit signal; a clock unit connected to the control ends of the first controlled switch unit and the second controlled switch unit, and used for generating non-overlapping clock signals to control the switches in the first controlled switch unit and the second controlled switch unit to be opened or closed, so that the input power source charges the first pump capacitor and the second pump capacitor respectively, and enables the first pump capacitor and the second pump capacitor to transfer the charged charge to the load capacitor respectively; and switching the charging current limiting resistor and the discharging current limiting resistor in or out by controlling the switch to open and close; Wherein, the first controlled switch unit includes the first to eighth switches, the first ends of the third switch and the fifth switch are respectively connected to the input power supply through the charging current limiting resistor, the second end of the third switch and the first end of the fourth switch are commonly connected to the first node N1, the second end of the fifth switch and the first end of the sixth switch are commonly connected to the second node N2, the second end of the fourth switch and the second end of the sixth switch are respectively connected to the ground GND through the discharging current limiting resistor, and the first node N1 and the second node N2 are respectively connected to the upper plates of the first pump capacitor C1 and the first pump capacitor C2; Two ends of the first switch are respectively connected to the input power supply and the first node N1, and two ends of the second switch are respectively connected to the first node N1 and the ground GND; Two ends of the seventh switch are respectively connected to the input power supply and the second node N2, and two ends of the eighth switch are respectively connected to the second node N2 and the ground GND; The control ends of the first controlled switch unit are respectively the control ends of the first to eighth switches; or; The first controlled switch unit includes first to eighth switches, the first ends of the third switch and the fifth switch are respectively connected to the input power supply through the charging current limiting resistor, the second end of the third switch and the first end of the fourth switch are commonly connected to the first node N1, the second end of the fifth switch and the first end of the sixth switch are commonly connected to the second node N2, the second end of the fourth switch and the second end of the sixth switch are respectively connected to the ground GND through the discharging current limiting resistor, and the first node N1 and the second node N2 are respectively connected to the upper plate of the first pump capacitor C1 and the upper plate of the second pump capacitor C2; A first end of the first switch is connected to an input power supply, and a second end is connected to a node between the third switch and a charging current limiting resistor; A first end of the second switch is connected to a node between the fourth switch and the discharge current limiting resistor; a second end of the second switch is connected to the ground GND; A first end of the seventh switch is connected to the input power supply, and a second end is connected to a node between the fifth switch and the charging current limiting resistor; A first end of the eighth switch is connected to a node between the sixth switch and the discharge current limiting resistor; and a second end of the eighth switch is connected to the ground GND.

2. The charge pump circuit for reducing noise according to claim 1, characterized in that: The second controlled switch unit includes a ninth to twelfth switch, the first ends of the ninth switch and the eleventh switch are both connected to the ground GND, the second end of the ninth switch and the first end of the tenth switch are commonly connected to the third node N3, the second end of the eleventh switch and the first end of the twelfth switch are commonly connected to the fourth node N4, the second ends of the tenth switch and the twelfth switch are both connected to the lower plate of the load capacitor C3, the upper plate of the load capacitor C3 is connected to the ground GND, the lower plate of the first pump capacitor C1 is connected to the third node N3 and the control end of the twelfth switch, and the lower plate of the second pump capacitor C2 is connected to the fourth node N4 and the control end of the tenth switch.

3. The charge pump circuit for reducing noise according to claim 2, characterized in that: The control ends of the second controlled switch unit are respectively the control ends of the ninth switch and the eleventh switch.

4. The charge pump circuit for reducing noise according to claim 2, characterized in that: The first switch, the third switch, the fifth switch, the seventh switch, the ninth switch and the eleventh switch are all Mp type switches, and a low level input to the control end of the Mp type switch turns it on, and a high level input turns it off; the second switch, the fourth switch, the sixth switch, the eighth switch and the tenth switch are all Mn type switches, and a high level input to the control end of the Mn type switch turns it on, and a low level input turns it off.

Images