Line driver with adjustable current mirror array

Abstract

Embodiments of the present application disclose a line driver with an adjustable current mirror array. The line driver includes a first resistive element, a second resistive element, an operational amplifier, and an adjustable current mirror array circuit. A first end of the second resistive element and the first resistive element are coupled to a node, and a second end of the second resistive element is coupled to an output terminal. The operational amplifier receives a common mode voltage via the first resistive element, and generates a first signal and a second signal according to the common mode voltage and an input signal. The adjustable current mirror array circuit generates a first current to the node and a second current to the output terminal in response to the first signal and the second signal, and adjusts a ratio between the second current and the first current in response to a plurality of control bits to set an output impedance of the output terminal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of line driver, in particular to a line driver with adjustable current mirror array. BACKGROUND

[0002] Line drivers can be applied in network systems to improve driving capability. In order to improve the quality of transmitted data, the output impedance of the line driver needs to be matched with the impedance of the transmission line. In the prior art, the line driver uses a resistance array formed by multiple switches and multiple resistors to adjust the output impedance. However, in actual applications, due to the influence of process variation, the resistance values of the multiple resistors will deviate, thereby making the output impedance inaccurate and reducing impedance matching. In addition, since the data signals received or transmitted by the line driver have a large voltage swing, a transistor with high voltage resistance is usually used to implement the multiple switches, which does not meet the needs or design limitations of some applications (such as advanced processes). SUMMARY

[0003] The present application provides a line driver with adjustable current mirror array.

[0004] In some embodiments, the line driver includes a first resistive element, a second resistive element, an operational amplifier, and an adjustable current mirror array circuit. A first end of the second resistive element and the first resistive element are coupled to a node, and a second end of the second resistive element is coupled to an output terminal. The operational amplifier receives a common mode voltage via the first resistive element and generates a first signal and a second signal according to the common mode voltage and an input signal. The adjustable current mirror array circuit generates a first current to the node and a second current to the output terminal in response to the first signal and the second signal, and adjusts the ratio between the second current and the first current in response to multiple control bits to set an output impedance of the output terminal.

[0005] The features, implementations, and effects of the present application are described in detail below with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of a line driver according to some embodiments of the present application;

[0007] Figure 2 A schematic diagram of the adjustable current mirror array circuit in Figure 1 according to some embodiments of the present application;

[0008] Figure 3 A schematic diagram of the current mirror circuit in Figure 2 according to some embodiments of the present application;

[0009] Figure 4 a schematic diagram of a current mirror circuit in accordance with some embodiments of the present application; and Figure 2 a schematic diagram of a current mirror circuit in accordance with some embodiments of the present application; and

[0010] Figure 5 a schematic diagram of a current mirror circuit in accordance with some embodiments of the present application; and Figure 2 a schematic diagram of a current mirror circuit in accordance with some embodiments of the present application; and DETAILED DESCRIPTION

[0011] All words used herein are to be interpreted according to their normal and customary meaning. Definitions of words in common dictionaries are included in the content of the present application, and the use of any of the words discussed herein is merely an example and should not limit the scope and meaning of the present application. Likewise, the present application is not limited to the various embodiments shown in the specification.

[0012] As used herein, "coupled" or "connected" can mean two or more elements are in direct physical or electrical contact with one another, or can mean that two or more elements are not in direct contact with one another, but yet still co-operate or interact with one another. As used herein, the term "circuit" can be a device that has at least one transistor and / or at least one passive element connected in a certain manner to process a signal.

[0013] Figure 1 A schematic diagram of a line driver 100 in accordance with some embodiments of the present application. In some embodiments, the line driver 100 can be applied to data transceiving of a wired network. In some embodiments, the line driver 100 can operate as, but not limited to, a class AB amplifier.

[0014] The line driver 100 includes a resistive element Rl, a resistive element R2, an operational amplifier 110, and an adjustable current mirror array circuit 120. A first end of the resistive element Rl receives a common mode voltage VCM, a second end of the resistive element Rl and a first end of the resistive element R2 are coupled to a node A (which is coupled to a positive input of the operational amplifier 110), and a second end of the resistive element R2 is coupled to an output O. In some embodiments, the resistive elements Rl and R2 can be on-chip resistors, which can be, but are not limited to, a voltage-controlled resistor implemented with a transistor, a polysilicon resistor, etc. In some embodiments, the resistive elements Rl and R2 can be resistors with fixed resistance values, or can be adjustable resistor arrays with variable resistance values.

[0015] The negative input of the operational amplifier 110 receives an input signal VIP. The operational amplifier 110 can receive a common mode signal VCM via the resistive element Rl, and generate a signal VP and a signal VN according to the common mode voltage VCM and the input signal VIP. In some embodiments, the signal VP and the signal VN can be differential signals. The adjustable current mirror array circuit 120 generates a current II to a first end (i.e., a node A) of the resistive element R2 and a current I2 to an output O in response to the signal VP and the signal VN, and adjusts a ratio (hereinafter referred to as a ratio N) between the current I2 and the current II in response to a plurality of control bits D[0]-D[3] to set an output impedance of the output O. For ease of understanding, the circuits for generating currents in the adjustable current mirror array circuit 120 (e.g., the current mirror circuit 230) can be classified according to the conduction mode of the actual transistors as follows: Figure 2 The adjustable current mirror array circuit 120 can include a PMOS current mirror 121 and an NMOS current mirror 122. The PMOS current mirror 121 and the NMOS current mirror 122 are stacked and coupled to ground to generate the current II and the current I2 as described above. A specific implementation of the adjustable current mirror array circuit 120 will be described later with reference to Figure 2 and Figure 3 The present application is not limited to the examples of Figure 2 and Figure 3 .

[0016] By circuit analysis, it can be deduced that the output impedance Rout of the output O satisfies the following equation:

[0017] Rout = R2 / (1 + N)

[0018] In the above equation, R2 represents the resistance of the resistive element R2. By adjusting the ratio N between the current I2 and the current II, the output impedance Rout of the output O can be adjusted to match the load impedance (e.g., the impedance of a transmission line). For example, the larger the ratio N, the lower the output impedance Rout; conversely, the smaller the ratio N, the higher the output impedance Rout. In some related technologies, the output impedance of a line driver is set only by adjusting the resistance of a resistor (e.g., the resistance of the resistive element R2). However, in practical applications, the resistance of a resistor can easily deviate due to various variations (e.g., but not limited to, process variations). Compared with the above related technology, in some embodiments of the present application, the adjustable current mirror array circuit 120 can trim the current value of the current I2 to adjust the ratio N in response to the plurality of control bits D[0]-D[3], thereby accurately adjusting the output impedance Rout.

[0019] In addition, the voltage swing of the output terminal O has to have a large range (e.g., but not limited to, about 0.4 volts to 2.9 volts) according to the protocol requirement of the partial application. Generally, to support this range of voltage, a transistor with high voltage withstand is usually used to implement each circuit portion. In some embodiments, as will be described later Figure 3 , each circuit in the line driver 100 can be implemented with a transistor with low voltage withstand. For example, as shown in Figure 1 , the adjustable current mirror array circuit 120 is driven by a supply voltage VDD, and the voltage withstand of each of the transistors included in the adjustable current mirror array circuit 120 (e.g., the transistors shown in Figure 3 ) can be lower than the supply voltage VDD. Thus, in some applications where a transistor with high voltage withstand cannot be used, a transistor with low voltage withstand can still be used to implement the line driver 100. For example, the supply voltage VDD is 3.3 volts, and the transistors included in the adjustable current mirror array circuit 120 can be implemented by transistors preset to operate at 1.8 volts. The values of the supply voltage VDD and / or the voltage withstand described above are examples, and the present application is not limited to the values described above.

[0020] Figure 2 A schematic diagram of the adjustable current mirror array circuit 120 in Figure 1 is drawn according to some embodiments of the present application. To facilitate understanding, Figure 2 , the adjustable current mirror array circuit 120 is described and classified functionally. In this example, the adjustable current mirror array circuit 120 includes a reference voltage generator 210, a level shift circuit 220, and a current mirror circuit 230. The reference voltage generator 210 generates a reference voltage VREFP and a reference voltage VREFN. In some embodiments, the reference voltage generator 210 can be implemented by a low dropout regulator to directly generate the reference voltage VREFP and the reference voltage VREFN. In some embodiments, the reference voltage generator 210 can be implemented by the setup shown in Figure 5 .

[0021] The level conversion circuit 220 converts the levels of the plurality of control bits D[0]-D[3] to generate the plurality of bits P[0]-P[3] and the plurality of Pb[0]-Pb[3], and generates the plurality of bits N[0]-N[3] and the plurality of Nb[0]-Nb[3] based on the plurality of control bits D[0]-D[3]. As mentioned previously, the plurality of transistors included in the adjustable current mirror array circuit 120 can be implemented by transistors preset to operate at 1.8 volts, while the adjustable current mirror array circuit 120 is powered by a supply voltage VDD of 3.3 volts. To ensure that the PMOS current mirror 121 can operate correctly, the level conversion circuit 220 can convert the levels of the signals used to control the P-type transistors in the PMOS current mirror 121. For example, the level conversion circuit 220 can sequentially perform a first level conversion and a second level conversion according to the plurality of control bits D[0]-D[3]. In the first level conversion, the levels of the plurality of control bits D[0]-D[3] are adjusted from 0 volts to 1.8 volts to 0 volts to 3.3 volts (i.e., the level of the supply voltage VDD). In the second level conversion, the levels of the plurality of control bits D[0]-D[3] are adjusted from 0 volts to 3.3 volts to 1.8 volts to 3.3 volts. By the above operations, the level of logic value 0 of each of the plurality of bits P[0]-P[3] and the plurality of Pb[0]-Pb[3] corresponds to 1.8 volts, and the level of logic value 1 of each of the plurality of bits P[0]-P[3] and the plurality of Pb[0]-Pb[3] corresponds to 3.3 volts. In this way, it can be ensured that the PMOS current mirror 121 can operate correctly.

[0022] By the protection circuit 233 to be described later, the NMOS current mirror 122 can operate in a lower voltage range. Therefore, the level conversion circuit 220 can not perform level conversion on signals (e.g., the bits N[0]-N[3] and the bits Nb[0]-Nb[3]) used to control the NMOS current mirror 122. For example, the level conversion circuit 220 can include a buffer circuit (not shown) that can be used to output the control bits D[0]-D[3] as the bits N[0]-N[3] and the bits Nb[0]-Nb[3]. In some embodiments, one of the bits P[0]-P[3] and one of the bits Pb[0]-Pb[3] have different logic values, and one of the bits N[0]-N[3] and one of the bits Nb[0]-Nb[3] have different logic values. For example, when the bit P[0] has a logic value of 0, the bit Pb[0] has a logic value of 1; or, when the bit P[1] has a logic value of 1, the bit Pb[1] has a logic value of 0. Similarly, when the bit N[0] has a logic value of 0, the bit Nb[0] has a logic value of 1; or, when the bit N[1] has a logic value of 1, the bit Nb[1] has a logic value of 0. It should be understood that the correspondence between the remaining bits P[2]-P[3], P2b[0]-P2b[3], N[2]-N[3], and Nb[2]-Nb[3] works in a similar manner.

[0023] In some embodiments, the level conversion circuit 220 can be implemented by a unidirectional level converter. In some embodiments, the level conversion circuit 220 can be implemented by a cross-coupled CMOS level converter. The above-described implementation of the level conversion circuit 220 is used for illustration only, and the present application is not limited thereto. Various level conversion circuits 220 that can perform similar operations are within the scope of the present application.

[0024] The current mirror circuit 230 includes a current mirror array 231, a current mirror array 232, and a protection circuit 233, where the P-type transistors (as shown) in the current mirror array 231 and the protection circuit 233 can correspond to the PMOS current mirror 121, and the N-type transistors (as shown) in the current mirror array 232 and the protection circuit 233 can correspond to the NMOS current mirror 122. Figure 3 Figure 1 Figure 3 Figure 1 ​​​The NMOS current mirror 122. The current mirror array 231 is biased by the signal VP and switched according to multiple bits P[0]~P[3] and multiple bits Pb[0]~Pb[3], and the current mirror array 232 is biased by the signal VN and switched according to multiple bits N[0]~N[3] and multiple bits Nb[0]~Nb[3]. The protection circuit 233 is coupled between the current mirror array 231 and the current mirror array 232 and is biased by the reference voltage VREFP and the reference voltage VREFN to provide voltage protection for the current mirror array 231 and the current mirror array 232. The current mirror array 231, the current mirror array 232 and the protection circuit 233 together generate the aforementioned currents I1 and I2.

[0025] Figure 3 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the current mirror circuit 230 is shown. The current mirror array 231 includes multiple transistors P11-P61 and multiple switches SP0-SP3 and SP0b-SP3b. The current mirror array 233 includes multiple transistors N11-N61 and multiple switches SN0-SN3 and SN0b-SN3b. The protection circuit 233 includes multiple transistors P12-P62 and N12-N62. The multiple transistors P11-P61 and P12-P62 are P-type transistors, and the multiple transistors N11-N61 and N12-N62 are N-type transistors.

[0026] Functionally, the current mirror array 231, the current mirror array 232, and the protection circuit 233 can be divided into circuit section CP1 and circuit section CP2. Circuit section CP1 includes multiple transistors P11, P12, N11, and N12, while circuit section CP2 includes multiple transistors P21 to P61, P22 to P62, N21 to N61, and N22 to N62, and multiple switches SP0 to SP3, SP0b to SP3b, SN0 to SN3, and SN0b to SN3b.

[0027] In detail, a first terminal (e.g., source) of the transistor P11 receives a supply voltage VDD, a second terminal (e.g., drain) of the transistor P11 is coupled to a first terminal of the transistor P12, and a control terminal (e.g., gate) of the transistor P11 receives a signal VP. In other words, the transistor P11 can be biased by the signal VP. A second terminal of the transistor P12 is coupled to the node A, and a control terminal of the transistor P12 receives a reference voltage VREFP. A first terminal (e.g., drain) of the transistor N12 is coupled to the node A, a second terminal (e.g., source) of the transistor N12 is coupled to a first terminal of the transistor N11, and a control terminal (e.g., gate) of the transistor N12 receives a reference voltage VREFN. In other words, the transistor P12 can be biased by the reference voltage VREFP, the transistor N12 can be biased by the reference voltage VREFN, and the transistors P12 and N12 are coupled to the node A. A second terminal of the transistor N11 is coupled to ground to receive a ground voltage GND, and a control terminal of the transistor N12 receives a signal VN. In other words, the transistor N11 can be biased by the signal VN and coupled between the transistor N12 and ground. By the above arrangement, the circuit portion CP1 can generate a current II to the node A.

[0028] Further, the circuit portion CP2 can be divided into a first current path and a plurality of second current paths coupled in parallel. For example, the transistors P21, P22, N21, and N22 form the first current path, the transistors P31, P32, N31, N32, and the switches SP0, SP0b, SN0, and SN0b form the first second current path, the transistors P41, P42, N41, N42, and the switches SP1, SP1b, SN1, and SN1b form the second second current path, the transistors P51, P52, N51, N52, and the switches SP2, SP2b, SN2, and SN2b form the third second current path, and the transistors P61, P62, N61, N62, and the switches SP3, SP3b, SN3, and SN3b form the fourth second current path.

[0029] The first current path is biased to generate a portion of the current I2, I2b, fixedly. In detail, the first terminal of the transistor P21 receives the supply voltage VDD, the second terminal of the transistor P21 is coupled to the first terminal of the transistor P22, and the control terminal of the transistor P21 receives the signal VP. The second terminal of the transistor P22 is coupled to the output terminal O, and the control terminal of the transistor P22 receives the reference voltage VREFP. The first terminal of the transistor N22 is coupled to the output terminal O, the second terminal of the transistor N22 is coupled to the first terminal of the transistor N21, and the control terminal of the transistor N22 receives the reference voltage VREFN. The second terminal of the transistor N21 is coupled to the ground to receive the ground voltage GND, and the control terminal of the transistor N21 receives the signal VN. By the above arrangement, the first current path can generate the portion of the current I2, I2b. In some embodiments, the aspect ratios of the transistors P21, P22, N21 and N22 are a certain multiple (e.g., m1 times) of the aspect ratios of the transistors P11, P12, N11 and N12 in the circuit portion CP1, so that the portion of the current I2, I2b, is m1 times of the current I1.

[0030] The second current paths selectively generate portions of the current I2, I20, I21, I22 and I23, according to the bits P[0]-P[3], Pb[0]-Pb[3], N[0]-N[3] and Nb[0]-Nb[3]. Take the first second current path as an example, the first terminal of the transistor P31 receives the supply voltage VDD, the second terminal of the transistor P31 is coupled to the first terminal of the transistor P32, and the control terminal of the transistor P31 is coupled to one terminal of the switch SP0 and one terminal of the switch SP0b. The other terminal of the switch SP0 receives the signal VP, and the switch SP0 is selectively turned on according to the bit P[0] to provide the signal VP to bias the transistor P31. The other terminal of the switch SP0b receives the supply voltage VDD, and the switch SP0b is selectively turned on according to the bit Pb[0] to provide the supply voltage VDD to turn off the transistor P31. When the switch SP0 is turned on, the switch SP0b is turned off. In this way, the transistor P31 can receive the signal VP via the switch SP0 and be biased by the signal VP. Alternatively, when the switch SP0b is turned on, the switch SP0 is turned off. In this way, the transistor P31 can receive the supply voltage VDD via the switch SP0b and be turned off accordingly. The second terminal of the transistor P32 is coupled to the output terminal O, and the control terminal of the transistor P32 receives the reference voltage VREFP.

[0031] Similarly, a first terminal of transistor N32 is coupled to the output terminal O, a second terminal of transistor N32 is coupled to a first terminal of transistor N31, and a control terminal of transistor N32 receives the reference voltage VREFN. A second terminal of transistor N31 is coupled to the ground to receive the ground voltage GND, and a control terminal of transistor N31 is coupled to one terminal of switch SN0 and one terminal of switch SN0b. Another terminal of switch SN0 receives the signal VN, and switch SN0 is selectively turned on according to the bit N[0] to provide the signal VN to bias transistor N31. Another terminal of switch SN0b receives the ground voltage GND, and switch SN0b is selectively turned on according to the bit Nb[0] to provide the ground voltage GND to turn off transistor N31. Thus, when switch SN0 is turned on, switch SN0b is turned off. In this way, transistor N31 can receive the signal VN via switch SN0 and be biased by the signal VN. Alternatively, when switch SN0b is turned on, switch SN0 is turned off. In this way, transistor N31 can receive the ground voltage GND via switch SN0b and be turned off accordingly.

[0032] In some embodiments, in the same second current path (e.g., the first second current path), switches SP0 and SN0 have the same on state, and switches SP0b and SN0b have the same on state. For example, when switch SP0 is turned on, switch SN0 is also turned on (at this time, switches SP0b and SN0b are both turned off). Under this condition, the first second current path can generate the partial current I20. Alternatively, when switch SP0 is turned off, switch SN0 is also turned off (at this time, switches SP0b and SN0b are both turned on). Under this condition, the first second current path is closed and does not generate the partial current I20. The arrangement of the remaining second current paths can refer to the arrangement of the first second current path described above, and will not be repeated here.

[0033] In some embodiments, the aspect ratios of the plurality of transistors P31, P32, N31, and N32 in the second current path of the first embodiment are specific multiples (e.g., m²) of the aspect ratios of the plurality of transistors P11, P12, N11, and N12 in the circuit portion CP1, such that a portion of the current I20 is a current I1 that is m². Similarly, the aspect ratios of the plurality of transistors P41, P42, N41, and N42 in the second current path of the second embodiment are specific multiples (e.g., m³) of the aspect ratios of the plurality of transistors P11, P12, N11, and N12 in the circuit portion CP1, such that a portion of the current I21 is a current I1 that is m³. In the second current path of Article 3, the aspect ratios of transistors P51, P52, N51, and N52 are a specific multiple (e.g., m4 times) of the aspect ratios of transistors P11, P12, N11, and N12 in circuit section CP1, such that a portion of the current I22 is a current I1 that is m4 times its length. In the second current path of Article 4, the aspect ratios of transistors P61, P62, N61, and N62 are a specific multiple (e.g., m5 times) of the aspect ratios of transistors P11, P12, N11, and N12 in circuit section CP1, such that a portion of the current I23 is a current I1 that is m5 times its length. In some embodiments, the aforementioned values ​​m2, m3, m4, and m5 may be (but are not limited to) determined based on binary encoding. For example, the value m1 is 12, and the values ​​m2, m3, m4, and m5 may be 1, 2, 4, and 8 respectively. In this way, if all the second current paths are closed, the current I2 is equivalent to a portion of the current I2b. Under this condition, the ratio N is 12. Alternatively, if all the second current paths are open, the current I2 is equivalent to the sum of multiple portions of the current I2b and I20 to I23. Under this condition, the ratio N is 27 (i.e., 12+1+2+4+8). By using the above settings, the current I2 can be adjusted by turning on (or off) more second current paths, thereby adjusting the output impedance Rout.

[0034] In addition, such as Figure 3 As shown, transistors P12 to P62 in protection circuit 233 are turned on by a reference voltage VREFP, and transistors N12 to N62 in protection circuit 233 are turned on by a reference voltage VREFN. These transistors can withstand excess voltage differences for the transistors in current mirror arrays 231 and 232, ensuring that the transistors in current mirror arrays 231 and 232 are not damaged. In this way, the transistors in current mirror circuit 230 can be implemented by transistors with lower voltage ratings.

[0035] Figure 4 Drawings based on some embodiments of this application Figure 2A schematic diagram of the current mirror circuit 230 in the diagram. Different from... Figure 3 In this example of protection circuit 233, the first terminals (e.g., sources) of multiple transistors P12 to P62 are coupled to each other, and the second terminals (e.g., sources) of multiple transistors N12 to N62 are coupled to each other. The above-described connection method of protection circuit 233 is for illustrative purposes only, and this application is not limited thereto. Various related configurations that can provide voltage protection are all covered by the protection circuit 233 of this application.

[0036] Figure 5 Drawings based on some embodiments of this application Figure 2 A schematic diagram of the reference voltage generator 210 is shown. The reference voltage generator 210 includes a low-dropout regulator 510, a comparator 520, and a comparator 530. The low-dropout regulator 510 generates an output voltage Vout. The comparator 520... Figure 1 or Figure 3 The voltage at output terminal O (hereinafter referred to as voltage VO) and the output voltage Vout, with the higher level, are output as the reference voltage VREFP. Comparator 530 outputs the lower level of voltage VO and output voltage Vout as the reference voltage VREFN.

[0037] As previously stated, the line driver 100 can be used for data transmission and reception in wired networks. The line driver 100 may not operate when the system receives data signals via output terminal O. If the swing of the data signal (equivalent to voltage VO) received at output terminal O is too large, it may cause damage to multiple transistors in the protection circuit 233 (e.g., but not limited to...). Figure 3 or Figure 4 Transistors P62 and N62 in the protection circuit 233 may be mis-activated, thereby reducing the linearity of the received data. To avoid this problem, comparators 520 and 530 can be used to detect voltage VO to dynamically generate a reference voltage VREFP with a higher level and a reference voltage VREFN with a lower level, thereby ensuring that the multiple transistors in the protection circuit 233 will not be mis-activated.

[0038] In some embodiments, the low-dropout regulator 510 includes resistive elements R51, R52, and R53, a transistor 515, and an amplifier 512. Resistive element R51 receives a supply voltage VDD and outputs a voltage V1. Resistive element R52 is coupled between resistive element R51 and ground. Amplifier 512 generates a voltage V2 based on the output voltage Vout and voltage V1. Transistor 515 generates an output voltage Vout based on voltage V2. Resistive element R53 is coupled between transistor 515 and ground.

[0039] In detail, a first end of the resistive element R51 receives a supply voltage VDD, and a second end of the resistive element R51 is coupled to a first end of a resistive element R52 and outputs a voltage V1 to a negative input terminal of the amplifier 512. A second end of the resistive element R52 is coupled to ground to receive a ground voltage GND. The transistor 515 is a P-type transistor. A first end of the transistor 515 receives the supply voltage VDD, a second end of the transistor 515 is coupled to a first end of a resistive element R53, and is used to generate an output voltage Vout. A second end of the resistive element R53 is coupled to ground to receive the ground voltage GND. A positive input terminal of the amplifier 512 is coupled to the second end of the transistor 515 to receive the output voltage Vout. The amplifier 512 can generate a voltage V2 according to the voltage V1 and the output voltage Vout, and transmit the voltage V2 to a control terminal of the transistor 515. In this way, the transistor 515 can adjust the current flowing through the resistive element R53 according to the voltage V2 and generate a corresponding output voltage Vout. The above-mentioned embodiments regarding the low-dropout regulator 510 are used for illustration, and the present application is not limited thereto. Various types of low-dropout regulators 510 are all within the scope of the present application.

[0040] In some embodiments, the comparator 520 includes a transistor 521 and a transistor 522. The transistor 521 and the transistor 522 are two P-type transistors that are cross-coupled. In detail, a first end of the transistor 521 is coupled to a control terminal of the transistor 522 and receives the voltage VO, a first end of the transistor 522 is coupled to a control terminal of the transistor 521 and receives the output voltage Vout, and the second ends of the transistor 521 and the transistor 522 are coupled to each other to generate a reference voltage VREFP. Similarly, the comparator 530 includes a transistor 531 and a transistor 532. The transistor 531 and the transistor 532 are two N-type transistors that are cross-coupled. In detail, a first end of the transistor 531 is coupled to a control terminal of the transistor 532 and receives the voltage VO, a first end of the transistor 532 is coupled to a control terminal of the transistor 531 and receives the output voltage Vout, and the second ends of the transistor 531 and the transistor 532 are coupled to each other to generate a reference voltage VREFN. The above-mentioned embodiments regarding the comparator 520 and the comparator 530 are used for illustration, and the present application is not limited thereto. Various comparators 520 and 530 that can perform similar operations are all within the scope of the present application.

[0041] In summary, the line driver in some embodiments of the present application can use the adjustable current mirror array circuit to adjust the output impedance. In this way, the problem of inaccurate resistive elements caused by process variation can be improved and the output impedance can be accurately trimmed. In addition, the line driver in some embodiments of the present application can be implemented using transistors with lower voltage resistance, so it can have a wider range of applications.

[0042] Although the present application has been described in connection with the embodiments thereof, it will occur to those skilled in the art that modifications can be made of the present application, from its teachings, without departing from the spirit and scope of the application. That is, the technical features of the present application can be changed according to the contents explicitly or implicitly disclosed in the present application by those skilled in the art, and all such changes are intended to fall within the scope of the present application. In other words, the scope of the patent protection of the present application is defined by the scope of the patent application as defined in the present specification.

[0043] Symbol explanation

[0044] 100: line driver

[0045] 110: operational amplifier

[0046] 120: adjustable current mirror array circuit

[0047] 121: PMOS current mirror

[0048] 122: NMOS current mirror

[0049] 210: reference voltage generator

[0050] 220: level conversion circuit

[0051] 230: current mirror circuit

[0052] 231, 232: current mirror array

[0053] 233: protection circuit

[0054] 510: low dropout regulator

[0055] 512: amplifier

[0056] 515, 521, 522, 531, 532: transistor

[0057] 520, 530: comparator

[0058] A: node

[0059] CP1, CP2: circuit part

[0060] D[0] ~ D[3]: control bit

[0061] GND: ground voltage

[0062] I1, I2: current

[0063] I20, I21, I22, I23, I2b: partial current

[0064] N11, N12, N21, N22, N31, N32, N41, N42, N51, N52, N61, N62: transistor;

[0065] N[0] ~ N[3], Nb[0] ~ Nb[3], P[0] ~ P[3], Pb[0] ~ Pb[3]: bit;

[0066] P11, P12, P21, P22, P31, P32, P41, P42, P51, P52, P61, P62: transistor;

[0067] O: output terminal;

[0068] R1, R2, R51, R52, R53: resistive element;

[0069] Rout: output impedance;

[0070] SN0, SN0b, SN1, SN1b, SN2, SN2b, SN3, SN3b: switch;

[0071] SP0, SP0b, SP1, SP1b, SP2, SP2b, SP3, SP3b: switch;

[0072] V1, V2: voltage;

[0073] VCM: common mode voltage;

[0074] VDD: supply voltage;

[0075] VIP: input signal;

[0076] VN, VP: signal;

[0077] VO: voltage;

[0078] VREFN, VREFP: reference voltage;

[0079] Vout: output voltage.

Claims

1. A line driver, characterized in that, include: A first resistive element; A second resistive element, wherein a first end of the second resistive element is coupled to a node with the first resistive element, and a second end of the second resistive element is coupled to an output terminal; An operational amplifier receives a common-mode voltage via a first resistive element and generates a first signal and a second signal based on the common-mode voltage and an input signal. as well as An adjustable current mirror array circuit generates a first current to the node and a second current to the output terminal in response to the first signal and the second signal, and adjusts the ratio between the second current and the first current in response to multiple control bits to set an output impedance of the output terminal. The adjustable current mirror array circuit includes: A reference voltage generator generates a first reference voltage and a second reference voltage; A bit-level conversion circuit converts the bit levels of the plurality of control bits to generate a plurality of first bits and a plurality of second bits, and generates a plurality of third bits and a plurality of fourth bits based on the plurality of control bits; Wherein, a corresponding entity among the plurality of first bits has a different logical value from a corresponding entity among the plurality of second bits, and a corresponding entity among the plurality of third bits has a different logical value from a corresponding entity among the plurality of fourth bits; and A current mirror circuit is biased by a first reference voltage and a second reference voltage, and controlled by a plurality of first bits, a plurality of second bits, a third bit and a fourth bit to generate the first current and the second current.

2. The line driver as described in claim 1, characterized in that, The current mirror circuit includes: A first current mirror array, biased by the first signal and switched according to the plurality of first bits and the plurality of second bits; A second current mirror array, biased by the second signal and switched according to the plurality of third bits and the plurality of fourth bits; and A protection circuit is coupled between the first current mirror array and the second current mirror array, and biased via the first reference voltage and the second reference voltage to provide voltage protection for the first current mirror array and the second current mirror array, wherein the first current mirror array, the second current mirror array and the protection circuit together generate the first current and the second current.

3. The line driver as described in claim 2, characterized in that, The first current mirror array, the second current mirror array, and the protection circuit include a first circuit portion for generating the first current, and the first circuit portion includes: A first P-type transistor is biased by the first signal and receives a supply voltage; A second P-type transistor is biased via the first reference voltage; A first N-type transistor, biased by the second reference voltage, and coupled to the second P-type transistor at the node; and A second N-type transistor is biased by the second signal and coupled between the first N-type transistor and ground.

4. The line driver as described in claim 2, characterized in that, The first current mirror array, the second current mirror array, and the protection circuit include a second circuit portion for generating the second current, and the second circuit portion includes: A first current path, via the first signal, the first reference voltage, the second reference voltage, and the second signal bias, to consistently generate a first portion of the second current; and Multiple second current paths selectively generate multiple second portion currents in the second current based on the multiple first bits, the multiple second bits, the multiple third bits, and the multiple fourth bits.

5. The line driver as described in claim 4, characterized in that, One of the plurality of second current paths includes: A third P-type transistor receives the supply voltage; A first switch is selectively turned on according to one of the plurality of first bits to provide the supply voltage to turn off the third P-type transistor; A second switch is selectively turned on according to one of the plurality of second bits to provide the first signal to bias the third P-type transistor; A fourth P-type transistor is biased via the first reference voltage and coupled between the third P-type transistor and the output terminal; A third N-type transistor is biased via the second reference voltage and coupled to the output terminal; A fourth N-type transistor is coupled between the third N-type transistor and ground; A third switch, selectively turned on according to a corresponding one of the plurality of third bits, to provide a ground voltage to turn off the fourth N-type transistor; and A fourth switch is selectively turned on according to one of the plurality of fourth bits to provide the second signal to bias the fourth N-type transistor.

6. The line driver as described in claim 5, characterized in that, The source of the second P-type transistor is coupled to the source of the fourth P-type transistor, and the source of the second N-type transistor is coupled to the source of the third N-type transistor.

7. The line driver as claimed in claim 1, characterized in that, The reference voltage generator includes: A low-dropout regulator generates an output voltage; A first comparator outputs the higher of a voltage at the output terminal and the output voltage as the first reference voltage; and A second comparator outputs the voltage at the output terminal and the lower of the output voltages as the second reference voltage.

8. The line driver as claimed in claim 7, characterized in that, The low-dropout regulator includes: A third resistive element receives the supplied voltage and outputs a first voltage; A fourth resistive element is coupled between the third resistive element and ground; An amplifier that generates a second voltage based on the output voltage and the first voltage; A transistor that generates the output voltage according to the second voltage; and A fifth resistive element is coupled between the transistor and ground.

9. The line driver as claimed in claim 7, characterized in that, The first comparator includes: A first P-type transistor, wherein a first terminal of the first P-type transistor receives the voltage at the output terminal; and A second P-type transistor, wherein a first terminal of the second P-type transistor is coupled to a control terminal of the first P-type transistor and receives the output voltage, a second terminal of the second P-type transistor is coupled to a second terminal of the first P-type transistor to generate the first reference voltage, and a control terminal of the second P-type transistor is coupled to a first terminal of the first P-type transistor.

10. The line driver as claimed in claim 7, characterized in that, The second comparator includes: A first N-type transistor, wherein a first terminal of the first N-type transistor receives the voltage at the output terminal; and A second N-type transistor, wherein a first terminal of the second N-type transistor is coupled to a control terminal of the first N-type transistor and receives the output voltage, a second terminal of the second N-type transistor is coupled to a second terminal of the first N-type transistor to generate the second reference voltage, and a control terminal of the second N-type transistor is coupled to a first terminal of the first N-type transistor.

11. The line driver as claimed in claim 1, characterized in that, The adjustable current mirror array circuit includes a plurality of transistors powered by a supply voltage, and each of the plurality of transistors has a withstand voltage lower than the supply voltage.

12. The line driver as claimed in claim 1, characterized in that, The greater the ratio between the second current and the first current, the lower the output impedance.

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