A low-latency signal-to-noise ratio calculation method based on FPGA

Abstract

A low-latency signal-to-noise ratio calculation method based on FPGA is disclosed. The invention introduces an intermediate variable in the signal-to-noise ratio calculation process, accumulates the signal-to-noise ratio to obtain a final value by continuously comparing the main spectrum power with a base and gradually reducing the main spectrum power and the base; firstly, the main spectrum power is compared with the base, and then the signal-to-noise ratio is obtained by multiplying the multiple by the number of spectral line roots n‑p, and the division operation of the base divided by the number of spectral line roots n‑p is converted into a multiplication operation; the need to call the division IP core twice to perform the division operation is avoided, so that the operation is simplified; the advantage of FPGA parallel execution is fully utilized, and the main spectrum power is continuously compared with the accumulated sum of the noise base, so that the signal-to-noise ratio result can be quickly calculated, the real-time performance is good, and the detection performance of the detection device is improved; the running time of the signal-to-noise ratio calculation in the system is shortened, which is of great help to reduce the inherent delay of the system and has high practical value.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal processing, and in particular relates to a low-delay signal-to-noise ratio calculation method based on FPGA. Background Art

[0002] like Figure 2 This is a schematic diagram of the spectrum of the echo signal received by the detection device. The spectrum line with the largest power in the spectrum of the echo signal is the main spectrum f z , remove the main frequency band (f z-3 ~f z+3 ) and then average the power of the spectrum lines after accumulating to calculate the noise average floor N, that is, N = (W1 + W2 + W3 + W4 + ... + W n -W Z-3 -W Z-2 -W Z-1 -W Z -W Z+1 -W Z+2 -W Z+3 ) / (np), the echo signal-to-noise ratio SN is the ratio of the target main spectrum power WZ to the noise average floor N (i.e. SN = W Z / N).

[0003] Usually, the FPGA implementation method is to first find the main spectrum power W Z , and then calculate the base (the sum of the power of the remaining spectral lines except the main frequency band) SUM = W1 + W2 + W3 + W4 + ... + W n -W Z-3 -W Z-2 -W Z-1 -W Z -W Z+1 -W Z+2 -W Z+3 , then call a division IP core (development tool ISE or Vivado comes with) to calculate the noise average floor N = SUM / (np), and finally call the second division IP core to calculate the signal-to-noise ratio SN = W Z / N, the flow chart is as follows Figure 3 As shown in the figure, calling the division IP core twice to perform calculations greatly prolongs the program running time, which is not conducive to reducing the inherent delay.

[0004] The method of calculating the signal-to-noise ratio by calling the division IP core is simple in principle, but it will prolong the program running time. Especially when the signal-to-noise ratio of multiple spectral lines needs to be calculated, the value of the signal-to-noise ratio cannot be calculated quickly, and the real-time performance is poor, which is not conducive to radio detection devices that require a small inherent delay. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a low-latency signal-to-noise ratio calculation method based on FPGA, which reduces inherent delay, improves real-time performance, and optimizes the performance of radio detection devices.

[0006] The present invention is achieved through the following technical solutions.

[0007] The present invention provides a low-latency signal-to-noise ratio calculation method based on FPGA, comprising the following steps:

[0008] Step 1: Each time the clock rises or the reset signal rises, if the reset signal is valid, the main spectrum 1, base 1, signal-to-noise ratio, signal-to-noise ratio calculation end flag and state machine are set to 0 for initialization. If the reset signal is invalid, enter state machine 0, the signal-to-noise ratio calculation end flag is set to 0, if the base calculation end flag is 1, the state machine is set to 1, if the base calculation end flag is 0, the state machine remains at 0;

[0009] Step 2: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 1, assign the main spectrum power to main spectrum 1, assign the base to base 1, set the signal-to-noise ratio to 0, and set the state machine to 2;

[0010] Step 3: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 2 and set state machine 3. If main spectrum 1 is greater than or equal to M times base 1, main spectrum 1 minus M times base 1 is assigned to main spectrum 1, and the signal-to-noise ratio is equal to M×(np). If main spectrum 1 is less than M times base 1, main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0.

[0011] Step 4: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 3 and set state machine 4. If the main spectrum 1 is greater than or equal to M / 2 1 Multiply the base by 1, and subtract M / 2 from the main spectrum 1 1 The base 1 is assigned to the main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2 1 ×(np), if the main spectrum 1 is less than M / 21 times the basis 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0012] Step 5: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 4 and set state machine 5. If the main spectrum 1 is greater than or equal to M / 2 2 Multiply the base by 1, and subtract M / 2 from the main spectrum 1 2 The base 1 is assigned to the main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2 2 ×(np), if the main spectrum 1 is less than M / 2 2 The base is 1, the main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0;

[0013] Step 6: Recursively subtract M / 2 from the main spectrum 1x The method of assigning multiple basis 1 to main spectrum 1 continuously reduces main spectrum 1 and makes it close to basis 1. When M / 2 x When it is 1, the state machine is set to a and enters the next step;

[0014] Step 7: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a, set the state machine to a+1, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np), if main spectrum 1 is less than base 1, main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0;

[0015] Step 8. When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+1, set state machine to a+2, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 21, if main spectrum 1 is less than base 1, main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0;

[0016] Step 9: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+2, set state machine a+3, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 2 3 , if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0017] Step 10: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+3, set state machine a+4, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 2 2 , if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0018] Step 11: Recursively reduce the basis 1 by shifting the basis 1 right by 1 bit at a time. If the main spectrum 1 is greater than or equal to the basis 1, subtract the basis 1 from the main spectrum 1 and assign it to the main spectrum 1, so that it approaches the main spectrum 1 until M / 2 y ×(np) reaches the required accuracy of the signal-to-noise ratio, the state machine is set to b, and enters the next step;

[0019] Step 12: Set the state machine to b+1. If the main spectrum 1 is greater than or equal to the base 1, subtract the base 1 from the main spectrum 1 and assign it to the main spectrum 1. The signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2. y ×(np), if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0020] Step 13: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine b+1, set the signal-to-noise ratio calculation end flag to 1, the calculation ends, the state machine is set to 0, and the signal-to-noise ratio is the value calculated in step 12.

[0021] Furthermore, in step 11, M / 2 y ×(np) to achieve the accuracy required for signal-to-noise ratio, i.e. M / 2 y ×(np) is 1.

[0022] Furthermore, the value of x in step 6 is obtained by subtracting 3 from the current state machine value.

[0023] Furthermore, the value of y in step 11 is obtained by subtracting (a+1) from the current state machine value.

[0024] Furthermore, in step 2-7, when the reset signal is valid, the system is reset and returns to step 1.

[0025] Furthermore, in steps 8-11, when the reset signal is valid, the system is reset and returns to step 1.

[0026] Furthermore, the (np) is the number of spectral lines in the current echo signal spectrum diagram.

[0027] Furthermore, the value of M is a positive integer.

[0028] The beneficial effects of the present invention are as follows: through the implementation of the present invention, an intermediate variable is introduced in the signal-to-noise ratio calculation process, and the signal-to-noise ratio is accumulated to obtain a final value by continuously comparing the main spectrum power with the base and gradually reducing the main spectrum power and the base; the signal-to-noise ratio is obtained by first comparing the main spectrum power with the base, and then multiplying the multiple by the number of spectral line roots np, and the division operation of the base divided by the number of spectral line roots np is converted into a multiplication operation; the need to call the division IP core twice to perform the division operation is avoided, so that the operation is simplified; the advantage of FPGA parallel execution is fully utilized, and the signal-to-noise ratio result can be quickly calculated by continuously comparing the main spectrum power with the accumulated sum of the noise base, with good real-time performance, which is beneficial to improving the detection performance of the detection device; the running time of the signal-to-noise ratio calculation in the system is shortened, which is of great help in reducing the inherent delay of the system and has high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a flow chart of the signal-to-noise ratio calculation process of the present invention;

[0030] Figure 2 is a schematic diagram of the frequency spectrum of the echo signal;

[0031] Figure 3 Flowchart for a general signal-to-noise ratio calculation. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0033] like Figure 1 As shown, a low-latency signal-to-noise ratio calculation method based on FPGA includes the following steps:

[0034] Step 1: Each time the clock rises or the reset signal rises, if the reset signal is valid, the main spectrum 1, base 1, signal-to-noise ratio, signal-to-noise ratio calculation end flag and state machine are set to 0 for initialization. If the reset signal is invalid, enter state machine 0, the signal-to-noise ratio calculation end flag is set to 0, if the base calculation end flag is 1, the state machine is set to 1, if the base calculation end flag is 0, the state machine remains at 0;

[0035] Step 2: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 1, assign the main spectrum power to main spectrum 1, assign the base to base 1, set the signal-to-noise ratio to 0, and set the state machine to 2;

[0036] Step 3: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 2 and set state machine 3. If main spectrum 1 is greater than or equal to M times base 1, main spectrum 1 minus M times base 1 is assigned to main spectrum 1, and the signal-to-noise ratio is equal to M×(np). If main spectrum 1 is less than M times base 1, main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0.

[0037] Step 4: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 3 and set state machine 4. If the main spectrum 1 is greater than or equal to M / 2 1 Multiply the base by 1, and subtract M / 2 from the main spectrum 1 1 The base 1 is assigned to the main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2 1 ×(np), if the main spectrum 1 is less than M / 21 times the basis 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0038] Step 5: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 4 and set state machine 5. If the main spectrum 1 is greater than or equal to M / 2 2 Multiply the base by 1, and subtract M / 2 from the main spectrum 1 2 The base 1 is assigned to the main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2 2 ×(np), if the main spectrum 1 is less than M / 2 2 The base is 1, the main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0;

[0039] Step 6: Recursively subtract M / 2 from the main spectrum 1 xThe method of assigning multiple basis 1 to main spectrum 1 continuously reduces main spectrum 1 and makes it close to basis 1. When M / 2 x When it is 1, the state machine is set to a and enters the next step; the value of x is the current state machine value minus 3;

[0040] Step 7: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a, set the state machine to a+1, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np), if main spectrum 1 is less than base 1, main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0;

[0041] Step 8. When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+1, set state machine to a+2, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 21, if main spectrum 1 is less than base 1, main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0;

[0042] Step 9: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+2, set state machine a+3, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 2 3 , if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0043] Step 10: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+3, set state machine a+4, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 2 2 , if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0044] Step 11: Recursively reduce the basis 1 by shifting the basis 1 right by 1 bit at a time. If the main spectrum 1 is greater than or equal to the basis 1, subtract the basis 1 from the main spectrum 1 and assign it to the main spectrum 1, so that it approaches the main spectrum 1 until M / 2 y ×(np) reaches the required accuracy of the signal-to-noise ratio (usually 1), the state machine is set to b, and enters the next step; the value of y is obtained by subtracting (a+1) from the current state machine value;

[0045] Step 12: Set the state machine to b+1. If the main spectrum 1 is greater than or equal to the base 1, subtract the base 1 from the main spectrum 1 and assign it to the main spectrum 1. The signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2. y×(np), if the main spectrum 1 is smaller than the basis 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0;

[0046] Step 13: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine b+1, set the signal-to-noise ratio calculation end flag to 1, the calculation ends, the state machine is set to 0, and the signal-to-noise ratio is the value calculated in step 12.

[0047] In any of the above steps, the reset signal needs to be judged. When the reset signal is valid, the system is reset and returns to step 1.

[0048] In the above steps, (np) is the number of spectral lines in the current echo signal spectrum diagram.

[0049] The value of M is a positive integer and can be adjusted according to the actual situation of the detection device, such as the starting threshold, etc. The calculated signal-to-noise ratio accuracy can be controlled by the number of state machines and the value of the y parameter. The maximum value of the signal-to-noise ratio is (M+M / 21+M / 22+···+M / 2y)×(np).

[0050] The novel calculation method of signal-to-noise ratio in FPGA provided by the present invention introduces an intermediate variable, accumulates the signal-to-noise ratio to obtain a final value by continuously comparing the main spectrum power with a base and gradually reducing the main spectrum power and the base; firstly, the main spectrum power is compared with the base, and then the signal-to-noise ratio is obtained by multiplying the multiple by the number of spectral line roots np, and the division operation of the base divided by the number of spectral line roots np is converted into a multiplication operation; the need to call the division IP core twice to perform the division operation is avoided, so that the operation is simplified; the advantage of FPGA parallel execution is fully utilized, and the signal-to-noise ratio result can be quickly calculated by continuously comparing the main spectrum power with the accumulated sum of the noise base, with good real-time performance, which is beneficial to improving the detection performance of the detection device; the running time of the signal-to-noise ratio calculation in the system is shortened, which is of great help to reducing the inherent delay of the system and has high practical value.

Claims

1. A low-latency signal-to-noise ratio calculation method based on FPGA, characterized in that: The following steps are involved: Step 1, each time the clock rising edge or reset signal rising edge arrives, if the reset signal is valid, the main spectrum 1, base 1, signal-to-noise ratio, signal-to-noise ratio calculation end flag and state machine are set to 0 for initialization processing respectively. If the reset signal is invalid, enter state machine 0, the signal-to-noise ratio calculation end flag is set to 0, if the base calculation end flag is 1, the state machine is set to 1, if the base calculation end flag is 0, the state machine remains at 0; Step 2: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 1, assign the main spectrum power to main spectrum 1, assign the base to base 1, set the signal-to-noise ratio to 0, and set the state machine to 2; Step 3: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 2 and set state machine 3. If main spectrum 1 is greater than or equal to M times base 1, main spectrum 1 minus M times base 1 is assigned to main spectrum 1, and the signal-to-noise ratio is equal to M×(np). If main spectrum 1 is less than M times base 1, main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0. Step 4: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 3 and set state machine 4. If the main spectrum 1 is greater than or equal to M / 2 1 Multiply the base by 1, and subtract M / 2 from the main spectrum 1 1 The base 1 is assigned to the main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2 1 ×(np), if the main spectrum 1 is less than M / 2 1 The base is 1, the main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0; Step 5: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine 4 and set state machine 5. If the main spectrum 1 is greater than or equal to M / 2 2 Multiply the base by 1, and subtract M / 2 from the main spectrum 1 2 The base 1 is assigned to the main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2 2 ×(np), if the main spectrum 1 is less than M / 2 2 The base is 1, the main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0; Step 6: Recursively subtract M / 2 from the main spectrum 1 x The method of assigning multiple basis 1 to main spectrum 1 continuously reduces main spectrum 1 and makes it close to basis 1. When M / 2 x When it is 1, the state machine is set to a and enters the next step; Step 7: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a, set the state machine to a+1, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np), if main spectrum 1 is less than base 1, main spectrum 1 remains unchanged, and the signal-to-noise ratio remains 0; Step 8: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+1, set state machine to a+2, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 2 1 , if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0; Step 9: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+2, set state machine a+3, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 2 2 , if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0; Step 10: When the next clock rising edge arrives, if the reset signal is invalid, enter state machine a+3, set state machine a+4, shift base 1 right by 1 bit, if main spectrum 1 is greater than or equal to base 1, subtract base 1 from main spectrum 1 and assign it to main spectrum 1, and the signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + (np) / 2 3 , if the main spectrum 1 is smaller than the base 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0; Step 11: Recursively reduce the basis 1 by shifting the basis 1 right by 1 bit at a time. If the main spectrum 1 is greater than or equal to the basis 1, subtract the basis 1 from the main spectrum 1 and assign it to the main spectrum 1, so that it approaches the basis 1 until M / 2 y ×(np) reaches the required accuracy of the signal-to-noise ratio, the state machine is set to b, and enters the next step; Step 12: Set the state machine to b+1. If the main spectrum 1 is greater than or equal to the base 1, subtract the base 1 from the main spectrum 1 and assign it to the main spectrum 1. The signal-to-noise ratio is equal to the signal-to-noise ratio of the previous clock cycle + M / 2. y ×(np), if the main spectrum 1 is smaller than the basis 1, the main spectrum 1 remains unchanged and the signal-to-noise ratio remains 0; Step 13: When the next clock rising edge arrives, if the reset signal is invalid, enter the state machine b+1, set the signal-to-noise ratio calculation end flag to 1, the calculation ends, the state machine is set to 0, and the signal-to-noise ratio is the value calculated in step 12; The value of x in step 6 is obtained by subtracting 3 from the current state machine value; The value of y in step 11 is obtained by subtracting a+1 from the current state machine value; The np is the number of spectral lines in the current echo signal spectrum diagram; The value of M is a positive integer.

2. The low-latency signal-to-noise ratio calculation method based on FPGA as claimed in claim 1, characterized in that: In step 11, M / 2 y ×(np) to achieve the accuracy required for signal-to-noise ratio, i.e. M / 2 y ×(np) is 1.

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