A conversion device and method based on a hull sonar closed data structure

Abstract

The application relates to a conversion device and method based on a hull sonar closed data structure, the conversion device is based on customized machine box assembly design, and the conversion device comprises a power board and a power interface, a main control board, a gigabit network RJ45 interface and an LVDS interface; the main control board adopts Xilinx FPGA and is the control core of the conversion device; one end of the main control board is connected between a GMII to MDI gigabit network PHY and the gigabit network RJ45 interface, and the other end is connected between a two-way single-end to differential converter and the LVDS interface. A recording state design method is based on the conversion device and existing sonar equipment building design, and comprises the following steps: recording state, playback state and pause state. The conversion device and method convert hull sonar array element data into network data through the conversion device, realize real-time network transmission of the hull sonar array element data, and ensure the recording, playback function of the recording equipment of the hull sonar equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to hull sonar detection technology, and in particular to a conversion device and method based on a closed data structure of a hull sonar. BACKGROUND

[0002] In order to adapt to the development of technology, the existing hull sonar needs to be upgraded and improved, especially the improvement of the signal processing algorithm of the existing hull sonar, so as to improve the scientific research experiment and application efficiency of the hull sonar. After the improvement of the algorithm, the improved algorithm needs to be verified with the ship. At present, the hull sonar equipment cannot transmit the array element data to the external processing platform in real time for algorithm verification without affecting the normal use of the original equipment. The improved algorithm verification can only use the off-line verification of the sea test data recorded by the recording device, and cannot carry out algorithm verification with the ship. It cannot be compared with the actual installation processing result, which brings inconvenience to the algorithm improvement. SUMMARY

[0003] Therefore, the technical problem to be solved by the present application is to overcome the problem of hull sonar improved algorithm verification with the ship, improved algorithm processing result comparison with actual installation processing result, so as to provide a conversion device and method based on a closed data structure of a hull sonar.

[0004] In order to solve the above technical problems, the conversion device based on the closed data structure of the hull sonar of the present application is based on the assembly design of the customized machine box. The conversion device includes a power board and a power interface, a main control board, a gigabit network RJ45 interface and an LVDS interface. The main control board adopts Xilinx FPGA, and is the control core of the conversion device. One end of the main control board is connected between the gigabit network PHY and the gigabit network RJ45 interface through GMII to MDI conversion, and the other end is connected between the LVDS interface through two-way single-ended to differential converter. The power board is provided with a power interface, and an external power supply is connected. At the same time, the output end of the power board is connected with the main control board through a power line to provide 24V DC voltage.

[0005] In an embodiment of the present application, the customized machine box is composed of a front panel, a rear panel and a heat dissipation device. The front panel is provided with interfaces including AC power input switch, DC power switch, power indicator light and reinforced gigabit network RJ45 interface. At the same time, the rear panel interface is provided with two-way LVDS interface.

[0006] In an embodiment of the present application, the gigabit network RJ45 interface transmits the network data output by the main control board to the improved algorithm processing platform.

[0007] In one embodiment of the present application, the power board is composed of an input filter component and a power conversion component, wherein the input filter component integrates an input fuse and an input switch, and the filtered AC power is connected to the power conversion component to convert 24V DC voltage for the use of the back-end main control board.

[0008] In one embodiment of the present application, the power interface is composed of an ICE320-C14 power socket, a boat-shaped power switch and a fuse holder.

[0009] In one embodiment of the present application, the main control board serves as a gigabit network conversion dual-channel LVDS interface module in the conversion device, wherein the main processor is Xilinx FPGA XC6SLX16-2CSG324I, and the working frequency is adjustable.

[0010] In one embodiment of the present application, the LVDS interface adopts a marine plug, and includes an LVDS interface I and an LVDS interface II.

[0011] Another aspect of the present application further provides a recording state design method of the conversion device, which is based on the conversion device and the existing sonar equipment building design, and includes the following steps:

[0012] Step S1: recording state, the LVDS interface II receives a recording instruction of a sonar equipment recording device, specifically a DTE1 or ready1 signal, and transmits the instruction to a sonar equipment signal processor through the LVDS interface I, and the sonar equipment signal processor returns data DATA and a write clock WD_STB;

[0013] Step S2: receiving the data returned by the sonar equipment signal processor, the LVDS interface I packages the data and uploads the data to the sonar equipment recording device;

[0014] Step S3: playback state, the LVDS interface II receives a playback instruction of the recording device, specifically a DTE1 or ready1 signal, and transmits the instruction to the sonar device through the LVDS interface I, and the sonar device returns a playback time request clock DTR;

[0015] Step S4: the LVDS interface II transmits the DTR to the recording device, the recording device returns a read clock RD_STB1 and data DATA1, and the LVDS interface I transmits the data to the sonar device and packages the data for uploading;

[0016] Step S5: pause state, the LVDS interface II receives a pause instruction of the recording device, specifically a DTE1 or ready1 signal, and transmits the instruction to the sonar device through the LVDS interface I, and the sonar device returns a playback time request clock DTR;

[0017] Step S6: LVDS interface II transmits DTR to recording device, recording device stops data transmission, LVDS interface I has no data reception, data packet network suspension, and data transmission to sonar device suspension.

[0018] In an embodiment of the present application, the LVDS interface I is connected to the top socket of the sonar device receiver cabinet through an adapter cable.

[0019] In an embodiment of the present application, the LVDS interface II is connected to the recording device through the original cable or in combination with an adapter cable.

[0020] The above technical solution of the present application has the following advantages compared with the prior art: the conversion device and method of the present application convert the hull sonar array element data into network data through the conversion device, realize real-time network transmission of the hull sonar array element data, and in the recording / playback process of the hull sonar recording device, the transmitted LVDS data is converted into network data by the conversion device and forwarded to the improved algorithm processing platform, and through the internal logic control of the conversion device, the recording and playback functions of the recording device of the hull sonar equipment are ensured to be normal. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in combination with the accompanying drawings.

[0022] Figure 1 is the internal connection block diagram of the conversion device based on the closed data structure of the hull sonar of the present application;

[0023] Figure 2 is the composition principle block diagram of the master control module of the present application;

[0024] Figure 3 is the recording state design flow block diagram of the conversion device of the present application;

[0025] Figure 4 is the playback state design flow block diagram of the conversion device of the present application;

[0026] Figure 5 is the pause state design flow block diagram of the conversion device of the present application;

[0027] Figure 6 is the working process principle diagram of the conversion device of the present application;

[0028] Figure 7 is the use method flow block diagram of the conversion device of the present application. DETAILED DESCRIPTION

[0029] As Figure 1 andFigure 2 As shown in the embodiment, the conversion device based on the closed data structure of the hull sonar is based on the customized machine box assembly design. The conversion device comprises a power board and a power interface, a main control board, a gigabit network RJ45 interface and an LVDS interface. The main control board adopts Xilinx FPGA and is the control core of the conversion device. One end of the main control board is connected between the GMII to MDI gigabit network PHY and the gigabit network RJ45 interface, and the other end is connected between the two-way single-ended to differential converter and the LVDS interface. The power board input end is provided with the power interface, and an external power supply is connected. The power board output end is connected with the main control board through the power line to provide 24V DC voltage.

[0030] Further, as shown in the embodiment, Figure 2 The main function of the main control module is to input MDI signal (gigabit network) from outside, convert it into GMII signal through the PHY chip, and give it to the FPGA. After the FPGA is bridged through the internal logic, it is converted into 2-way LVDS interface (self-defined) to 2-way navigation plug.

[0031] The customized machine box is composed of a front panel, a rear panel and a heat dissipation device. The front panel is provided with interfaces including AC power input switch, DC power switch, power indicator, and reinforced gigabit network RJ45 interface. The rear panel interface is provided with two-way LVDS interface.

[0032] The gigabit network RJ45 interface forwards the network data output by the main control board to the improved algorithm processing platform.

[0033] The power board is composed of an input filter component and a power conversion component. The input filter component integrates an input fuse and an input switch. The filtered AC power is converted into 24V DC voltage by the power conversion component for use by the rear-end main control board.

[0034] The power interface is composed of an ICE320-C14 power socket, a ship-shaped power switch and a fuse holder.

[0035] The main control board serves as the gigabit network to two-way LVDS interface module in the conversion device. The main processor is Xilinx FPGA XC6SLX16-2CSG324I, and the working frequency is adjustable.

[0036] The LVDS interface adopts a navigation plug and includes LVDS interface I and LVDS interface II.

[0037] Further, the main control board is matched with the software part, the record state design method of the conversion device includes record state design, playback state design, pause state design, realizes that the LVDS format data sent by the sonar equipment signal processor is received, is sent through the gigabit Ethernet after the format conversion through the FPGA, simultaneously with the data transmission to the sonar equipment record device in the LVDS format;The LVDS format data of the sonar equipment record device is received, is sent through the gigabit Ethernet after the format conversion through the FPGA, simultaneously with the data transmission back to the sonar equipment signal processor.

[0038] A record state design method of a conversion device, the record state design method is based on the conversion device and the existing sonar equipment building design, including the following steps:

[0039] Step S1: as shown in Figure 3 Record state, LVDS interface II receives the record instruction of the sonar equipment record device, specifically DTE1 or ready1 signal, and the instruction is transmitted to the sonar equipment signal processor through LVDS interface I, and the sonar equipment signal processor returns data DATA and write clock WD_STB;

[0040] Step S2: receiving the data returned by the sonar equipment signal processor, LVDS interface I packs the data and uploads the network, and simultaneously transmits the data to the sonar equipment record device;

[0041] Step S3: as shown in Figure 4 Playback state, LVDS interface II receives the playback instruction of the record device, specifically DTE1 or ready1 signal, and the instruction is transmitted to the sonar device through LVDS interface I, and the sonar device returns the playback time request clock DTR;

[0042] Step S4: LVDS interface II transmits DTR to the record device, the record device returns read clock RD_STB1 and data DATA1, and LVDS interface I transmits the data to the sonar device, and simultaneously packs the data and uploads the network;

[0043] Step S5: as shown in Figure 5 Pause state, LVDS interface II receives the pause instruction of the record device, specifically DTE1 or ready1 signal, and the instruction is transmitted to the sonar device through LVDS interface I, and the sonar device returns the playback time request clock DTR;

[0044] Step S6: LVDS interface II transmits DTR to the record device, the record device stops data transmission, LVDS interface I has no data reception, data packet uploading is suspended, and data transmission to the sonar device is suspended.

[0045] The LVDS interface I is connected to the socket on the top of the sonar equipment receiving cabinet through a switching cable.

[0046] The LVDS interface II is connected to the recording device via the original cable or a matching adapter cable.

[0047] Furthermore, if Figure 6 As shown, the conversion device defaults to a recording state level, causing the LVDS interface board in the sonar equipment signal processor to always send data out;

[0048] The conversion device always converts LVDS data into network data and outputs it to the improved algorithm processing platform;

[0049] After the conversion device obtains the recording status of the sonar equipment recording device, it sends the LVDS data to the sonar equipment recording device through its own LVDS interface while performing data conversion to realize the recording function;

[0050] After the conversion device obtains the playback status of the sonar equipment recording device, it terminates the default recording state level and sends the playback state level, causing the sonar equipment signal processor to enter the playback state (waiting for LVDS data). It then splits the LVDS data played back by the sonar equipment recording device into two parts, forwarding one path to the sonar equipment signal processor and the other path to be converted into network data and output to the improved algorithm processing platform.

[0051] Furthermore, if Figure 7 As shown, the LVDS interface I of the conversion device is connected to the sonar equipment signal processor, the LVDS interface II of the conversion device is connected to the sonar equipment recording device, and the gigabit network interface of the conversion device is connected to the improved algorithm processing platform.

[0052] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A method of designing a recording state of a conversion device, characterized by, The method comprises the following steps: Step S1: recording state, the LVDS interface II receives the recording instruction of the sonar equipment recording device, specifically DTE1 or ready1 signal, and transmits the instruction to the sonar equipment signal processor through the LVDS interface I, and the sonar equipment signal processor returns data DATA and write clock WD_STB; Step S2: receiving the data returned by the sonar equipment signal processor, the LVDS interface I uploads the data packet to the network, and transmits the data to the sonar equipment recording device; Step S3: playback state, the LVDS interface II receives the playback instruction of the recording device, specifically DTE1 or ready1 signal, and transmits the instruction to the sonar device through the LVDS interface I, and the sonar device returns the playback time request clock DTR; Step S4: the LVDS interface II transmits DTR to the recording device, the recording device returns read clock RD_STB1 and data DATA1, and the LVDS interface I transmits the data to the sonar device, and uploads the data packet to the network; Step S5: pause state, the LVDS interface II receives the pause instruction of the recording device, specifically DTE1 or ready1 signal, and transmits the instruction to the sonar device through the LVDS interface I, and the sonar device returns the playback time request clock DTR; Step S6: the LVDS interface II transmits DTR to the recording device, the recording device stops data transmission, the LVDS interface I has no data reception, the data packet is uploaded to the network, and the data transmission to the sonar device is paused.

2. A method of designing the recording state of a conversion device according to claim 1, characterized in that: The LVDS interface I is connected with the top socket of the sonar device receiver cabinet through a conversion cable.

3. The recording state design method of a conversion device according to claim 1, characterized in that: The LVDS interface II is connected with the recording device through the original cable or a conversion cable.

4. A conversion device based on the closed data structure of the hull sonar, said conversion device is based on the recording state design method and the custom machine box assembly design according to any one of claims 1-3, characterized in that, The conversion device comprises a power board and a power interface, a main control board, a gigabit network RJ45 interface and an LVDS interface. The main control board adopts Xilinx FPGA and is the control core of the conversion device. One end of the main control board is connected between the gigabit network PHY and the gigabit network RJ45 interface through GMII to MDI conversion, and the other end is connected between the LVDS interface through two-way single-ended to differential converter. The power board is provided with a power interface at the input end, and an external power supply is connected. The power board output end is connected with the main control board through a power line to provide 24V DC voltage.

5. The conversion device based on the closed data structure of the hull sonar according to claim 4, characterized in that: The customized machine box is composed of a front panel, a rear panel and a heat dissipation device. The front panel is provided with interfaces including an AC power input switch, a DC power switch, a power indicator light and a reinforced gigabit network RJ45 interface. The rear panel interface is provided with two-way LVDS interface.

6. The conversion device based on the closed data structure of the hull sonar according to claim 4, characterized in that: The gigabit network RJ45 interface forwards the network data output by the main control board to the improved algorithm processing platform.

7. The conversion device based on the closed data structure of the hull sonar according to claim 4, characterized in that: The power board is composed of an input filter component and a power conversion component. The input filter component is integrated with an input fuse and an input switch. The filtered AC power is converted into 24V DC voltage by the power conversion component for use by the back-end main control board.

8. The conversion device based on the closed data structure of the hull sonar according to claim 4, characterized in that: The power interface is composed of an ICE320-C14 power socket, a ship-shaped power switch and a fuse holder.

9. The conversion device based on the closed data structure of hull sonar according to claim 4, characterized in that: The main control board is used as a gigabit network conversion dual LVDS interface module, wherein the main processor is Xilinx FPGA XC6SLX16-2CSG324I, and the working frequency is adjustable.

10. The conversion device based on the closed data structure of the hull sonar according to claim 4, characterized in that: The LVDS interface adopts an aviation plug, and comprises an LVDS interface I and an LVDS interface II.

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