Fault recording triggering method and device

Abstract

The present disclosure relates to a fault recording triggering method, device, computer equipment, and storage medium, the method comprising: collecting continuous power frequency current signals of a set number of cycles closest to the current moment, processing the continuous power frequency current signals to obtain a periodic first discrete sequence; performing sinusoidal fitting on the first discrete sequence to obtain a sinusoidal function; sampling the sinusoidal function to obtain a second discrete sequence of a single cycle; performing a difference calculation between the third discrete sequence of the cycle closest to the current moment in the first discrete sequence and the second discrete sequence to obtain a first cycle difference; judging whether the first cycle difference of the power frequency current signal of each phase reaches a preset signal mutation triggering condition, performing a logical operation on the judgment results of all phases, and triggering the recording when the logical operation output is yes. The present disclosure reduces the omission of fault recording, while improving the accuracy of the recording triggering timing and reducing invalid waveforms.

Description

Technical Field

[0001] The present disclosure relates to the field of data analysis, and in particular to a fault recording triggering method and device. Background Art

[0002] Cables are bridges between power supply equipment and power-consuming equipment, and are mainly used for power transmission and distribution. Among them, high-voltage cables such as XLPE high-voltage cables are increasingly widely used, but their laying environments are complex and diverse, including direct burial, cable trenches, drainage pipes, tunnels and other environments, which cause certain difficulties in troubleshooting and locating faults. Especially for mixed-frame lines, T-type lines and other occasions, the primary difficulty is to determine the fault interval or branch, followed by accurate positioning. Therefore, in recent years, distributed online fault recording and positioning systems have been promoted and applied, and fault recording devices are arranged in each branch segment of overhead lines or cables, using precise synchronization methods such as GNSS (Global Navigation Satellite System) and PTP (Precision Time Protocol) to achieve accurate fault positioning.

[0003] As a distributed recording device, the key is how to automatically trigger the fault recording, timely and completely capture the signal at the time of the fault, including the high-frequency traveling wave current signal and the low-frequency power frequency current signal, and then use the principle of double-end positioning to process the fault recording data at both ends of the master and slave to obtain the interval and precise location of the fault. At present, the industry generally uses threshold triggering to trigger automatic fault recording, and a fixed threshold must be preset manually. In this way, on the one hand, it is inevitable to rely on unreliable experience values, which will leak if they are too high and flood if they are too low; on the other hand, the impedance characteristics, operating loads and fault causes of the cable are different, and the mutation amplitude of the fault signal will also be different. The fixed mutation threshold that is one-size-fits-all is not resistant enough. Summary of the invention

[0004] Based on this, it is necessary to provide a fault recording triggering method, device, computer equipment, storage medium and computer program product to address the above technical problems.

[0005] In a first aspect, the present disclosure provides a fault recording triggering method. The method comprises:

[0006] For each phase power frequency current signal, collect the continuous power frequency current signal of a set number of cycles closest to the current moment, and process the continuous power frequency current signal to obtain a periodic first discrete sequence;

[0007] Performing sine fitting on the first discrete sequence to obtain a sine function;

[0008] Sampling the sine function according to a set sampling frequency to obtain a second discrete sequence of a single period;

[0009] Subtract the third discrete sequence in the first discrete sequence that has the closest period to the current moment from the second discrete sequence to obtain a first period difference;

[0010] It is determined whether the first period difference of each phase power frequency current signal reaches a preset signal mutation trigger condition, a logic operation is performed on the judgment results of all phases, and the recording is triggered if the output of the logic operation is yes.

[0011] In one embodiment, the collected continuous power frequency current signal is superimposed to eliminate white noise interference, so as to obtain the first discrete sequence after denoising.

[0012] In one embodiment, performing sinusoidal fitting on the first discrete sequence to obtain a sinusoidal function comprises:

[0013] The amplitude, angle offset, and amplitude offset of the sine function are calculated using a trigonometric function algorithm and a sine curve algorithm.

[0014] In one embodiment, the step of calculating the difference between the third discrete sequence in the first discrete sequence having the closest period to the current moment and the second discrete sequence to obtain the first period difference comprises:

[0015] The third discrete sequence is compared with the second discrete sequence to calculate a first-order difference.

[0016] In one embodiment, the determining whether the first period difference of each phase power frequency current signal reaches a preset signal mutation trigger condition, performing a logic operation on all phase determination results, and triggering the recording when the logic operation output is yes includes:

[0017] Calculate and obtain each corresponding mutation upper limit threshold according to the continuous power frequency current signal of each phase;

[0018] Determine the difference between the first period difference of each phase and the mutation upper limit threshold value, if the first period difference is greater than or equal to the corresponding mutation upper limit threshold value, then determine that the preset signal mutation trigger condition is met;

[0019] The judgment results of all phases are obtained and logic operations are performed. When the judgment results of the phases all meet the preset signal mutation trigger conditions, the logic operation output is.

[0020] In one embodiment, the step of calculating each corresponding mutation upper limit threshold according to the continuous power frequency current signal of each phase comprises:

[0021] Calculating a second period difference between two consecutive adjacent periods in the first discrete sequence;

[0022] The step-by-step range of the mutation outlier value is calculated using mathematical statistics methods to determine the mutation upper limit threshold.

[0023] In a second aspect, the present disclosure further provides a fault recording triggering device. The device comprises:

[0024] An acquisition module, for acquiring continuous power frequency current signals of a set number of cycles closest to the current moment for each phase power frequency current signal, and processing the continuous power frequency current signals to obtain a periodic first discrete sequence;

[0025] A sine fitting module, used for performing a sine fitting on the first discrete sequence to obtain a sine function;

[0026] A sampling module, used for sampling the sine function according to a set sampling frequency to obtain a second discrete sequence of a single period;

[0027] A difference module, used for performing difference calculation between a third discrete sequence in the first discrete sequence with a cycle closest to the current moment and the second discrete sequence to obtain a first cycle difference;

[0028] The condition judgment module is used to judge whether the first period difference of each phase power frequency current signal reaches the preset signal mutation trigger condition, perform logical operation on the judgment results of all phases, and trigger the recording when the logical operation output is yes.

[0029] In one embodiment, the acquisition module includes:

[0030] The denoising unit is used to eliminate white noise interference from the collected continuous power frequency current signal by superposition to obtain the denoised first discrete sequence.

[0031] In one embodiment, the sine fitting module includes:

[0032] An algorithm unit is used to calculate the amplitude, angle offset, and amplitude offset of the sine function using a trigonometric function algorithm and a sine curve algorithm.

[0033] In one embodiment, the difference module includes:

[0034] The calculation unit is used to compare the third discrete sequence with the second discrete sequence and calculate the first-order difference.

[0035] In one embodiment, the condition determination module includes:

[0036] A threshold unit, used for calculating each corresponding mutation upper limit threshold according to the continuous power frequency current signal of each phase;

[0037] A single-phase judgment unit, used for judging the difference between the first cycle value of each phase and the mutation upper limit threshold value, and if the first cycle difference value is greater than or equal to the corresponding mutation upper limit threshold value, the judgment result is that a preset signal mutation trigger condition is reached;

[0038] The logic judgment unit is used to obtain the judgment results of all phases and perform logic operations. When the judgment results of the phases all meet the preset signal mutation trigger conditions, the logic operation output is.

[0039] In one embodiment, the threshold unit comprises:

[0040] An adjacent period calculation subunit, which calculates a second period difference between two consecutive adjacent periods in the first discrete sequence;

[0041] The mathematical statistics subunit is used to calculate the step range of the mutation abnormal value by using the mathematical statistics method to determine the mutation upper limit threshold.

[0042] In a third aspect, the present disclosure further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the above-mentioned fault recording triggering method are implemented.

[0043] In a fourth aspect, the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the above-mentioned fault recording triggering method are implemented.

[0044] In a fifth aspect, the present disclosure further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned fault recording triggering method are implemented.

[0045] The above-mentioned fault recording triggering method, device, computer equipment, storage medium and computer program product have at least the following beneficial effects:

[0046] The present invention uses the real-time collected industrial frequency current signal as historical data, performs sinusoidal fitting to simulate the waveform of the next cycle, compares it with the actual waveform, and logically determines whether to trigger the recording based on the preset signal mutation trigger condition. The recording trigger is more sensitive, reduces the omission of fault recording, and at the same time improves the accuracy of the recording trigger timing and reduces invalid waveforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A waveform diagram of a power frequency current signal when a sudden change occurs in an embodiment;

[0049] Figure 2 A schematic diagram of a flow chart of a fault recording triggering method in an embodiment;

[0050] Figure 3 A schematic diagram of a process of triggering a wave recording step in an embodiment;

[0051] Figure 4 A schematic diagram of a process for determining a mutation upper threshold in one embodiment;

[0052] Figure 5 is a box plot of the second period difference in one embodiment;

[0053] Figure 6 is a structural block diagram of a fault recording triggering device in one embodiment;

[0054] Figure 7 It is a structural block diagram of a condition judgment module in an embodiment;

[0055] Figure 8 is a structural block diagram of a threshold unit in one embodiment;

[0056] Fig. 9 FIG. 4 is a block diagram of the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0059] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are only examples of devices and methods consistent with some aspects of the present disclosure as detailed in the attached claims. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, product or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such process, method, product or device. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or device including the elements. For example, if the words first, second, etc. are used to represent the name, they do not represent any specific order.

[0060] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0061] The fault recording triggering method provided in the embodiment of the present application can be applied to a distributed fault recording device. When a high-voltage cable fault occurs, it is often accompanied by a trip and power failure, causing the operating current of the three phases to drop to zero. At the moment of the fault, the power frequency current signal will inevitably undergo a sudden change and then tend to zero, such as Figure 1 As shown. Due to the different causes of faults and the different impedance characteristics of cables, the amplitude of the power frequency current signal mutation is also different; and due to the inevitable zero drift and interference of the detection system, it is difficult to ensure that the power frequency amplitude will absolutely become zero in a short time (the recording time is generally ≤500ms). Therefore, it is difficult to judge the mutation through a suitable fixed threshold, and it is also impossible to simply judge the tripping zero through zero value comparison. A more reliable automatic fault judgment mechanism is needed.

[0062] Based on this, in some embodiments of the present disclosure, Figure 2 As shown, a fault recording triggering method is provided, comprising the following steps:

[0063] Step S10: for each phase power frequency current signal, collect the continuous power frequency current signal of a set number of cycles closest to the current moment, and process the continuous power frequency current signal to obtain a periodic first discrete sequence.

[0064] Specifically, the high-voltage cable is generally a three-phase cable. For the power frequency current signal of each phase, the continuous power frequency current signal of the set number of cycles closest to the current moment is collected. In order to reduce the complexity of data processing, the current moment can be selected at the end of each complete cycle. That is, each time the power frequency current signal of a cycle is collected, the continuous power frequency current signal of the nearest m cycles is collected. Among them, m is a positive integer, preferably a positive integer greater than or equal to 50. The collected continuous power frequency current signal is sampled and processed to obtain a periodic first discrete sequence.

[0065] Step S20: performing sinusoidal fitting on the first discrete sequence to obtain a sinusoidal function.

[0066] Specifically, the first discrete sequence is sinusoidally fitted so that the collected continuous power frequency current signal finally generates a standard sinusoidal function. When the first discrete sequence is sinusoidally fitted, Matlab software tools can be used for fitting, or a linear regression model can be used for multi-layer neural network fitting.

[0067] Step S30: sampling the sine function according to the set sampling frequency to obtain a second discrete sequence of a single period.

[0068] Specifically, according to the standard sine function obtained in step S20, a complete cycle is selected for sampling to obtain a second discrete sequence of a single cycle.

[0069] Step S40: performing a difference calculation between the third discrete sequence in the first discrete sequence and the period closest to the current moment and the second discrete sequence to obtain a first period difference.

[0070] Specifically, a cycle closest to the current moment in the first discrete sequence is selected to form a third discrete sequence. The second discrete sequence and the third discrete sequence are both discrete sequences within a single cycle, and have the same sampling frequency. The second discrete sequence can be regarded as an expected value, and the third discrete sequence can be regarded as an actual value. The second discrete sequence and the third discrete sequence are subtracted to calculate the first cycle difference between the two.

[0071] Step S50: determine whether the first period difference of each phase power frequency current signal reaches a preset signal mutation trigger condition, perform a logic operation on the determination results of all phases, and trigger the recording if the logic operation output is yes.

[0072] Specifically, according to steps S10-S40, the first cycle difference of each phase can be calculated, and the first cycle difference of each phase is judged with each corresponding signal mutation trigger condition to obtain the judgment result of each phase. Finally, a logical operation is performed according to the judgment result of each phase to output the final result. The logical operation may include but is not limited to AND, OR, weight calculation, etc. The recording is triggered when the logical operation output is yes.

[0073] In the above-mentioned fault recording triggering method, the real-time collected industrial frequency current signal is used as historical data, and a sine fitting is performed to simulate the waveform of the next cycle, which is compared with the actual waveform. The recording is triggered based on the preset signal mutation trigger condition through logic judgment. The recording trigger is more sensitive, reducing the omission of fault recording, while improving the accuracy of the recording trigger timing and reducing invalid waveforms.

[0074] In some embodiments of the present disclosure, the above step S10 includes:

[0075] The collected continuous power frequency current signal is superimposed to eliminate white noise interference, so as to obtain the first discrete sequence after denoising.

[0076] Specifically, when collecting the power frequency current signal, it is inevitably interfered by white noise. White noise generally refers to noise whose power spectrum density is constant in the entire frequency domain. Random noise with the same energy density at all frequencies is called white noise. This embodiment reduces the interference of white noise by superposition, and the first discrete sequence W after denoising is obtained as:

[0077]

[0078] This embodiment reduces the interference of white noise by superposition, which helps to improve the accuracy of subsequent data processing.

[0079] In some embodiments of the present disclosure, the above step S20 includes:

[0080] The amplitude, angle offset, and amplitude offset of the sine function are calculated using a trigonometric function algorithm and a sine curve algorithm.

[0081] Specifically, this embodiment implements sine fitting through trigonometric function algorithm and sine curve algorithm. Assume that the discrete sampling sequence of the power frequency current signal of one period (for example, 20ms) is: y(i), i = 0, 1, ..., N-1, where N is the number of sampling points in one period, and its corresponding sine function is:

[0082]

[0083] Among them, A is the amplitude, B is the angle offset, that is, the initial angle phase, C is the amplitude offset, t is the time, and T is the cycle length. In order to simplify the calculation, the trigonometric function and the characteristics of the sine curve are used for calculation.

[0084] (1) Calculate the C value

[0085] For a periodic sinusoid, its mean (i.e., baseline) is equal to the amplitude offset C:

[0086]

[0087] The corresponding discrete sequence formula is:

[0088]

[0089] (2) Calculate the A value

[0090] Performing definite integral operation on the sine function, we get:

[0091]

[0092] set up

[0093]

[0094] but

[0095]

[0096] therefore

[0097]

[0098] Considering the symmetry of the sine function, the definite integral from 0 to T / 4 accounts for one quarter of the absolute area of ​​the entire period of the sine wave. In order to reduce the symmetry error, the absolute value full integral from 0 to T is used in the actual calculation, that is:

[0099]

[0100] The corresponding discrete sequence formula is:

[0101]

[0102] (3) Calculate the B value according to the trigonometric formula:

[0103]

[0104] Do the definite integral and we get:

[0105]

[0106] Also available:

[0107]

[0108] Do the definite integral and we get:

[0109]

[0110] therefore:

[0111]

[0112]

[0113]

[0114] Only when p1 and p2 are only valid when

[0115] And f1 and f2 can actually be obtained by the discrete sequence summation formula:

[0116]

[0117]

[0118] therefore

[0119]

[0120] In practical application of this embodiment, the zero-crossing sampling can be controlled to make B=0, which can further simplify the calculation.

[0121] In this embodiment, the amplitude, angle offset, and amplitude offset of the sine function are calculated by a trigonometric function algorithm and a sine curve algorithm. The algorithm is simple and controllable, and sine fitting can be performed quickly and accurately.

[0122] In some embodiments of the present disclosure, the above step S40 includes:

[0123] The third discrete sequence is compared with the second discrete sequence to calculate a first-order difference.

[0124] Specifically, the second discrete sequence is recorded as P, the third discrete sequence is recorded as W, and the first-order difference is used. Then the first period difference e is:

[0125]

[0126] Wherein, i=0,1,…,N-1, and N is the number of sampling points in one cycle.

[0127] In this embodiment, by subtracting the second discrete sequence from the third discrete sequence, the period difference between the expected value and the actual value can be calculated, and the period difference is used to determine whether to trigger the recording, so that the recording triggering is more reliable.

[0128] In some embodiments of the present disclosure, Figure 3 As shown, the above step S50 includes:

[0129] Step S52: Calculate and obtain each corresponding mutation upper limit threshold according to the continuous power frequency current signal of each phase.

[0130] Specifically, the mutation upper limit threshold for each corresponding phase is calculated based on the collected continuous power frequency current signal of each phase, that is, the mutation upper limit threshold is specified based on a priori statistical values.

[0131] Step S54: Determine the magnitude of the first period difference of each phase and the mutation upper limit threshold. If the first period difference is greater than or equal to the corresponding mutation upper limit threshold, the determination result is that the preset signal mutation trigger condition is met.

[0132] Specifically, the calculated first period difference of each phase is compared with each corresponding mutation upper limit threshold. If the first period difference is greater than or equal to the corresponding mutation upper limit threshold, it can be judged that the phase has reached the preset signal mutation trigger condition. Otherwise, it can be judged that the phase has not reached the preset signal mutation trigger condition.

[0133] Step S56: Obtain the judgment results of all phases and perform logic operations. When the judgment results of the phases all meet the preset signal mutation trigger condition, the logic operation output is.

[0134] Specifically, a logic operation is performed on the judgment result of each phase, for example, an AND logic operation is used, that is, when the judgment results of all phases meet the preset signal mutation trigger condition, the logic operation output is yes, otherwise the logic operation output is no. When the logic operation output is yes, the wave recording is triggered.

[0135] In this embodiment, a corresponding mutation upper limit threshold is set for each phase, and a logic operation is performed on the judgment results of all phases, so that the wave recording trigger mechanism is more flexible and accurate.

[0136] In some embodiments of the present disclosure, Figure 4 As shown, the above step S52 includes:

[0137] Step S522: Calculate the second period difference between two consecutive adjacent periods in the first discrete sequence.

[0138] Specifically, the collected power frequency current signal is used as historical data to calculate the second period difference between two consecutive adjacent periods in the first discrete sequence. Assuming that the discrete sequences of two consecutive periods are represented by W and P respectively, and N is the number of sampling points in one period, the second period difference e is:

[0139]

[0140] Step S524: Calculate the step-by-step range of the mutation abnormal value using a mathematical statistics method to determine the mutation upper limit threshold.

[0141] Specifically, the mathematical statistics can be a combination of one or more of normal distribution and box plot, or other mathematical statistics tools. In this embodiment, a combination of normal distribution and box plot is used.

[0142] The mean u and mean square error s of the normal distribution are calculated according to the second period difference calculated in step S522:

[0143]

[0144]

[0145] According to the 6σ criterion of normal distribution, the outlier threshold is

[0146] th=μ±3σ

[0147] Secondly, in actual application, data samples are not easy to obey normal distribution, and the statistical methods of mean and mean square error are less resistant, so non-normal distribution needs to be considered. A box plot that is easy to observe outliers is used to examine the data distribution. The lower quartile Q1, median Q2, and upper quartile Q3 are calculated by sorting, and the quartile gap is:

[0148] IRQ = Q3 - Q1

[0149] Take the upper and lower limits H m and L m For mild anomaly threshold:

[0150] H m =Q3+1.5IRQ,

[0151] L m =Q1-1.5IRQ

[0152] Take the upper outer limit H e and the lower outer limit L e is the extreme anomaly threshold:

[0153] H e =Q3+3IRQ,

[0154] L e =Q1-3IRQ

[0155] Box plots such as Figure 5 As shown, the upper and lower thresholds of the period difference mutation are:

[0156] h=max(μ+3σ,H e)

[0157] l=min(μ-3σ,L e )

[0158] Considering that the second cycle difference is calculated using an absolute value, there is no need to determine the lower limit, and only the mutation upper limit threshold needs to be determined.

[0159] This embodiment uses the collected continuous power frequency current signal as historical prior sample data, and calculates the distribution range of the mutation abnormal value through mathematical statistics, so as to obtain the appropriate mutation upper limit threshold at any time according to sufficient historical data, which serves as the trigger threshold for the fault mutation of the power frequency current signal, thereby enhancing the reliability of the automatic fault judgment mechanism.

[0160] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0161] Based on the same inventive concept, the disclosed embodiment also provides a fault recording trigger device for implementing the fault recording trigger method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more fault recording trigger device embodiments provided below can refer to the limitations of the fault recording trigger method above, and will not be repeated here.

[0162] The device may include a system (including a distributed system), software (application), module, component, server, client, etc. using the method described in the embodiments of this specification and a device in combination with necessary implementation hardware. Based on the same innovative concept, the device in one or more embodiments provided in the embodiments of the present disclosure is as described in the following embodiments. Since the implementation scheme and method for solving the problem of the device are similar, the implementation of the specific device in the embodiments of this specification can refer to the implementation of the aforementioned method, and the repetitions will not be repeated. As used below, the term "unit" or "module" can implement a combination of software and / or hardware for predetermined functions. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0163] In some embodiments of the present disclosure, Figure 6 As shown, a fault recording triggering device is provided, Z00 may include:

[0164] The acquisition module Z10 is used to acquire the continuous power frequency current signal of a set number of cycles closest to the current moment for each phase power frequency current signal, and process the continuous power frequency current signal to obtain a periodic first discrete sequence;

[0165] A sine fitting module Z20, configured to perform a sine fitting on the first discrete sequence to obtain a sine function;

[0166] A sampling module Z30, used for sampling the sine function according to a set sampling frequency to obtain a second discrete sequence of a single period;

[0167] A difference module Z40, configured to perform a difference calculation between a third discrete sequence in the first discrete sequence having a cycle closest to the current moment and the second discrete sequence to obtain a first cycle difference;

[0168] The condition judgment module Z50 is used to judge whether the first period difference of each phase power frequency current signal reaches the preset signal mutation trigger condition, perform logical operation on the judgment results of all phases, and trigger recording when the logical operation output is yes.

[0169] In some embodiments of the present disclosure, the acquisition module includes:

[0170] The denoising unit is used to eliminate white noise interference from the collected continuous power frequency current signal by superposition to obtain the denoised first discrete sequence.

[0171] In some embodiments of the present disclosure, the sine fitting module includes:

[0172] An algorithm unit is used to calculate the amplitude, angle offset, and amplitude offset of the sine function using a trigonometric function algorithm and a sine curve algorithm.

[0173] In some embodiments of the present disclosure, the difference module includes:

[0174] The calculation unit is used to compare the third discrete sequence with the second discrete sequence and calculate the first-order difference.

[0175] In some embodiments of the present disclosure, Figure 7 As shown, the condition judgment module Z50 includes:

[0176] A threshold unit Z52, used for calculating each corresponding mutation upper limit threshold according to the continuous power frequency current signal of each phase;

[0177] The single-phase judgment unit Z54 is used to judge the difference between the first cycle difference of each phase and the mutation upper limit threshold value. If the first cycle difference is greater than or equal to the corresponding mutation upper limit threshold value, the judgment result is that the preset signal mutation trigger condition is met;

[0178] The logic judgment unit Z56 is used to obtain the judgment results of all phases and perform logic operations. When the judgment results of the phases all meet the preset signal mutation trigger conditions, the logic operation output is.

[0179] In some embodiments of the present disclosure, Figure 8 As shown, the threshold unit Z52 includes:

[0180] The adjacent period calculation subunit Z522 calculates the second period difference between two consecutive adjacent periods in the first discrete sequence;

[0181] The mathematical statistics subunit Z524 is used to calculate the step range of the mutation abnormal value by using the mathematical statistics method to determine the mutation upper limit threshold.

[0182] Each module in the above-mentioned fault recording trigger device can be fully or partially implemented by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules. It should be noted that the division of modules in the embodiments of the present disclosure is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0183] Based on the above-mentioned description of the embodiment of the fault recording triggering method, in another embodiment provided by the present disclosure, a computer device is provided, which may be a terminal device, and its internal structure diagram may be as follows: Fig. 9As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a fault recording triggering method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0184] Those skilled in the art will understand that the structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0185] Based on the description of the embodiment of the fault recording triggering method mentioned above, in another embodiment provided in the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0186] Based on the description of the embodiment of the fault recording triggering method, in another embodiment provided in the present disclosure, a computer program product is provided, including a computer program, which implements the steps in the above-mentioned method embodiments when executed by a processor.

[0187] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0188] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0189] It is understandable that the various embodiments of the above method in this specification are described in a progressive manner, and the same / similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. For related parts, refer to the description of other method embodiments.

[0190] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0191] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A fault recording triggering method, characterized in that: The method comprises: For each phase power frequency current signal, collect the continuous power frequency current signal of a set number of cycles closest to the current moment, and process the continuous power frequency current signal to obtain a periodic first discrete sequence; Performing sine fitting on the first discrete sequence to obtain a sine function; Sampling the sine function according to a set sampling frequency to obtain a second discrete sequence of a single period; A third discrete sequence in the first discrete sequence with the closest period to the current moment is subtracted from the second discrete sequence to obtain a first period difference; the sampling frequency of the third discrete sequence is the same as the set sampling frequency; Calculate and obtain each corresponding mutation upper limit threshold value according to the continuous power frequency current signal of each phase; Determine the magnitude of the first period difference of each phase and the mutation upper limit threshold, and if the first period difference is greater than or equal to the corresponding mutation upper limit threshold, determine that a preset signal mutation trigger condition is met; The judgment results of all phases are obtained and logic operations are performed. When the judgment results of the phases all meet the preset signal mutation trigger condition, the logic operation output is.

2. The method according to claim 1, characterized in that The step of processing the continuous power frequency current signal to obtain a periodic first discrete sequence comprises: The collected continuous power frequency current signal is superimposed to eliminate white noise interference, so as to obtain the first discrete sequence after denoising.

3. The method according to claim 1, characterized in that The performing sinusoidal fitting on the first discrete sequence to obtain a sinusoidal function comprises: The amplitude, angle offset, and amplitude offset of the sine function are calculated using a trigonometric function algorithm and a sine curve algorithm.

4. The method according to claim 1, characterized in that: The step of performing a difference calculation between the third discrete sequence in the first discrete sequence and the second discrete sequence to obtain a first period difference includes: The third discrete sequence is compared with the second discrete sequence to calculate a first-order difference.

5. The method according to claim 1, characterized in that The step of calculating each corresponding mutation upper limit threshold value according to the continuous power frequency current signal of each phase includes: Calculate the second period difference between two consecutive adjacent periods in the first discrete sequence; The step-by-step range of the mutation outlier value is calculated using mathematical statistics methods to determine the mutation upper limit threshold.

6. A fault recording trigger device, characterized in that: The device comprises: An acquisition module, for acquiring continuous power frequency current signals of a set number of cycles closest to the current moment for each phase power frequency current signal, and processing the continuous power frequency current signals to obtain a periodic first discrete sequence; A sine fitting module, used for performing a sine fitting on the first discrete sequence to obtain a sine function; A sampling module, used for sampling the sine function according to a set sampling frequency to obtain a second discrete sequence of a single period; A difference module, used for performing a difference calculation between a third discrete sequence in the first discrete sequence with the closest period to the current moment and the second discrete sequence to obtain a first period difference; the sampling frequency of the third discrete sequence is the same as the set sampling frequency; A threshold unit, used for calculating each corresponding mutation upper limit threshold according to the continuous power frequency current signal of each phase; A single-phase judgment unit, used for judging the magnitude of the first period difference of each phase and the mutation upper limit threshold, if the first period difference is greater than or equal to the corresponding mutation upper limit threshold, the judgment result is that a preset signal mutation trigger condition is reached; The logic judgment unit is used to obtain the judgment results of all phases and perform logic operations. When the judgment results of the phases all meet the preset signal mutation trigger conditions, the logic operation output is.

7. The device according to claim 6, characterized in that The sine fitting module comprises: An algorithm unit is used to calculate the amplitude, angle offset, and amplitude offset of the sine function using a trigonometric function algorithm and a sine curve algorithm.

8. The device according to claim 6, characterized in that The threshold unit comprises: An adjacent period calculation subunit, which calculates a second period difference between two consecutive adjacent periods in the first discrete sequence; The mathematical statistics subunit is used to calculate the step range of the mutation abnormal value by using the mathematical statistics method to determine the mutation upper limit threshold.

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