System and method for processing large data sets

Abstract

The present disclosure provides a system and method for processing a large data set. The device includes: a block array of non-volatile memory cells located on an integrated circuit die; and an arithmetic logic unit located on the integrated circuit die, the arithmetic logic unit being coupled to the block array. The arithmetic logic unit is used to perform arithmetic logic operations on the contents of the block array in response to instructions received from outside the integrated circuit die. The non-volatile memory cells may include NAND-type flash memory cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims the benefit of priority to U.S. Application No. 17 / 087,203, filed on November 2, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to data processing technology, and more particularly to a system and method for processing large data sets. Background Art

[0004] Many recent and growing fields of research and commercial applications rely on very large datasets, such as graph data. Example applications include computational fluid dynamics, computational biophysics, image processing, genome analysis, e-commerce, search engines, machine learning, and neural networks including graph neural networks (GNNs). The size of such large datasets can exceed 10TB or even larger.

[0005] The processing of large data sets is often performed by loading the data sets into a dynamic random access memory (DRAM) that is configured as the main memory of a processor deployed in a distributed computer system. For example, because the dynamic random access memory is volatile, the data set must first be transferred from a permanent storage (e.g., a hard drive) to the dynamic random access memory. This can be an unfavorable and time-consuming operation. After the data set is loaded into the main memory, portions of the data set need to be read from the dynamic random access memory to the processor, processed by the processor, and then written back to the dynamic random access memory. Unfortunately, the access time of the dynamic random access memory, which is limited by factors including, for example, the bandwidth of the computer's data bus, is very slow. For example, accessing the main memory (DRAM) may be an order of magnitude or more slower than the operations that the processor is able to perform. This may result in undesirable and / or unacceptable performance levels. In addition, the cost of such large amounts of dynamic random access memory (e.g., TB size), coupled with the computer systems required to support such large amounts of dynamic random access memory, is generally considered commercially unfeasible, thereby limiting the use of such very large data sets. Summary of the invention

[0006] One object of the present disclosure is to implement an apparatus for processing large data sets.

[0007] Therefore, what is needed is a system and method for processing large data sets. What is also needed is a system and method for processing large data sets that can overcome the bandwidth limitations of transferring large data sets back and forth from main memory to processors. Further, what is needed is a system and method for processing large data sets that can be compatible and complementary to existing systems and methods for processing large data sets (e.g., processing graphs).

[0008] According to an embodiment of the present disclosure, a device is provided, which includes: a block array of non-volatile memory cells, located on an integrated circuit die; an arithmetic logic unit, located on the integrated circuit die, and coupled to the block array. The arithmetic logic unit is used to perform arithmetic logic operations on the contents of the block array in response to instructions received from outside the integrated circuit die. The non-volatile memory cells may include NAND-type flash memory cells.

[0009] According to another embodiment of the present disclosure, a drive controller is provided, which includes: an interface configured to functionally couple the drive controller to multiple memory integrated circuit devices; a bus interface configured to functionally couple the drive controller to a computer system; and a data set controller for performing data set operations on data sets stored in multiple memory integrated circuit devices without transmitting the contents of the data sets through the bus interface.

[0010] According to another embodiment of the present disclosure, a solid-state drive unit is provided, which includes a plurality of non-volatile memory integrated circuit dies of a chip. Each memory integrated circuit die includes a block array of non-volatile memory cells located on the integrated circuit die, and an arithmetic logic unit located on the integrated circuit die and coupled to the block array. The arithmetic logic unit is used to perform arithmetic logic operations on the contents of the block array in response to instructions received from outside the integrated circuit die. The solid-state drive unit also includes: a bus interface configured to functionally couple the drive unit to a computer system; and a data set controller for performing data set operations on data sets stored in a plurality of non-volatile memory integrated circuit dies without transmitting the contents of the data sets through the bus interface.

[0011] Through the above scheme, the bandwidth limitation of transmitting large data sets back and forth from the main memory to the processor can be overcome, so that the large data sets can be processed efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Unless otherwise specified, the accompanying drawings may not be drawn to scale.

[0013] Figure 1 An exemplary block diagram of a memory integrated circuit according to an embodiment of the present disclosure is shown.

[0014] Figure 2 An exemplary block diagram of a novel driving unit for processing a large data set according to an embodiment of the present disclosure is shown.

[0015] Figure 3 Exemplary instructions sent to a memory integrated circuit according to an embodiment of the present disclosure are shown.

[0016] Figure 4 An exemplary data set that facilitates processing of very large data sets according to an embodiment of the present disclosure is shown.

[0017] Figure 5 An exemplary block diagram of an exemplary electronic system is shown, which can be used as a platform for implementing embodiments of the present disclosure. Specific embodiments

[0018] Reference will now be made in detail to various embodiments of the present disclosure, examples of which are shown in the accompanying drawings. Although the present disclosure will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present disclosure as defined by the appended claims. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those of ordinary skill in the art will recognize that the present disclosure can be implemented without these specific details. In other examples, well-known methods, processes, components and circuits are not described in detail to avoid unnecessarily obscuring aspects of the present disclosure.

[0019] The following will describe an embodiment of the present disclosure based on a solid-state drive (SSD) of a NAND-type flash memory, which is functionally connected to a computer system via a high-speed peripheral component interconnect (PCIe) computer expansion bus. These descriptions are exemplary and not restrictive. It should be understood that the embodiments of the present disclosure are very suitable for various memory cell technologies, including, for example, bubble memory, NOR-type flash memory, resistive random access memory (ReRAM), conductive bridge RAM (CBRAM), ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), ferroelectric field effect transistor (FeFET) memory, domain wall memory (DWM), carbon nanotube memory (NRAM), millipede memory, electrochemical random access memory (ECRAM), etc.

[0020] Similarly, embodiments of the present disclosure are well suited for various functional connections of computer systems, including, for example, computer expansion buses, such as Industry Standard Architecture (ISA), Extended ISA (EISA), Micro Channel, Multibus, IEEE 796, IEEE 1196, IEEE 1496, PCI, Computer Automatic Measurement and Control (CAMAC), Instrument Bus (MBus), Runway Bus, Computer Express Link (CXL), etc. In addition, embodiments of the present disclosure are well suited for various peripheral connection buses, such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial ATA (SATA), IEEE 1394, Small Computer System Interface (SCSI), etc.

[0021] Figure 1 An exemplary block diagram of a novel memory integrated circuit 100 of an embodiment of the present disclosure is shown. Although the memory integrated circuit 100 is shown as a NAND-type flash memory, this is exemplary and the embodiments of the present disclosure are not limited to this memory technology. In addition, any size notation, such as array size and / or bus width, is exemplary and not limiting.

[0022] The memory integrated circuit 100 includes a block array 110 of memory cells, such as NAND memory cells. Those skilled in the art will appreciate the distinction between a block array and other types of memory, such as cache memory or register memory. The block array 110 of memory cells includes a plurality of planes, such as n+1, labeled plane 0 120 to plane n 130. For example, each plane may include four thousand (4K) bytes of memory. Memory arrays are often organized into blocks including a plurality of memory cells, organized as a plurality of word lines including a plurality of bit lines. A plane includes a plurality of such blocks. In some embodiments, each plane has an associated pre-fetch buffer (e.g., pre-fetch buffer 122 of plane 0 120) and an associated output buffer (e.g., output buffer 123 of plane 0 120).

[0023] The memory integrated circuit 100 also includes a novel memory-level arithmetic logic unit (ALU) 150. The memory-level arithmetic logic unit 150 is associated with the block array 110. In some embodiments, the memory-level arithmetic logic unit 150 may be located on the same integrated circuit die as the block array 110. The memory-level arithmetic logic unit 150 is configured to perform logic and / or arithmetic operations on the contents of the pre-fetch buffers and output buffers of the planes of the block array 110. For example, as shown, the memory-level arithmetic logic unit 150 may perform operations on the pre-fetch buffer 122 of plane 0 120 and the output buffer 123 of plane 0 120. The memory integrated circuit 100 may include a logic unit (not shown) to selectively route the pre-fetch buffer and the output buffer from any plane of the block array 110 to the memory-level arithmetic logic unit 150. In some embodiments, the memory-level arithmetic logic unit 150 may use the buffers of the memory planes, such as the pre-fetch buffer 122 of plane 0 120 and the output buffer 123 of plane 0 120. In other embodiments, the buffer contents may be duplicated in additional registers dedicated to the memory level arithmetic logic unit 150 .

[0024] The memory-level arithmetic logic unit 150 can generally perform a set of operations to facilitate processing a given data set. According to an embodiment of the present disclosure, any suitable operation can be implemented. Typical operations may include, for example, addition, subtraction, multiplication, division, comparison, shift, rotation, two's complement, multiplication and accumulation (MAC), or, exclusive or, etc. The memory-level arithmetic logic unit 150 may include, for example, a combinational logic unit, a finite state machine and / or a stored program processing unit and any combination of the above, and may also include microcode. The memory-level arithmetic logic unit 150 is configured to receive an opcode to perform a desired operation on the input from the available operation and store the result in an accumulator register 170.

[0025] Figure 2 An exemplary block diagram of a novel drive unit 200 for processing large data sets according to an embodiment of the present disclosure is shown. In some embodiments, the drive unit 200 may be characterized as a solid state drive (SSD). The drive unit 200 includes a memory die array 210, which includes a plurality of memory integrated circuits 211, 212, and 213. There will typically be more than the three shown. The memory integrated circuits 211, 212, and 213 may include, for example, Figure 1 Memory integrated circuit 100. According to an embodiment of the present disclosure, each such die of memory die array 210 includes a memory-level arithmetic logic unit, such as Figure 1 A memory-level arithmetic logic unit 150 is provided.

[0026] The drive unit 200 includes a memory unit controller 220. As is well known, the storage device (e.g., memory integrated circuit) of the drive unit (e.g., solid state drive) is usually not directly connected to the computer bus and / or processor (e.g., processor 290). The memory unit controller 220 provides a series of functions to enable the drive unit to functionally interact with the processor via the bus 292, including, for example, bus interface control, logical to physical address conversion, reading, memory unit programming (writing), memory unit erasure, wear leveling, defect management, etc.

[0027] According to an embodiment of the present disclosure, the memory unit controller 220 includes additional functions in addition to conventional functions required to implement a storage functional unit. The memory unit controller 220 includes a novel data set controller 230. In some embodiments, the data set controller may share hardware with the memory unit controller 220. The data set controller 230 controls and distributes data set operations among its own components and controls and distributes data set operations to memory-level arithmetic logic units of the memory die 100 of the memory die array 210, such as Figure 1 For example, an operation on a single data set node, or an operation between two data set nodes stored on the same memory die, can be performed by the memory level arithmetic logic unit of that particular die as directed by the data set controller 230.

[0028] The data set controller 230 may also be capable of performing data set operations, such as addition, subtraction, multiplication, division, comparison, shift, rotation, two's complement, multiply-accumulate (MAC), sum, or, exclusive-or, matrix multiplication, vector operations, etc. In some embodiments, the data set controller 230 may be more capable than the memory level arithmetic logic unit 150. For example, the data set controller 230 may be capable of performing more complex operations, different operations, and / or in a faster manner on a larger amount of data than the memory level arithmetic logic unit 150. According to an embodiment of the present disclosure, if a data set operation requires nodes stored on different memory dies, such a data set operation may be performed by the data set controller 230. The data set controller 230 may also perform data set operations that are enhanced by the relatively greater computational power of the data set controller 230. According to an embodiment of the present disclosure, the data set controller 230 may receive extended data set operation commands from the processor 290.

[0029] The data set controller 230 includes a data set placement control functional unit 240. The data set placement control functional unit 240 may include, for example, a combinatorial logic unit, a finite state machine and / or a stored program processing unit, and any combination thereof, and may also include microcode. The data set placement control functional unit 240 places data received from the processor 290 into a location and a data structure in the memory die array 210 that facilitates processing of very large data sets and facilitates operations by the memory level arithmetic logic unit. For example, the data set placement control functional unit 240 attempts to place logically adjacent nodes and / or edges within the same memory integrated circuit that are physically adjacent, such as the memory integrated circuit 100 ( Figure 1 ) to enable a memory-level arithmetic logic unit (e.g., memory-level arithmetic logic unit 150 ( Figure 1 )) to perform data set operations. The following Figure 4 An exemplary dataset organization is shown.

[0030] The data set controller 230 includes a data set data acquisition and pre-fetch control functional unit 250. The data acquisition and pre-fetch control functional unit 250 may include, for example, a combinational logic unit, a finite state machine and / or a stored program processing unit, and any combination thereof, and may also include microcode. The data acquisition and pre-fetch control functional unit 250 may be used to access data values ​​of a data set, for example, by accessing and tracking pointers and / or links to such data in the data set. For example, according to the further description below Figure 4 In the embodiment of the data set organization in the data acquisition and pre-fetch control function unit 250 can be from the metaband 420 ( Figure 4 ) access the vector element address, from the feature address band 430 ( Figure 4 ) accesses the address of the vector feature data, and uses the address of the vector feature data to search and / or access the address stored in the feature data band 440 ( Figure 4 ) in the vector feature data.

[0031] The data set controller 230 includes a data set accelerator 270. The data set accelerator 270 may include, for example, combinatorial logic, a finite state machine, and / or a stored program processing unit, and any combination thereof, and may also include microcode. The data set accelerator 270 may be used to perform a wide range of data set operations, including, for example, as previously described with respect to the memory level arithmetic logic unit (ALU) 150 ( Figure 1 ) type of operations. In some embodiments, the data set accelerator 270 may include additional functionality for data set processing not shown in the memory level arithmetic logic unit (ALU). Such additional functionality may include, for example, matrix multiplication and / or a vector processing unit (VPU).

[0032] Typically, the data set accelerator 270 is used to perform data set operations that are not suitable for a memory-level arithmetic logic unit (ALU). For example, a memory-level arithmetic logic unit (ALU) located in a first die may not be suitable for performing operations that require operands stored in a second die. In some embodiments, the data set accelerator 270 is capable of performing operations that exceed the capabilities of the memory-level arithmetic logic unit (ALU). In some embodiments, the data set accelerator 270 can perform operations more efficiently than the memory-level arithmetic logic unit (ALU), such as performing operations faster.

[0033] The data set controller 230 includes a functional unit 260 for offloading data set operations to the memory die array. The functional unit 260 for offloading data set operations to the memory die array may include, for example, a combinatorial logic unit, a finite state machine, and / or a stored program processing unit, and any combination thereof, and may also include microcode. The functional unit 260 for offloading data set operations to the memory die array may be used to determine whether a data set operation (e.g., an operation of accumulating a series of vector data values) can be performed by an arithmetic logic unit (e.g., a memory level arithmetic logic unit 150) of the memory integrated circuit. Figure 1 For example, the functional unit 260 of offloading a data set operation to the memory die array determines whether the operands of the data set operation are located within a single memory integrated circuit (e.g., the memory integrated circuit 100 ( Figure 1 )). If the operands are located within a single memory integrated circuit, the operation may be performed by the arithmetic logic unit of the memory integrated circuit. Typically, if the operands are not located within a single memory integrated circuit, the operation will not be performed by the arithmetic logic unit of the memory integrated circuit. In this case, the data set operation may be performed by the data set accelerator 270.

[0034] Similarly, the functional unit 260 that offloads the data set operation to the memory die array determines whether the arithmetic logic unit of the memory integrated circuit is capable of performing the data set operation. As previously described, the data set accelerator 270 is capable of performing more complex operations, different operations, and / or in a faster manner on a larger amount of data than the memory level arithmetic logic unit. In this case, the functional unit 260 that offloads the data set operation to the memory die array may instruct the data set accelerator 270 to perform the data set operation.

[0035] According to an embodiment of the present disclosure, the function unit 260 for offloading data set operations to the memory die array may instruct a portion of the data set operation to be performed by the arithmetic logic units of one or more memory integrated circuits, while other portions of the data set operation are performed by the data set accelerator 270. For example, the arithmetic logic units of memory integrated circuits on different memory integrated circuits may perform an accumulation operation on data stored in the corresponding memory integrated circuit, while the data set accelerator 270 accesses the results from the arithmetic logic units of the memory integrated circuits to perform accumulation on data stored on multiple memory integrated circuits.

[0036] Figure 3 The present disclosure shows that the transmission to the memory integrated circuit (eg, Figure 1 The exemplary instructions 300 of the memory integrated circuit 100 of the present invention are shown in Figure 3. The instructions 300 include a new superset of conventional instructions that may be received by, for example, a conventional NAND-type flash memory chip. For example, a conventional NAND-type flash memory chip may receive an opcode that instructs the chip to read or write a page, or to erase a memory block. Similarly, a conventional NAND-type flash memory chip may receive an address within the chip at which to perform the operation specified by the opcode. Several forms of addresses are typically available, including plane, page and / or block numbers, and offset addresses.

[0037] According to an embodiment of the present disclosure, instruction 300 is issued by a data set controller (e.g., Figure 2 The instruction 300 is sent to the memory integrated circuit, for example, Figure 1 The memory integrated circuit 100 of FIG. 300 includes a data set operation code 340. The data set operation code 340 indicates that the memory level arithmetic logic unit (eg, Figure 1 The arithmetic logic unit 150) performs data set operations, such as multiplying the feature data of two vectors.

[0038] Instruction 300 includes a prefetch address 330. In some embodiments, the prefetch address may be provided by data acquisition and prefetch control functional unit 250 ( Figure 2) is generated. The memory-level arithmetic logic unit can use the prefetch address 330 to determine some data to be operated on based on the data set operation code 340. The instruction 300 includes a flag 350, which is used to indicate that the result of the data set operation corresponding to the operation code 340 is to be added to the accumulation register of the memory-level arithmetic logic unit. The address 320 is a conventional address for performing conventional operations of the memory integrated circuit. In some embodiments, the basic operation code field 310 is extended to include a flag and / or a new operation code to indicate that the instance of the instruction 300 is not a conventional memory operation, but includes a data set operation code, such as a valid data set operation code 340. In some embodiments, the data set operation code group 340 includes a "no operation" code to indicate that the instance of the instruction 300 is a conventional memory operation.

[0039] Figure 4 An exemplary data set 400 that facilitates processing of very large data sets according to an embodiment of the present disclosure is shown. The data set 400 includes data that spans multiple memory integrated circuits 411, 412 (e.g., Figure 2 2. The memory die array 210 of FIG. 2 shows three bands 420, 430, 440 of information. For example, each memory integrated circuit 411, 412 is characterized by having a similar organization including three data types corresponding to the three bands. There will typically be many more memory integrated circuits than shown, for example, 100 or more memory integrated circuits.

[0040] Data set 400 includes feature data band 440. Feature data band 440 includes a typical large amount of data corresponding to a data set (e.g., each node of a graph). These data can generally be represented as an array or vector of data. These data can be referred to as the information content of a node. Data entries are generally fixed length, although this is not required. Variable length feature data is enabled according to embodiments of the present disclosure.

[0041] Data set 400 includes feature address band 430. Feature address band 430 includes information about the data set, such as a graph structure. Feature address band 430 identifies neighbor vectors of each vector. In some embodiments, address band 430 is limited to address information of the data set (e.g., a graph) as opposed to storing feature data of the data set. For example, feature address band 430 includes a pointer to data stored in feature data band 440, which will be further described below. For example, Figure 4 As shown on the right side of the feature address band 430, if vector 0 has two neighbors, the feature address band 430 includes the address of the vector 0 data (the feature address "V0_f_addr" of vector 0) and the feature data addresses of the neighbors of vector 0 (the feature address "V0_Nb0_f_addr" of neighbor 0 of vector 0 and the feature address "V0_Nb1_f_addr" of neighbor 1 of vector 0).

[0042] Similarly, the feature data addresses of the neighbors of vector 1 are listed: feature address "V1_f_addr" of vector 1, feature data address "V1_Nb0_f-addr" of neighbor 0 of vector 1, etc. The feature data addresses of all neighbors of all vectors are listed in feature address band 430. It will be appreciated that in some embodiments, some neighbors may be located in different memory integrated circuits. In this novel manner, multiple relationships (e.g., graph structures) between data sets may be encoded.

[0043] The data set 400 includes a metaband 420. The metaband 420 includes address information corresponding to the feature data addresses of various nodes or vertices of the graph. For example, the metaband 420 includes a pointer to an entry in the feature address band 430. The pointers of the metaband 420 are located at fixed and / or easily determined addresses within the memory integrated circuit, which enables various processes to find the feature data addresses from the feature address band 430 and ultimately access the feature data within the feature data band 440. For example, to access the feature data of vector 0, the process can look up the metaaddress of vector 0 from the metaband 420. The metaaddress in the metaband 420 will point to an entry in the feature address band 430. Accessing the entry in the feature address band 420 will provide the address of the feature data of vector 0 located in the feature data band 440.

[0044] According to an embodiment of the present disclosure, the entire large data set is stored in a single drive unit, e.g. Figure 2 The drive unit 200 of the present invention may include 160 NAND-based memory integrated circuits to accommodate a data set of up to 16 TB in size. For convenience, the size of the drive page may be set to a size corresponding to the characteristic data size of the node. Neighboring nodes may be located in different memory integrated circuits so that read operations from different memory integrated circuits are performed in parallel. According to an embodiment of the present disclosure, the pre-fetch function is used to find the next neighboring node of the current memory integrated circuit instead of loading the next page in sequence. Figure 4 The prefetch 450 shows the feature data to be prefetched. In some embodiments, the prefetch data can be loaded into Figure 1 in the pre-fetch buffer 122 .

[0045] Figure 5A block diagram of an exemplary electronic system 500 is shown, and the electronic system is used as a platform for implementing embodiments of the present disclosure. In some embodiments, the electronic system 500 can be a "server" computer system. The electronic system 500 includes an address / data bus 550 for communicating information, and a central processing unit complex 505 functionally coupled to the bus for processing information and instructions. The bus 550 may include, for example, a high-speed peripheral component interconnect (PCIe) computer expansion bus, an industrial standard architecture (ISA), an extended ISA (EISA), a microchannel, a multi-bus, IEEE 796, IEEE 1196, IEEE 1496, PCI, a computer automatic measurement and control (CAMAC), an instrument bus (MBus), a runway bus, a computer high-speed link (CXL), etc.

[0046] In some embodiments, the CPU complex 505 may include a single processor or multiple processors, for example, a multi-core processor, or multiple independent processors. The CPU complex 505 may include various types of well-known processors in any combination, including, for example, a digital signal processor (DSP), a graphics processor (GPU), a complex instruction set (CISC) processor, a reduced instruction set (RISC) processor, and / or a very long word instruction set (VLIW) processor. The electronic system 500 may also include a volatile memory 515 (e.g., a random access memory, RAM) coupled to the bus 550 for storing information and instructions of the CPU complex 505, and a non-volatile memory 510 (e.g., a read-only memory, ROM) coupled to the bus 550 for storing static information and instructions of the processor complex 505. Optionally, the electronic system 500 also includes a replaceable non-volatile memory 520 (e.g., NOR flash memory), which is used to store information and instructions of the CPU complex 505, and the information and instructions can be updated after the system 500 is manufactured. In some embodiments, only one of ROM 510 or flash memory 520 may be included.

[0047] Figure 5 An optional input device 530 is also included in the electronic system 500. The device 530 can communicate information and command selections to the central processor 505. The input device 530 can be any suitable device for communicating information and / or commands to the electronic system 500. For example, the input device 530 can take the form of a keyboard, a button, a joystick, a trackball, an audio sensor (e.g., a microphone), a touch-sensitive digitizing panel, an eye scanner, etc.

[0048] The electronic system 500 may include a display unit 525. The display unit 525 may include a liquid crystal display (LCD) device, a cathode ray tube (CRT), a field emission device (FED, also known as a flat-panel CRT), a light emitting diode (LED), a plasma display device, an electroluminescent display, electronic paper, electronic ink (e-ink), or other display devices suitable for creating user-recognizable graphic images and / or alphanumeric characters. In some embodiments, the display unit 525 may have an associated lighting device.

[0049] Optionally, the electronic system 500 further includes an expansion interface 535 coupled to the bus 550. The expansion interface 535 may implement many well-known standard expansion interfaces, including but not limited to a secure digital card interface, a universal serial bus (USB) interface, a compact flash, a personal computer (PC) card interface, a card bus (Card Bus), a peripheral component interconnect (PCI) interface, a high-speed peripheral component interconnect (PCI Express), a mini PCI interface, IEEE 5394, a small computer system interface (SCSI), a personal computer memory card international association (PCMCIA) interface, an industry standard architecture (ISA) interface, an RS-232 interface, etc. In some embodiments of the present disclosure, the expansion interface 535 may include signals that are substantially consistent with signals of the bus 550.

[0050] A variety of well-known devices can be connected to the electronic system 500 via the bus 550 and / or expansion interface 535. Examples of such devices include, but are not limited to, rotating magnetic memory devices, flash memory devices, digital cameras, wireless communication modules, digital audio players, and global positioning system (GPS) devices.

[0051] Optionally, the system 500 also includes a communication port 540. The communication port 540 can be implemented as part of the expansion interface 535. When implemented as an independent interface, the communication port 540 can generally be used to exchange information with other devices via a communication-oriented data transmission protocol. Examples of communication ports include, but are not limited to, RS-232 ports, universal asynchronous receiver-transmitters (UARTs), USB ports, infrared light transceivers, Ethernet ports, IEEE 5394, and synchronous ports.

[0052] Optionally, the system 500 includes a network interface 560, which may implement a wired or wireless network interface. In some embodiments, the electronic system 500 may include additional software and / or hardware features (not shown).

[0053] The various modules of system 500 can access computer-readable media, and it is known or understood that this term includes removable media such as Secure Digital ("SD") cards, CD and / or DVD ROMs, disks, etc., as well as non-removable or internal media such as hard drives, RAM, ROM, flash memory, etc.

[0054] The electronic system 500 includes one or more data set drivers 570 that are functionally coupled to the processor complex 505. In some embodiments, the data set driver 570 may be coupled to the processor complex 505 via the bus 550. In some embodiments, the data set driver 570 may be coupled to the processor complex 505 via the expansion interface 535. According to an embodiment of the present disclosure, the data set driver 570, for example, as described with respect to Figure 2 The driver unit 200 includes features for performing various operations on large data sets within the data set driver 570 itself, and without transferring large amounts of data to the processor complex 505.

[0055] According to embodiments of the present disclosure, systems and methods for processing large data sets are provided. In addition, according to embodiments of the present disclosure, systems and methods for processing large data sets are provided, which can overcome the bandwidth limitations of transmitting large data sets back and forth from main memory to processors. In addition, according to embodiments of the present disclosure, systems and methods for processing large data sets are provided, which are compatible and complementary to existing systems and methods for processing large data sets (e.g., graphics processing).

[0056] Various embodiments of the present disclosure are described above. Although the present disclosure is described in specific embodiments, it should be understood that the present disclosure should not be interpreted as being limited to these embodiments but rather interpreted according to the above claims.

Claims

1. An apparatus for processing a large data set, comprising: a block array of non-volatile memory cells on an integrated circuit die, wherein the block array of non-volatile memory cells comprises a plurality of planes, each plane comprising a pre-fetch buffer and an output buffer; and An arithmetic logic unit (150) is located on the integrated circuit die and is coupled to the block array, wherein the arithmetic logic unit is used to perform arithmetic logic operations on the contents of the block array in response to instructions received from outside the integrated circuit die.

2. The device according to claim 1, wherein: The non-volatile memory cells include NAND-type flash memory cells.

3. The device according to claim 1, wherein: The arithmetic logic unit is used to perform the arithmetic logic operation independently of accessing data from outside the integrated circuit die.

4. The device according to claim 1, wherein: The arithmetic logic unit is configured to selectively couple to a pre-fetch buffer and an output buffer of each of the plurality of planes; as well as The arithmetic logic unit is configured to receive an instruction from outside the integrated circuit die, the instruction specifying a prefetch address and an operation code indicating an operation to be performed on data contained in a prefetch buffer and an output buffer of a given plane.

5. A drive controller, comprising: an interface configured to functionally couple the drive controller to a plurality of memory integrated circuit devices; a bus interface configured to functionally couple the drive controller to a computer system; as well as a data set controller for performing data set operations on data sets stored in the plurality of memory integrated circuit devices without transmitting contents of the data sets through the bus interface, distributing processing of the data set operations to arithmetic logic units on the plurality of memory integrated circuit devices, the arithmetic logic units being configured to selectively couple to pre-fetch buffers and output buffers of each of a plurality of planes of a block array of non-volatile memory cells.

6. The drive controller according to claim 5, wherein: The data set controller is further configured to perform at least one of the following: Create and maintain dataset structures; Get the data of the dataset by following the pointer of the dataset structure; A data set operation is performed on the data stored within the plurality of memory integrated circuit devices.

7. The drive controller according to claim 5, wherein: The data set controller includes a vector processing unit.

8. The drive controller according to claim 5, wherein: The drive controller is also used to receive, decode and execute data set operations.

9. A solid state drive unit, comprising: A plurality of non-volatile memory integrated circuit dies, each memory integrated circuit die comprising: a block array of non-volatile memory cells on an integrated circuit die, wherein the block array of non-volatile memory cells includes a plurality of planes, each plane including a pre-fetch buffer and an output buffer; an arithmetic logic unit located on the integrated circuit die, the arithmetic logic unit coupled to the block array, wherein the arithmetic logic unit is used to perform arithmetic logic operations on contents of the block array in response to instructions received from outside the integrated circuit die; a bus interface configured to functionally couple the drive unit to a computer system; and A data set controller is configured to perform data set operations on data sets stored in the plurality of non-volatile memory integrated circuit dies without transmitting contents of the data sets through the bus interface.

10. The solid-state drive unit according to claim 9, wherein: The data set controller is further configured to: distributing processing of said data set operations to said arithmetic logic units on said plurality of non-volatile memory integrated circuit dies; Create and maintain dataset structures; Obtaining data of the data set by following a pointer of the data set structure; An operation is performed on elements of a data set located in different ones of the plurality of non-volatile memory integrated circuit dies.

11. The solid-state drive unit according to claim 9, wherein: The multiple data set operations include matrix multiplication.

Images