Configuration circuit for flash FPGAs that implement external monitoring and configuration

Abstract

The present invention discloses a configuration circuit for a flash-type FPGA that realizes external monitoring and configuration, and relates to the field of flash-type FPGAs. In the configuration circuit, the positive high-voltage output end of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port via a positive high-voltage bidirectional switch circuit and also serves as the positive output end of a voltage supply circuit; the negative high-voltage output end of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port via a negative high-voltage bidirectional switch circuit and also serves as the negative output end of the voltage supply circuit; a mode control circuit controls entry into an external monitoring mode or an external configuration mode according to a received mode adjustment signal. Based on the structure of the configuration circuit of the present application, only a small amount of logic needs to be added to the JTAG protocol to monitor the positive and negative high voltages provided by the internal high-voltage charge pump during erase and programming operations, or to input the required positive and negative high voltages from an external input, thereby improving reliability.

Description

Technical Field

[0001] The present invention relates to the field of flash type FPGA, in particular to a configuration circuit of the flash type FPGA for realizing external monitoring and configuration. Background Art

[0002] Flash FPGAs are designed based on reconfigurable flash storage technology. By reprogramming the flash storage unit (flash cell), the internal logic relationship of the circuit is changed, thereby realizing different logical functions for the user. The core of the flash FPGA function is the programmable logic block. Each programmable logic block contains an m*n flash cell array. These flash cell arrays are distributed in small blocks throughout the flash FPGA. Figure 1 shown.

[0003] During the development of flash FPGAs, the configuration logic obtains the configuration bitstream via the JTAG protocol and uses wordline (WL) and bitline (BL) driver circuits to perform operations such as erasing and programming on the flash cells within the programmable logic block. Flash FPGAs are very large. For a flash FPGA with a system equivalent gate count of 3 million and a 0.11µm process, the chip area reaches 12mm*15mm, far larger than a flash memory of the same capacity. Therefore, the traces of the wordline and bitline driver circuits that configure the flash cells are relatively long and heavily loaded, posing reliability challenges. Summary of the Invention

[0004] In response to the above problems and technical requirements, the inventors have proposed a configuration circuit for a flash-type FPGA that implements external monitoring and configuration. The technical solution of the present invention is as follows:

[0005] A configuration circuit for a flash-type FPGA that implements external monitoring and configuration. The flash-type FPGA includes a positive high-voltage external monitoring port and a negative high-voltage external monitoring port. The configuration circuit includes a voltage supply circuit, a word line drive circuit, and a bit line drive circuit. The positive output terminal of the voltage supply circuit is connected to the positive voltage terminals of the word line drive circuit and the bit line drive circuit, and the negative output terminal of the voltage supply circuit is connected to the negative voltage terminals of the word line drive circuit and the bit line drive circuit. In the voltage supply circuit of the flash-type FPGA:

[0006] The oscillator is connected to the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump through a mode control circuit. The mode control circuit also outputs a switch control signal to control the on and off of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit.

[0007] The positive high-voltage output end of the positive high-voltage charge pump is connected to the positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the common end of the positive high-voltage charge pump and the positive high-voltage bidirectional switch circuit serves as the positive output end of the voltage providing circuit;

[0008] The negative high-voltage output terminal of the negative high-voltage charge pump is connected to the negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the common terminal of the negative high-voltage charge pump and the negative high-voltage bidirectional switch circuit serves as the negative output terminal of the voltage providing circuit;

[0009] The mode control circuit obtains the mode adjustment signal based on the JTAG of the flash FPGA. Based on the obtained mode adjustment signal, it controls the on / off of the path between the oscillator and the clock signal terminals of the two high-voltage charge pumps, and controls the on / off of the two high-voltage bidirectional switch circuits to control the flash FPGA to enter the external monitoring mode or external configuration mode:

[0010] In the external monitoring mode, the positive high voltage provided by the positive high voltage charge pump is externally monitored through the positive high voltage external monitoring port, and the negative high voltage provided by the negative high voltage charge pump is externally monitored through the negative high voltage external monitoring port;

[0011] In the external configuration mode, the external positive high voltage is input through the positive high voltage external monitoring port and output through the positive output terminal of the voltage providing circuit, and the external negative high voltage is input through the negative high voltage external monitoring port and output through the negative output terminal of the voltage providing circuit.

[0012] The beneficial technical effects of the present invention are:

[0013] The present application discloses a configuration circuit for a flash-type FPGA that implements external monitoring and configuration. Based on the structure of the configuration circuit of the present application, only a small amount of logic needs to be added to the JTAG protocol of the flash-type FPGA configuration circuit to monitor the positive high voltage and negative high voltage provided by the internal high-voltage charge pump during the erase and programming operations of the flash-type FPGA through the positive high voltage external monitoring port and the negative high voltage external monitoring port. This allows for timely detection of abnormalities in the positive high voltage and negative high voltage, thereby improving reliability.

[0014] In addition, positive high voltage and negative high voltage can be input from the outside through the positive high voltage external monitoring port and the negative high voltage external monitoring port. When inputting externally, the two high voltage charge pumps are turned off to prevent conflicts with the high voltage provided externally. When the positive high voltage and negative high voltage provided by the internal high voltage charge pump are monitored to be abnormal, the positive high voltage and negative voltage required during the erase and programming operations can be input externally, so as to timely adjust the range of the positive high voltage and negative high voltage output to the word line drive circuit and the bit line drive circuit, thereby further improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the layout of the programmable logic blocks in a flash FPGA.

[0016] Figure 2 It is a circuit structure diagram of the configuration circuit of this application.

[0017] Figure 3 FIG. 4 is a circuit diagram of a voltage supply circuit in one embodiment of the present application. DETAILED DESCRIPTION

[0018] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0019] The present application discloses a configuration circuit of a flash type FPGA for realizing external monitoring and configuration. The flash type FPGA also provides a positive high voltage external monitoring port HV_PAD and a negative high voltage external monitoring port LV_PAD.

[0020] Please refer to Figure 2 , inside the flash type FPGA, the configuration circuit includes a voltage supply circuit, a word line driving circuit and a bit line driving circuit. The positive output terminal HV_OUT of the voltage supply circuit is connected to the positive voltage terminal VPC of the word line driving circuit and the bit line driving circuit, and the negative output terminal LV_OUT of the voltage supply circuit is connected to the negative voltage terminal VGC of the word line driving circuit and the bit line driving circuit. The word line driving circuit and the bit line driving circuit can adopt the existing driving circuit structure, which is not described in detail in this application. The voltage supply circuit of the flash type FPGA includes a mode control circuit, an oscillator OSC, a positive high-voltage charge pump, a negative high-voltage charge pump, a positive high-voltage bidirectional switch circuit and a negative high-voltage bidirectional switch circuit. Among them, the positive high-voltage charge pump and the negative high-voltage charge pump can specifically adopt the existing circuit structure, Figure 3 Take a possible circuit structure as an example.

[0021] The positive high-voltage output terminal of the positive high-voltage charge pump is connected to the positive high-voltage external monitoring port HV_PAD via a positive high-voltage bidirectional switch circuit. The common terminal of the positive high-voltage charge pump and the positive high-voltage bidirectional switch circuit serves as the positive output terminal HV_OUT of the voltage supply circuit. The negative high-voltage output terminal of the negative high-voltage charge pump is connected to the negative high-voltage external monitoring port LV_PAD via a negative high-voltage bidirectional switch circuit. The common terminal of the negative high-voltage charge pump and the negative high-voltage bidirectional switch circuit serves as the negative output terminal LV_OUT of the voltage supply circuit.

[0022] The oscillator provides a clock signal, clk, which is connected to the clock signal terminals of the positive and negative high-voltage charge pumps via a mode control circuit. The mode control circuit also outputs a switch control signal, ctrl, to control the on and off of the positive and negative high-voltage bidirectional switch circuits.

[0023] The mode control circuit obtains a mode adjustment signal based on the JTAG of the flash FPGA. Based on the obtained mode adjustment signal, it controls the on / off of the path between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump, as well as the on / off of the high-voltage bidirectional switch and the negative high-voltage bidirectional switch circuit, thereby controlling the flash FPGA to enter different modes, including:

[0024] 1. External Monitoring Mode. When the mode control circuit obtains the second mode adjustment signal for instructing the flash type FPGA to enter the external monitoring mode, the mode control circuit controls the path between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump to be conductive. The oscillator normally provides the clock signal clk to the positive high-voltage charge pump and the negative high-voltage charge pump via the mode control circuit, so that the positive high-voltage charge pump and the negative high-voltage charge pump operate normally. The positive high voltage provided by the positive high-voltage charge pump is output through the positive output terminal HV_OUT of the voltage supply circuit to the word line driver circuit and the bit line driver circuit, and the negative high voltage provided by the negative high-voltage charge pump is output through the negative output terminal LV_OUT of the voltage supply circuit to the word line driver circuit and the bit line driver circuit.

[0025] At the same time, the mode control circuit also outputs a switch control signal ctrl of an effective level to control the conduction of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit. The positive high voltage provided by the positive high-voltage charge pump is also output by the positive high-voltage external monitoring port HV_PAD through the positive high-voltage bidirectional switch circuit, and the negative high voltage provided by the negative high-voltage charge pump is also output by the negative high-voltage external monitoring port LV_PAD through the negative high-voltage bidirectional switch circuit.

[0026] By utilizing this mode, external monitoring of positive high voltage and negative high voltage can be realized, so that abnormal conditions of positive high voltage and negative high voltage can be discovered in time, thereby improving reliability.

[0027] 2. External Configuration Mode: When the mode control circuit receives the third mode adjustment signal, which instructs the flash FPGA to enter external configuration mode, it disconnects the path between the oscillator and the clock signal terminals of the positive and negative high-voltage charge pumps. The clock signal provided by the oscillator is shut off by the mode control circuit and cannot be transmitted to the positive and negative high-voltage charge pumps, causing both the positive and negative high-voltage charge pumps to cease operation.

[0028] At the same time, the mode control circuit also outputs a switch control signal of an active level to control the conduction of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit. In this mode, the positive high-voltage external monitoring port HV_PAD inputs an external positive high voltage, and the negative high-voltage external monitoring port LV_PAD inputs an external negative high voltage. The external positive high voltage input to the positive high-voltage external monitoring port HV_PAD is transmitted via the positive high-voltage bidirectional switch circuit to the positive output terminal HV_OUT of the voltage supply circuit, which is then provided to the word line driver circuit and the bit line driver circuit. The external negative high voltage input to the negative high-voltage external monitoring port LV_PAD is transmitted via the negative high-voltage bidirectional switch circuit to the negative output terminal LV_OUT of the voltage supply circuit, which is then provided to the word line driver circuit and the bit line driver circuit.

[0029] This mode allows for external input of the required positive and negative high voltages. During this input, the two high-voltage charge pumps are shut down to prevent conflicts with the externally supplied high voltage. A typical application scenario involves detecting abnormalities in the positive and negative high voltages provided by the internal high-voltage charge pumps through external monitoring mode. The positive and negative voltages required for erase and program operations can then be externally input, allowing for timely adjustment of the range of the positive and negative high voltages output to the word line driver circuit and the bit line driver circuit.

[0030] 3. Default Operating Mode. When the mode control circuit receives the first mode adjustment signal for instructing the flash FPGA to enter the default operating mode, the mode control circuit controls the path between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump to be conductive. The oscillator normally provides the clock signal clk to the positive high-voltage charge pump and the negative high-voltage charge pump via the mode control circuit, enabling the positive high-voltage charge pump and the negative high-voltage charge pump to operate normally. The positive high-voltage provided by the positive high-voltage charge pump is output through the positive output terminal HV_OUT of the voltage supply circuit to the word line driver circuit and the bit line driver circuit, and the negative high-voltage provided by the negative high-voltage charge pump is output through the negative output terminal LV_OUT of the voltage supply circuit to the word line driver circuit and the bit line driver circuit. At the same time, the mode control circuit outputs a switch control signal ctrl of an inactive level to control the disconnection of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit.

[0031] This mode is the same as the working process of the existing FPGA in which the high voltage charge pump provides the required high voltage, that is, the flash type FPGA is also compatible with the conventional mode without external monitoring and configuration functions.

[0032] Please refer to Figure 3 , shows a specific circuit diagram of a voltage providing circuit provided by an embodiment:

[0033] (1) Mode control circuit.

[0034] The mode control circuit includes control logic, a three-input OR gate A1, and a two-input NOR gate B1. The first input Q0 and second input Q1 of the control logic are connected to the two inputs of the three-input OR gate A1, respectively. The oscillator is connected to the other input of the three-input OR gate A1. The output of the three-input OR gate A1 is connected to the clock signal terminals of the positive and negative high-voltage charge pumps.

[0035] The second input terminal Q1 and the third input terminal Q2 of the control logic are connected to the two input terminals of the two-input NOR gate B1 , and the output terminal of the two-input NOR gate B1 is connected to the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit to control on and off.

[0036] The mode control circuit obtains the mode adjustment signal through the control logic. The control logic controls the outputs of the three-input OR gate A1 and the two-input NOR gate B1 based on the obtained mode adjustment signal:

[0037] (a) When the mode control circuit obtains the first mode adjustment signal through the control logic, the first input terminal Q0, the second input terminal Q1 and the third input terminal Q2 are all low level, which is recorded as<Q0、Q1、Q2> =3'b000. At this time, the output of the three-input OR gate A1 outputs the clock signal provided by the oscillator, and the two-input NOR gate B1 outputs a high-level invalid switch control signal to disconnect both the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit.

[0038] (b) When the mode control circuit obtains the second mode adjustment signal through the control logic, the first input terminal Q0 and the second input terminal Q1 are at a low level, and the third input terminal Q2 is at a high level, which is recorded as<Q0、Q1、Q2> =3'b001. At this time, the output of the three-input OR gate A1 outputs the clock signal provided by the oscillator, and the two-input NOR gate B1 outputs a low-level active switch control signal, turning on both the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit.

[0039] (c) When the mode control circuit obtains the third mode adjustment signal through the control logic, the first input terminal Q0 and the second input terminal Q1 are high level, and the third input terminal Q2 is low level, which is recorded as<Q0、Q1、Q2> =3'b110. At this point, the output of three-input OR gate A1 is constantly high, shutting off the clock signal from the oscillator. Two-input NOR gate B1 outputs an active-low switch control signal, turning on both the positive and negative high-voltage bidirectional switch circuits.

[0040] In one embodiment, the mode control circuit obtains the mode adjustment signal through the TDI terminal and TRST terminal of the JTAG of the flash type FPGA. The control logic includes three shift registers dff00, dff01, and dff02 and three control registers dff10, dff11, and dff12, where:

[0041] The D terminal of dff00 is connected to the TDI terminal, and the Q terminal of dff00 is connected to the D terminal of dff10. The Q terminal of dff10 serves as the first input terminal Q0 of the control logic. The Q terminal of dff00 is also connected to the D terminal of dff01, and the Q terminal of dff01 is connected to the D terminal of dff11. The Q terminal of dff11 serves as the second input terminal Q1 of the control logic. The Q terminal of dff01 is also connected to the D terminal of dff02, and the Q terminal of dff02 is connected to the D terminal of dff12. The Q terminal of dff12 serves as the third input terminal Q2 of the control logic. The RST terminals of dff00, dff01, dff02, dff10, dff11, and dff12 are all connected to the TRST terminal. The CLK terminals of dff00, dff01, and dff02 are all connected to the data shift clock signal SHIFT_CK issued by the TAP state machine of the JTAG of the flash type FPGA. The CLK terminals of dff10, dff11, and dff12 are all connected to another data update clock signal UPDATE_CK issued by the TAP state machine of the JTAG of the flash type FPGA.

[0042] (2) Positive high voltage bidirectional switch circuit.

[0043] The positive high-voltage bidirectional switch circuit includes PMOS transistors P3 and P10, as well as a first positive level conversion circuit and a second positive level conversion circuit. The source of P3 is connected to the positive high-voltage output terminal of the positive high-voltage charge pump. The drain of P3 is connected to the source of P10, and the drain of P10 is connected to the positive high-voltage external monitoring port HV_PAD. The input terminal of the first positive level conversion circuit receives the switch control signal ctrl output by the mode control circuit, and the output terminal HZ0 is connected to the gate of P3. The power supply terminal of the first positive level conversion circuit is connected to the positive high-voltage output terminal of the positive high-voltage charge pump. The input terminal of the second positive level conversion circuit receives the switch control signal ctrl output by the mode control circuit, and the output terminal HZ1 is connected to the gate of P10. The power supply terminal of the second positive level conversion circuit is connected to the positive high-voltage external monitoring port HV_PAD.

[0044] When the mode control circuit outputs a switch control signal ctrl of a valid level, both the first positive level conversion circuit and the second positive level conversion circuit output a low level, P3 and P10 are both turned on, and bidirectional transmission is possible between the positive high-voltage external monitoring port HV_PAD and the positive output terminal HV_OUT, that is, the positive high-voltage bidirectional switch circuit is turned on. Otherwise, when the mode control circuit outputs a switch control signal ctrl of an invalid level, both the first positive level conversion circuit and the second positive level conversion circuit output a high level, the voltage at the output terminal HZ0 of the first positive level conversion circuit is equal to the positive high voltage output by the positive high-voltage charge pump, and the voltage at the output terminal HZ1 of the second positive level conversion circuit is equal to the voltage of the positive high-voltage external monitoring port HV_PAD. In this way, the path between the positive high-voltage external monitoring port HV_PAD and the positive output terminal HV_OUT can be closed, that is, the positive high-voltage bidirectional switch circuit is turned off.

[0045] As mentioned above, in Figure 3 In the example, the switch control signal ctrl is active at a low level. The first and second positive level conversion circuits have the same circuit structure. In each level conversion circuit, the source of PMOS transistor P1 is connected to the source of PMOS transistor P2 and is also connected to the power supply terminal of the positive level conversion circuit. The drain of P1 is connected to the drain of NMOS transistor N4 and the gate of P2, and the drain of P2 is connected to the drain of NMOS transistor N5 and the gate of P1. The source of N4 is grounded, the source of N5 is grounded, and the gate of N4 is connected to the input of the positive level conversion circuit. The input of the positive level conversion circuit is also connected to the gate of N5 via inverter I3, and the drain of N5 is also connected to the output of the positive level conversion circuit. For differentiation, the first positive level conversion circuit is represented by P1, P2, N4, and N5, and the second positive level conversion circuit is represented by P8, P9, N6, and N7.

[0046] (3) Negative high voltage bidirectional switch circuit.

[0047] The high-voltage bidirectional switch circuit includes NMOS tubes N14 and N19 and a first negative level conversion circuit and a second negative level conversion circuit. The source of N19 is connected to the negative high-voltage output end of the negative high-voltage charge pump, the drain of N19 is connected to the source of N14, and the drain of N14 is connected to the negative high-voltage external monitoring port LV_PAD.

[0048] The switch control signal ctrl output by the mode control circuit is provided to the input of the first negative level conversion circuit and the input of the second negative level conversion circuit via inverter I5. The output terminal LZ0 of the first negative level conversion circuit is connected to the gate of N19, and the power supply terminal of the first negative level conversion circuit is connected to the negative high-voltage output terminal of the negative high-voltage charge pump. The output terminal LZ1 of the second negative level conversion circuit is connected to the gate of N14, and the power supply terminal of the second negative level conversion circuit is connected to the negative high-voltage external monitoring port LV_PAD.

[0049] When the mode control circuit outputs a switch control signal ctrl of a valid level, both the first negative level conversion circuit and the second negative level conversion circuit output a high level, N19 and N14 are both turned on, and bidirectional transmission between the negative high-voltage external monitoring port LV_PAD and the negative output terminal LV_OUT is possible, thus causing the negative high-voltage bidirectional switch circuit to be turned on. Otherwise, when the mode control circuit outputs a switch control signal ctrl of an invalid level, both the first negative level conversion circuit and the second negative level conversion circuit output a low level, the voltage at the output terminal LZ0 of the first negative level conversion circuit equals the negative high voltage output by the negative high-voltage charge pump, and the voltage at the output terminal LZ1 of the second negative level conversion circuit equals the voltage at the negative high-voltage external monitoring port LV_PAD. This closes the path between the negative high-voltage external monitoring port LV_PAD and the negative output terminal LV_OUT, thus causing the negative high-voltage bidirectional switch circuit to be turned off.

[0050] As mentioned above, in Figure 3 In the embodiment, the switch control signal ctrl is active low. The first and second negative level conversion circuits have the same circuit structure. In each negative level conversion circuit, the source of NMOS transistor N12 is connected to the source of NMOS transistor N13 and to the power supply terminal of the negative level conversion circuit. The drain of N12 is connected to the drain of PMOS transistor P11 and the gate of N13, and the drain of N13 is connected to the drain of PMOS transistor P12 and the gate of N12. The source of P11 is connected to the source of P12 and to the chip voltage VDD, and the gate of P11 is connected to the input of the negative level conversion circuit. The input of the negative level conversion circuit is also connected to the gate of P12 via an inverter, and the drain of N13 serves as the output of the negative level conversion circuit. For differentiation, the second negative level conversion circuit is represented by P11, P12, N12, and N13, while the first positive level conversion circuit is represented by P15, P16, N17, and N18.

[0051] The above description is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. A configuration circuit for a flash FPGA that implements external monitoring and configuration, characterized in that: The flash type FPGA includes a positive high-voltage external monitoring port and a negative high-voltage external monitoring port. The configuration circuit includes a voltage supply circuit, a word line drive circuit, and a bit line drive circuit. The positive output terminal of the voltage supply circuit is connected to the positive voltage terminals of the word line drive circuit and the bit line drive circuit, and the negative output terminal of the voltage supply circuit is connected to the negative voltage terminals of the word line drive circuit and the bit line drive circuit. In the voltage supply circuit of the flash type FPGA: The oscillator is connected to the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump through a mode control circuit, and the mode control circuit also outputs a switch control signal to control the on and off of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit; The positive high-voltage output end of the positive high-voltage charge pump is connected to the positive high-voltage external monitoring port through the positive high-voltage bidirectional switch circuit, and the common end of the positive high-voltage charge pump and the positive high-voltage bidirectional switch circuit serves as the positive output end of the voltage providing circuit; The negative high-voltage output terminal of the negative high-voltage charge pump is connected to the negative high-voltage external monitoring port through the negative high-voltage bidirectional switch circuit, and the common terminal of the negative high-voltage charge pump and the negative high-voltage bidirectional switch circuit serves as the negative output terminal of the voltage providing circuit; The mode control circuit acquires a mode adjustment signal based on the JTAG of the flash type FPGA, and controls the on / off of the path between the oscillator and the clock signal terminals of the two high-voltage charge pumps, and controls the on / off of the two high-voltage bidirectional switch circuits according to the acquired mode adjustment signal, so as to control the flash type FPGA to enter the external monitoring mode or the external configuration mode: In the external monitoring mode, the positive high voltage provided by the positive high voltage charge pump is externally monitored through the positive high voltage external monitoring port, and the negative high voltage provided by the negative high voltage charge pump is externally monitored through the negative high voltage external monitoring port; In the external configuration mode, an external positive high voltage is input through the positive high voltage external monitoring port and output through the positive output terminal of the voltage providing circuit, and an external negative high voltage is input through the negative high voltage external monitoring port and output through the negative output terminal of the voltage providing circuit.

2. The configuration circuit according to claim 1, wherein: When the mode control circuit obtains the second mode adjustment signal for instructing the flash type FPGA to enter the external monitoring mode, the mode control circuit controls the path between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump to be turned on, and outputs a switch control signal of an effective level to control the conduction of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit. The positive high voltage provided by the positive high-voltage charge pump is output through the positive output terminal of the voltage supply circuit and the positive high-voltage external monitoring port, and the negative high voltage provided by the negative high-voltage charge pump is output through the negative output terminal of the voltage supply circuit and the negative high-voltage external monitoring port.

3. The configuration circuit according to claim 1, wherein: When the mode control circuit obtains the third mode adjustment signal for instructing the flash type FPGA to enter the external configuration mode, the mode control circuit controls the path between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump to be disconnected, and outputs a switch control signal of an effective level to control the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit to be turned on. The positive high-voltage charge pump and the negative high-voltage charge pump both stop working, the external positive high voltage input to the positive high-voltage external monitoring port is output through the positive output terminal of the voltage supply circuit, and the external negative high voltage input to the negative high-voltage external monitoring port is output through the negative output terminal of the voltage supply circuit.

4. The configuration circuit according to claim 1, wherein: The mode control circuit includes control logic, a three-input OR gate A1 and a two-input NOR gate B1; The first input terminal Q0 and the second input terminal Q1 of the control logic are respectively connected to the two input terminals of the three-input OR gate A1, the oscillator is connected to the other input terminal of the three-input OR gate A1, and the output terminal of the three-input OR gate A1 is connected to the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump; The second input terminal Q1 and the third input terminal Q2 of the control logic are connected to the two input terminals of the two-input NOR gate B1, and the output terminal of the two-input NOR gate B1 is connected to the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit to control on and off; When the mode control circuit obtains the second mode adjustment signal for instructing the flash type FPGA to enter the external monitoring mode through the control logic, the first input terminal Q0 and the second input terminal Q1 of the control logic both output a low level, the third input terminal Q2 of the control logic outputs a high level, the output terminal of the three-input OR gate A1 outputs the clock signal provided by the oscillator, and the two-input NOR gate B1 outputs a low-level effective switch control signal so that the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit are both turned on; When the mode control circuit obtains the third mode adjustment signal for instructing the flash type FPGA to enter the external configuration mode through the control logic, the first input terminal Q0 and the second input terminal Q1 of the control logic both output a high level, the third input terminal Q2 of the control logic outputs a low level, the output terminal of the three-input OR gate A1 constantly outputs a high level to turn off the clock signal provided by the oscillator, and the two-input NOR gate B1 outputs a low-level valid switch control signal so that the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit are both turned on.

5. The configuration circuit according to claim 4, characterized in that: The mode control circuit obtains the mode adjustment signal through the TDI terminal and TRST terminal of the JTAG of the flash type FPGA. The control logic includes three shift registers dff00, dff01, and dff02 and three control registers dff10, dff11, and dff12, wherein: The D end of dff00 is connected to the TDI terminal, the Q end of dff00 is connected to the D end of dff10, and the Q end of dff10 serves as the first input terminal Q0 of the control logic; the Q end of dff00 is also connected to the D end of dff01, the Q end of dff01 is connected to the D end of dff11, and the Q end of dff11 serves as the second input terminal Q1 of the control logic; the Q end of dff01 is also connected to the D end of dff02, the Q end of dff02 is connected to the D end of dff12, and the Q end of dff12 serves as the third input terminal Q2 of the control logic; the RST ends of dff00, dff01, dff02, dff10, dff11 and dff12 are all connected to the TRST terminal; The CLK ends of dff00, dff01, and dff02 are all connected to a data shift clock signal SHIFT_CK emitted by the TAP state machine of the JTAG of the flash type FPGA, and the CLK ends of dff10, dff11, and dff12 are all connected to another data update clock signal UPDATE_CK emitted by the TAP state machine of the JTAG of the flash type FPGA.

6. The configuration circuit according to claim 1, wherein: The positive high-voltage bidirectional switch circuit includes PMOS tubes P3 and P10 and a first positive level conversion circuit and a second positive level conversion circuit. The source of P3 is connected to the positive high-voltage output end of the positive high-voltage charge pump, the drain of P3 is connected to the source of P10, and the drain of P10 is connected to the positive high-voltage external monitoring port. The input end of the first positive level conversion circuit obtains the switch control signal output by the mode control circuit, the output end is connected to the gate of P3, and the power supply end of the first positive level conversion circuit is connected to the positive high voltage output end of the positive high voltage charge pump; The input end of the second positive level conversion circuit obtains the switch control signal output by the mode control circuit, the output end is connected to the gate of P10, and the power supply end of the second positive level conversion circuit is connected to the positive high voltage external monitoring port; When the mode control circuit outputs a switch control signal of a valid level, the first positive level conversion circuit and the second positive level conversion circuit both output a low level, P3 and P10 are both turned on, so that the positive high-voltage bidirectional switch circuit is turned on; otherwise, the positive high-voltage bidirectional switch circuit is disconnected.

7. The configuration circuit according to claim 6, characterized in that: The switch control signal is effective at a low level. The first positive level conversion circuit and the second positive level conversion circuit have the same circuit structure. In each positive level conversion circuit, the source of the PMOS transistor P1 and the source of the PMOS transistor P2 are connected and connected to the power supply end of the positive level conversion circuit. The drain of P1 is connected to the drain of the NMOS transistor N4 and the gate of P2. The drain of P2 is connected to the drain of the NMOS transistor N5 and the gate of P1. The source of N4 is grounded, the source of N5 is grounded, and the gate of N4 is connected to the input end of the positive level conversion circuit. The input end of the positive level conversion circuit is also connected to the gate of N5 through an inverter I3. The drain of N5 is also connected to the output end of the positive level conversion circuit.

8. The configuration circuit according to claim 1, wherein: The negative high-voltage bidirectional switch circuit includes NMOS transistors N14 and N19 and a first negative level conversion circuit and a second negative level conversion circuit, the source of N19 is connected to the negative high-voltage output end of the negative high-voltage charge pump, the drain of N19 is connected to the source of N14, and the drain of N14 is connected to the negative high-voltage external monitoring port; The switch control signal output by the mode control circuit is provided to the input end of the first negative level conversion circuit and the input end of the second negative level conversion circuit through an inverter, the output end of the first negative level conversion circuit is connected to the gate of N19, and the power supply end of the first negative level conversion circuit is connected to the negative high-voltage output end of the negative high-voltage charge pump; The output end of the second negative level conversion circuit is connected to the gate of N14, and the power supply end of the second negative level conversion circuit is connected to the negative high voltage external monitoring port; When the mode control circuit outputs a switch control signal of a valid level, the first negative level conversion circuit and the second negative level conversion circuit both output a high level, N19 and N14 are both turned on, so that the negative high-voltage bidirectional switch circuit is turned on, otherwise the negative high-voltage bidirectional switch circuit is disconnected.

9. The configuration circuit according to claim 8, characterized in that: The switch control signal is effective at a low level. The first negative level conversion circuit and the second negative level conversion circuit have the same circuit structure. In each negative level conversion circuit, the source of the NMOS transistor N12 is connected to the source of the NMOS transistor N13 and is also connected to the power supply terminal of the negative level conversion circuit. The drain of N12 is connected to the drain of the PMOS transistor P11 and the gate of N13. The drain of N13 is connected to the drain of the PMOS transistor P12 and the gate of N12. The source of P11 is connected to the source of P12 and is also connected to the chip voltage VDD. The gate of P11 is connected to the input terminal of the negative level conversion circuit. The input terminal of the negative level conversion circuit is also connected to the gate of P12 via an inverter. The drain of N13 serves as the output terminal of the negative level conversion circuit.

10. The configuration circuit according to claim 1, wherein: When the mode control circuit obtains the first mode adjustment signal for instructing the flash type FPGA to enter the default working mode, the mode control circuit controls the path between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump to be turned on, and outputs an invalid level switch control signal to control the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit to be disconnected. The positive high voltage provided by the positive high-voltage charge pump is output through the positive output terminal of the voltage supply circuit, and the negative high voltage provided by the negative high-voltage charge pump is output through the negative output terminal of the voltage supply circuit.

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