Memory failure area identification method and device, electronic equipment and storage medium

Abstract

The application provides a memory fault area identification method and device, electronic equipment and storage medium. The method comprises the following steps: checking whether the current memory configuration of a system is changed compared with the memory configuration at the last operation; if the current memory configuration is not changed, obtaining a current suspicious memory area list of the system, wherein the current suspicious memory area list records the fault addresses of the current suspicious memory area; and performing shielding processing on the corresponding memory area according to the current suspicious memory area list. By shielding the fault memory area, the use of the fault memory area by the system is isolated, and the reliability of the system is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a method, apparatus, electronic device, and storage medium for identifying faulty regions in a memory. Background Technology

[0002] With the development of computer technology, software program design and development have become increasingly complex, putting greater pressure on memory access and demanding higher standards for memory stability. In particular, for devices such as servers, which require long-term operation and monitoring, the stable operation of applications faces even stricter requirements, demanding high reliability and stability from memory.

[0003] Due to factors such as accumulated wear and tear during use and physical damage caused by improper use, memory will inevitably experience read and write errors.

[0004] To address this issue, various detection and repair techniques are commonly used to correct data for recoverable errors (CE). However, extensive data repair consumes hardware processing time and impacts system memory access performance. More importantly, unrecoverable errors cannot be repaired, and these memory access errors severely affect system stability and data reliability.

[0005] In existing technology, a method for training a memory detection model has been proposed for fault monitoring. This method trains a memory monitoring sub-model by combining historical memory state data with real-world fault scenarios, achieving fault prediction at the memory module level.

[0006] In the process of realizing this invention, the inventors discovered at least the following technical problems in the prior art:

[0007] Current technologies can only assess memory health status and risk level based on prediction results, but they cannot effectively resolve actual memory failures. Summary of the Invention

[0008] This invention provides a method, apparatus, electronic device, and storage medium for identifying faulty memory regions, which can shield faulty memory regions and isolate the system from using faulty memory regions.

[0009] This invention provides a method for identifying faulty regions in a memory, comprising:

[0010] Check whether the current memory configuration in the system has changed compared to the memory configuration during the last run;

[0011] If the current memory configuration has not changed, then obtain the current list of suspicious memory regions of the system, which records the fault addresses of the current suspicious memory regions;

[0012] Based on the current list of suspicious memory regions, the corresponding memory regions are masked.

[0013] Optionally, the step of masking the corresponding memory region based on the current list of suspicious memory regions includes:

[0014] Scan the memory regions corresponding to the current list of suspicious memory regions;

[0015] If the scanned memory region fails the test, the memory region is kept in the current list of suspected memory regions to update the current list of suspected memory regions;

[0016] If the scanned memory region passes the test, the memory region is removed from the list of currently suspected memory regions to update the list of currently suspected memory regions.

[0017] Based on the updated list of currently suspicious memory regions, the corresponding memory regions are masked.

[0018] Optionally, after the step of checking whether the current memory configuration in the system has changed compared to the memory configuration during the last run, the method further includes:

[0019] If the current memory configuration changes, the list of currently suspicious memory regions is cleared.

[0020] Monitor read / write errors in the memory;

[0021] Based on the read / write error status of the memory, and according to the fault determination strategy, newly added suspicious memory regions are detected.

[0022] Analyze the fault addresses corresponding to the newly added suspicious memory regions;

[0023] Based on the fault addresses corresponding to the newly added suspicious memory regions, the areas to be shielded are defined;

[0024] Update the list of currently suspicious storage regions based on the regions to be blocked;

[0025] Based on the current list of suspicious memory regions, the corresponding memory regions are masked.

[0026] Optionally, the fault determination strategy includes:

[0027] Any combination of the number of CRC errors, ECC errors, repairable CE errors, and unrepairable UE errors within a predetermined time period.

[0028] Optionally, the step of parsing the fault address corresponding to the newly added suspicious memory region specifically involves: parsing the fault address corresponding to the newly added suspicious memory region based on the current memory interleaving type; or

[0029] The step of defining the area to be shielded based on the fault address corresponding to the newly added suspicious memory area is as follows: based on the fault address corresponding to the newly added suspicious memory area, the area to be shielded is defined according to the minimum memory alignment rule required by the system.

[0030] Optionally, the step of parsing the fault address corresponding to the newly added suspicious memory region according to the current memory interleaving type specifically includes:

[0031] If the current system is of the Socket Interleave type, the memory is interleaved across the entire system address space, with the Interleave Size as the granularity and address alignment rule, and is mapped to each memory Channel in an interleaved manner according to the Socket / Die before encapsulation / Channel as the index.

[0032] If the current system is a single-chip interleaved die-interleave type before packaging, the memory is stacked sequentially with the socket as the index in the entire system address. Within the memory range of the same socket, the memory is mapped to each memory channel in an interleaved manner with the interleave size as the granularity and address alignment rule, respectively according to the die and the channel as the index.

[0033] If the current system is of the Channel Interleave type, the memory is stacked sequentially with Socket / Die as the index across the entire system address. Within the memory range of the same Die, the memory is mapped to each memory Channel in an interleaved manner with Interleave Size as the granularity and address alignment rule, according to Channel as the index.

[0034] If the current system is a non-interleaved type, the memory will be stacked in the entire system address space, indexed by Socket / Die / Channel respectively.

[0035] Optionally, the step of updating the current list of suspicious storage regions based on the region to be blocked specifically includes:

[0036] Get the minimum address alignment size supported by the system;

[0037] Obtain the fault address, divide the fault location by the minimum address alignment size, and obtain the calculation result;

[0038] The calculation result is rounded forward and then multiplied by the minimum address alignment size to obtain the low address boundary of the region to be shielded.

[0039] Add the minimum address alignment size to the low address boundary to obtain the high address boundary of the region to be masked;

[0040] The list of currently suspected memory regions is updated based on the low-high address boundary and the high address boundary of the region to be shielded.

[0041] Optionally, the step of masking the corresponding memory region according to the current list of suspicious memory regions specifically includes:

[0042] No address mapping is performed on the memory regions in the current list of suspicious memory regions.

[0043] Optionally, the step of checking whether the current memory configuration in the system has changed compared with the memory configuration during the last run is specifically as follows:

[0044] After superimposing the serial presence detection (SPD) information of the memory, a cyclic redundancy check is performed to determine whether the current memory configuration has changed compared to the memory configuration during the last run; or

[0045] After overlaying the hardware identification information of the memory, a cyclic redundancy check is performed to determine whether the current memory configuration has changed compared to the memory configuration during the last run.

[0046] The present invention also provides a device for identifying faulty regions in a memory, comprising:

[0047] The checking unit is used to check whether the current memory configuration in the system has changed compared to the memory configuration during the last run;

[0048] The acquisition unit is used to acquire a list of currently suspicious memory regions of the system when the current memory configuration has not changed. The list of currently suspicious memory regions records the fault addresses of the currently suspicious memory regions.

[0049] The shielding unit is used to shield the corresponding memory regions according to the current list of suspicious memory regions.

[0050] The present invention also provides an electronic device, which includes the above-mentioned memory fault region identification device.

[0051] The present invention also provides a device for identifying faulty regions in a memory, comprising:

[0052] Memory;

[0053] And a processor coupled to the memory, the processor being configured to execute the aforementioned memory fault region identification method based on instructions stored in the memory.

[0054] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the method for identifying memory fault regions.

[0055] The method, apparatus, electronic device, and storage medium for identifying faulty memory regions provided by this invention effectively improve the reliability of the system by shielding the faulty memory regions and isolating the system from using the faulty memory regions. Attached Figure Description

[0056] Figure 1 This is a flowchart of a method for identifying memory fault regions according to an embodiment of the present invention;

[0057] Figure 2 This is a flowchart of a method for identifying memory fault regions according to another embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of a memory fault region identification device according to an embodiment of the present invention;

[0059] Figure 4 This is a connection diagram of the memory fault area identification device described in the application scenario of the present invention;

[0060] Figure 5 This is a flowchart illustrating a method for identifying memory fault regions according to an embodiment of the present invention;

[0061] Figure 6 This is a schematic diagram of memory addressing under fault-free conditions in one embodiment of the present invention;

[0062] Figure 7 This is a schematic diagram illustrating the readdressing of a faulty memory address in one embodiment of the present invention;

[0063] Figure 8 This is a schematic diagram of the structure of a memory fault region identification device according to another embodiment of the present invention. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0065] This invention provides a method for identifying faulty regions in a memory, such as... Figure 1 As shown, the method includes:

[0066] S11. Check whether the current memory configuration in the system has changed compared to the memory configuration during the last run; the memory can be RAM, etc.

[0067] S12. If the current memory configuration has not changed, obtain the current suspicious memory region list of the system, which records the fault address of the current suspicious memory region.

[0068] S13. Based on the current list of suspicious memory regions, the corresponding memory regions are masked.

[0069] This invention precisely locates faulty memory access areas by dynamically detecting memory access errors in real time. Furthermore, by shielding the faulty memory areas, it isolates the system from their use, effectively improving system reliability. This solution eliminates the need for manual monitoring of memory wear and reduces the need to replace memory modules, minimizing hardware replacement costs while improving system stability.

[0070] like Figure 2 As shown, another embodiment of the present invention provides a method for identifying memory fault regions, comprising:

[0071] S11. Check whether the current memory configuration in the system has changed compared to the memory configuration during the last run. Specifically, this involves: overlaying the SPD (Serial Presence Detect) information of the memory and performing a CRC (Cyclic Redundancy Check) to determine whether the current memory configuration has changed compared to the memory configuration during the last run; or overlaying the hardware identification information of the memory and performing a CRC to determine whether the current memory configuration has changed compared to the memory configuration during the last run. If the current memory configuration has not changed, proceed to step S12; if the current memory configuration has changed, proceed to step S14.

[0072] Step S12: When the current memory configuration has changed, obtain the current suspicious memory region list of the system. The current suspicious memory region list records the fault address of the current suspicious memory region.

[0073] Step S13: Based on the current list of suspicious memory regions, mask the corresponding memory regions.

[0074] Step S13 includes:

[0075] Step S131: Scan the memory regions corresponding to the current list of suspicious memory regions;

[0076] Step S132: If the scanned memory region fails the test, the memory region is kept in the current suspicious memory region list to update the current suspicious memory region list; proceed to step S134.

[0077] Step S133: If the scanned memory region passes the test, remove the memory region from the current suspicious memory region list to update the current suspicious memory region list; proceed to step 134.

[0078] Step S134: Based on the updated list of current suspicious memory regions, the corresponding memory regions are masked.

[0079] Step S14: Clear the list of currently suspicious memory regions;

[0080] Step S15: Monitor the read / write errors of the memory;

[0081] Step S16: Based on the read / write error status of the memory, a new suspicious memory region is detected according to the fault determination strategy. The fault determination strategy includes any combination of the number of CRC errors, ECC (Error Checking and Correcting) errors, CE (Correctable Error) errors, and UE (Un-Correctable Error) errors within a predetermined time period.

[0082] Step S17: Parse the fault address corresponding to the newly added suspicious memory region; specifically, this step involves parsing the fault address corresponding to the newly added suspicious memory region based on the current memory interleaving type. More specifically:

[0083] If the current system is of the Socket Interleave type, the memory is mapped to each memory channel in an interleaved manner across the entire system address space, using the Interleave Size as the granularity and address alignment rule, and indexed by Socket (packaging unit) / Die (single chip before packaging) / Channel (channel).

[0084] If the current system is of the Die Interleave type (single-chip interleaving before packaging), the memory is stacked sequentially with the socket as the index in the entire system address. Within the memory range of the same socket, the memory is mapped to each memory channel in an interleaved manner with the Interleave Size as the granularity and address alignment rule, respectively according to the Die and the memory channel as the index.

[0085] If the current system is of the Channel Interleave type, the memory is stacked in order with Socket / Die as the index across the entire system address. Within the memory range of the same Die, the memory is mapped to each memory Channel in an interleaved manner with Interleave Size as the granularity and address alignment rule.

[0086] If the current system is of the Non-Interleave type, the memory is stacked in the order of Socket / Die / Channel index across the entire system address.

[0087] Step S18: Based on the fault address corresponding to the newly added suspicious memory region, delineate the region to be shielded; this step specifically involves: based on the fault address corresponding to the newly added suspicious memory region, delineate the region to be shielded according to the minimum memory alignment rule required by the system.

[0088] Step S19: Update the list of currently suspicious memory regions based on the region to be shielded;

[0089] Step S110: Based on the current list of suspicious memory regions, mask the corresponding memory regions. Specifically, do not perform address mapping on the memory regions in the current list of suspicious memory regions.

[0090] Step S19 is as follows:

[0091] Step S191: Obtain the minimum address alignment size supported by the system;

[0092] Step S192: Obtain the fault address, divide the fault location by the minimum address alignment size, and obtain the calculation result;

[0093] Step S193: Round the obtained calculation result forward and multiply it by the minimum address alignment size to obtain the low address boundary of the region to be shielded;

[0094] Step S194: Add the minimum address alignment size to the low address boundary to obtain the high address boundary of the region to be masked;

[0095] Step S195: Update the list of currently suspicious memory regions based on the low-high address boundary and the high address boundary of the region to be shielded.

[0096] In the above embodiments, the least address is aligned, and rounding to the lower address is required.

[0097] This invention also provides a device for identifying faulty regions in a memory, such as... Figure 3 As shown, the device includes:

[0098] The checking unit 11 is used to check whether the current memory configuration in the system has changed compared with the memory configuration during the last run;

[0099] The acquisition unit 12 is used to acquire a list of currently suspicious memory regions of the system when the current memory configuration has not changed. The list of currently suspicious memory regions records the fault addresses of the currently suspicious memory regions.

[0100] The shielding unit 13 is used to shield the corresponding memory region according to the current list of suspicious memory regions.

[0101] Specifically, the shielding unit 13 performs the following steps: scanning the memory regions corresponding to the current suspicious memory region list; if the scanned memory region fails the test, the memory region is kept in the current suspicious memory region list to update the current suspicious memory region list; if the scanned memory region passes the test, the memory region is removed from the current suspicious memory region list to update the current suspicious memory region list; and according to the updated current suspicious memory region list, the corresponding memory region is shielded.

[0102] Optionally, the device further includes:

[0103] The clearing unit clears the list of currently suspicious memory regions if the current memory configuration changes.

[0104] A monitoring unit is used to monitor read / write errors in the memory.

[0105] The detection unit, based on the read / write error status of the memory and according to the fault determination strategy, detects newly added suspicious memory regions.

[0106] The parsing unit parses the fault addresses corresponding to the newly added suspicious memory regions;

[0107] The slicing unit delineates the area to be shielded based on the fault address corresponding to the newly added suspicious memory area;

[0108] The updating unit updates the list of currently suspicious storage regions based on the region to be blocked.

[0109] The processing unit, based on the current list of suspicious memory regions, performs masking processing on the corresponding memory regions.

[0110] The fault determination strategy includes:

[0111] Any combination of the number of CRC errors, ECC errors, repairable CE errors, and unrepairable UE errors within a predetermined time period.

[0112] The parsing unit specifically performs the following functions: parsing the fault address corresponding to the newly added suspicious memory region based on the current memory interleaving type; or

[0113] The slicing unit specifically involves: based on the fault addresses corresponding to the newly added suspicious memory regions, and according to the minimum memory alignment rules required by the system, defining the regions to be shielded.

[0114] The parsing unit is specifically:

[0115] If the current system is of the Socket Interleave type, the memory is interleaved across the entire system address space, with the Interleave Size as the granularity and address alignment rule, and is mapped to each memory Channel in an interleaved manner according to the Socket / Die before encapsulation / Channel as the index.

[0116] If the current system is a single-chip interleaved die-interleave type before packaging, the memory is stacked sequentially with the socket as the index in the entire system address. Within the memory range of the same socket, the memory is mapped to each memory channel in an interleaved manner with the interleave size as the granularity and address alignment rule, respectively according to the die and the channel as the index.

[0117] If the current system is of the Channel Interleave type, the memory is stacked sequentially with Socket / Die as the index across the entire system address. Within the memory range of the same Die, the memory is mapped to each memory Channel in an interleaved manner with Interleave Size as the granularity and address alignment rule, according to Channel as the index.

[0118] If the current system is a non-interleaved type, the memory will be stacked in the entire system address space, indexed by Socket / Die / Channel respectively.

[0119] Specifically, the update unit is:

[0120] Get the minimum address alignment size supported by the system;

[0121] Obtain the fault address, divide the fault location by the minimum address alignment size, and obtain the calculation result;

[0122] The calculation result is rounded forward and then multiplied by the minimum address alignment size to obtain the low address boundary of the region to be shielded.

[0123] Add the minimum address alignment size to the low address boundary to obtain the high address boundary of the region to be masked;

[0124] The list of currently suspected memory regions is updated based on the low-high address boundary and the high address boundary of the region to be shielded.

[0125] Optionally, the shielding unit specifically means: not mapping the memory regions in the current list of suspicious memory regions.

[0126] Specifically, the inspection unit is:

[0127] After superimposing the serial presence detection (SPD) information of the memory, a cyclic redundancy check is performed to determine whether the current memory configuration has changed compared to the memory configuration during the last run; or

[0128] After overlaying the hardware identification information of the memory, a cyclic redundancy check is performed to determine whether the current memory configuration has changed compared to the memory configuration during the last run.

[0129] The apparatus in this embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effects are similar, and will not be repeated here.

[0130] The following describes the application scenarios of this invention.

[0131] like Figure 4 As shown, the processing apparatus of the present invention includes:

[0132] Startup module: Responsible for starting the entire system;

[0133] Memory module configuration verification module: It is responsible for checking whether the memory modules installed on the system have been replaced after each restart, and determining whether the memory suspicious area information stored on the memory status recording module is compatible (here, we refer to the memory area where errors frequently occur during memory read and write as the memory suspicious area).

[0134] Memory status scanning module: responsible for scanning and testing each suspicious memory area recorded on the memory status recording module to determine whether the memory read and write functions of that area are normal.

[0135] Memory fault monitoring module: Monitors for abnormal errors during memory read and write operations and performs statistical analysis;

[0136] Memory status recording module: used to record and store information about suspicious memory areas on the current system;

[0137] Memory Fault Area Handling Module: Used to locate the location of the problematic memory area and to mask that memory area.

[0138] like Figure 5 As shown, the processing flow of this solution includes:

[0139] Step 1. Configure the system working environment and start the system;

[0140] Step 2. Check if the memory configuration of the current system has changed compared to the last run. If it has not changed, proceed to Step 3; if it has changed, clear the currently stored list of suspicious memory regions in the system and then proceed directly to Step 6.

[0141] Step 3. If the memory configuration has not changed, obtain a list of suspicious memory regions in the system;

[0142] Step 4. Scan each memory range in the suspicious memory region list one by one, such as performing read / write verification tests. If the currently scanned region fails the test, keep the region in the suspicious memory region list; if the currently scanned region passes the test, remove the region from the suspicious memory region list.

[0143] Step 5. Based on the scan results from the above steps, generate a new list of suspicious memory regions;

[0144] Step 6. During system startup, load the list of suspicious memory regions in the system;

[0145] Step 7. During the system startup phase, based on the list of suspicious memory regions, mask the corresponding memory regions.

[0146] Step 8. System startup complete, execute the use case;

[0147] Step 9. The system monitors and collects read / write error information on each memory channel;

[0148] Step 10. Based on the various read and write error information collected from each memory channel, determine whether there are any newly added suspicious memory areas according to the established fault determination strategy.

[0149] If no new suspicious memory regions are found, repeat step 10.

[0150] If a new suspicious memory region is found, proceed to step 11;

[0151] Step 11. Analyze the location of the newly added suspicious memory region according to the current memory interleaving type, delineate the shielded area according to the minimum memory alignment rule required by the system, reduce memory waste, and add the region to the list of suspicious memory regions.

[0152] The memory interleaving parsing rules here are:

[0153] (1) If the current system is Socket Interleave, the memory in the entire system address uses InterleaveSize as the granularity and address alignment rule, and is interleaved and mapped to each memory Channel according to Socket / Die / Channel as the index;

[0154] (2) If the current system is Die Interleave, the memory is stacked sequentially with Socket as the index in the entire system address. Within the memory range of the same Socket, the memory is mapped to each memory Channel in an interleaved manner with Interleave Size as the granularity and address alignment rule, respectively according to Die / Channel as the index.

[0155] (3) If the current system is Channel Interleave, the memory is stacked in order with Socket / Die as the index on the entire system address. Within the memory range of the same Die, the memory is mapped to each memory Channel in an interleaved manner with Interleave Size as the granularity and address alignment rule.

[0156] (4) If the current system is Non-Interleave, the memory is stacked in order of Socket / Die / Channel in the entire system address;

[0157] The rules for defining the shielded area here are as follows:

[0158] (1) Obtain the minimum address alignment size supported by the system;

[0159] (2) Obtain the fault address, divide it by the minimum address alignment size, round the result forward, and multiply it by the minimum address alignment size to obtain the low address boundary of the shielded area.

[0160] (3) Add the minimum address alignment size to the low address to obtain the high address boundary of the shielded area;

[0161] (4) In the case of multiple fault addresses, if their corresponding shielding areas completely or partially overlap, they shall be merged according to the largest coverage area.

[0162] Step 12. Restart the system and repeat step 6.

[0163] The following describes the application scenarios of this invention.

[0164] The following example uses a system consisting of one Socket, which contains two Dies.

[0165] Each die in this system has two memory channels, and each channel is equipped with a 1GB DIMM (Dual-Inline-Memory Module). Configured to not perform any type of memory interleaving, address allocation uses Die0 and Channel as indices for sequential addressing. Figure 6 As shown:

[0166] The processing flow includes:

[0167] Step 1: Correctly install the hardware environment for the operating system, configure memory modules for each memory channel through the dedicated interface, connect the power and start the system;

[0168] Step 2: The system checks whether the current memory configuration has changed compared to the last time it was run.

[0169] Due to the uniqueness of the SPD on each DIMM, this example uses the method of superimposing the SPD information of all DIMMs on the system to generate a CRC check code for inspection.

[0170] The specific method is as follows: After each CRC checksum is generated, the value is stored in Flash memory. Upon the next system startup, the CRC checksum is recalculated and compared with the value stored in Flash memory.

[0171] If they are different, write the newly calculated CRC value into Flash to overwrite the original value and then proceed with the next steps;

[0172] If the results are the same, it is assumed that the memory module has not been replaced, and the subsequent steps are continued. This example uses this situation as an example.

[0173] Step 3: The system obtains a list of suspicious memory regions. Taking the first startup as an example, the list is empty.

[0174] Step 4: Perform read and write verification on each memory range in the list of suspicious memory regions. Since the list of suspicious memory regions is empty at this time, this step is skipped.

[0175] Step 5: Generate a new list of suspicious memory regions; in this example, the list remains empty.

[0176] Step 6: During system startup, load the list of suspicious memory regions in the system;

[0177] Step 7: During the system startup phase, since the list of suspicious memory regions is empty at this time, no memory regions are blocked.

[0178] Step 8: The system has started up and will now execute the current usage scenario.

[0179] Step 9: During use, the system begins to collect access error information on each memory channel through counters set on each memory channel;

[0180] Step 10: Analyze the memory access error data within 12 hours and check if there are any memory addresses that have "occurred 5 or more CRC / ECCCE errors or 2 or more UE errors".

[0181] Based on the current memory interleaving situation of the system, the actual location of the faulty memory address is determined. In this example, since memory interleaving logic is not enabled, memory storage space is sequentially addressed. Under the continuous address distribution, memory is mapped to the respective Channels on each Socket and Die using Socket / Die / Channel as indices. The actual location of the faulty memory address is as follows: Figure 6 As shown.

[0182] Since the hardware design of this system dictates that the minimum address alignment rule is 256MB, the address range containing this memory address is added to the list of suspicious memory locations in accordance with the minimum alignment rule.

[0183] Step 11: Restart the system, load the list of suspicious memory locations, and then re-address the memory addresses. Figure 7 As shown.

[0184] The embodiments of the present invention have the following beneficial effects:

[0185] 1. By shielding the faulty memory region and isolating the system from its use, the reliability of the system is effectively improved.

[0186] 2. No manual monitoring of memory wear is required, reducing the need to replace memory modules and minimizing hardware replacement costs while improving system stability;

[0187] 3. This invention can dynamically detect memory errors in real time and use strategies to accurately locate faulty areas.

[0188] 4. This invention can improve the stability and reliability of system operation by shielding faulty memory regions;

[0189] 5. This invention can check whether the memory module has been replaced after each restart;

[0190] 6. This invention can rescan suspicious memory areas after each restart and unblock memory that has returned to normal.

[0191] In this embodiment of the invention, there are several ways to mask memory regions based on a list of suspicious memory regions. For example, faulty regions can be left unmapped, preventing upper-layer software from accessing them. In this step, the system only sees normal memory addresses, while abnormal regions are not mapped, indirectly achieving the goal of blocking the use of those address ranges.

[0192] In this embodiment of the invention, there are various ways to scan suspicious memory regions, such as basic read-write verification tests.

[0193] In this embodiment of the invention, there are multiple ways to determine whether the memory module configuration on the current system has changed. For example, CRC verification can be performed after superimposing the SPD information of all DIMMs. Specifically, a checksum is generated according to the CRC rule, and then the checksum is compared to see if the two checksums are consistent.

[0194] In this embodiment of the invention, there can be multiple ways to determine suspicious memory regions. Different error types can be weighted, and the granularity of the shielded memory space can be adjusted according to the actual system situation or hardware design requirements.

[0195] This invention also provides an electronic device, which includes the aforementioned memory fault region identification device.

[0196] This invention also provides a device for identifying faulty regions in a memory, such as... Figure 8 As shown, the device 8 includes:

[0197] Memory 81;

[0198] And a processor 82 coupled to the memory 81, the processor 82 being configured to execute the aforementioned memory fault region identification method based on instructions stored in the memory 81.

[0199] This invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the above-described method for identifying memory fault regions.

[0200] Those skilled in the art will understand that all or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0201] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for identifying faulty regions in a memory, characterized in that, include: Check whether the current memory configuration in the system has changed compared to the memory configuration during the last run; If the current memory configuration has not changed, then obtain the current list of suspected memory regions of the system, which records the fault addresses of the current suspected memory regions; based on the current list of suspected memory regions, the corresponding memory regions are masked. If the current memory configuration changes, the list of currently suspicious memory regions is cleared. Monitor read / write errors in the memory; Based on the read / write error status of the memory, and according to the fault determination strategy, newly added suspicious memory regions are detected. Analyze the fault addresses corresponding to the newly added suspicious memory regions; based on the fault addresses corresponding to the newly added suspicious memory regions, delineate the areas to be shielded; Update the list of currently suspicious storage regions based on the regions to be blocked; Based on the current list of suspicious memory regions, the corresponding memory regions are masked. The step of parsing the fault address corresponding to the newly added suspicious memory region specifically involves: parsing the fault address corresponding to the newly added suspicious memory region based on the current memory interleaving type, specifically as follows: If the current system is of the Socket Interleave type, the memory is interleaved across the entire system address space, with the Interleave Size as the granularity and address alignment rule, and is mapped to each memory Channel in an interleaved manner according to the Socket / Die before encapsulation / Channel as the index. If the current system is a single-chip interleaved die-interleave type before packaging, the memory is stacked sequentially with the socket as the index in the entire system address. Within the memory range of the same socket, the memory is mapped to each memory channel in an interleaved manner with the interleave size as the granularity and address alignment rule, respectively according to the die and the channel as the index. If the current system is of the Channel Interleave type, the memory is stacked sequentially with Socket / Die as the index across the entire system address. Within the memory range of the same Die, the memory is mapped to each memory Channel in an interleaved manner with Interleave Size as the granularity and address alignment rule, according to Channel as the index. If the current system is a non-interleaved type, the memory will be stacked in the entire system address space, indexed by Socket / Die / Channel respectively.

2. The method according to claim 1, characterized in that, The step of masking the corresponding memory region based on the current list of suspicious memory regions includes: Scan the memory regions corresponding to the current list of suspicious memory regions; If the scanned memory region fails the test, the memory region is kept in the current list of suspected memory regions to update the current list of suspected memory regions; If the scanned memory region passes the test, the memory region is removed from the list of currently suspected memory regions to update the list of currently suspected memory regions. Based on the updated list of currently suspicious memory regions, the corresponding memory regions are masked.

3. The method according to claim 1, characterized in that, The fault determination strategy includes: Any combination of the number of CRC errors, ECC errors, repairable CE errors, and unrepairable UE errors within a predetermined time period.

4. The method according to claim 3, characterized in that: The step of defining the area to be shielded based on the fault address corresponding to the newly added suspicious memory area is as follows: based on the fault address corresponding to the newly added suspicious memory area, the area to be shielded is defined according to the minimum memory alignment rule required by the system.

5. The method according to claim 3, characterized in that, The step of updating the list of current suspicious storage regions based on the region to be blocked is specifically as follows: Get the minimum address alignment size supported by the system; Obtain the fault address, divide the fault address by the minimum address alignment size, and obtain the calculation result; The calculation result is rounded forward and then multiplied by the minimum address alignment size to obtain the low address boundary of the region to be shielded. Add the minimum address alignment size to the low address boundary to obtain the high address boundary of the region to be masked; The list of currently suspected memory regions is updated based on the low address boundary and the high address boundary of the region to be shielded.

6. The method according to claim 1, characterized in that, The step of masking the corresponding memory region based on the current list of suspicious memory regions specifically involves: No address mapping is performed on the memory regions in the current list of suspicious memory regions.

7. The method according to claim 1, characterized in that: The specific steps for checking whether the current memory configuration in the system has changed compared to the memory configuration during the last run are as follows: After superimposing the serial presence detection (SPD) information of the memory, a cyclic redundancy check is performed to determine whether the current memory configuration has changed compared with the memory configuration during the last run. or After overlaying the hardware identification information of the memory, a cyclic redundancy check is performed to determine whether the current memory configuration has changed compared to the memory configuration during the last run.

8. A device for identifying faulty regions in a memory, characterized in that, include: The checking unit is used to check whether the current memory configuration in the system has changed compared to the memory configuration during the last run; The acquisition unit is used to acquire a list of currently suspicious memory regions of the system when the current memory configuration has not changed. The list of currently suspicious memory regions records the fault addresses of the currently suspicious memory regions. The shielding unit is used to shield the corresponding memory regions according to the current list of suspicious memory regions; The clearing unit is used to clear the list of currently suspicious memory regions when the current memory configuration changes. A monitoring unit is used to monitor read / write errors in the memory. The detection unit is used to detect newly added suspicious memory areas based on the read / write error status of the memory and according to the fault determination strategy. The parsing unit is used to parse the fault address corresponding to the newly added suspicious memory region; The slicing unit is used to delineate the area to be shielded based on the fault address corresponding to the newly added suspicious memory area; An update unit is used to update the list of currently suspicious memory regions based on the region to be blocked. The processing unit is used to mask the corresponding memory regions according to the current list of suspicious memory regions; The parsing unit is specifically used to parse the fault address corresponding to the newly added suspicious memory region according to the current memory interleaving type, specifically as follows: If the current system is of the Socket Interleave type, the memory is interleaved across the entire system address space, with the Interleave Size as the granularity and address alignment rule, and is mapped to each memory Channel in an interleaved manner according to the Socket / Die before encapsulation / Channel as the index. If the current system is a single-chip interleaved die-interleave type before packaging, the memory is stacked sequentially with the socket as the index in the entire system address. Within the memory range of the same socket, the memory is mapped to each memory channel in an interleaved manner with the interleave size as the granularity and address alignment rule, respectively according to the die and the channel as the index. If the current system is of the Channel Interleave type, the memory is stacked sequentially with Socket / Die as the index across the entire system address. Within the memory range of the same Die, the memory is mapped to each memory Channel in an interleaved manner with Interleave Size as the granularity and address alignment rule, according to Channel as the index. If the current system is a non-interleaved type, the memory will be stacked in the entire system address space, indexed by Socket / Die / Channel respectively.

9. An electronic device, characterized in that, The electronic device includes the memory fault region identification device as described in claim 8.

10. A device for identifying faulty regions in a memory, comprising: Memory; And a processor coupled to the memory, the processor being configured to perform a memory fault region identification method as described in any one of claims 1 to 7 based on instructions stored in the memory.

11. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the method for identifying memory fault regions as described in any one of claims 1 to 7.

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