Process for manufacturing silicon carbide semiconductor devices with improved characteristics

Abstract

The present disclosure relates to processes for fabricating silicon carbide semiconductor devices with improved characteristics. A process for fabricating a silicon carbide semiconductor device includes providing a silicon carbide wafer having a substrate. Epitaxial growth for forming an epitaxial layer is performed on the substrate, the epitaxial layer having a top surface. After the step of performing epitaxial growth, the process includes a step of removing a surface portion of the epitaxial layer from the top surface, thereby removing surface damage present at the top surface due to propagation of dislocations from the substrate during the previous epitaxial growth, and thereby defining a resulting top surface that is substantially free of defects.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a process for manufacturing silicon carbide semiconductor devices having improved characteristics. BACKGROUND

[0002] Electronic semiconductor devices made starting from silicon carbide substrates, such as diodes or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), are known, in particular for electronic power applications.

[0003] The above devices prove advantageous thanks to the good chemico-physical properties of silicon carbide. For example, silicon carbide generally has a wider band gap than silicon, which is normally used in electronic power devices. Therefore, also with a relatively small thickness, the breakdown voltage of silicon carbide is higher than that of silicon and therefore can be advantageously used in high-voltage, high-power and high-temperature applications.

[0004] However, the manufacturing of silicon carbide semiconductor devices is affected by some problems.

[0005] For example, the problem of the crystal quality of silicon carbide can represent an obstacle to achieve high production yields, which generally prove lower than similar devices obtained starting from silicon, thus causing an increase in production costs.

[0006] In particular, the epitaxial processes generally used for the manufacturing of devices tend to propagate the crystal defects buried in the starting substrate towards the surface of the epitaxial layer grown.

[0007] In detail, the propagation of TSDs (Threading Screw Dislocations) from the substrate towards the epitaxial layer can generate pits or nanopits (i.e. pits having nanometric dimensions, with a diameter of a few nanometres, for example less than 30 nm) on the surface of the same epitaxial layer.

[0008] It has been shown that the presence of such defects causes a reduction in the electrical performance of the devices, and in particular a decrease in reliability, due to the high leakage currents that can be generated in the reverse bias condition, with the consequence of a reduction in the yield after the electrical tests.

[0009] The aforementioned problems are particularly important for certain applications, in particular in the automotive field, where during the active use of the devices (on the board of a motor vehicle, in this example) it is allowed a very low percentage of failures (for example, less than 1%).

[0010] Figure 1 A wafer 1 of a semiconductor material, in particular silicon carbide (SiC), is schematically shown, comprising a substrate 2 on which an epitaxial layer 3 is grown, in particular with a homoepitaxial process, the epitaxial layer 3 having a top surface 3a. Defects, in particular TSDs, designated by 4, propagate from the substrate 2 (as indicated by the arrows) towards the overlying epitaxial layer 3, generating surface pits 5 on its top surface 3a.

[0011] The presence of surface pits 5, in particular if in the active region of the corresponding power device formed in the epitaxial layer 3, for example a diode or a MOSFET, can cause a decrease in the performance and reliability of the power device; for example, the surface pits 5 can jeopardize the proper growth of subsequent layers on the top surface 3a of the epitaxial layer 3, for example a dielectric layer grown via surface oxidation and / or a conductive layer designed to form an electrode of the power device, jeopardizing the reliability of the power device.

[0012] Research and experimental tests, for example see T. Kimoto, “Material science and device physics in SiC technology for high-voltage power devices”, Japanese Journal of Applied Physics 54, 040103 (2015), have confirmed that the presence of the aforementioned surface pits (nanopits) deriving from the propagation of dislocations from the substrate in fact jeopardize the device performance.

[0013] In this regard, Figure 2A and Figure 2B It is shown that, in the case of the presence of nanopits in the active region due to the propagation of dislocations from the substrate ( Figure 2A ), as well as in the case of the presence of dislocations, but these do not cause the presence of surface pits ( Figure 2B ), the plot of the leakage current I r versus the reverse bias voltage V leak for a power device made starting from a silicon carbide substrate, in this case a Schottky diode. According to the examination of the plots Figure 2A and Figure 2B it is evident that the leakage current is significantly higher in the case of the presence of surface pits in the active region compared to the case of the presence of dislocations through the substrate, but in the absence of surface pits.

[0014] The solutions proposed so far to overcome the problem of the prominence of the defects (see, for example, N. Piluso, A. Campione, S. Lorenti, A. Severino, G. Arena, S. Coffa, F. La Via, "High Quality 4H-SiC Epitaxial Layer by Tuning CVD Process", Materials Science Forum, ISSN: 1662-9752, Vol. 963, pp. 91-96) and, in particular, to reduce the effects of the defects on the surface of the epitaxial layer, envisage appropriate steps aimed at improving the epitaxial growth performed starting from a silicon carbide substrate. However, since the TSDs are defects of a crystalline nature, it is not possible to prevent their propagation towards the epitaxial layer.

[0015] Other known solutions (see, for example, N. Piluso, A. Severino, R. Anzalone, M. A. Di Stefano, E. Fontana, M. Salanitri, S. Lorenti, A. Campione, P. Fiorenza, F. La Via, "Growth of 4H-SiC Epitaxial Layer through Optimization of Buffer Layer", Materials Science Forum, ISSN: 1662-9752, Vol. 924, pp. 84-87) envisage the introduction of a buffer layer interposed between the substrate and the epitaxial layer; however, these solutions also enable at most a limited reduction in the density of dislocations, but do not prevent the propagation of the same dislocations towards the surface of the epitaxial layer.

[0016] Therefore, there is indeed a felt need to provide a solution that will enable to reduce the drawbacks related to the propagation of the crystalline defects, in particular the TSDs, towards the surface of the epitaxial layer grown on a silicon carbide substrate. SUMMARY

[0017] In various embodiments, the present solution provides a process for manufacturing a silicon carbide semiconductor device that will enable to overcome the drawbacks previously highlighted.

[0018] In at least one embodiment, the present disclosure provides a process for manufacturing a silicon carbide semiconductor device, comprising: providing a silicon carbide wafer having a substrate; performing epitaxial growth for forming an epitaxial layer having a top surface on the substrate, during which a propagation of dislocations from the substrate toward the top surface occurs, thus forming a surface damage; and after performing the epitaxial growth, removing a surface portion of the epitaxial layer starting from the top surface, thereby removing the surface damage at the top surface and defining a resulting top surface substantially free of defects.

[0019] In at least one embodiment, the present disclosure provides a method, comprising: forming an epitaxial layer on a silicon carbide substrate, a threading screw dislocation defect in the substrate extending through the epitaxial layer, and forming a pit at a surface of the epitaxial layer, the pit having a diameter less than 30 nm; and removing the pit at the surface of the epitaxial layer by performing chemical mechanical polishing (CMP) to remove a surface portion of the epitaxial layer, thereby defining a top surface of the epitaxial layer substantially free of defects.

[0020] In at least one embodiment, the present disclosure provides a method, comprising: forming an epitaxial layer on a silicon carbide substrate, a threading screw dislocation defect in the substrate extending through the epitaxial layer, and forming a pit at a surface of the epitaxial layer, the pit having a diameter less than 30 nm; removing the pit at the surface of the epitaxial layer by performing chemical mechanical polishing (CMP) to remove a surface portion of the epitaxial layer, thereby defining a top surface of the epitaxial layer substantially free of defects; and cleaning the resulting top surface. After cleaning, the resulting top surface has a roughness value lower than 0.1 nm. BRIEF DESCRIPTION OF DRAWINGS

[0021] For a better understanding of the present application, a preferred embodiment thereof will now be described, by way of non-limiting example only, and with reference to the accompanying drawings, in which:

[0022] Figure 1 is a schematic and simplified cross-sectional view of a portion of a silicon carbide semiconductor device;

[0023] Figure 2A and Figure 2B shows a plot of leakage current in a semiconductor device associated with the presence of surface defects;

[0024] Figure 3 shows a simplified flowchart of operations according to a process for manufacturing a silicon carbide semiconductor device, according to the present solution;

[0025] Figure 4A and Figure 4B is a schematic and simplified cross-sectional view of a portion of a silicon carbide semiconductor device during respective steps of a manufacturing process according to the present solution; and

[0026] Figure 5 is a schematic representation of a CMP (Chemical Mechanical Polishing) system used during a process for manufacturing a silicon carbide semiconductor device according to the present solution. DETAILED DESCRIPTION

[0027] As will be discussed in detail hereinafter, instead of following the approach of acting on the stop or reduction of the propagation of defects (in particular, TSDs), one aspect of the present solution envisages intervening to reduce the topographical damage produced on the surface by the propagation of the same defects, in particular to reduce the pits (nanopits) produced on the surface of the epitaxial layer.

[0028] The proposed solution allows to improve the subsequent processing operations envisaged by the manufacturing process on the epitaxial layer, such as the oxidation step for growing a dielectric layer on the epitaxial layer, preventing the effects of electric field concentration and ensuring a uniform oxidation.

[0029] According to one aspect of the present solution, an additional CMP step is introduced into the manufacturing process, i.e. a step of chemical-mechanical polishing of the surface of the epitaxial layer formed on the silicon carbide substrate. With the associated surface processing, which is a combination of chemical etching and mechanical planarization, this process step makes it possible to remove a thin layer of surface material (on the order of a few hundred nanometers starting from the surface of the epitaxial layer), thus making the surface of the epitaxial layer substantially free of pits. Since the aforementioned layer of surface material is removed, the pits produced as a result of the propagation of TSDs are substantially completely removed.

[0030] REFERENCE Figure 3 A process for manufacturing a generic silicon carbide semiconductor device, such as a power device (such as a diode or a MOSFET), is now described.

[0031] As indicated at step 10, the process first envisages providing a wafer 21 of silicon carbide (in particular, 4H-SiC) comprising a substrate 22 (which is schematically illustrated in Figure 4A ). Next (step 11), epitaxial growth is carried out, for example with chemical vapor deposition (CVD), for forming an epitaxial layer 23 (of 4H-SiC again) on the substrate 22, the epitaxial layer 23 having a top surface 23a.

[0032] As previously discussed, during the epitaxial growth, defects (in particular, TSDs) can propagate from the substrate 22 towards the covering epitaxial layer 23, producing surface pits 25 on the top surface 23a thereof, which can for example have a diameter of some nanometers (for example, less than 30 nm). Figure 4A

[0033] ​According to one aspect of the present solution, the manufacturing process envisages, after (and in particular immediately after) the aforesaid epitaxial growth step, an additional step of so-called "soft" chemical-mechanical polishing (CMP) (indicated in Figure 3 the figure by 14) of the top surface 23a of the epitaxial layer 23 formed on the substrate 22.

[0034] As indicated again Figure 3 , the CMP process is preceded by a step of cleaning the surface of the wafer (indicated by 15), in particular the top surface 23a of the aforesaid epitaxial layer 23; for example, cleaning is obtained via a water jet at high pressure and via drying of the surface by sample rotation, or alternatively via the use of chemical agents such as HF, NH4OH, H2O2, HC1.

[0035] As schematically illustrated in Figure 4B , the CMP process, via the combined action of chemistry and mechanics, causes the removal of a thin surface layer of the epitaxial layer 23 starting from the top surface 23a of the epitaxial layer 23, thus removing the surface pits 25 deriving from the propagation of the TSDs 24, thus making the resulting top surface of the epitaxial layer 23 (indicated by 23a') substantially flat and defect-free.

[0036] In detail, the thickness of the surface layer removed (considered in the direction orthogonal to the aforesaid top surface 23a) can be comprised between 100 nm and 500 nm, for example 300 nm, as previously mentioned, it is in any case sufficient to remove the surface pits 25, possibly completely.

[0037] As will be clear, the actual thickness of the surface layer removed will result from a compromise between the desire to remove as little material as possible (thus optimizing the time and costs of the manufacturing process) and at the same time guaranteeing the thorough removal of the surface defects. The Applicant has found that the removal of a layer of 100 nm thickness can generally be sufficient to make the top surface 23a' resulting from the CMP process uniform. However, it can be convenient to remove greater thicknesses, for example 300 nm, in order to have a greater certainty of obtaining the desired result.

[0038] In any case, the CMP process has the further advantage of reducing the surface roughness of the aforesaid resulting top surface 23a' of the epitaxial layer 23.

[0039] In this regard, it is known that the typical roughness measured on the top surface of the epitaxial layer (generally indicated as parameter Rq) is variable between 0.1 nm and 1 nm; moreover, a phenomenon known as "step bunching" often occurs, i.e. the formation of surface steps, which is substantially due to the CVD epitaxial growth on "off-axis" substrates.

[0040] The Applicant has found that the aforementioned CMP process makes it possible to significantly reduce the roughness values of the resulting top surface 23a', in which the value of the Rq parameter is even less than 0.1 nm (i.e. a value comparable to the noise of the instrument used for detecting the same thickness), and moreover the aforementioned CMP process makes it possible to completely eliminate the step bunching phenomenon.

[0041] In general, after the CMP process, the resulting top surface 23a' is optimized and ready for subsequent chemical and / or mechanical processing steps, which can be envisaged for the manufacture of electronic devices (for example power devices, such as diodes or MOSFETs).

[0042] In this regard, with reference again to Figure 3 After the aforementioned CMP process, the manufacturing process envisages a step designated by 16: cleaning of the resulting top surface 23a' of the epitaxial layer (in particular via C6H8O7 and H2O2), and subsequent standard oxidation process of the same resulting top surface 23a' to form an oxide layer on the epitaxial layer 23.

[0043] Advantageously, the physical / chemical properties of the oxide layer formed are optimized thanks to the absence of defects and the low roughness of the starting surface (the aforementioned resulting top surface 23a').

[0044] As generally indicated at step 18, the manufacturing process can then proceed with the processing operations necessary or otherwise desirable for forming the desired power device (known and not described in detail herein), for example steps for the formation and definition of conductive layers for providing electrodes, steps for the formation of passivation layers, etc.

[0045] It will thus be noted that the proposed solution is quite different from the existing solutions, since an additional CMP process step (with standard preliminary cleaning and subsequent dedicated cleaning) is envisaged, thus not involving a substantial increase in terms of cost or time of the manufacturing process.

[0046] Moreover, the Applicant has found that the CMP process can be suitably configured (in particular in terms of process parameters and in terms of consumables used), so that the same CMP process does not cause defects such as scratches, etc. on the resulting top surface 23a' of the epitaxial layer 23.

[0047] In this regard, Figure 5 A system 30 for implementing the CMP process on a silicon carbide wafer (again designated by 21) which has undergone the step of epitaxial growth for forming the epitaxial layer 23 on the corresponding substrate 22 is shown.

[0048] In particular, the system 30 comprises a polishing pad 32 carried by a rotating support 33 which is caused to rotate at a certain speed; the wafer 21 is arranged in contact with the polishing pad 32 by means of a support head 34 which is attached to the support head 34 by means of a fixing layer 35; the support head 34, in addition to rotating about its rotation axis, also exerts a force to press the wafer 21 against the polishing pad 32.

[0049] A polishing agent (so-called "slurry") 36 is caused to flow over the surface of the polishing pad 32, so as to come into contact with the wafer 21 due to the rotation of the same polishing pad 32, so as to grind its surface and cause it to be chemically etched.

[0050] Furthermore, a conditioning pad 37 which is supported in a cantilevered manner above the surface of the polishing pad 32 carries out cleaning of the polishing pad 32, so as to clean it from residues which can be trapped on its surface and thus prevent any scratches of the wafer 21.

[0051] The Applicant has experimentally found that, using a particle-free polishing agent 35 having a pH < 5, it is possible to achieve better electrical and physical characteristics after the CMP process.

[0052] Furthermore, it has been found that it is optimal for the pressure P exerted by the support head 34 on the polishing pad 32 to be comprised between 1 psi and 3 psi, as well as for the temperature T of the CMP process to be lower than 50°C.

[0053] Furthermore, the Applicant has found that it is advantageous to use one or more of the following further parameters of the CMP process: the rotation rate of the polishing pad 32 is less than 70 rpm; the rotation rate of the support head 34 is less than 60 rpm; the thrust of the conditioning pad 37 on the polishing pad is approximately 6 lbf (i.e. about 3 kgf); the flow rate of the polishing agent 36 is less than 100 ml / min.

[0054] From the foregoing description, the advantages of the proposed solution emerge clearly.

[0055] In any case, it is emphasized that, by introducing the CMP process step after the epitaxial growth, the described process makes it possible to remove surface defects and thus to enable an optimized preparation of the resulting top surface of the wafer for the subsequent processing operations for manufacturing a semiconductor device (for example, to enable an increase in the robustness of the oxide layer grown subsequently on the epitaxial layer).

[0056] In particular, the aforementioned CMP process makes it possible to eliminate surface pits generated due to the propagation of dislocations from the substrate during the step of epitaxial growth. Moreover, the CMP process also has the further advantage of reducing the surface roughness and, in particular, the so-called step bunching phenomenon. As mentioned previously, the surface roughness of the top surface 23a' obtained after CMP has a low value, in particular wherein the value of the Rq parameter is less than 0.5 nm, preferably less than 0.2 nm, and even more preferably less than 0.1 nm.

[0057] Moreover, advantageously, as discussed previously and as demonstrated by the experimental tests carried out by the Applicant, the aforementioned CMP process can be configured so as not to cause scratches or surface defects.

[0058] The present solution thus makes it possible to increase the electrical yield associated with the manufacturing process, to save manufacturing costs, and moreover to save area.

[0059] Finally, it is clear that modifications and changes can be made to what is described and illustrated herein, without thereby departing from the scope of the present application as defined in the appended claims.

[0060] In particular, it is emphasized that the described process can find advantageous application for any device (diode, MOSFET, etc.) obtained starting from a silicon carbide (SiC) substrate, on which epitaxial growth is carried out during the processing steps envisaged for manufacturing the same device.

[0061] A process for manufacturing a silicon carbide semiconductor device can be summarized as comprising:

[0062] providing a silicon carbide wafer (21) having a substrate (22); and

[0063] carrying out epitaxial growth for forming an epitaxial layer (23) having a top surface (23a) on the substrate (22), during which propagation of dislocations (24) from the substrate (22) towards the top surface (23a) occurs, thus forming surface damage; and

[0064] subsequent to the step of carrying out epitaxial growth: removing a surface portion of the epitaxial layer (23) starting from the top surface (23a), thus removing the surface damage at the top surface (23a) and defining a resulting top surface (23a') substantially free of defects.

[0065] The surface damage can be pits (25) generated due to the propagation of dislocations (24) from the substrate (22) towards the top surface (23a) during the epitaxial growth.

[0066] The removed surface portion of the epitaxial layer (23) can have a thickness comprised between 100 nm and 500 nm.

[0067] The thickness can be equal to 300 nm.

[0068] The step of removing can comprise a step of Chemical Mechanical Polishing - CMP - carried out on the top surface (23a) of the epitaxial layer (23).

[0069] The CMP step can be carried out using a polishing agent (36) which is particle-free and has a pH lower than 5. During the CMP step, the wafer (21) can be pressed against the polishing pad (32) by the support head (34) with a pressure (P) comprised between 1 psi and 3 psi.

[0070] Furthermore, the CMP step can be carried out with one or more of the following parameters: rotation rate of the polishing pad (32) < 70 rpm; rotation rate of the support head (34) < 60 rpm; thrust of the support head (34) against the polishing pad (32) of about 3 kgf; flow rate of the polishing agent (36) < 100 ml / min.

[0071] The CMP step can be carried out at a temperature (T) lower than 50 °C.

[0072] The process can further comprise, before the CMP step, cleaning the top surface (23a) of the epitaxial layer (23); and furthermore, after the CMP step, subjecting the resulting top surface (23a') to a dedicated washing; wherein, after the CMP step and the dedicated washing, the resulting top surface (23a') has a roughness (Rq) value lower than 0.1 nm.

[0073] The epitaxial growth can be carried out with Chemical Vapour Deposition - CVD.

[0074] The epitaxial layer (23) can be made of 4H-SiC.

[0075] The process can further comprise, after the step of removing a surface portion of the epitaxial layer (23), starting from the resulting top surface (23a') carrying out further processing operations to form the semiconductor device.

[0076] The semiconductor device can be an electronic power device.

[0077] The electronic power device can be a diode or a MOSFET.

[0078] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all embodiments falling within the scope of the claims and their equivalents. Accordingly, the claims are not limited to the above described embodiments.

Claims

1. A method for manufacturing a silicon carbide semiconductor device, comprising: A silicon carbide wafer is provided, the silicon carbide wafer having a substrate; Epitaxial growth is performed to form an epitaxial layer on the substrate using a homoepitaxial process. The epitaxial layer has a top surface. During the epitaxial growth, dislocations propagate from the substrate toward the top surface, thus causing surface damage. as well as Following the epitaxial growth, the surface portion of the epitaxial layer is removed starting from the top surface, thereby removing the surface damage at the top surface and defining a substantially defect-free top surface. The surface damage described therein is a pit, which is caused by the propagation of the dislocation from the substrate toward the top surface during the epitaxial growth. The removal of the surface portion of the epitaxial layer includes: performing chemical mechanical polishing (CMP) on the top surface of the epitaxial layer; The CMP is performed using a polishing agent that is free of particles and has a pH below 5.

2. The method of claim 1, wherein the removed surface portion of the epitaxial layer has a thickness between 100 nm and 500 nm.

3. The method according to claim 2, wherein the thickness is equal to 300 nm.

4. The method of claim 1, wherein during the CMP, the wafer is pressed against a polishing pad by a support head using a pressure between 1 psi and 3 psi.

5. The method of claim 4, wherein the CMP is performed using one or more of the following parameters: the rotational speed of the polishing pad is <70 rpm; the rotational speed of the support head is <60 rpm; the thrust of the support head on the polishing pad is 3 kgf; and the flow rate of the polishing agent is <100 ml / min.

6. The method of claim 1, wherein the CMP is performed at a temperature below 50°C.

7. The method according to claim 1, further comprising: Before the CMP, the top surface of the epitaxial layer is cleaned; as well as Following the CMP, the resulting top surface is cleaned. After the CMP step and the cleaning, the resulting top surface has a roughness value of less than 0.1 nm.

8. The method of claim 1, wherein the epitaxial growth is performed using chemical vapor deposition (CVD).

9. The method according to claim 1, wherein the epitaxial layer is made of 4H-SiC.

10. The method according to claim 1, further comprising: After removing the surface portion of the epitaxial layer, further processing operations are performed starting from the resulting top surface to form the semiconductor device.

11. The method of claim 1, wherein the semiconductor device is an electronic power device.

12. The method of claim 11, wherein the electronic power device is a diode or a MOSFET.

13. A method comprising: An epitaxial layer is formed on a silicon carbide substrate using a homoepitaxial process, wherein a through-spiral dislocation defect in the substrate extends through the epitaxial layer and forms a pit on the surface of the epitaxial layer, the pit having a diameter of less than 30 nm. as well as The pits at the surface of the epitaxial layer are removed by performing chemical mechanical polishing (CMP) to remove the surface portion of the epitaxial layer, thereby defining a substantially defect-free top surface of the epitaxial layer. The CMP is performed using a polishing agent that is free of particles and has a pH below 5.

14. The method of claim 13, wherein the CMP is performed using the following parameters: the rotational speed of the polishing pad is <70 rpm; the rotational speed of the support head is <60 rpm; the thrust of the support head on the polishing pad is 3 kgf; and the flow rate of the polishing agent is <100 ml / min.

15. A method comprising: An epitaxial layer is formed on a silicon carbide substrate using a homoepitaxial process, wherein a through-spiral dislocation defect in the substrate extends through the epitaxial layer and forms a pit on the surface of the epitaxial layer, the pit having a diameter of less than 30 nm. The pits at the surface of the epitaxial layer are removed by performing chemical mechanical polishing (CMP) to remove the surface portion of the epitaxial layer, thereby defining a substantially defect-free top surface of the epitaxial layer, wherein the CMP is performed using a polishing agent that is free of particles and has a pH below 5; as well as The cleaned top surface, The top surface obtained after the cleaning process has a roughness value of less than 0.1 nm.

16. The method of claim 15, further comprising: Following the cleaning of the top surface, an oxide layer is formed on the top surface of the epitaxial layer.

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