Silicon on patterned insulator wafer

Abstract

A wafer structure is disclosed comprising a top silicon layer with a polished surface, an oxide layer selectively removed in defined regions, and a bottom silicon layer. Selective oxide removal improves dicing, prevents small molecule ingress, and enhances MEMS device release and performance. The invention addresses challenges of conventional silicon-on-insulator (SOI) wafers, including jagged edges, particle generation during stealth dicing, slow and uncontrolled under-etch rates, and high resistive losses in radio frequency (RF) applications due to parasitic surface conduction. Patterning the oxide layer enables precise MEMS structure release, reduces die size, and improves RF isolation. The wafer structure is suitable for high-speed electronics, RF analog circuits, and MEMS devices such as resonators, accelerometers, and waveguides, offering improved manufacturability and device reliability.

Description

SILICON ON PATTERNED INSULATOR WAFERCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 708,725, filed on October 17, 2024, the disclosure of which is incorporated herein by reference in its entirety.BACKGROUND

[0002] An oscillator may be a circuit that generates an oscillating electronic signal, typically a periodic waveform such as a sine wave or square wave. The output frequency of an oscillator may be controlled by a resonator. Oscillators are components in various electronic devices, for example, generating clock signals for digital systems.SA1095-PCTBRIEF DESCRIPTION OF THE DRAWINGS

[0003] The drawings illustrate embodiments of the present disclosure and are provided for the purposes of illustration and discussion of the principles and conceptual aspects of the technology. The embodiments depicted in the drawings are intended to illustrate, rather than limit, the scope of the disclosure Similar or identical reference numbers are used to identify similar or identical elements in the various drawings and descriptions. In the accompanying drawings:

[0004] FIG. 1 shows SOI wafer variations, according to some embodiments.

[0005] FIGS. 3 and 4 illustrate stealth dicing, according to various embodiments.

[0006] FIGS. 4 depicts an SOI wafer fabrication process, in accordance with some embodiments.

[0007] FIGS. 5 presents an etch process, in accordance with various embodiments.

[0008] FIGS. 6-8 show cantilever structures, according to some embodiments.

[0009] FIG. 9 illustrates a waveguide, according to various embodiments.

[0010] FIG. 10 depicts SOI wafers, in accordance with some embodiments.

[0011] FIGS. 11 presents SOPI wafers, in accordance with various embodiments.- 2 - SA1095-PCTDETAILED DESCRIPTION

[0012] While this technology is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail several specific embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the technology and is not intended to limit the technology to the embodiments illustrated. It is understood that non-stoichiometric forms of the compounds disclosed herein may be used.

[0013] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0014] In this application, the terms “and / or,” “at least one of,” and “one or more of’ include all combinations (and, depending on context, permutations) of the specified elements. For example, “A, B, and / or C” is understood to mean only A, only B, only C, A and B, A and C, B and C, or A, B, and C. The same interpretation applies to “at least one of A, B, and C” and “one or more of A, B, and C.” There may be any number of elements (e g., A, B, C, and D; A, B, C, D, and E; etc ).

[0015] It is understood that like or analogous elements and / or components, referred to herein, may be identified throughout tire drawings with like reference characters. It is further understood that several of the figures are merely schematic representations of the present technology. As such, some of the components may have been distorted from their actual scale for pictorial clarity Moreover, various combinations of the structures, components, materials, and / or elements, other than those specifically shown, are contemplated and are within the scope of the present technology.OVERVIEW

[0016] A silicon-on-insulator (SOI) wafer may be a type of semiconductor substrate comprising a thin layer of monocn stalline silicon (device layer) separated from a bulk silicon handle wafer by an insulating layer. The insulating layer, commonly referred to as the buried oxide (BOX) layer, may be composed of silicon dioxide ( SiO: ). The device layer may include a polished surface suitable for microfabrication processes such as lithography, etching, and thin-film deposition. SOI wafers may be used for high-speed electronics and radio frequency (RF) analog circuits. These substrates can also be used for microelectromechanical systems (MEMS) devices, such as accelerometers, gyroscopes, microphones, resonators, and tire like.

[0017] The present technology may address issues that arise when using SOI wafers for MEMS devices, such as: jagged edges, particles, and the like from stealth dicing; ingress of small-molecule gasses (e.g., helium (He) and hydrogen (Hi)) along BOX-silicon interfaces; long structure release time due to a slow etch rate (e g , 0.2 pm / minute - 3 pm / minute) during removal of the BOX layer — which acts as a sacrificial layer to release a MEMS device — such as by using vapor hydrogen fluoride (HF) etch or wet HF etch; uncontrolled under-etch distance; high resistive losses of RF signals even when using a high-resistivity (e.g , very low doped silicon)- 3 - SA1095-PCThandle wafer due to the parasitic surface conduction (PSC) effect at the BOX-silicon interface; and the like.

[0018] In the context of the present disclosure, a resonator refers to a structure or device configured to oscillate at a specific frequency when excited by an external stimulus. Resonators are commonly employed in timing, sensing, filtering, and signal processing applications, and may utilize various physical transduction mechanisms to convert electrical energy into mechanical motion and vice versa.SOI WAFERS

[0019] FIG. 1 illustrates SOI wafer variations 100A-D, according to some embodiments. SOI wafer variations 100A-D may include device silicon layer 110, buried oxide layer (BOX) layer 120, handle wafer 130 (e.g , on the order of 725 pm thick for 200 mm wafers) For high-speed semiconductor devices (e.g., > 1 GHz), the device layer (110) may be very thin (e.g., on the order of 0.1 pm to 2 pm), whereas for MEMS devices thicknesses up to 100 pm may be used. In some cases, the backside of SOI wafer 100 may have oxide layer 140. Oxide layer 140 may include silicon dioxide (SiOj), silicon nitride (SiN), and / or tire like.STEALTH DICING

[0020] An SOI BOX layer may interfere with the stealth dicing process. FIG. 2 shows stealth dicing of SOI wafers before 200A and after expansion 200B, according to various embodiments. During stealth dicing, a high-power optical laser may focus light 230 inside tire SOI wafer 210 to weaken the atomic bonds and create a very localized amorphous silicon layer The wafer may be scanned by the laser horizontally and vertically with a defined step-size. After stealth dicing, the wafer may be expanded, leading to the singulation of chips, without having to use a mechanical dicing saw. However, depending on the thickness of the BOX layer and / or the thickness of the device layer, problems may arise.

[0021] During expansion, BOX layer 290 (e.g., comprising brittle silicon dioxide) may shatter and create particles and jagged edges 280 along the die perimeter. This results from the stealth dicing laser not being absorbed by BOX layer 290 and hence the bonds in BOX layer 290 do not break

[0022] The stealth dicing process may use the silicon layer optically to focus the laser and achieve very localized heating of the silicon substrate for breaking the bonds. As silicon has a very' high dielectric constant and related optical refractive index, it may strongly participate in the focusing of the light. However, BOX layer 290 (e.g., including silicon dioxide with a low refractive index) may perturb the focus, leading to imperfect focus and absorption of optical energy by the device layer and handle wafer during dicing

[0023] Alternatively, the laser dosage for SOI wafers may be introduced from the wafer backside. MEMS wafers may have released frail / sensitive structures, so a chuck may support these frail / sensitive structures, or a laminated protective tape may be laminated to the MEMS wafer to prevent damage. Removal of the laminated protective tape may damage the MEMS die and cause quality issues. The chuck may abrade the surface of tire SOI wafer, causing damage to the device

[0024] FIG. 3 depicts stealth dicing of a Silicon on Patterned Insulator (SOPI) wafer before 300A and after expansion 300B, in some embodiments. As shown, the BOX layer of SOPI wafer 310 may be patterned to remove the BOX layer from the dicing lines, so that the BOX layer does not interfere with the stealth dicing- 4 - SA1095-PCTlaser. The patterned BOX layer — because it does not protrude 370 into the dicing lane — may contribute to very' smooth die edges 380. In this way, SOPI wafer 310 advantageously does not have a jagged protrusions 270 outside of the die of SOI wafer 210 (FIG. 2) because BOX layer 390 has been removed in the respective region and no particles are generated.SMALL MOLECULE DIFFUSION

[0025] Referring back to FIG. 2, small molecules (e.g., hydrogen gas (Hj) and helium gas (He)) may diffuse along the BOX-silicon interface. This can lead to the loss of vacuum in encapsulated MEMS devices and / or a shift in device performance (e g., the resonance frequency of a MEMS device inside the cavity, degradation of the quality factor of a resonating device inside a vacuum cavity, and the like) Small molecule ingress may cause the MEMS structure to collide with the gas molecules, leading to energy being lost and resulting in a reduction in the quality factor Moreover, the resonance frequency may shift due to the gas molecules becoming attached to the structure. This may cause drift or frequency noise over temperature (or even at a constant temperature) as the gas molecules detach / re-attach

[0026] Referring back to FIG. 3, SOPI wafer 310 may advantageously avoid small molecule diffusion, because the BOX layer of SOPI wafer 310 does not protrude into the dicing lanes. Since helium and hydrogen are not able to penetrate silicon, they do not reach the BOX-silicon interface.BOX LAYER UNDER-ETCH CONTROL

[0027] A reason SOI wafers are popular in manufacturing MEMS devices is the ability to use the BOX layer as a sacrificial etch layer. This process typically has two main features. Firstly, the BOX layer consisting of silicon dioxide can be etched in hydrofluoric (HF) acid or in vapor HF, with very high selectivity against silicon Even prolonged exposure to the HF etchant may not alter the silicon structure Secondly, the device layer may be high quality single crystal silicon. Single crystal silicon’s material properties may be well understood such that for a given geometry the resulting properties of a device may be highly reproducible. Moreover, silicon may have very low material losses and be easy to structure (e.g., with deep reactive ion etching (DRIE)). However, using SOI wafers also has challenges.

[0028] FIG. 4 depicts an example fabrication process 400 for SOI wafer 210 (FIG. 2) on the left side and SOPI wafer 310 (FIG. 3) on the right side, in various embodiments. Process 400 is provided by way of example and not limitation to illustrate the under-etch challenge of releasing a MEMS structure when using the BOX layer as a sacrificial layer. At 401 an SOI wafer 210 with an unpattemed BOX layer 420-1 and / or a SOPI wafer 310 with patterned BOX layer 420-2 may be received.

[0029] At 402, the device silicon layer may be etched (e.g , with DRIE, anisotropic wet etching, ion-beam milling, and / or any other suitable technique). As a result, in one or more areas 440 the BOX layer is now exposed. At 403, the BOX layer may be etched 460 (e.g., with hydrofluoric acid (HF), vapor HF (VHF), and / or any other suitable technique).

[0030] In the case of SOT wafer 210, the BOX layer is continuous and hence the etching must be interrupted, or the entire BOX layer will be removed For SOPI wafer 310, the etching may be self-terminating- 5 - SA1095-PCTas soon as the entire BOX layer is consumed. The disadvantage of SOI wafer 210 is that the under-etch distance is related to the process time, as well as the etch rate, which depends on many parameters. Example parameters for HF or VHF etching may include at least one of: etch time, temperature, concentration of etchant, depletion of etchant, spiking (e.g., adding fresh etchant ), concentration of water in the etchant, pressure, and the like.

[0031] When, for example, a cantilever beam is created at 404 using SOI wafer 210, anchor point 490 of the cantilever 480 defined by the etch progression may be very uncertain. The effective mechanical length of the cantilever may depend on the etch time control and the etch rate, that depend on a multitude of factors as described above. The resonance frequency of the cantilever may be proportional to length2, which means that the resonance frequency of the structure fabricated using SOI wafer 210 may exhibit a large spread in frequency, directly related to the uncertainty of the cantilever length, arising from the etch rate variation. In contrast, the resonance frequency distribution can advantageously be very tightly controlled when SOPI wafer 310 used.

[0032] Another disadvantage of using SOI wafer 210 (FIG. 2) is that tire under-etch occurs not only under the structure that is to be released, but also all around it, as the BOX layer is unbounded. Accordingly, the die size must be large enough to avoid the under-etch removing oxide under the future dicing lane. By comparison, SOPI wafer 310 allows the die size to be much smaller, leading to more dice per wafer and lower die cost. In addition to the die size growing to maintain the BOX layer around the die perimeter, the die size further increases when probe-pads are part of the design. With the BOX layer being etched away under the probe-pad areas, the probe force can crack, deflect, and / or penetrate the silicon layer. Accordingly, probe pads are pulled far away from released areas, further leading to an increase in the die size on SOI wafer 210.BOX EAYER UNDER-ETCH RATE

[0033] Although the buried oxide layer in SOI wafer 210 is suitable as a sacrificial layer, the etch rate of silicon dioxide is low (e.g., typically on tire order of 0.2 pm / minute - 0.6 pm / minute for vapor phase etching and 1 pm / minute - 3 pm / minute for HF wet etching). MEMS structures may be fragile upon release. Devices may not be released using wet chemical etching, because during the drying process, the receding liquid may contribute to excessive capillary forces that cause structures to crack, break, deform, or be permanently stuck.

[0034] As a non-limiting example, a cantilever that is 200 pm long and 40 pm wide, may use 20 pm of etching from each side. At an etch rate of 0.2 pm / minute, and including a 20% over etch, to account for fluctuations in the etch rate, will take 2 hours. In order to improve the through-put of these tools, and therefore in order to reduce the required release time, etch holes may be used.

[0035] FIG. 5 illustrates etch process 500, according to some embodiments. In order to release the cantilever etched into the device silicon of tire SOI wafer 510, the BOX layer is exposed with the opening 520. After a time tl, the cantilever is under-etched 540. However, the etch duration may be insufficient to completely release the cantilever. At a longer etch time t2, a larger under-etch 550 can lead to the cantilever now being fully released

[0036] The total etch time may be improved by adding etch holes 530 shown in the right column of FIG. 5. Under-etching from the center of the cantilever using etch holes 530 may effectively reduce the total time to release the structure by a factor of two. The amount of under-etch 545 and final under-etch 555 after full release- 6 - SA1095-PCTmay be smaller than under-etch 550 and hence may be better controlled than under-etch 550 However, etch holes 530 may negatively affect the device performance.

[0037] FIGS. 6 and 7 show a top view of cantilever structure 600 for SOI wafer 210 and 700 for SOPI wafer 310, according to various embodiments. In cantilever structure 600, under-etch 550 may be unbounded and only a result of the etch rate and etch duration. In contrast, the release area 750 is well-defined in cantilever structure 700 The total etch time for both under-etch 550 and 750 may be roughly the same. In order to shorten the release time, the patterned BOX layer 730 may be segmented as shown in FIG. 8.

[0038] FIG. 8 depicts a top view of cantilever structure 800, in some embodiments. As shown in FIG. 8, the BOX layer may be separated into strips 830, in contrast to a continuous SOI BOX layer 120. The separation may allow the etchant access in betw een spaces 820 betw een strips 830. The total etch time may now be determined as a function of the width of the strips 830, rather than from dimensions of the structure to be released. Furthermore, etch holes may not be needed to shorten the release process.

[0039] By way of example and not limitation, a cantilever may serve as a resonating structure. A resonating structure may include, but is not limited to, microelectromechanical systems (MEMS) resonators configured to operate via various transduction mechanisms. It is understood that the cantilever may function as an electrostatic and / or piezoelectric resonator. Other suitable resonating structures may employ electrostatic, piezoelectric, electrostrictive, magnetic, thermal, or similar transduction modalities. Embodiments are not limited to cantilevers and may encompass a wide range of MEMS-based resonators designed to achieve desired frequency response characteristics.RADIO FREQUENCY PERFORMANCE

[0040] For high-frequency applications (e.g., RF circuitry; RF filters based on FBAR, SMR, I.H.P., and SAW; coplanar waveguides; monolithic strip-line filters, high-frequency resonators for timing applications, and the like) high isolation between input and output connections may be required. High resistive substrates (e.g., > 500 Ohm-cm) may be used to limit signal leakage through the high resistive wafer substrate. A dielectric layer — like the BOX layer (e.g., silicon dioxide (SiOz), silicon nitride (SiN), aluminum nitride (AIN), and the like) — in contact with a high resistive silicon surface may lead to parasitic surface conduction (PSC). PSC may effectively be a thin conductive layer at the dielectric / silicon interface that is caused by fixed trapped charges in the dielectric that attract free carriers in the high-resistivity silicon. This is a significant downside of conventional SOI wafers (e.g., SOI wafer 210).

[0041] FIG. 9 depicts cross-sections 901 A, 901B, 902A, and 902B of a Ground- Signal-Ground (GSG ) coplanar waveguide View 901A may be on glass 910 and views 901B, 902A, and 902B may be on high-resistive silicon 912. Metal 920 may be directly deposited onto glass 910 and / or high-resistive silicon 912. Capacitance 960 through substrate 910 and 912 may be formed In the case of high-resistive silicon 912 the resistivity may be very high (e.g., at least 1000 Ohm-cm or even 10,000 Ohm-cm).

[0042] In contrast to directly depositing metal RF stripline 920 on high resistive silicon 912 as in view' 901B, a dielectric layer separates the metal from the high resistive silicon in view 902A. Here, high resistive silicon substrate 912 may no longer function as a low-loss dielectric, but includes a large resistive loss. This loss may be due to PSC layer 932, the unwanted parasitic surface conduction that may arise from trapped- 7 - SA1095-PCTcharges in dielectric layer 930, attracting free carriers in the high resistive silicon and leading to a conductive layer at the interface of dielectric and silicon. As a result, RF stripline 920 may no longer be low loss and instead include resistor 950 in the equivalent circuit model. In addition to capacitance 960 through the silicon substrate in view 901B, there may be capacitances 940 from dielectric 930 to the PSC. Capacitance 940 in series with capacitance 960 may be negligible, but the loss from resistor 950 may lower performance.

[0043] Resistive losses originating from the PSC, such as resistor 950, may lower performance of RF devices fabricated on high resistive silicon. Dielectric layers cannot be avoided, in part because they may be needed to allow' metal lines to cross each other w'ithout shorting for routing purposes.

[0044] View 902B shows the dielectric in contact with the high resistive substrate in area 935 etched away to prevent the resistive losses. Here, the PSC may no longer be continuous between the Ground and Signal lines. The equivalent circuit may include capacitance 960 but no longer have resistor 950

[0045] FIG. 10 depicts SOI wafer 1000, in various embodiments. SOI wafer 1000 may include silicon pads with RF signals (silicon structures 1020). Challenges associated with the fabrication of metal RF structures described above in FIG. 9, may also occur with SOI wafer 210A in views 1001 A and 1001B. In some embodiments, metal may be deposited on silicon 1020 (not showm in FIG. 10), but the examples and analysis herein may still apply.

[0046] View 1001 A depicts an SOI wafer 210A where the device layer has been patterned and is carrying different RF signals. The PSC may be formed at the BOX-silicon handle wafer interface. Although the silicon handle wafer of SOI wafer 210A may have high resistivity (e.g., effectively an insulator), the PSC introduces a relatively low resistance resistor 950 which acts a conductive path. The BOX layer may be etched, so that the PSC layer at the interface of BOX-silicon is separated with cut 1025.

[0047] Advantageously, SOPI wafer 310A shown in view' 1101A includes a patterned silicon oxide layer to begin w ith, which has built-in separation 1030. While the PSC may also exist w ithin SOPI wafer 310A, the built-in separation 1030 inherently avoids the resistor 950 in view 1101B.

[0048] FIG. 11 shows SOPI wafers 1201A and 1201B having a strong doping 1040 applied to the device layer 1022. Strong doping 1040 of the device layer may lead to dopant entering through gap 1030 in the BOX layer 930, as shown in view 1201 A. The doping in gap 1030 may electrically connect the PSC layer 932 from one side of gap to the other side, connection 1050. This contributes to significant RF losses. Silicon etching (e.g , deep-reactive ion etching or any other suitable technique) may be used to etch into the handle wafer to level or depth where the dopant levels from the surface doping are low (e.g., < 1E14 cm'3), such that the high resistivity of the silicon handle wafer does not lead to an electrically conductive path 1050 and a purely capacitive element 930 arises

[0049] The SOI wafer having a patterned BOX layer as described herein may be designed for one or more of a particular die size, particular pad configuration, particular sacrificial layer dimensions, and the like.- 8 - SA1095-PCT

Claims

CLAIMSWhat is claimed is:

1. A wafer comprising : a top silicon layer having a polished surface; an oxide layer coupled to the top silicon layer and having an area selectively removed; and a bottom silicon layer coupled to the oxide layer2. The wafer of claim 1 wherein the selectively removed area includes an area used for dicing.

3. The wafer of claim 2 wherein the selectively removed area prevents small molecule ingress.

4. The wafer of claim 1 wherein selectively removed area is below a structure to be released.

5. The wafer of claim 1 wherein the selectively removed area is smaller than a lateral undercut.- 9 - SA1095-PCT

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