Semiconductor memory device

Abstract

A semiconductor memory device according to the inventive concept includes a semiconductor base; a common-source semiconductor layer doped with impurities of a first conductivity type located on the semiconductor base; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common-source semiconductor layer; a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering inner walls of a channel hole extending in a vertical direction; and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer on which the memory cell dielectric layer is disposed, the channel layer filling at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling a portion of an upper portion of the channel hole.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0129507, filed on October 7, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a semiconductor memory device, and more specifically, to a capacitor-free semiconductor memory device. Background Technology

[0003] With the rapid development of the electronics industry and the increasing demand from users for high-performance electronic systems, electronic devices have become more compact and lightweight. Therefore, semiconductor devices, as key components of electronic devices, need to have high integration and high capacity.

[0004] In semiconductor memory devices, dynamic random access memory (DRAM) devices include capacitors, but there are limitations on high integration because it is difficult to reduce the capacitance of the capacitors in order to perform memory functions. Summary of the Invention

[0005] The present invention provides a capacitor-free semiconductor memory device that can be highly integrated.

[0006] The present invention provides a semiconductor memory device as follows. An embodiment of the semiconductor memory device according to the present invention includes: a semiconductor substrate; a common-source semiconductor layer doped with impurities of a first conductivity type and disposed on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common-source semiconductor layer; a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering the inner wall of a vertically extending channel via; and a memory cell structure filling the channel via, wherein the memory cell structure includes a channel layer and a drain layer, the memory cell dielectric layer is disposed on the channel layer, the channel layer fills at least a portion of the channel via, and the drain layer covers the upper surface of the channel layer, is doped with impurities of a second conductivity type, and fills a portion of the upper part of the channel via, and the memory cell dielectric layer includes a gate insulating layer covering the inner wall of the channel via and a charge trapping layer disposed between the gate insulating layer and the channel layer.

[0007] A semiconductor memory device according to an embodiment of the present invention includes: a semiconductor substrate; a plurality of memory cell structures, each memory cell structure including a cell source layer, a channel layer, and a drain layer sequentially stacked from the semiconductor substrate in a vertical direction, and each memory cell structure having a vertical pillar shape extending in the vertical direction; a plurality of word line structures, separated from each other in the vertical direction and surrounding the plurality of memory cell structures; a plurality of memory cell dielectric layers, each memory cell dielectric layer being disposed between the channel layer of each memory cell structure in the plurality of memory cell structures and the plurality of word line structures; and a plurality of bit lines, each bit line being electrically connected to the drain layer of each memory cell structure in the plurality of memory cell structures, extending in a first horizontal direction on the plurality of word line structures, and having a certain distance from each other in a second horizontal direction orthogonal to the first horizontal direction, wherein the drain layer is doped with an impurity of a first conductivity type, the cell source layer is doped with an impurity of a second conductivity type different from the first conductivity type, and each memory cell dielectric layer in the plurality of memory cell dielectric layers includes a gate insulating layer covering the plurality of word line structures and a charge trapping layer disposed between the gate insulating layer and the channel layer.

[0008] A semiconductor memory device according to an embodiment of the present invention includes: a semiconductor substrate; an etch stop layer disposed on the semiconductor substrate; a common-source semiconductor layer doped with an impurity of a first conductivity type and disposed on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common-source semiconductor layer; a memory cell dielectric layer including a gate insulating layer and a charge trapping layer sequentially covering the inner walls of each of a plurality of channel holes, the plurality of channel holes penetrating the plurality of insulating layers, the plurality of word line structures and the etch stop layer in a vertical direction and extending into the semiconductor substrate; a plurality of memory cell structures, each memory cell structure including a filling semiconductor layer, a channel layer and a drain layer, wherein a barrier insulating layer positioned separately from the memory cell dielectric layer is disposed on the filling semiconductor layer. A fill semiconductor layer fills a portion of the lower part of each of the plurality of channel vias, and a memory cell dielectric layer is disposed on the channel layer. The channel layer is separate from the fill semiconductor layer, and a common source semiconductor layer is disposed between the channel layer and the fill semiconductor layer. The channel layer fills a portion of each channel via and comprises the same material as the fill semiconductor layer. A drain layer covers the upper surface of the channel layer, fills a portion of the upper part of each channel via, and is doped with impurities of a second conductivity type different from the first conductivity type. Multiple bit lines are also present, each bit line being electrically connected to the drain layer of each memory cell structure in the plurality of memory cell structures. These bit lines extend in a first horizontal direction in the plurality of memory cell structures and are spaced apart from each other in a second horizontal direction orthogonal to the first horizontal direction. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1A and Figure 1C This is a top view of a semiconductor memory device according to an embodiment of the present invention. Figure 1B This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention, and Figure 1D This is a cross-sectional view of a semiconductor memory device used to describe the operation of the semiconductor memory device according to an embodiment of the present invention.

[0011] Figures 2A to 2C , Figures 3A to 3C , Figures 4A to 4C , Figures 5A to 5C , Figure 6A and Figure 6B , Figures 7A to 7C , Figure 8 , Figure 9 , Figure 10 , Figures 11A to 11C , Figures 12A to 12C as well as Figures 13A to 13C These are top views and cross-sectional views sequentially illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention; and

[0012] Figures 14 to 17 These are cross-sectional views of semiconductor memory devices according to embodiments of the present invention.

[0013] because Figures 1A to 17 The accompanying drawings are intended for illustrative purposes, and therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0014] Figure 1A and Figure 1C This is a top view of a semiconductor memory device according to an embodiment of the present invention. Figure 1B This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention, and Figure 1D This is a cross-sectional view of a semiconductor memory device used to describe the operation of a semiconductor memory device according to an embodiment of the present invention. Figure 1A This is a top view of a semiconductor memory device according to an embodiment of the present invention. Figure 1B and Figure 1D It is along the semiconductor memory device of the embodiment of the present invention. Figure 1A The sectional view taken by line B-B' in the middle, and Figure 1C It is along the semiconductor memory device of the embodiment of the present invention. Figure 1B The sectional view taken by line C-C' in the figure.

[0015] Refer to together Figures 1A to 1C The semiconductor memory device 1 may include a common-source semiconductor layer 180 disposed on a semiconductor substrate 102, a plurality of insulating layers 132 disposed on the common-source semiconductor layer 180 and separated from each other in the vertical direction (Z direction), a plurality of word line structures WL disposed between the plurality of insulating layers 132 and separated from each other in the vertical direction (Z direction), and a plurality of memory cell structures MCS extending in the vertical direction (Z direction). For example, the plurality of insulating layers 132 and the plurality of word line structures WL may be alternately stacked on the common-source semiconductor layer 180 disposed on the semiconductor substrate 102. The plurality of memory cell structures MCS may be disposed inside a plurality of channel vias CH, which penetrate the plurality of insulating layers 132, the plurality of word line structures WL, and the common-source semiconductor layer 180 and extend into the semiconductor substrate 102. An etch stop layer 110 may be disposed between the semiconductor substrate 102 and the common-source semiconductor layer 180. Therefore, the channel vias CH may also penetrate through the etch stop layer 110. In embodiments of the present invention, the plurality of channel holes CH can be arranged in a matrix. Optionally, the plurality of channel holes CH can be arranged to form a hexagonal array.

[0016] For example, the semiconductor substrate 102 may include silicon (Si), such as crystalline Si (c-Si), polycrystalline silicon Si (p-Si), or amorphous Si (p-Si). Optionally, the semiconductor substrate 102 may include a semiconductor element such as germanium (Ge) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), lead tellurium (PbTe) compound, gallium antimonide (GaSb), indium phosphide (InP), and indium gallium arsenide (InGaAs). Optionally, the semiconductor substrate 102 may include a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. For example, the semiconductor substrate 102 may include a buried oxide (BOX) layer. The semiconductor substrate 102 may include conductive regions, such as impurity-doped wells or impurity-doped structures. In addition, the semiconductor substrate 102 may include one or more semiconductor layers or semiconductor structures, and may include active or operable portions of a semiconductor device. The semiconductor substrate 102 may have a main surface extending in a first horizontal direction (X direction) and a second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) (e.g., in the XY plane).

[0017] In embodiments of the present invention, a device isolation layer may be formed on a semiconductor substrate 102. The device isolation layer may include at least one of, for example, a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and a silicon oxynitride (SiON) layer. The device isolation layer may include a single layer comprising one insulating layer, a double layer comprising two insulating layers, or a multilayer comprising a combination of at least three insulating layers. For example, the device isolation layer may include two different types of insulating layers, such as a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer. For example, the device isolation layer may include a three-layer structure comprising a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and a silicon oxide (SiO2) layer. The device isolation layer may include a shallow trench isolation (STI) structure. In embodiments of the present invention, a device isolation trench can be formed by removing the upper portion of the semiconductor substrate 102 through an anisotropic etching process, and then an insulating film comprising, for example, silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride (SiON) can be provided to fill the device isolation trench, thereby forming a device isolation layer.

[0018] The etch stop layer 110 may include oxide oxynitride. For example, the etch stop layer 110 may include silicon oxynitride (SiON). The insulating layer 132 may include oxides. For example, the insulating layer 132 may include silicon oxide (SiO2).

[0019] Multiple word line structures WL can extend horizontally (X or Y direction) on the semiconductor substrate 102 and be stacked on top of each other in a vertical direction (Z direction) perpendicular to the semiconductor substrate 102. The word line structures WL can include metals (such as tungsten (W), nickel (Ni), cobalt (Co), and / or tantalum (Ta) as examples), metal silicides (such as tungsten silicide (WSi)... x Nickel silicide (NiSi) x ), cobalt silicide (CoSi) x ) and / or tantalum silicide (TaSi) x For example, p-Si (doped polycrystalline silicon) or combinations thereof. In embodiments of the present invention, the word line structure WL may further include a diffusion barrier layer, and the diffusion barrier layer may include, for example, tungsten nitride (WN), tantalum nitride (TaN), and / or titanium nitride (TiN).

[0020] In an embodiment of the present invention, each of the plurality of vias CH may have a tapered shape in which its width in the horizontal direction (X or Y direction) decreases toward the semiconductor substrate 102. This can be attributed to the characteristics of the etching process used to form the vias CH. In an embodiment of the present invention, the width of each of the plurality of vias CH in the horizontal direction (X or Y direction) may have the maximum width at the lower end of each of the plurality of vias CH, rather than at the uppermost end, and may decrease toward the semiconductor substrate 102 from the portion having the maximum width. In other words, the portion having the maximum width is located between the lowermost and uppermost ends of each of the plurality of vias CH.

[0021] The memory cell dielectric layer MCD can be disposed between multiple word line structures WL and the channel layer 150. The memory cell structure MCS can include a channel layer 150 and a drain layer 170. The channel layer 150 includes the memory cell dielectric layer MCD disposed between or on the channel layer 150 and covers at least a portion of the channel via CH. The drain layer 170 covers the upper surface of the channel layer 150 and fills the upper portion of the channel via CH. For example, the memory cell dielectric layer MCD can be disposed on the sidewall of the channel layer 150 and can be disposed between the channel layer 150 and multiple word line structures WL. As described later, the memory cell structure MCS can also include a cell source layer 180S. In embodiments of the inventive concept, the channel layer 150 can each have a cylindrical shape on which the memory cell dielectric layer MCD is disposed, and can cover the inner wall of the channel via CH. The memory cell structure MCS can also include a filling insulating layer 160 filling the interior of the cylindrical channel layer 150. For example, the channel layer 150 may have a cylindrical shape, and the filling insulating layer 160 may have a columnar shape. In embodiments of the inventive concept, the channel layer 150 may have a substantially constant thickness and may conformally cover the memory cell dielectric layer MCD. The memory cell dielectric layer MCD may surround the outer wall of the channel layer 150. Throughout this specification, the terms "cover" or "on" may mean covering the sidewall of an object or on the sidewall of an object, or may mean covering the object from below or on the object from below.

[0022] The upper surface of the channel layer 150 may contact the drain layer 170, and the lower surface of the channel layer 150 may contact the common source semiconductor layer 180. A buried semiconductor layer 150E may fill the lower portion of the channel via CH extending into the semiconductor substrate 102. The buried semiconductor layer 150E may also be referred to as a filled semiconductor layer. The buried semiconductor layer 150E may be separate from the channel layer 150, and the common source semiconductor layer 180 is disposed between the buried semiconductor layer 150E and the channel layer 150. In embodiments of the inventive concept, a filling insulating layer 160 may penetrate the common source semiconductor layer 180 from within the channel layer 150 and extend into the buried semiconductor layer 150E. In the lower portion of the channel via CH (e.g., the portion inside the semiconductor substrate 102), a barrier insulating layer MCI may be disposed between the buried semiconductor layer 150E and the semiconductor substrate 102. In an embodiment of the present invention, the barrier insulating layer MCI may cover the semiconductor substrate 102 and the etch stop layer 110 in the lower portion of the channel via CH. The barrier insulating layer MCI may surround the side and lower surfaces of the buried semiconductor layer 150E.

[0023] In embodiments of the present invention, the channel layer 150 may comprise an intrinsic semiconductor material that is not doped with impurities. For example, the channel layer 150 may comprise intrinsic polysilicon (p-Si). In embodiments of the present invention, the channel layer 150 may comprise polysilicon (p-Si) with a relatively low doping concentration p0.

[0024] The buried semiconductor layer 150E may comprise the same material as the channel layer 150. For example, the buried semiconductor layer 150E may comprise an intrinsic semiconductor material. In embodiments of the present invention, the buried semiconductor layer 150E may comprise undoped intrinsic polysilicon (p-Si). In embodiments of the present invention, the buried semiconductor layer 150E may comprise polysilicon (p-Si) with a lower doping concentration than the channel layer 150. For example, the doping concentration of the buried semiconductor layer 150E may be lower than a relatively low doping concentration p0, where p0 is the concentration of impurities doped in the channel layer 150.

[0025] The drain layer 170 may include a semiconductor material doped with impurities of a first conductivity type. In embodiments of the present invention, the first conductivity type may be p-type. For example, the drain layer 170 may include p+ polysilicon (p-Si) highly doped with p-type impurities (e.g., boron (B), aluminum (Al), gallium (Ga), etc.). The common source semiconductor layer 180 may include a semiconductor material doped with impurities of a second conductivity type different from the first conductivity type. In embodiments of the present invention, the second conductivity type may be n-type. For example, the common source semiconductor layer 180 may include n+ polysilicon (p-Si) highly doped with n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0026] In embodiments of the present invention, the memory cell dielectric layer (MCD) may extend from the common source semiconductor layer 180 to the drain layer 170 along the inner wall of the channel via CH. For example, the memory cell dielectric layer (MCD) may have a substantially constant thickness and may conformally cover the inner wall of the channel via CH. In embodiments of the present invention, multiple memory cell dielectric layers (MCDs) may be arranged between multiple word line structures (WL) and the channel layer 150, and may be separated from each other.

[0027] The memory cell dielectric layer MCD and the barrier insulating layer MCI may include a stacked insulating structure 140, which includes a gate insulating layer 142 and a charge trapping layer 144. For example, the barrier insulating layer MCI may include the same material as the memory cell dielectric layer MCD. For example, the barrier insulating layer MCI may have a substantially constant thickness and may conformally cover the inner wall and bottom surface of the channel via CH extending into the semiconductor substrate 102. The gate insulating layer 142 may contact the word line structure WL, and the charge trapping layer 144 may be separated from the word line structure WL, with the gate insulating layer 142 positioned between the charge trapping layer 144 and the word line structure WL. The charge trapping layer 144 may contact the channel layer 150, and the gate insulating layer 142 may be separated from the channel layer 150, with the charge trapping layer 144 positioned between the gate insulating layer 142 and the channel layer 150.

[0028] In an embodiment of the present invention, the gate insulating layer 142 can conformally cover the inner wall of the channel via CH, and the charge trapping layer 144 can conformally cover the gate insulating layer 142 covering the inner wall of the channel via CH. In an embodiment of the present invention, multiple gate insulating layers 142 can respectively cover multiple word line structures WL exposed on the inner wall of the channel via CH and can be separated from each other; multiple charge trapping layers 144 can respectively cover multiple gate insulating layers 142. In an embodiment of the present invention, the gate insulating layer 142 can conformally cover the inner wall of the channel via CH, and multiple charge trapping layers 144 can respectively face multiple word line structures WL and be separated from each other, and the gate insulating layer 142 can be positioned between the multiple charge trapping layers 144 and the multiple word line structures WL.

[0029] Gate insulating layer 142 may include a material with a relatively low trapping site density, and charge trapping layer 144 may include a material with a relatively high trapping site density. For example, charge trapping layer 144 may include a material with a higher trapping site density and permittivity than the material included in gate insulating layer 142. For example, gate insulating layer 142 may include silicon oxide (SiO2). In embodiments of the inventive concept, charge trapping layer 144 may include a high-k material with a higher dielectric constant than that of gate insulating layer 142. For example, charge trapping layer 144 may include at least one of silicon nitride (Si3N4), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), aluminum lanthanum oxide (LaAlO3), hafnium oxysilicon (HfSiON), hafnium oxysilicon (HfON), and aluminum hafnium oxide (HfAlO3). In embodiments of the present invention, the charge trapping layer 144 may include a dielectric layer doped with transition metal atoms. For example, the charge trapping layer 144 may include hafnium oxide (HfO2) doped with transition metal atoms (such as tantalum (Ta), vanadium (V), ruthenium (Ru), niobium (Nb), manganese (Mn), palladium (Pd), and iridium (Ir)) or antimony (Sb), or aluminum oxide (Al2O3) doped with transition metal atoms (such as Zn, tungsten (W), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), nickel (Ni), and platinum (Pt)) or silicon (Si).

[0030] The stacked insulating structure 140 may have a channel opening 140O, which is positioned at the same vertical level as the portion between the semiconductor substrate 102 and the lowermost insulating layer 132 of the plurality of insulating layers 132. For example, the channel opening 140O may be positioned at the same vertical level as the substrate source layer 180B located between the etch stop layer 110 and the lowermost insulating layer 132 of the plurality of insulating layers 132, which will be described thereto. The channel opening 140O may extend along the inner wall of the channel hole CH and completely surround a portion of the lower side of the channel hole CH.

[0031] The memory cell dielectric layer MCD and the barrier insulating layer MCI may include a channel opening 140O disposed between them and are separated from each other. Each of the memory cell dielectric layer MCD and the barrier insulating layer MCI may be part of a stacked insulating structure 140 positioned on the upper and lower sides of the channel opening 140O. The portions of the gate insulating layer 142 constituting the memory cell dielectric layer MCD and the portions of the charge trapping layer 144 constituting the memory cell dielectric layer MCD may be referred to as a first gate insulating layer and a first charge trapping layer, respectively, and the portions of the gate insulating layer 142 constituting the barrier insulating layer MCI and the portions of the charge trapping layer 144 constituting the barrier insulating layer MCI may be referred to as a second gate insulating layer and a second charge trapping layer, respectively. Therefore, the first gate insulating layer and the second gate insulating layer may include a channel opening 140O disposed between them and are separated from each other, and the first charge trapping layer and the second charge trapping layer may include a channel opening 140O disposed between them and are separated from each other.

[0032] The common-source semiconductor layer 180 may include a substrate source layer 180B and a unit source layer 180S. The substrate source layer 180B extends horizontally (in both the X and Y directions) between the etch stop layer 110 and the lowermost insulating layer 132 of a plurality of insulating layers 132. The unit source layer 180S extends from the substrate source layer 180B and is disposed in a channel via CH between the channel layer 150 and the buried semiconductor layer 150E. In the channel via, a filling insulating layer 160 can penetrate the unit source layer 180S and extend into the buried semiconductor layer 150E. The upper surface of the unit source layer 180S can contact the lower surface of the channel layer 150, and the lower surface of the unit source layer 180S can contact the upper surface of the buried semiconductor layer 150E.

[0033] The substrate source layer 180B can extend from between the etch stop layer 110 and the lowermost insulating layer 132 of the plurality of insulating layers 132 to the channel opening 140O at substantially the same vertical height. The substrate source layer 180B can fill the internal space 120S between the etch stop layer 110 and the lowermost insulating layer 132 of the plurality of insulating layers 132. In embodiments of the inventive concept, the vertical height of the unit source layer 180S can be greater than the vertical height of the substrate source layer 180B. For example, the lower surface of the unit source layer 180S can be located at a vertical level lower than the vertical level of the lower surface of the substrate source layer 180B, and the upper surface of the unit source layer 180S can be located at a vertical level higher than the vertical level of the upper surface of the substrate source layer 180B. For example, the common-source semiconductor layer 180 may include a substrate source layer 180B and a unit source layer 180S. The substrate source layer 180B extends with substantially the same vertical height in a horizontal plane (XY plane), and the unit source layer 180S extends from the substrate source layer 180B and extends above and below the channel hole CH inside the channel hole CH. For example, the substrate source layer 180B may have an upper surface with the same vertical height as the lower surface of the lowermost insulating layer 132 among the plurality of insulating layers 132, and may extend in a horizontal direction (X direction or Y direction). The unit source layer 180S may extend upward and downward in a vertical direction (Z direction) inside the channel hole CH; therefore, the vertical height of the upper surface of the unit source layer 180S may be higher than the vertical height of the upper surface of the substrate source layer 180B. For example, the vertical height of the upper surface of the substrate source layer 180B can be lower than the vertical height of the upper surface of the unit source layer 180S.

[0034] Each of the multiple memory cell structures (MCS) may include a cell source layer 180S and a drain layer 170 separated from each other in the vertical direction (Z direction), and a channel layer 150 disposed between the cell source layer 180S and the drain layer 170. The cell source layers 180S included in the multiple memory cell structures (MCS) may be connected to each other through a substrate source layer 180B. For example, the substrate source layer 180B may be disposed on a semiconductor substrate 102 (e.g., on an etch stop layer 110), and the cell source layer 180S included in each of the multiple memory cell structures (MCS) may be connected to another (other) cell source layer 180S adjacent to that cell source layer 180S. In other words, the memory cell structure (MCS) may have a vertical pillar shape in which the cell source layer 180S, the channel layer 150, and the drain layer 170 are sequentially stacked from the semiconductor substrate 102 in the vertical direction (Z direction) and disposed inside the channel via CH. Multiple word line structures (WL) can be separated from each other in the vertical direction (Z direction) and can surround the memory cell structure (MCS). The memory cell dielectric layer (MCD) can be disposed on the sidewall of the channel layer 150 and can be placed between the channel layer 150 of the memory cell structure (MCS) and the multiple word line structures (WL).

[0035] The word line dicing region (WLC) can penetrate multiple insulating layers 132, multiple word line structures (WL), and the substrate source layer 180B of the common source semiconductor layer 180. The word line dicing region (WLC) can be arranged separately from multiple memory cell structures (MCS). For example, an etch stop layer 110 can be exposed at the bottom of the word line dicing region (WLC). In embodiments of the inventive concept, the word line dicing region (WLC) can extend in a second horizontal direction (Y direction). For example, multiple word line dicing regions (WLC) can extend in the second horizontal direction (Y direction) to dice the cell array region to form multiple memory cell blocks. Thus, each of the multiple memory cell blocks can be formed between two adjacent word line dicing regions (WLC). A buried insulating layer 192 can fill the word line dicing region (WLC). For example, the buried insulating layer 192 can include, for example, an oxide layer, a nitride layer, or a combination thereof. In embodiments of the inventive concept, the buried insulating layer 192 can include the same material as the insulating layer 132.

[0036] The selected wire cut region SLC can penetrate the uppermost insulating layer 132 of a plurality of insulating layers 132 and the uppermost word line structure WL of a plurality of word line structures WL. For example, the insulating layer 132 in contact with the lower surface of the uppermost word line structure WL can be exposed in the selected wire cut region SLC. In an embodiment of the inventive concept, the selected wire cut region SLC can extend in a second horizontal direction (Y direction). In an embodiment of the inventive concept, the selected wire cut region SLC can extend into the next insulating layer of the plurality of insulating layers 132 after the uppermost insulating layer 132 and in contact with the lower surface of the uppermost word line structure WL. An insulating isolation layer 194 can fill the selected wire cut region SLC. For example, the insulating isolation layer 194 can include, for example, an oxide layer, a nitride layer, or a combination thereof. In an embodiment of the inventive concept, the insulating isolation layer 194 can include the same material as the buried insulating layer 192.

[0037] In embodiments of the present invention, a plurality of word line structures WL may include three word line structures WL separated from each other in the vertical direction (Z direction). The uppermost word line structure WL, separated by a Selected Line Cutting Region (SLC), may include a selection line SL. For example, memory cell structures (MCS) spaced apart from each other by the Selected Line Cutting Region (SLC) can be individually selected and controlled by the selection line SL. For two word line structures WL separated by word line cutting regions WLC but not by the Selected Line Cutting Region (SLC), the upper word line structure WL may include a first barrier line UBA, and the lower word line structure WL may include a second barrier line LBA.

[0038] Multiple bit lines BL electrically connected to the drain layer 170 can be arranged on multiple insulating layers 132. In embodiments of the present invention, the multiple bit lines BL can have a substantially constant distance from each other in a second horizontal direction (Y direction) and can extend in a first horizontal direction (X direction) orthogonal to the second horizontal direction (Y direction). For example, each of the multiple bit lines BL can extend to contact the drain layer 170 of a row of memory cells arranged in the first horizontal direction (X direction) in a plurality of memory cell structures MCS. Figure 1B The diagram shows multiple bit lines BL contacting the drain layer 170 of multiple memory cell structures (MCS), but the inventive concept is not limited thereto. For example, the multiple bit lines BL can be electrically connected to the drain layer 170 of the multiple memory cell structures (MCS) via conductive vias and / or conductive studs.

[0039] and Figures 1A to 1C Refer to together Figure 1DBy applying a drain voltage VD to the drain layer 170, a source voltage VS to the common-source semiconductor layer 180, a selection voltage VG to the selection line SL, a first barrier voltage VA to the first barrier line UBA, and a second barrier voltage VB to the second barrier line LBA, the semiconductor memory device 1 can be operated. The selection voltage VG can be provided as a voltage that enables the selection of one memory cell structure MCS from a plurality of memory cell structures MCS.

[0040] When a relatively large voltage, as the first barrier voltage VA, is provided to the first barrier line UBA, and a relatively small voltage, as the second barrier voltage VB, is provided to the second barrier line LBA, a first carrier region 150A can be formed in the portion of the channel layer 150 adjacent to the first barrier line UBA, and a second carrier region 150B can be formed in another portion of the channel layer 150 adjacent to the second barrier line LBA. In embodiments of the present invention, the first barrier voltage VA can be a positive voltage as a forward voltage, and the second barrier voltage VB can be a negative voltage as a reverse voltage. For example, the first barrier voltage VA can be about 5V, and the second barrier voltage VB can be about -5V, but these are merely examples, and the present invention is not limited thereto. The voltage values ​​mentioned in the present invention are for relative comparison only and are not limited to the corresponding values. Optionally, in embodiments of the present invention, the first barrier voltage VA can be a negative voltage, and the second barrier voltage VB can be a positive voltage (refer to the description to be continued). Figure 14 For example, a positive voltage can be provided to one of the first barrier line UBA and the second barrier line LBA, and a negative voltage can be provided to the other of the first barrier line UBA and the second barrier line LBA.

[0041] The drain layer 170 may include a region doped with an impurity of a first conductivity type, and the common source semiconductor layer 180 may include a region doped with an impurity of a second conductivity type. In embodiments of the inventive concept, the first conductivity type may be p-type, and the second conductivity type may be n-type. For example, the drain layer 170 may be a p+ region, and the common source semiconductor layer 180 may be an n+ region.

[0042] When a first barrier voltage VA is applied to a first barrier line UBA, the first carrier region 150A can become a region of the second conductivity type in which electrons exist as multiple carriers, and when a second barrier voltage VB is applied to a second barrier line LBA, the second carrier region 150B can become a region of the first conductivity type in which holes exist as multiple carriers. For example, the first carrier region 150A provided with the first barrier voltage VA may include an n+ region, and the second carrier region 150B provided with the second barrier voltage VB may include a p+ region.

[0043] The drain layer 170, the first carrier region 150A, and the second carrier region 150B can constitute a pnp transistor, and the first carrier region 150A, the second carrier region 150B, and the common-source semiconductor layer 180 can constitute an npn transistor. Therefore, the memory cell structure MCS can form a pnpn thyristor. For example, the memory cell structure MCS may include alternating p-type and n-type semiconductors (pnpn) and may have three junctions: pn, np, and pn. For example, the memory cell structure MCS may include two transistors coupled together (e.g., a pnp transistor and an npn transistor).

[0044] When the difference between the drain voltage VD and the source voltage VS is applied to the drain layer 170 and the common-source semiconductor layer 180 by a sweep from approximately 0V to a voltage equal to or greater than the trigger voltage, thyristor operation can be performed in the memory cell structure MCS, and a high-current state with high drain current can be maintained for a certain period of time. Conversely, when the difference between the drain voltage VD and the source voltage VS is applied to the drain layer 170 and the common-source semiconductor layer 180 as a voltage less than the trigger voltage, a low-current state with small current flow can be maintained for a certain period of time due to the potential barrier in the memory cell structure MCS. In an embodiment of the present invention, the trigger voltage can be approximately 3V.

[0045] When the difference between the drain voltage VD and the source voltage VS is provided as a read voltage of about 1 / 2 of the trigger voltage to the drain layer 170 and the common source semiconductor layer 180, two current states (i.e., 1 bit of stored data) can be read, namely the high current state and the low current state.

[0046] Semiconductor memory device 1 can constantly provide a first barrier voltage VA to a first barrier line UBA and a second barrier voltage VB to a second barrier line LBA, such that: the memory cell structure MCS has a pnpn thyristor, which can select one of the multiple memory cell structures MCS by providing a selection voltage VG to the selection line SL, and can be used as a volatile memory device such as DRAM that can perform write and read operations by providing trigger voltages and read voltages by controlling the drain voltage VD and the source voltage VS respectively. In other words, each of the multiple memory cell structures MCS can include a volatile memory device with a thyristor structure.

[0047] A memory cell dielectric layer MCD (i.e., stacked insulating structure 140), including a gate insulating layer 142 and a charge trapping layer 144, can be disposed between a first barrier line UBA and a channel layer 150 and between a second barrier line LBA and a channel layer 150. Therefore, when a first carrier region 150A and a second carrier region 150B are formed by providing a first barrier voltage VA to the first barrier line UBA and a second barrier voltage VB to the second barrier line LBA, a plurality of carriers in the first carrier region 150A can be trapped in the portion of the charge trapping layer 144 adjacent to the first carrier region 150A, and a plurality of carriers in the second carrier region 150B can be trapped in the portion of the charge trapping layer 144 adjacent to the second carrier region 150B. For example, electrons, which are charge carriers in the first carrier region 150A (which can be a region of the second conductivity type), can be trapped in the portion of the charge trapping layer 144 located between the first barrier line UBA and the channel layer 150. Similarly, holes, which are charge carriers in the second carrier region 150B (which can be a region of the first conductivity type), can be trapped in the portion of the charge trapping layer 144 located between the second barrier line LBA and the channel layer 150. Therefore, by using multiple charge carriers trapped in the charge trapping layer 144, the two current states for storing data in the memory cell structure MCS can be maintained for a relatively long time. Furthermore, the current difference between the high current state and the low current state can be increased due to the multiple charge carriers trapped in the charge trapping layer 144.

[0048] The semiconductor memory device 1 conceived according to the present invention allows each of the multiple memory cell structures (MCS) to have a pnpn structure thyristor, thereby enabling it to be used as a DRAM capable of performing write and read operations for each of the multiple memory cell structures (MCS) respectively (e.g., performing a write operation by providing a trigger voltage, and performing a read operation for two current states (i.e., for 1 bit of stored data) by providing approximately 1 / 2 trigger voltage), and the charge carriers can be captured in the charge trapping layer 144 in contact with the channel layer 150, thus improving the retention time and memory window characteristics.

[0049] Figures 2A to 2C , Figures 3A to 3C , Figures 4A to 4C , Figures 5A to 5C , Figure 6A and Figure 6B , Figures 7A to 7C , Figure 8 , Figure 9 , Figure 10 , Figures 11A to 11C , Figures 12A to 12C as well as Figures 13A to 13C These are top views and cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 11A , Figure 12A and Figure 13A This is a top view showing a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8 , Figure 9 , Figure 10 , Figure 11B , Figure 12B and Figure 13B They are along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 11A , Figure 12A and Figure 13A The sectional view taken by line B-B' in the middle, and Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 7C , Figure 11C , Figure 12C and Figure 13C They are along Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 7B , Figure 11B , Figure 12B and Figure 13B The sectional view taken by line C-C' in the figure.

[0050] Reference Figures 2A to 2CA sacrificial semiconductor layer 120 can be formed on the semiconductor substrate 102, and multiple insulating layers 132 and multiple sacrificial layers 134 can be alternately stacked on the sacrificial semiconductor layer 120. In embodiments of the present invention, the multiple insulating layers 132 can be formed one more layer than the multiple sacrificial layers 134, so that the sacrificial layers 134 can be arranged between the multiple insulating layers 132 that are separated from each other in the vertical direction (Z direction). For example, the insulating layers 132 can be arranged below the lowermost sacrificial layer 134 and above the uppermost sacrificial layer 134 among the multiple sacrificial layers 134.

[0051] In an embodiment of the present invention, an etch stop layer 110 may be formed on a semiconductor substrate 102 before the sacrificial semiconductor layer 120 is formed, and then the sacrificial semiconductor layer 120 may be formed on the etch stop layer 110.

[0052] For example, the semiconductor substrate 102 may include silicon (Si), such as crystalline silicon (c-Si), polycrystalline silicon (p-Si), or amorphous silicon (a-Si). Optionally, the semiconductor substrate 102 may include a semiconductor element such as germanium (Ge) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), lead tellurium (PbTe) compound, gallium antimonide (GaSb), indium phosphide (InP), and indium gallium arsenide (InGaAs). Optionally, the semiconductor substrate 102 may include a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. For example, the semiconductor substrate 102 may include a BOX layer. The semiconductor substrate 102 may include conductive regions, such as impurity-doped wells or impurity-doped structures. In addition, the semiconductor substrate 102 may include one or more semiconductor layers or semiconductor structures, and may include active or operable portions of a semiconductor device.

[0053] In embodiments of the present invention, a device isolation layer can be formed on a semiconductor substrate 102. The device isolation layer may include at least one of, for example, a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and a silicon oxynitride (SiON) layer. The device isolation layer may include a single layer comprising one insulating layer, a double layer comprising two insulating layers, or a multilayer comprising a combination of at least three insulating layers. For example, the device isolation layer may include two different types of insulating layers, such as a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer. For example, the device isolation layer may include three layers comprising a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, and a silicon oxide (SiO2) layer. The device isolation layer may include an STI structure. In embodiments of the present invention, a device isolation trench can be formed by removing the upper portion of the semiconductor substrate 102 through an anisotropic etching process, and then an insulating film comprising, for example, silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride (SiON) can be provided to fill the device isolation trench.

[0054] The etch stop layer 110 may comprise a material that is etch-selective with respect to each of the semiconductor substrate 102, the sacrificial semiconductor layer 120, the insulating layer 132, and the sacrificial layer 134. For example, each of the semiconductor substrate 102, the sacrificial semiconductor layer 120, the insulating layer 132, and the sacrificial layer 134 may be selectively and rapidly etched away, while the etch stop layer 110 may be etched very slowly or not at all. In embodiments of the inventive concept, the semiconductor substrate 102 may comprise silicon (Si), the sacrificial semiconductor layer 120 may comprise polycrystalline silicon (p-Si), the insulating layer 132 may comprise an oxide, and when the sacrificial layer 134 comprises a nitride, the etch stop layer 110 may comprise an oxide nitride. For example, the etch stop layer 110 may comprise silicon oxynitride (SiON).

[0055] The sacrificial semiconductor layer 120 may comprise a material that is etch-selective with respect to each of the etch stop layer 110, insulating layer 132, and sacrificial layer 134. For example, the sacrificial semiconductor layer 120 may be selectively and rapidly etched away, while each of the etch stop layer 110, insulating layer 132, and sacrificial layer 134 may be etched very slowly or not at all. The sacrificial semiconductor layer 120 may be formed by performing a deposition process. In embodiments of the inventive concept, the sacrificial semiconductor layer 120 may comprise polycrystalline silicon (p-Si).

[0056] The insulating layer 132 and the sacrificial layer 134 may comprise materials with different etching selectivity. The insulating layer 132 and the sacrificial layer 134 may be formed by performing processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. In embodiments of the inventive concept, the insulating layer 132 may comprise, for example, silicon oxide (SiO2), and the sacrificial layer 134 may comprise, for example, silicon nitride (Si3N4).

[0057] Refer to together Figures 3A to 3C Multiple channel vias CH can be formed, penetrating multiple insulating layers 132, multiple sacrificial layers 134, and sacrificial semiconductor layer 120, and extending into the semiconductor substrate 102. The semiconductor substrate 102 may be exposed at the bottom of the multiple channel vias CH. In an embodiment of the present invention, when the etch stop layer 110 is placed between the semiconductor substrate 102 and the sacrificial semiconductor layer 120, the multiple channel vias CH can penetrate the multiple insulating layers 132, multiple sacrificial layers 134, sacrificial semiconductor layer 120, and etch stop layer 110, and can extend into the semiconductor substrate 102. In an embodiment of the present invention, the multiple channel vias CH can be formed by performing an anisotropic etching process. For example, the anisotropic etching process may be a reactive ion etching (RIE) process.

[0058] exist Figure 3A and Figure 3C The diagram illustrates a matrix arrangement of multiple channel holes CH forming columns in each of a first horizontal direction (X direction) and a second horizontal direction (Y direction), but the inventive concept is not limited thereto. In embodiments of the inventive concept, the multiple channel holes CH can be arranged in rows in the first horizontal direction (X direction) and in a zigzag pattern in the second horizontal direction (Y direction). For example, the multiple channel holes CH can be arranged in a honeycomb pattern.

[0059] In embodiments of the present invention, the width of each of the plurality of vias CH in a first horizontal direction (X direction) or a second horizontal direction (Y direction) may taper toward the semiconductor substrate 102. This can be attributed to the characteristics of the etching process used to form the vias CH. In embodiments of the present invention, the width of each of the plurality of vias CH in the first horizontal direction (X direction) or the second horizontal direction (Y direction) may have the maximum width on the lower side of each via CH rather than at the uppermost end, and may taper toward the semiconductor substrate 102 from the portion of maximum width due to a bowing phenomenon generated during the anisotropic etching process of the plurality of insulating layers 132, the plurality of sacrificial layers 134, the sacrificial semiconductor layer 120, and the etch stop layer 110.

[0060] Refer to together Figures 4A to 4C A stacked insulating structure 140 can be formed covering the inner walls and bottom surface of each of a plurality of vias CH. The stacked insulating structure 140 may include a gate insulating layer 142 covering the inner walls and bottom surface of each of the plurality of vias CH, and a charge trapping layer 144 covering the gate insulating layer 142. The gate insulating layer 142 may have a substantially constant thickness and conformally cover the inner walls and bottom of the vias CH, and the charge trapping layer 144 may have a substantially constant thickness and conformally cover the gate insulating layer 142. The gate insulating layer 142 and the charge trapping layer 144 may be conformally configured to have a thickness that does not fill each via CH. The gate insulating layer 142 and the charge trapping layer 144 may be formed by performing, for example, an ALD process. In embodiments of the inventive concept, the stacked insulating structure 140 including the gate insulating layer 142 and the charge trapping layer 144 may also cover the upper surface (e.g., the uppermost surface of the uppermost insulating layer 132) of the stacked structure of the plurality of insulating layers 132 and the plurality of sacrificial layers 134.

[0061] Gate insulating layer 142 may include a material with a relatively low trapping site density, and charge trapping layer 144 may include a material with a relatively high trapping site density. For example, charge trapping layer 144 may include a material with a higher trapping site density and permittivity than the material included in gate insulating layer 142. For example, gate insulating layer 142 may include silicon oxide (SiO2). In embodiments of the present invention, charge trapping layer 144 may include a high-k material with a higher dielectric constant than that of gate insulating layer 142. For example, charge trapping layer 144 may include at least one of silicon nitride (Si3N4), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), aluminum lanthanum oxide (LaAlO3), hafnium oxysilane (HfSiON), hafnium oxysilane (HfON), and aluminum hafnium oxide (HfAlO3). In embodiments of the present invention, charge trapping layer 144 may include a dielectric layer doped with transition metal atoms. For example, the charge trapping layer 144 may comprise hafnium oxide (HfO2) doped with transition metal atoms (such as tantalum (Ta), vanadium (V), ruthenium (Ru), niobium (Nb), manganese (Mn), palladium (Pd) and iridium (Ir)) or antimony (Sb) or aluminum oxide (Al2O3) doped with transition metal atoms (such as zinc (Zn), tungsten (W), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), nickel (Ni) and platinum (Pt)) or silicon (Si).

[0062] Reference Figures 5A to 5CA channel layer 150 filling at least a portion of the channel hole CH can be formed on the stacked insulating structure 140. In embodiments of the present invention, the channel layer 150 can conformally cover the charge trapping layer 144 of the stacked insulating structure 140 and fill a portion of the channel hole CH, and a filling insulating layer 160 filling all the remaining portions of the channel hole CH can be formed on the channel layer 150. The channel layer 150 formed on the stacked insulating structure 140 can have a cylindrical shape. Therefore, the filling insulating layer 160 can be surrounded by the channel layer 150. For example, the filling insulating layer 160 can include an insulating material. In embodiments of the present invention, the filling insulating layer 160 can include silicon oxide (SiO2). In embodiments of the present invention, the channel layer 150 can be formed on the charge trapping layer 144 of the stacked insulating structure 140 to fill the entire channel hole CH, in which case the filling insulating layer 160 may not be formed. For example, the channel layer 150 formed on the stacked insulating structure 140 can have a solid pillar shape.

[0063] In embodiments of the present invention, the channel layer 150 may comprise intrinsic polysilicon (p-Si) without any impurities. In embodiments of the present invention, the channel layer 150 may comprise polysilicon (p-Si) with a relatively low doping concentration p0.

[0064] Reference Figure 6A and Figure 6B The portion of the channel layer 150 positioned at a vertical level higher than the vertical level of the upper surface of the stacked structure of the plurality of insulating layers 132 and the plurality of sacrificial layers 134, as well as the portion of the fill insulating layer 160 positioned at a vertical level higher than the vertical level of the upper surface of the stacked structure of the plurality of insulating layers 132 and the plurality of sacrificial layers 134, can be removed. Furthermore, the upper portion of the channel layer 150 filling the plurality of channel holes CH and the upper portion of the fill insulating layer 160 filling the plurality of channel holes CH can also be removed. By removing a portion of the channel layer 150 and a portion of the fill insulating layer 160, the upper surfaces of the channel layer 150 and the fill insulating layer 160 can each have a vertical level lower than the vertical level of the upper surface of the stacked structure of the plurality of insulating layers 132 and the plurality of sacrificial layers 134, respectively. In an embodiment of the present invention, after the removal process, the upper surface of the channel layer 150 and the upper surface of the filling insulating layer 160 may have a vertical level higher than the lower surface of the uppermost insulating layer 132 among the plurality of insulating layers 132.

[0065] Subsequently, a drain layer 170 can be formed on the upper portion of each of the plurality of channel vias CH, wherein a portion of the channel layer 150 and a portion of the insulating layer 160 have been removed. The drain layer 170 may comprise a semiconductor material doped with impurities of a first conductivity type. In embodiments of the inventive concept, the first conductivity type may be p-type. For example, the drain layer 170 may comprise p+ polysilicon (p-Si) doped with a high concentration of p-type impurities (e.g., boron (B), aluminum (Al), gallium (Ga), etc.).

[0066] Reference Figures 6A to 7C A word line dicing region (WLC) penetrating multiple insulating layers 132 and multiple sacrificial layers 134 can be formed. The WLC can be formed by performing anisotropic etching to remove a portion of each of the multiple insulating layers 132, multiple sacrificial layers 134, and sacrificial semiconductor layers 120, thereby exposing the sacrificial semiconductor layer 120. In embodiments of the inventive concept, the WLC can penetrate the multiple insulating layers 132, multiple sacrificial layers 134, and sacrificial semiconductor layer 120, such that the etch stop layer 110 is exposed on the lower surface of the WLC. In embodiments of the inventive concept, the WLC can extend in a second horizontal direction (Y direction). For example, the WLC can extend in a direction intersecting multiple bit lines BL, which can extend in a first horizontal direction (X direction).

[0067] In an embodiment of the present invention, the width of the word line cut region WLC in the first horizontal direction (X direction) can decrease in a tapered shape toward the semiconductor substrate 102. This can be attributed to the characteristics of the etching process used to form the word line cut region WLC.

[0068] Refer to together Figures 7A to 8 The sacrificial semiconductor layer 120 can be removed via the word line dicing region (WLC). For example, the sacrificial semiconductor layer 120 can be removed by performing an isotropic etching process using an etchant supplied via the word line dicing region (WLC). For example, a wet etching process, as an isotropic etching process, can be used to selectively remove the sacrificial semiconductor layer 120 relative to the plurality of insulating layers 132, the plurality of sacrificial layers 134, and the etch stop layer 110. Alternatively, an isotropic dry etching process can be used to selectively remove the sacrificial semiconductor layer 120. An internal space 120S can be formed in the portion of the sacrificial semiconductor layer 120 that has been removed. The internal space 120S can be the space between the etch stop layer 110 and the lowermost insulating layer 132 of the plurality of insulating layers 132. The word line dicing region (WLC) and the internal space 120S can be interconnected with each other.

[0069] Reference Figure 9The channel opening 140O, which exposes the channel layer 150, can be formed by removing a portion of the stacked insulating structure 140 exposed to the internal space 120S. The channel opening 140O can be formed by removing a portion of the stacked insulating structure 140 through an isotropic etching process using an etchant supplied via the word line cutting region WLC and the internal space 120S.

[0070] The stacked insulating structure 140 can be separated into a memory cell dielectric layer MCD and a barrier insulating layer MCI through a channel opening 140O. The memory cell dielectric layer MCD and the barrier insulating layer MCI can be portions of the stacked insulating structure 140 located on the upper and lower sides of the channel opening 140O, respectively. The memory cell dielectric layer MCD and the barrier insulating layer MCI can be separated from each other, and the channel opening 140O is located between the memory cell dielectric layer MCD and the barrier insulating layer MCI.

[0071] The portion of the gate insulating layer 142 constituting the memory cell dielectric layer MCD and the portion of the charge trapping layer 144 constituting the memory cell dielectric layer MCD can be referred to as the first gate insulating layer and the first charge trapping layer, respectively. Similarly, the portion of the gate insulating layer 142 constituting the barrier insulating layer MCI and the portion of the charge trapping layer 144 constituting the barrier insulating layer MCI can be referred to as the second gate insulating layer and the second charge trapping layer, respectively. Therefore, the first gate insulating layer and the second gate insulating layer may include a channel opening 140O disposed between them and are separated from each other, and the first charge trapping layer and the second charge trapping layer may include a channel opening 140O disposed between them and are separated from each other.

[0072] Reference Figure 10 A substrate source layer 180B can be formed that fills the internal space 120S and the channel opening 140O. In an embodiment of the present invention, after forming a preliminary source layer that fills the channel opening 140O, the internal space 120S, and the word line dicing region WLC, the substrate source layer 180B can be formed by removing a portion of the preliminary source layer that fills the word line dicing region WLC. The preliminary source layer can be formed by performing, for example, a CVD process. In an embodiment of the present invention, the substrate source layer 180B can be formed by performing a selective epitaxial growth (SEG) process using a portion of the channel layer 150 exposed through the channel opening 140O as a seed crystal.

[0073] The substrate source layer 180B may include a semiconductor material doped with impurities of a second conductivity type. In embodiments of the present invention, the second conductivity type may be n-type. For example, the substrate source layer 180B may include n+ polycrystalline silicon (p-Si) doped with a high concentration of n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0074] When the substrate source layer 180B is formed by performing a CVD process, after the amorphous semiconductor material layer is formed, the amorphous semiconductor material layer can be changed to polycrystalline silicon (p-Si) by performing a heat treatment, or the amorphous semiconductor material layer can be formed into polycrystalline silicon (p-Si) by controlling the deposition temperature conditions during the deposition process. When the substrate source layer 180B is formed by performing a SEG process, if the portion used as the seed crystal for the channel layer 150 is polycrystalline silicon (p-Si), the substrate source layer 180B may also include polycrystalline silicon (p-Si).

[0075] In the process of forming the substrate source layer 180B, impurities of a second conductivity type doped on the substrate source layer 180B can diffuse into a portion of the channel layer 150, and the portion of the channel layer 150 on which the impurities of the second conductivity type have been diffused can become a unit source layer 180S. For example, the impurities of the second conductivity type can diffuse laterally from the substrate source layer 180B into the channel layer 150 in a first horizontal direction (X direction) and a second horizontal direction (Y direction) through the channel opening 140O, and can also diffuse upward and downward in the vertical direction (Z direction) within the channel layer 150 inside the channel hole CH. Then, the channel layer 150 inside the channel hole CH doped with the impurities of the second conductivity type can form a unit source layer 180S. In this way, a common source semiconductor layer 180 including the substrate source layer 180B and the unit source layer 180S and doped with impurities of the second conductivity type can be formed.

[0076] Because the substrate source layer 180B is formed by filling the channel opening 140O and the internal space 120S, the substrate source layer 180B can extend from between the etch stop layer 110 and the lowermost insulating layer 132 of the plurality of insulating layers 132 with a substantially constant vertical height in the first horizontal direction (X direction) and the second horizontal direction (Y direction). In an embodiment of the inventive concept, the unit source layer 180S can be formed to have a vertical height greater than that of the substrate source layer 180B. Because the unit source layer 180S is formed by diffusing impurities of the second conductivity type into a portion of the channel layer 150, the lower surface of the unit source layer 180S can be positioned at a vertical level lower than that of the lower surface of the substrate source layer 180B, and the upper surface of the unit source layer 180S can be positioned at a vertical level higher than that of the upper surface of the substrate source layer 180B.

[0077] The common-source semiconductor layer 180 may include a substrate source layer 180B extending at substantially the same vertical height in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and a unit source layer 180S extending from the substrate source layer 180B and extending above and below the channel hole CH. In other words, the unit source layer 180S may extend upward and downward in the vertical direction (Z direction) inside the channel hole CH. Therefore, the vertical height of the lower surface of the unit source layer 180S may be lower than the vertical height of the lower surface of the substrate source layer 180B, and the vertical height of the upper surface of the unit source layer 180S may be higher than the vertical height of the upper surface of the substrate source layer 180B.

[0078] The memory cell dielectric layer MCD and the barrier insulating layer MCI may include a common source semiconductor layer 180 that fills the channel opening 140O disposed between them, and may be separated from each other.

[0079] When the unit source layer 180S of the common source semiconductor layer 180 is formed, the lower portion of the channel layer 150 can be separated from the remaining portion of the channel layer 150 and is referred to as the buried semiconductor layer 150E. The buried semiconductor layer 150E can fill the lower portion of the channel via CH extending into the semiconductor substrate 102. Because the buried semiconductor layer 150E is separated from the remaining portion of the channel layer 150 and the unit source layer 180S is disposed between the buried semiconductor layer 150E and the remaining portion of the channel layer 150, the buried semiconductor layer 150E can include the same material as the remaining portion of the channel layer 150. In embodiments of the inventive concept, the buried semiconductor layer 150E can include undoped intrinsic polysilicon (p-Si). In embodiments of the inventive concept, the channel layer 150 can include polysilicon (p-Si) with a relatively low doping concentration p0.

[0080] Refer to together Figures 10 to 11C By removing multiple sacrificial layers 134 via the word line dicing region WLC, multiple word line spaces WS interconnected with the word line dicing region WLC can be formed. The multiple sacrificial layers 134 can be removed by performing an isotropic etching process using an etchant supplied via the word line dicing region WLC. For example, a wet etching process as an isotropic etching process can be used to selectively remove the multiple sacrificial layers 134 relative to the multiple insulating layers 132 and the etch stop layer 110. Alternatively, an isotropic dry etching process can be used to selectively remove the multiple sacrificial layers 134. For example, when the multiple sacrificial layers 134 are formed of silicon nitride (Si3N4) and the multiple insulating layers 132 are formed of silicon oxide (SiO2), the multiple sacrificial layers 134 can be removed by an etching process using an etching solution including phosphoric acid (H3PO4). However, the inventive concept is not limited thereto.

[0081] Refer to together Figures 12A to 12C Multiple word line structures WL can be formed to fill multiple word line spaces WS. After forming a word line material layer that fills multiple word line spaces WS and word line cutting regions WLC, multiple word line structures WL can be formed by removing the portion of the word line material layer formed in the word line cutting regions WLC.

[0082] Multiple word line structures WL can extend on the semiconductor substrate 102 in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and are stacked on top of each other in a vertical direction (Z direction) perpendicular to the semiconductor substrate 102. The word line structures WL can include metals (such as tungsten (W), nickel (Ni), cobalt (Co) and / or tantalum (Ta) as examples), metal silicides (such as tungsten silicide (WSix), nickel silicide (NiSi)), etc. x ), cobalt silicide (CoSi) x ) and / or tantalum silicide (TaSi) x For example, polycrystalline silicon (p-Si) doped with impurities or a combination thereof.

[0083] After forming multiple word line structures WL, a buried insulating layer 192 can be formed to fill the word line cutting regions WLC. For example, the buried insulating layer 192 may include, for example, an oxide layer, a nitride layer, or a combination thereof. In embodiments of the inventive concept, the buried insulating layer 192 may include the same material as the insulating layer 132.

[0084] Reference Figures 13A to 13C A selective wire-cut region (SLC) can be formed that penetrates the uppermost insulating layer 132 of a plurality of insulating layers 132 and the uppermost word line structure WL of a plurality of word line structures WL. The SLC can be formed by performing anisotropic etching to remove a portion of each of the uppermost insulating layer 132 and the uppermost word line structure WL, thereby exposing a next insulating layer of the plurality of insulating layers 132 that follows the uppermost insulating layer 132 and contacts the lower surface of the uppermost word line structure WL. In embodiments of the inventive concept, the SLC can extend into the next insulating layer of the plurality of insulating layers 132 that follows the uppermost insulating layer 132 and contacts the lower surface of the uppermost word line structure WL. In embodiments of the inventive concept, the SLC can extend in a second horizontal direction (Y direction).

[0085] Subsequently, the selective wire-cut region SLC can be filled with the insulating layer 194. For example, the insulating layer 194 may include, for example, an oxide layer, a nitride layer, or a combination thereof. In embodiments of the inventive concept, the insulating layer 194 filling the selective wire-cut region SLC may include the same material as the buried insulating layer 192 filling the word wire-cut region WLC.

[0086] The uppermost word line structure WL, separated by the Selected Line Cutting Region (SLC), can be called the Selected Line (SL). The upper word line structure WL, which is referred to as multiple word lines and is not separated by the Selected Line Cutting Region (SLC) but by the Word Line Cutting Region (WLC), can be the first barrier line (UBA), and its lower word line structure WL can be the second barrier line (LBA).

[0087] After that, as Figures 1A to 1C As shown, a semiconductor memory device 1 can be formed by forming multiple bit lines BL disposed on multiple insulating layers 132 and electrically connected to multiple drain layers 170. In an embodiment of the present invention, the multiple bit lines BL may have a substantially constant distance from each other in a second horizontal direction (Y direction) and may extend in a first horizontal direction (X direction).

[0088] Figures 14 to 17 These are cross-sectional views of semiconductor memory devices according to embodiments of the present invention. Figures 14 to 17 In, with Figures 1A to 13C Components with the same component number can represent the same component, and their repeated descriptions can be omitted.

[0089] Reference Figure 14 The semiconductor memory device 1a may include a common-source semiconductor layer 180a disposed on a semiconductor substrate 102, a plurality of insulating layers 132 disposed on the common-source semiconductor layer 180a and separated from each other in the vertical direction (Z direction), a plurality of word line structures WL disposed between the plurality of insulating layers 132 and separated from each other in the vertical direction (Z direction), and a plurality of memory cell structures MCSa extending in the vertical direction (Z direction). For example, the plurality of insulating layers 132 and the plurality of word line structures WL may be alternately stacked on the common-source semiconductor layer 180a disposed on the semiconductor substrate 102. The plurality of memory cell structures MCSa may be disposed within a plurality of channel vias CH that penetrate the plurality of insulating layers 132, the plurality of word line structures WL, and the common-source semiconductor layer 180a and extend into the semiconductor substrate 102. An etch stop layer 110 may be disposed between the semiconductor substrate 102 and the common-source semiconductor layer 180a.

[0090] The memory cell dielectric layer MCD can have a substantially constant thickness and can conformally cover the inner wall of the channel via CH. The memory cell structure MCSa can include a channel layer 150 and a drain layer 170a. The channel layer 150 includes the memory cell dielectric layer MCD disposed between or on the channel layer 150 and covering at least a portion of the channel via CH. The drain layer 170a covers the upper surface of the channel layer 150 and fills the upper portion of the channel via CH. The memory cell structure MCSa can also include a filling insulating layer 160 filling the interior of the channel layer 150, which has a cylindrical or tubular shape. The upper surface of the channel layer 150 can contact the drain layer 170a, and the lower surface of the channel layer 150 can contact the common source semiconductor layer 180a. A buried semiconductor layer 150E can fill the lower portion of the channel via CH extending into the semiconductor substrate 102. The buried semiconductor layer 150E can be separated from the channel layer 150, and the common source semiconductor layer 180a is disposed between them.

[0091] The drain layer 170a may comprise a semiconductor material doped with impurities of a second conductivity type. In embodiments of the present invention, the second conductivity type may be n-type. For example, the drain layer 170a may comprise n+ polysilicon (p-Si) highly doped with n-type impurities (e.g., phosphorus (P), arsenic (As), etc.). The common source semiconductor layer 180a may comprise a semiconductor material doped with impurities of a first conductivity type. In embodiments of the present invention, the first conductivity type may be p-type. For example, the common source semiconductor layer 180a may comprise p+ polysilicon (p-Si) highly doped with p-type impurities (e.g., boron (B), aluminum (Al), gallium (Ga), etc.).

[0092] The common-source semiconductor layer 180a may include a base source layer 180Ba extending in the horizontal direction (X and Y directions) between the etch stop layer 110 and the lowermost insulating layer 132 of a plurality of insulating layers 132, and a unit source layer 180Sa extending from the base source layer 180Ba and disposed in the channel hole CH between the channel layer 150 and the buried semiconductor layer 150E. For example, the common-source semiconductor layer 180a may include a base source layer 180Ba extending at substantially the same vertical height in the horizontal plane (XY plane), and a unit source layer 180Sa extending from the base source layer 180Ba and extending above and below the channel hole CH inside the channel hole CH. In other words, the unit source layer 180Sa can extend upward and downward in the vertical direction (Z direction) inside the channel hole CH. Therefore, the vertical height of the lower surface of the unit source layer 180Sa can be lower than the vertical height of the lower surface of the substrate source layer 180Ba, and the vertical height of the upper surface of the unit source layer 180Sa can be higher than the vertical height of the upper surface of the substrate source layer 180Ba.

[0093] The word line dicing region WLC can penetrate multiple insulating layers 132, multiple word line structures WL, and the common source semiconductor layer 180a. The selected wire dicing region SLC can penetrate the uppermost insulating layer 132 among the multiple insulating layers 132 and the uppermost word line structure WL among the multiple word line structures WL.

[0094] The uppermost word line structure WL, separated by the Selected Line Cutting Region SLC among multiple word line structures WL, may include a selection line SL. For two word line structures WL that are not separated by the Selected Line Cutting Region SLC but are separated by the word line cutting region WLC, the upper word line structure WL may include a first barrier line UBAa, and the lower word line structure WL may include a second barrier line LBAa.

[0095] Multiple bit lines BL electrically connected to the drain layer 170a can be arranged on multiple insulating layers 132.

[0096] When a first barrier voltage VA with a relatively low voltage is applied to the first barrier line UBAa, the channel layer 150 adjacent to the first barrier line UBAa can become a region of the first conductivity type (i.e., p-type), and when a second barrier voltage VB with a relatively high voltage is applied to the second barrier line LBAa, the channel layer 150 adjacent to the second barrier line LBAa can become a region of the second conductivity type (i.e., n-type).

[0097] The semiconductor memory device 1a can, for example, provide a relatively low voltage to the first barrier line UBAa and a relatively high voltage to the second barrier line LBAa, such that the memory cell structure MCSa forms an npnp thyristor structure. For example, a voltage of about -5V can be provided to the first barrier line UBAa and a voltage of about 5V can be provided to the second barrier line LBAa.

[0098] The semiconductor memory device 1a conceived according to the present invention allows each of the plurality of memory cell structures MCSa to have an npnp structure thyristor, thereby enabling it to be used as a DRAM capable of performing write and read operations for each of the plurality of memory cell structures MCSa respectively (e.g., performing a write operation by providing a trigger voltage, and performing a read operation for two current states (i.e., for 1 bit of stored data) by providing approximately 1 / 2 trigger voltage), and the charge carriers can be captured in the charge trapping layer 144 in contact with the channel layer 150, thus improving the retention time and memory window characteristics.

[0099] Reference Figure 15The semiconductor memory device 2 may include a common-source semiconductor layer 180 disposed on a semiconductor substrate 102, a plurality of insulating layers 132 disposed on the common-source semiconductor layer 180 and separated from each other in the vertical direction (Z direction), a plurality of word line structures WL disposed between the plurality of insulating layers 132 and separated from each other in the vertical direction (Z direction), and a plurality of memory cell structures MCS extending in the vertical direction (Z direction). For example, the plurality of insulating layers 132 and the plurality of word line structures WL may be alternately stacked on the common-source semiconductor layer 180 disposed on the semiconductor substrate 102. The memory cell dielectric layer MCD may have a substantially constant thickness and may conformally cover the inner wall of the channel via CH.

[0100] Selecting the wire cutting region SLCb allows it to penetrate the lowest insulating layer 132 of the multiple insulating layers 132 and the lowest word line structure WL of the multiple word line structures WL.

[0101] The drain layer 170 may include a semiconductor material doped with impurities of a first conductivity type (i.e., p-type), and the common source semiconductor layer 180 may include a semiconductor material doped with impurities of a second conductivity type (i.e., n-type) different from the first conductivity type (i.e., p-type).

[0102] The lowest word line structure WL, separated by the selected line cutting region SLCb, may include the selection line SLb. For two word line structures WL separated by the word line cutting region WLC instead of the selected line cutting region SLCb, the upper word line structure WL may include the first barrier line UBAb, and the lower word line structure WL may include the second barrier line LBAb.

[0103] When a first barrier voltage VA with a relatively high voltage is applied to the first barrier line UBAb, the channel layer 150 adjacent to the first barrier line UBAb can become a region of the second conductivity type (i.e., n-type), and when a second barrier voltage VB with a relatively low voltage is applied to the second barrier line LBAb, the channel layer 150 adjacent to the second barrier line LBAb can become a region of the first conductivity type (i.e., p-type).

[0104] The semiconductor memory device 2 can, for example, provide a relatively high voltage to the first barrier line UBAb and a relatively low voltage to the second barrier line LBAb, such that the memory cell structure MCS forms a pnpn thyristor. A voltage can be provided to the select line SLb that allows selection of one memory cell structure MCS from a plurality of MCSs. For example, approximately 5V can be provided to the first barrier line UBAb and approximately -5V can be provided to the second barrier line LBAb.

[0105] The semiconductor memory device 2 conceived according to the present invention allows each of the multiple memory cell structures (MCS) to have a pnpn structure thyristor, thereby enabling it to be used as a DRAM capable of performing write and read operations for each of the multiple memory cell structures (MCS) respectively (e.g., performing a write operation by providing a trigger voltage, and performing a read operation for two current states (i.e., for 1 bit of stored data) by providing approximately 1 / 2 trigger voltage), and the charge carriers can be captured in the charge trapping layer 144 in contact with the channel layer 150, thus improving retention time and memory window characteristics.

[0106] Reference Figure 16 The semiconductor memory device 2a may include a common-source semiconductor layer 180a disposed on a semiconductor substrate 102, a plurality of insulating layers 132 disposed on the common-source semiconductor layer 180a and separated from each other in the vertical direction (Z direction), a plurality of word line structures WL disposed between the plurality of insulating layers 132 and separated from each other in the vertical direction (Z direction), and a plurality of memory cell structures MCSa extending in the vertical direction (Z direction). For example, the plurality of insulating layers 132 and the plurality of word line structures WL may be alternately stacked on the common-source semiconductor layer 180a disposed on the semiconductor substrate 102. The plurality of memory cell structures MCSa may be disposed within a plurality of channel vias CH that penetrate the plurality of insulating layers 132, the plurality of word line structures WL, and the common-source semiconductor layer 180a and extend into the semiconductor substrate 102. An etch stop layer 110 may be disposed between the semiconductor substrate 102 and the common-source semiconductor layer 180a.

[0107] The memory cell dielectric layer MCD can have a substantially constant thickness and can conformally cover the inner wall of the channel via CH. The memory cell structure MCSa can include a channel layer 150 and a drain layer 170a. The channel layer 150 includes the memory cell dielectric layer MCD disposed on the channel layer 150 and covering at least a portion of the channel via CH. The drain layer 170a covers the upper surface of the channel layer 150 and fills the upper portion of the channel via CH. The memory cell structure MCSa can also include a filling insulating layer 160 filling the interior of the channel layer 150, which has a cylindrical or tubular shape. The upper surface of the channel layer 150 can contact the drain layer 170a, and the lower surface of the channel layer 150 can contact the common source semiconductor layer 180a. A buried semiconductor layer 150E can fill the lower portion of the channel via CH extending into the semiconductor substrate 102. The buried semiconductor layer 150E can be separated from the channel layer 150, and the common source semiconductor layer 180a is disposed between the buried semiconductor layer 150E and the channel layer 150.

[0108] The drain layer 170a may include a semiconductor material doped with impurities of a second conductivity type. In an embodiment of the present invention, the second conductivity type may be n-type. The common source semiconductor layer 180a may include a semiconductor material doped with impurities of a first conductivity type. In an embodiment of the present invention, the first conductivity type may be p-type.

[0109] The common source semiconductor layer 180a may include a substrate source layer 180Ba extending in the horizontal direction (X and Y directions) between the etch stop layer 110 and the lowermost insulating layer 132 of a plurality of insulating layers 132, and a unit source layer 180Sa extending from the substrate source layer 180Ba and disposed in the channel via CH between the channel layer 150 and the buried semiconductor layer 150E.

[0110] The word line dicing region WLC can penetrate multiple insulating layers 132, multiple word line structures WL, and the common source semiconductor layer 180a. The selected wire dicing region SLCb can penetrate the lowest insulating layer 132 and the lowest word line structure WL among the multiple insulating layers 132 and multiple word line structures WL.

[0111] The lowest word line structure WL, separated by the selected line cutting region SLCb, may include a selection line SLc. For two word line structures WL separated by the word line cutting region WLC instead of the selected line cutting region SLCb, the upper word line structure WL may include a first barrier line UBAc, and the lower word line structure WL may include a second barrier line LBAc.

[0112] Multiple bit lines BL electrically connected to the drain layer 170a can be arranged on multiple insulating layers 132.

[0113] When a first barrier voltage VA with a relatively low voltage is applied to the first barrier line UBAc, the channel layer 150 adjacent to the first barrier line UBAc can become a region of the first conductivity type (i.e., p-type), and when a second barrier voltage VB with a relatively high voltage is applied to the second barrier line LBAc, the channel layer 150 adjacent to the second barrier line LBAc can become a region of the second conductivity type (i.e., n-type).

[0114] The semiconductor memory device 2a can, for example, provide a relatively low voltage to the first barrier line UBIc and a relatively high voltage to the second barrier line LBAc, such that the memory cell structure MCSa forms an npnp thyristor structure. For example, a voltage of approximately -5V can be provided to the first barrier line UBIc and a voltage of approximately 5V can be provided to the second barrier line LBAc.

[0115] The semiconductor memory device 2a conceived according to the present invention allows each of the plurality of memory cell structures MCSa to have an npnp structure thyristor, thereby enabling it to be used as a DRAM capable of performing write and read operations for each of the plurality of memory cell structures MCSa respectively (e.g., performing a write operation by providing a trigger voltage, and performing a read operation for two current states (i.e., for 1 bit of stored data) by providing approximately 1 / 2 trigger voltage), and the charge carriers can be captured in the charge trapping layer 144 in contact with the channel layer 150, thus improving the retention time and memory window characteristics.

[0116] Reference Figure 17 The semiconductor memory device 3 may include a first memory stack ST1 disposed on a semiconductor substrate 102 and a second memory stack ST2 stacked on the first memory stack ST1. An etch stop layer 110 may be disposed between the semiconductor substrate 102 and the first memory stack ST1. Figure 17 The semiconductor memory device 3 is shown to include two memory stacks, a first memory stack ST1 and a second memory stack ST2, stacked on a semiconductor substrate 102. However, the inventive concept is not limited thereto. For example, the semiconductor memory device 3 may include three or more memory stacks stacked on the semiconductor substrate 102.

[0117] The first memory stack ST1 may include a plurality of first insulating layers 132 separated from each other in the vertical direction (Z direction) on the first common-source semiconductor layer 180, a plurality of first word line structures WL-1 disposed between the plurality of first insulating layers 132 and separated from each other in the vertical direction (Z direction), and a plurality of first memory cell structures MCS-1 extending in the vertical direction (Z direction). For example, the plurality of first insulating layers 132 and the plurality of first word line structures WL-1 may be alternately stacked on the first common-source semiconductor layer 180 disposed on the semiconductor substrate 102. The first memory cell dielectric layer MCD-1 may have a substantially constant thickness and may conformally cover the inner wall of the first channel via CH-1. The first memory cell dielectric layer MCD-1 may include a first stacked insulating structure 140, which includes a first gate insulating layer 142 and a first charge trapping layer 144. The first memory cell structure MCS-1 may include a first channel layer 150 and a first drain layer 170. The first channel layer 150 includes a first memory cell dielectric layer MCD-1 disposed on the first channel layer 150 and fills at least a portion of the first channel via CH-1. The first drain layer 170 covers the upper surface of the first channel layer 150 and fills a portion of the upper side of the first channel via CH-1. The first memory cell structure MCS-1 may also include a first filling insulating layer 160 filling the interior of the first channel layer 150, which has a cylindrical or tubular shape. A buried semiconductor layer 150E may fill the lower portion of the first channel via CH-1 that extends into the semiconductor substrate 102.

[0118] The first word line dicing region WLC-1 can penetrate multiple first insulating layers 132, multiple first word line structures WL-1, and the first common source semiconductor layer 180. The first selective wire dicing region SLC-1 can penetrate the uppermost first insulating layer 132 among the multiple first insulating layers 132 and the uppermost first word line structure WL-1 among the multiple first word line structures WL-1.

[0119] The uppermost first word line structure WL-1, which is separated by the first selection line cutting region SLC-1 among multiple first word line structures WL-1, can be the first selection line SL-1. For two first word line structures WL-1 that are not separated by the first selection line cutting region SLC-1 but are separated by the first word line cutting region WLC-1, the upper first word line structure WL-1 may include the first lower barrier line UBA-1, and the lower first word line structure WL-1 may include the second lower barrier line LBA-1.

[0120] Multiple bit lines BL electrically connected to the first drain layer 170 can be arranged on multiple first insulating layers 132.

[0121] The first common-source semiconductor layer 180, the first insulating layer 132, the first word line structure WL-1, the first memory cell structure MCS-1, the first memory cell dielectric layer MCD-1, the first stacked insulating structure 140, the first gate insulating layer 142, the first charge trapping layer 144, the first channel via CH-1, the first channel layer 150, the first drain layer 170, the first filling insulating layer 160, the first word line dicing region WLC-1, the first select line dicing region SLC-1, the first select line SL-1, the first lower barrier line UBA-1, and the second lower barrier line LBA-1 can be respectively connected to the referenced... Figures 1A to 1D The common-source semiconductor layer 180, insulating layer 132, word line structure WL, memory cell structure MCS, memory cell dielectric layer MCD, stacked insulating structure 140, gate insulating layer 142, charge trapping layer 144, channel hole CH, channel layer 150, drain layer 170, filling insulating layer 160, word line cut region WLC, select line cut region SLC, select line SL, first barrier line UBA and second barrier line LBA are basically the same.

[0122] The second memory stack ST2 may include a second common-source semiconductor layer 280, a second insulating layer 232, a second word line structure WL-2, a second memory cell structure MCS-2, a second memory cell dielectric layer MCD-2, a second stacked insulating structure 240, a second gate insulating layer 242, a second charge trapping layer 244, a second channel via CH-2, a second channel layer 250, a second drain layer 270, a second fill insulating layer 260, a second word line dicing region WLC-2, a second select line dicing region SLC-2, a second select line SL-2, a first upper barrier line UBA-2, and a second upper barrier line LBA-2.

[0123] The second common-source semiconductor layer 280, second insulating layer 232, second word line structure WL-2, second memory cell structure MCS-2, second memory cell dielectric layer MCD-2, second stacked insulating structure 240, second gate insulating layer 242, second charge trapping layer 244, second channel via CH-2, second channel layer 250, second drain layer 270, second fill insulating layer 260, second word line dicing region WLC-2, second select line dicing region SLC-2, second select line SL-2, first upper barrier line UBA-2 and second upper barrier line LBA-2 included in the second memory stack ST2 can be packaged with The first common-source semiconductor layer 180, first insulating layer 132, first word line structure WL-1, first memory cell structure MCS-1, first memory cell dielectric layer MCD-1, first stacked insulating structure 140, first gate insulating layer 142, first charge trapping layer 144, first channel via CH-1, first channel layer 150, first drain layer 170, first fill insulating layer 160, first word line dicing region WLC-1, first select line dicing region SLC-1, first select line SL-1, first lower barrier line UBA-1 and second lower barrier line LBA-1 included in the first memory stack ST1 are basically similar.

[0124] In the second memory stack ST2, a second drain layer 270 can be formed on a stacked structure of multiple second insulating layers 232 and multiple second word line structures WL-2, such that the second drain layer 270 fills the lower part of the second channel via CH-2 and contacts the lower surface of the second channel layer 250. In embodiments of the present invention, such as Figure 17 As shown, the second drain layer 270 of the second memory stack ST2 can be electrically connected to the bit line BL, for example, by penetrating the lowest second insulating layer 232 (and the second etch stop layer 210) of a plurality of second insulating layers 232 to be electrically connected to the bit line BL.

[0125] The semiconductor memory device 3 according to the present invention can stack multiple memory stacks including a first memory stack ST1 and a second memory stack ST2 in the vertical direction (Z direction), and can increase the capacity of data to be stored in the same area (e.g., increase the capacity of the same area that can be used to store data).

[0126] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Semiconductor substrate; A common-source semiconductor layer, doped with impurities of a first conductivity type, is disposed on a semiconductor substrate; Multiple insulating layers and multiple word line structures are alternately stacked on the common source semiconductor layer; The memory cell dielectric layer penetrates the plurality of insulating layers and the plurality of word line structures, and covers the inner wall of the vertically extending channel hole; as well as Memory cell structure, filled with channel vias, The memory cell structure includes a channel layer and a drain layer. A memory cell dielectric layer is disposed on the channel layer. The channel layer fills at least a portion of the channel via. The drain layer covers the upper surface of the channel layer and is doped with impurities of a second conductivity type, filling a portion of the upper part of the channel via. The dielectric layer of a memory cell includes a gate insulating layer covering the inner wall of the channel via and a charge trapping layer disposed between the gate insulating layer and the channel layer. The plurality of word line structures include: First line of defense; and The second barrier line is located below the first barrier line. In this configuration, a positive voltage is applied to one of the first and second barrier lines, and a negative voltage is applied to the other of the first and second barrier lines.

2. The semiconductor memory device according to claim 1, wherein, The charge trapping layer comprises a material with a higher trapping site density and capacitance than the material included in the gate insulating layer.

3. The semiconductor memory device according to claim 1, wherein, The plurality of word line structures also include: The selection line is separated into regions by the selection line extending in the first horizontal direction. Among them, the first barrier line is not separated by the selected line cutting region, and the second barrier line is not separated by the selected line cutting region.

4. The semiconductor memory device according to claim 3, wherein, The selection line is the topmost word line structure among the plurality of word line structures.

5. The semiconductor memory device according to claim 3, wherein, The selection line is the lowest word line structure among the plurality of word line structures.

6. The semiconductor memory device of claim 1, further comprising a filling semiconductor layer, in, The channel hole extends into the semiconductor substrate. The filling semiconductor layer extends the filling channel hole to the lower part of the semiconductor substrate, and The fill semiconductor layer is separate from the channel layer, and the common source semiconductor layer is arranged between the fill semiconductor layer and the channel layer.

7. The semiconductor memory device according to claim 6, wherein, The channel layer and the filling semiconductor layer include intrinsic semiconductor materials.

8. The semiconductor memory device of claim 6, further comprising a barrier insulating layer disposed between the filling semiconductor layer and the semiconductor substrate, the barrier insulating layer comprising the same material as the dielectric layer of the memory cell.

9. The semiconductor memory device of claim 1, further comprising an etch stop layer disposed between the semiconductor substrate and the common-source semiconductor layer. in, The via penetrates the plurality of insulating layers, the plurality of word line structures, and the etch stop layer.

10. The semiconductor memory device according to claim 9, wherein, The common-source semiconductor layer includes: A substrate source layer extends horizontally between the lowest insulating layer and the etch stop layer among the plurality of insulating layers; and The unit source layer extends from the substrate source layer, includes an upper surface that contacts the lower surface of the channel layer, and is disposed in the channel hole.

11. The semiconductor memory device of claim 10, wherein, The substrate source layer has an upper surface with the same vertical height as the lower surface of the lowest insulating layer among the plurality of insulating layers, and extends in the horizontal direction. The vertical height of the upper surface of the unit source layer is greater than the vertical height of the upper surface of the substrate source layer.

12. A semiconductor memory device, the semiconductor memory device comprising: Semiconductor substrate; Multiple memory cell structures, each memory cell structure including a cell source layer, a channel layer and a drain layer sequentially stacked from a semiconductor substrate in a vertical direction, and each memory cell structure having a vertical column shape extending in a vertical direction; Multiple word line structures are separated from each other in the vertical direction and surround the multiple memory cell structures; Multiple memory cell dielectric layers, each memory cell dielectric layer being placed between the channel layer of each memory cell structure and the multiple word line structures in the multiple memory cell structure; as well as Multiple bit lines, each electrically connected to the drain layer of each memory cell structure in the plurality of memory cell structures, extend in a first horizontal direction on the plurality of word line structures, and are spaced apart from each other in a second horizontal direction orthogonal to the first horizontal direction. The drain layer is doped with impurities of the first conductivity type. The source layer of the unit cell is doped with impurities of a second conductivity type, different from the first conductivity type, and Each of the plurality of memory cell dielectric layers includes a gate insulating layer covering the plurality of word line structures and a charge trapping layer disposed between the gate insulating layer and the channel layer. The plurality of word line structures include: First line of defense; and The second barrier line is located below the first barrier line. In this configuration, a positive voltage is applied to one of the first and second barrier lines, and a negative voltage is applied to the other of the first and second barrier lines.

13. The semiconductor memory device of claim 12, further comprising a substrate source layer disposed on a semiconductor substrate, wherein a cell source layer in each of the plurality of memory cell structures is connected to another cell source layer adjacent to the cell source layer, and is doped with an impurity of a second conductivity type.

14. The semiconductor memory device according to claim 13, wherein, The lower surface of the unit source layer is located at a level lower than the lower surface of the substrate source layer, and the upper surface of the unit source layer is located at a level higher than the upper surface of the substrate source layer.

15. The semiconductor memory device of claim 13, further comprising a buried insulating layer that penetrates the plurality of word line structures and the substrate source layer, extends in a second horizontal direction, and fills word line dicing regions exposed to an etch stop layer, the etch stop layer being disposed on a semiconductor substrate on a lower surface of the buried insulating layer.

16. The semiconductor memory device according to claim 12, wherein, Each of the plurality of memory cell structures includes a volatile memory device with a thyristor structure.

17. The semiconductor memory device of claim 12, further comprising a filling semiconductor layer disposed in a semiconductor substrate and including an upper surface in contact with a lower surface of a cell source layer.

18. The semiconductor memory device of claim 17, further comprising a barrier insulating layer disposed between the filled semiconductor layer and the semiconductor substrate and surrounding the side and lower surfaces of the filled semiconductor layer.

19. A semiconductor memory device, the semiconductor memory device comprising: Semiconductor substrate; An etch stop layer is disposed on a semiconductor substrate; A common-source semiconductor layer, doped with impurities of a first conductivity type, is disposed on a semiconductor substrate; Multiple insulating layers and multiple word line structures are alternately stacked on the common source semiconductor layer; The memory cell dielectric layer includes a gate insulating layer and a charge trapping layer that sequentially cover the inner walls of each of a plurality of channel holes, the plurality of channel holes penetrating the plurality of insulating layers, the plurality of word line structures and the etch stop layer in a vertical direction and extending into the semiconductor substrate; Multiple memory cell structures, each memory cell structure comprising: a filling semiconductor layer, on which a barrier insulating layer positioned separate from the memory cell dielectric layer is disposed, and the filling semiconductor layer fills a portion of the lower part of each of the multiple channel vias; a channel layer, on which the memory cell dielectric layer is disposed, the channel layer being separate from the filling semiconductor layer and a common source semiconductor layer disposed between the channel layer and the filling semiconductor layer, the channel layer filling a portion of each of the multiple channel vias, and the channel layer comprising the same material as the filling semiconductor layer; and a drain layer, covering the upper surface of the channel layer, filling a portion of the upper part of each of the multiple channel vias, and doped with an impurity of a second conductivity type different from a first conductivity type; and Multiple bit lines, each electrically connected to the drain layer of each memory cell structure in the plurality of memory cell structures, extend along the plurality of memory cell structures in a first horizontal direction and are spaced apart from each other in a second horizontal direction orthogonal to the first horizontal direction. The plurality of word line structures include: First line of defense; and The second barrier line is located below the first barrier line. In this configuration, a positive voltage is applied to one of the first and second barrier lines, and a negative voltage is applied to the other of the first and second barrier lines.

20. The semiconductor memory device of claim 19, wherein, The charge trapping layer comprises a material with a higher trapping site density and capacitance than the material included in the gate insulating layer, and The common-source semiconductor layer includes: A single-cell source layer, located in each of the plurality of channel holes, and including an upper surface in contact with the lower surface of the channel layer; and The substrate source layer connects the unit source layer to another unit source layer adjacent to the unit source layer in each of the plurality of channel holes, is disposed between the lowermost insulating layer and the etch stop layer in the plurality of insulating layers, and has an upper surface located at a vertical height lower than the vertical height of the upper surface of the unit source layer.

Images