Memory cell structure for static random access memory and memory
By employing a fin-structure transistor cell layout and optimizing wiring in static random access memory, the problems of large area occupation and high cost of SRAM memory cell structure are solved, thereby improving circuit integration and reducing cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2021-12-14
- Publication Date
- 2026-06-26
AI Technical Summary
Existing static random access memory (SRAM) cell structures occupy a large area, resulting in low circuit integration and high cost.
The transistor cell layout adopts a fin structure, including transmission transistors and common-gate complementary field-effect transistors arranged in different directions, and uses buried metal wires and top metal interconnects to optimize the power line and bit line layout, reduce wiring difficulty, and improve integration.
By compact device layout and reduced wiring complexity, area savings and cost reductions in the memory cell structure are achieved, while improving circuit integration.
Smart Images
Figure CN114300455B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a storage cell structure and memory of a static random access memory. Background Technology
[0002] Static Random-Access Memory (SRAM) is a type of random access memory. A typical SRAM cell consists of a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG). In practical applications, SRAM occupies a large circuit area, and low integration density significantly increases chip cost.
[0003] Therefore, it is necessary to provide a novel storage cell structure and memory for static random access memory to solve the above-mentioned problems existing in the prior art. Summary of the Invention
[0004] The purpose of this invention is to provide a storage cell structure and memory for a static random access memory, thereby improving the integration of the circuit and reducing manufacturing costs.
[0005] To achieve the above objectives, the storage cell structure of the static random access memory of the present invention includes a transistor cell. The transistor cell includes a first transmission transistor and a first common-gate complementary field-effect transistor (CFFET) arranged sequentially along a first direction. The transistor cell also includes a second CFFET and a second transmission transistor arranged sequentially along a second direction. The channel of the first transmission transistor is formed by a first fin structure, the channel of the first CFFET is formed by a second fin structure, the channel of the second CFFET is formed by a third fin structure, and the channel of the second transmission transistor is formed by a fourth fin structure. The first direction is parallel to the second direction.
[0006] The beneficial effects of the storage cell structure of the static random access memory are as follows: the transistor cell includes a first transmission transistor and a first common-gate complementary field-effect transistor arranged sequentially along a first direction, and the transistor cell also includes a second common-gate complementary field-effect transistor and a second transmission transistor arranged sequentially along a second direction. The channel of the first transmission transistor is formed by a first fin structure, the channel of the first common-gate complementary field-effect transistor is formed by a second fin structure, the channel of the second common-gate complementary field-effect transistor is formed by a third fin structure, and the channel of the second transmission transistor is formed by a fourth fin structure. The first direction is parallel to the second direction, resulting in a compact device arrangement that reduces the occupied area and saves manufacturing costs.
[0007] Optionally, the storage cell structure of the static random access memory further includes a connection unit, which is used to realize the internal and external connections of the transistor cell.
[0008] Optionally, the connection unit includes word lines, a first bit line, a second bit line, a first interconnect line, a second interconnect line, a first power line, and a second power line. The word lines are used to control the first transmission transistor and the second transmission transistor. The first bit line and the second bit line are used to realize signal transmission of the transistor unit. The first interconnect line and the second interconnect line are used to realize internal connection of the transistor unit. The first power line and the second power line are used to supply power to the transistor unit or ground it.
[0009] Optionally, the word line, the first bit line, the second bit line, the first interconnect line, and the second interconnect line are top-mounted metal interconnect lines of the device, and the first power line and the second power line are buried metal interconnect lines in the substrate. The advantage is that using buried metal interconnect lines reduces the difficulty of top-mounted metal wiring of the device.
[0010] Optionally, the first power line is located between the first transmission transistor and the first common-gate complementary field-effect transistor, and the second power line is located between the second transmission transistor and the second common-gate complementary field-effect transistor, with both the first and second power lines parallel to the first direction. This has the advantage of facilitating power line routing and reducing routing difficulty.
[0011] Optionally, the number of the first power lines is 2. One first power line is located at the first edge of the memory cell structure of the static random access memory, and the other first power line is located at the second edge of the memory cell structure of the static random access memory. The first edge is close to the first transmission transistor and the first common-gate complementary field-effect transistor, and the second edge is close to the second common-gate complementary field-effect transistor and the second transmission transistor. The second power line is located between the first common-gate complementary field-effect transistor and the second common-gate complementary field-effect transistor, and both the first power line and the second power line are parallel to the first direction.
[0012] Optionally, the word line, the first power line, the second power line, the first interconnect line, and the second interconnect line are top-mounted metal interconnect lines of the device, and the first bit line and the second bit line are buried metal lines in the substrate. The advantage of this is that it facilitates reducing the wiring difficulty of the bit lines.
[0013] Optionally, the first bit line is located between the first transmission transistor and the first common-gate complementary field-effect transistor, and the second bit line is located between the second transmission transistor and the second common-gate complementary field-effect transistor, with both the first bit line and the second bit line parallel to the first direction.
[0014] Optionally, the first bit line is located at the first edge or the second edge of the memory cell structure of the static random access memory, and the second bit line is located between the first common gate complementary field-effect transistor and the second common gate complementary field-effect transistor. The first edge is close to the first transmission transistor and the first common gate complementary field-effect transistor, and the second edge is close to the second transmission transistor and the second common gate complementary field-effect transistor.
[0015] Optionally, the word line, the first bit line, the second bit line, the first interconnect, the second interconnect, the first power line, and the second power line are top-mounted metal interconnects of the device.
[0016] Optionally, the first interconnect and the second interconnect are located on a first metal interconnect layer on top of the device, the word line is located on a second metal interconnect layer on top of the device, and the first bit line, the second bit line, the first power line, and the second power line are all located on a third metal interconnect layer on top of the device.
[0017] Optionally, the first interconnect and the second interconnect are located on a first metal interconnect layer on top of the device, the first bit line, the second bit line, the first power line and the second power line are all located on a second metal interconnect layer on top of the device, and the word line is located on a third metal interconnect layer on top of the device.
[0018] Optionally, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together. Its advantages are: a shared gate reduces process complexity and area, greatly improving integration density.
[0019] Optionally, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.
[0020] Optionally, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the first transmission transistor. This has the advantage of facilitating the connection between the drains of the first N-type and the first P-type field-effect transistors and the first transmission transistor, greatly improving circuit integration while reducing manufacturing complexity.
[0021] Optionally, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.
[0022] Optionally, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the second transmission transistor. This has the advantage of facilitating the connection between the drains of the second N-type and the second P-type field-effect transistors and the second transmission transistor, greatly improving circuit integration while reducing manufacturing complexity.
[0023] Optionally, the gate height of the first transmission transistor, the gate height of the first common-gate complementary field-effect transistor, the height of the second common-gate complementary field-effect transistor, and the height of the second transmission transistor are the same; the channel, source, and drain heights of the first P-type field-effect transistor and the second P-type field-effect transistor are the same; and the channel, source, and drain heights of the first N-type field-effect transistor and the second N-type field-effect transistor are the same. The advantage is that the same gate height facilitates the simultaneous formation of the gates of all transistors, greatly reducing the process complexity.
[0024] Optionally, the height of the channel, source, and drain of the first transmission transistor is the same as the height of the channel, source, and drain of at least one of the first P-type field-effect transistor and the first N-type field-effect transistor.
[0025] Optionally, the height of the channel, source, and drain of the second transmission transistor is the same as the height of the channel, source, and drain of at least one of the second P-type field-effect transistor and the second N-type field-effect transistor.
[0026] Optionally, the number of channels of the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.
[0027] Optionally, both the first transmission transistor and the second transmission transistor are field-effect transistors.
[0028] Optionally, both the first transmission transistor and the second transmission transistor are N-type field-effect transistors or P-type field-effect transistors.
[0029] Optionally, the storage cell structure of the static random access memory further includes a connection unit, which is used to realize the internal and external connections of the transistor cell.
[0030] Optionally, the gate of the first transmission transistor extends to the edge of the memory cell structure of the static random access memory, and the gate of the second transmission transistor extends to the edge of the memory cell structure of the static random access memory.
[0031] The present invention also provides a memory, including at least one storage cell structure of the static random access memory.
[0032] The beneficial effects of the aforementioned storage are as follows: the use of a static random access memory (SRAM) cell structure makes it easier to use continuous fin structures for transistors in the same direction during manufacturing, eliminating the need to cut the fin structure process, reducing process risks, lowering costs, and improving circuit integration.
[0033] Optionally, the first transmission transistors of the memory cell structures adjacent to the static random access memory in the third direction share a common gate, and the second transmission transistors of the memory cell structures adjacent to the static random access memory in the fourth direction share a common gate, wherein the third direction and the fourth direction are both perpendicular to the first direction. Attached Figure Description
[0034] Figure 1 This is a front view of the storage cell structure of a static random access memory in some embodiments of the present invention;
[0035] Figure 2 This is a rear view of the storage cell structure of a static random access memory in some embodiments of the present invention;
[0036] Figure 3 This is a left view of the storage cell structure of a static random access memory in some embodiments of the present invention;
[0037] Figure 4 This is a right view of the storage cell structure of a static random access memory in some embodiments of the present invention;
[0038] Figure 5 This is a top view of the memory cell structure of a static random access memory in some embodiments;
[0039] Figure 6This is a top view of the memory in some embodiments of the present invention;
[0040] Figure 7 This is a circuit diagram of the storage cell structure of a static random access memory in some embodiments of the present invention;
[0041] Figure 8 This is a schematic diagram of the structure of a two-channel field-effect transistor in some embodiments of the present invention;
[0042] Figure 9 This is a schematic diagram of a finned structure in some embodiments of the present invention. Detailed Implementation
[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.
[0044] To address the problems existing in the prior art, embodiments of the present invention provide a memory, the memory including a storage cell structure of at least one static random access memory.
[0045] In some embodiments, the storage cell structure of the static random access memory includes transistor cells and connection cells.
[0046] Figure 1 This is a front view of the storage cell structure of a static random access memory in some embodiments of the present invention. Figure 2 This is a rear view of the storage cell structure of a static random access memory in some embodiments of the present invention. Figure 3 This is a left view of the storage cell structure of a static random access memory in some embodiments of the present invention. Figure 4 This is a right view of the memory cell structure of a static random access memory in some embodiments of the present invention. (Refer to...) Figures 1 to 4The storage cell structure of the static random access memory includes a transistor cell. The transistor cell includes a first transmission transistor 101 and a first common-gate complementary field-effect transistor 102 arranged sequentially along a first direction. The transistor cell also includes a second common-gate complementary field-effect transistor 103 and a second transmission transistor 104 arranged sequentially along a second direction. The channel of the first transmission transistor 101 is formed by a first fin structure, the channel of the first common-gate complementary field-effect transistor 102 is formed by a second fin structure, the channel of the second common-gate complementary field-effect transistor 103 is formed by a third fin structure, and the channel of the second transmission transistor 104 is formed by a fourth fin structure. The first direction is parallel to the second direction.
[0047] In some embodiments, the storage cell structure of the static random access memory further includes a connection unit, which is used to realize internal and external connections of the transistor cells.
[0048] Reference Figures 1 to 4 The connection unit includes a word line 201, a first bit line 202, a second bit line 203, a first interconnect line 204, a second interconnect line 205, a first power line 206, and a second power line 207. The number of first power lines 206 is two. The word line 201 controls the first transmission transistor 101 and the second transmission transistor 104. The first bit line 202 and the second bit line 203 are used for signal transmission. The first interconnect line 204 and the second interconnect line 205 are used for internal connections of the transistor unit. The first power line 206 and the second power line 207 are used to supply power to or ground the transistor unit. The first bit line 202, the second bit line 203, the first power line 206, and the second power line 207 are all parallel to the first direction, and the word line 201, the first interconnect line 204, and the second interconnect line 205 are all perpendicular to the first direction. The first power line is grounded, and the second power line is connected to the operating voltage.
[0049] In some embodiments, both the first transmission transistor and the second transmission transistor are field-effect transistors (FETs). In other embodiments, both the first transmission transistor and the second transmission transistor are N-type FETs or P-type FETs.
[0050] Reference Figures 1 to 4The first bit line 202 is connected to the first end of the first transmission transistor 101, and the second bit line 203 is connected to the first end of the second transmission transistor 104. The word line is connected to the gate of the first transmission transistor 101 and the gate of the second transmission transistor 104 through a metal via. The first interconnect line is connected to the second end of the first transmission transistor 101, the two drains of the first common-gate complementary field-effect transistor 102, and the gate of the second common-gate complementary field-effect transistor 103 through a metal via. The second interconnect line is connected to the second end of the second transmission transistor 104 and the gate of the second common-gate complementary field-effect transistor 103 through a metal via. The two drains of transistor 103 are connected to the gate of the first common-gate complementary field-effect transistor 102. One first power line 206 is connected to the source of the N-type field-effect transistor of the first common-gate complementary field-effect transistor 102 through a metal via. Another first power line 206 is connected to the source of the N-type field-effect transistor of the second common-gate complementary field-effect transistor 103 through a metal via. The second power line 207 is connected to the source of the P-type field-effect transistor of the first common-gate complementary field-effect transistor 102 and the source of the P-type transistor of the second common-gate complementary field-effect transistor 103 through a metal via.
[0051] In some embodiments, both the first and second transmission transistors are N-type field-effect transistors. In other embodiments, both the first and second transmission transistors are P-type field-effect transistors.
[0052] In some embodiments, the gate of the first transmission transistor extends to the edge of the memory cell structure of the static random access memory, and the gate of the second transmission transistor extends to the edge of the memory cell structure of the static random access memory.
[0053] In some embodiments, the first end of the first transmission tube is the drain, and the second end of the first transmission tube is the source.
[0054] In some embodiments, the first end of the first transmission tube is the source, and the second end of the first transmission tube is the drain.
[0055] In some embodiments, the first end of the second transmission tube is the drain, and the second end of the second transmission tube is the source.
[0056] In some embodiments, the first end of the second transmission tube is the source, and the second end of the second transmission tube is the drain.
[0057] In some embodiments, the storage cell structure of the static random access memory further includes a connection unit, which is used to realize internal and external connections of the transistor cell.
[0058] In some embodiments, the connection unit includes word lines, first bit lines, second bit lines, first interconnect lines, second interconnect lines, first power lines, and second power lines. The word lines are used to control the first transmission transistor and the second transmission transistor. The first bit lines and the second bit lines are used to realize signal transmission of the transistor unit. The first interconnect lines and the second interconnect lines are used to realize internal connections of the transistor unit. The first power lines and the second power lines are used to supply power to the transistor unit or ground it.
[0059] Optionally, the word line, the first bit line, the second bit line, the first interconnect line, and the second interconnect line are top-mounted metal interconnect lines of the device, and the first power line and the second power line are buried metal lines in the substrate.
[0060] In some embodiments, the first power line is located between the first transmission transistor and the first common-gate complementary field-effect transistor, the second power line is located between the second transmission transistor and the second common-gate complementary field-effect transistor, and both the first power line and the second power line are parallel to the first direction.
[0061] In some embodiments, the number of first power lines is two. One first power line is located at a first edge of the memory cell structure of the static random access memory (SRAM), and the other first power line is located at a second edge of the memory cell structure of the SRAM. The first edge is close to the first transmission transistor and the first common-gate complementary field-effect transistor (CFET), and the second edge is close to the second common-gate complementary field-effect transistor and the second transmission transistor. The second power line is located between the first CFET and the second CFET, and both the first power line and the second power line are parallel to the first direction.
[0062] In some embodiments, the word line, the first power line, the second power line, the first interconnect, and the second interconnect are top-mounted metal interconnects of the device, and the first bit line and the second bit line are buried metal lines in the substrate.
[0063] In some embodiments, the first bit line is located between the first transmission transistor and the first common-gate complementary field-effect transistor, and the second bit line is located between the second transmission transistor and the second common-gate complementary field-effect transistor, with both the first bit line and the second bit line parallel to the first direction.
[0064] In some embodiments, the first bit line is located at a first edge or a second edge of the memory cell structure of the static random access memory, and the second bit line is located between the first common gate complementary field-effect transistor and the second common gate complementary field-effect transistor. The first edge is close to the first transmission transistor and the first common gate complementary field-effect transistor, and the second edge is close to the second transmission transistor and the second common gate complementary field-effect transistor.
[0065] In some embodiments, the word line, the first bit line, the second bit line, the first interconnect, the second interconnect, the first power line, and the second power line are top-mounted metal interconnects of the device.
[0066] In some embodiments, the first interconnect and the second interconnect are located on a first metal interconnect layer on top of the device, the word line is located on a second metal interconnect layer on top of the device, and the first bit line, the second bit line, the first power line, and the second power line are all located on a third metal interconnect layer on top of the device.
[0067] In some embodiments, the first interconnect and the second interconnect are located on a first metal interconnect layer on top of the device, the first bit line, the second bit line, the first power line and the second power line are all located on a second metal interconnect layer on top of the device, and the word line is located on a third metal interconnect layer on top of the device.
[0068] Reference Figures 1 to 4 The first interconnect 204 and the second interconnect 205 are located on the first metal interconnect layer on top of the device, the word line 201 is located on the second metal interconnect layer on top of the device, and the first bit line 202, the second bit line 203, the first power line 206 and the second power line 207 are all located on the third metal interconnect layer on top of the device.
[0069] In some embodiments, the first transmission transistors of the memory cell structures adjacent to the third direction of the static random access memory share a common gate, and the second transmission transistors of the memory cell structures adjacent to the third direction of the static random access memory share a common gate, wherein both the third direction and the fourth direction are perpendicular to the first direction.
[0070] In some embodiments, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together.
[0071] In some embodiments, the first N-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked on top of the first P-type field-effect transistor. In still other embodiments, the first P-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked on top of the first N-type field-effect transistor.
[0072] In some embodiments, the second N-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked on top of the second P-type field-effect transistor. In still other embodiments, the second P-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked on top of the second N-type field-effect transistor.
[0073] In some embodiments, the first transmission transistor, the first common-gate complementary field-effect transistor, the second common-gate complementary field-effect transistor, and the second transmission transistor share the same substrate, and the gate heights of the first transmission transistor, the first common-gate complementary field-effect transistor, the second common-gate complementary field-effect transistor, and the second transmission transistor are the same. The channel, source, and drain of the first P-type field-effect transistor and the second P-type field-effect transistor are at the same height, and the channel, source, and drain of the first N-type field-effect transistor and the second N-type field-effect transistor are at the same height.
[0074] In some embodiments, the height of the channel, source, and drain of the first transmission transistor is the same as the height of the channel, source, and drain of at least one of the first P-type field-effect transistor and the first N-type field-effect transistor.
[0075] In some embodiments, the height of the channel, source, and drain of the second transmission transistor is the same as the height of the channel, source, and drain of at least one of the second P-type field-effect transistor and the second N-type field-effect transistor.
[0076] Reference Figures 1 to 4 The gate heights of the first transmission transistor 101, the first common-gate complementary field-effect transistor 102, the second common-gate complementary field-effect transistor 103, and the second transmission transistor 104 are the same.
[0077] Reference Figures 1 to 4 The first N-type field-effect transistor 1021 and the second N-type field-effect transistor 1031 are located at the same height, and the first P-type field-effect transistor 1022 and the second P-type field-effect transistor 1032 are located at the same height.
[0078] In some embodiments, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.
[0079] In some embodiments, the drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the first transmission transistor.
[0080] In some embodiments, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.
[0081] In some embodiments, the drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the second transmission transistor.
[0082] Reference Figures 1 to 4 The drain of the first P-type field-effect transistor 1022 faces the source of the first transmission transistor 101. The drain of the first N-type field-effect transistor 1021 and the drain of the first P-type field-effect transistor 1022 are located on the same side of the gate of the first common-gate complementary field-effect transistor 102. The drain of the second P-type field-effect transistor 1032 faces the source of the second transmission transistor 104. The drain of the second N-type field-effect transistor 1031 and the drain of the second P-type field-effect transistor 1032 are located on the same side of the gate of the second common-gate complementary field-effect transistor 103.
[0083] Reference Figure 1 and Figure 2 A gate dielectric layer 105 is provided between the channel and gate of the first transmission transistor 101, the second transmission transistor 104, the first N-type field-effect transistor 1021, the first P-type field-effect transistor 1022, the second N-type field-effect transistor 1031, and the second P-type field-effect transistor 1032.
[0084] Figure 5 This is a top view of the memory cell structure of a static random access memory in some embodiments. (Refer to...) Figure 5The word line 201 is located between the first interconnect line 204 and the second interconnect line 205, and the word line 201, the first interconnect line 204 and the second interconnect line 205 are parallel to each other. The first power line 206, the first bit line 202, the second bit line 203 and the first power line 206 are arranged sequentially and are parallel to each other.
[0085] Reference Figure 5 The gate of the first transmission transistor 101 and the gate of the second transmission transistor 104 both extend to the boundary of the transistor unit.
[0086] Figure 6 This is a top view of the memory in some embodiments of the present invention. (Refer to...) Figure 6 The storage cell structure of a row of static random access memory shares a word line 201, and the storage cell structure of a column of static random access memory shares a first bit line 202, a second bit line 203, two first power lines 206, and a second power line 207.
[0087] In some embodiments, the number of channels of the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.
[0088] Figure 7 This is a circuit schematic diagram of the storage cell structure of a static random access memory in some embodiments of the present invention. (Refer to...) Figure 7 Field-effect transistor PD1 is equivalent to the first N-type field-effect transistor, field-effect transistor PD2 is equivalent to the second N-type field-effect transistor, field-effect transistor PG1 is equivalent to the first transmission transistor, field-effect transistor PG2 is equivalent to the second transmission transistor, field-effect transistor PU1 is equivalent to the first P-type field-effect transistor, P-type field-effect transistor PU2 is equivalent to the second P-type field-effect transistor, bit line BL is equivalent to the first bit line, and bit line BLB is equivalent to the second bit line.
[0089] In some embodiments, the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor can all be referred to as field-effect transistors. When the number of channels of a field-effect transistor is greater than or equal to 2, the sources of all channels are epitaxially grown together to form the source of the transistor, and the drains of all channels are epitaxially grown together to form the drain of the field-effect transistor.
[0090] In some other embodiments, when the number of channels of a field-effect transistor is greater than or equal to 2, the sub-sources of all channels are interconnected by metal to form the source of the transistor, and the sub-drains of all channels are interconnected by metal to form the drain of the field-effect transistor.
[0091] Figure 8 This is a schematic diagram of the structure of a two-channel field-effect transistor in some embodiments of the present invention. (Refer to...) Figure 5 The field-effect transistor includes two channels 301, a gate 302, a source 303, a drain 304, a gate dielectric layer 105, and a substrate (not shown in the figure). The sub-sources 3031 of the two channels are interconnected by a first metal 3032 to form the source 303 of the field-effect transistor, and the sub-drains 3041 of the two channels are interconnected by a second metal 3042 to form the drain 304 of the field-effect transistor. The gate dielectric layer 105 is disposed between the channel 301 and the gate.
[0092] Figure 9 This is a schematic diagram of the fin structure in some embodiments of the present invention. Referring to 9, the channel of the first transmission transistor 101 is formed by a first fin structure 106, the channel of the first common-gate complementary field-effect transistor 102 is formed by a second fin structure 107, the channel of the second common-gate complementary field-effect transistor 103 is formed by a third fin structure 108, and the channel of the second transmission transistor 104 is formed by a fourth fin structure 109. The first fin structure 106, the second fin structure 107, the third fin structure 108, and the fourth fin structure 109 do not intersect each other.
[0093] In some embodiments, the shape of the metal via is not limited in any way, as long as it enables the connection between the source, drain, gate, word line, first bit line, second bit line, first interconnect, second interconnect, first power line, and second power line. In this application, the directions of the word line, first bit line, second bit line, first interconnect, second interconnect, first power line, and second power line all refer to the extension direction of their longest portions.
[0094] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A storage cell structure for a static random access memory, characterized in that, The device includes a transistor unit comprising a first transmission transistor and a first common-gate complementary field-effect transistor (CFFET) arranged sequentially along a first direction. The transistor unit also includes a second CFFET and a second transmission transistor arranged sequentially along a second direction. The channel of the first transmission transistor is formed by a first fin structure, the channel of the first CFFET is formed by a second fin structure, the channel of the second CFFET is formed by a third fin structure, and the channel of the second transmission transistor is formed by a fourth fin structure. The first direction is parallel to the second direction. The first fin structure, the second fin structure, the third fin structure, and the fourth fin structure do not intersect each other and are parallel but not collinear.
2. The storage cell structure of the static random access memory according to claim 1, characterized in that, It also includes a connection unit, which is used to realize the internal and external connections of the transistor unit.
3. The storage cell structure of the static random access memory according to claim 2, characterized in that, The connection unit includes word lines, first bit lines, second bit lines, first interconnect lines, second interconnect lines, first power lines, and second power lines. The word lines are used to control the first transmission transistor and the second transmission transistor. The first bit lines and the second bit lines are used to realize signal transmission of the transistor unit. The first interconnect lines and the second interconnect lines are used to realize the internal connection of the transistor unit. The first power lines and the second power lines are used to supply power to the transistor unit or ground it.
4. The storage cell structure of the static random access memory according to claim 3, characterized in that, The word line, the first bit line, the second bit line, the first interconnect line, and the second interconnect line are metal interconnect lines on the top of the device, and the first power line and the second power line are buried metal lines in the substrate.
5. The storage cell structure of the static random access memory according to claim 4, characterized in that, The first power line is located between the first transmission transistor and the first common-gate complementary field-effect transistor, and the second power line is located between the second transmission transistor and the second common-gate complementary field-effect transistor, and both the first power line and the second power line are parallel to the first direction.
6. The storage cell structure of the static random access memory according to claim 4, characterized in that, The number of first power lines is 2. One first power line is located at the first edge of the memory cell structure of the static random access memory, and the other first power line is located at the second edge of the memory cell structure of the static random access memory. The first edge is close to the first transmission transistor and the first common gate complementary field-effect transistor, and the second edge is close to the second common gate complementary field-effect transistor and the second transmission transistor. The second power line is located between the first common gate complementary field-effect transistor and the second common gate complementary field-effect transistor, and both the first power line and the second power line are parallel to the first direction.
7. The storage cell structure of the static random access memory according to claim 3, characterized in that, The word line, the first power line, the second power line, the first interconnect line, and the second interconnect line are metal interconnect lines on the top of the device, and the first bit line and the second bit line are buried metal lines in the substrate.
8. The storage cell structure of the static random access memory according to claim 7, characterized in that, The first bit line is located between the first transmission transistor and the first common-gate complementary field-effect transistor, and the second bit line is located between the second transmission transistor and the second common-gate complementary field-effect transistor. Both the first bit line and the second bit line are parallel to the first direction.
9. The storage cell structure of the static random access memory according to claim 7, characterized in that, The first bit line is located at the first edge or the second edge of the memory cell structure of the static random access memory, and the second bit line is located between the first common gate complementary field-effect transistor and the second common gate complementary field-effect transistor. The first edge is close to the first transmission transistor and the first common gate complementary field-effect transistor, and the second edge is close to the second transmission transistor and the second common gate complementary field-effect transistor.
10. The storage cell structure of the static random access memory according to claim 3, characterized in that, The word line, the first bit line, the second bit line, the first interconnect line, the second interconnect line, the first power line, and the second power line are top metal interconnect lines of the device.
11. The storage cell structure of the static random access memory according to claim 10, characterized in that, The first interconnect and the second interconnect are located on the first metal interconnect layer on top of the device, the word line is located on the second metal interconnect layer on top of the device, and the first bit line, the second bit line, the first power line and the second power line are all located on the third metal interconnect layer on top of the device.
12. The storage cell structure of the static random access memory according to claim 10, characterized in that, The first interconnect and the second interconnect are located on the first metal interconnect layer on top of the device. The first bit line, the second bit line, the first power line and the second power line are all located on the second metal interconnect layer on top of the device. The word line is located on the third metal interconnect layer on top of the device.
13. The storage cell structure of the static random access memory according to claim 1, characterized in that, The first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked together, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked together.
14. The storage cell structure of the static random access memory according to claim 13, characterized in that, The drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the source of the first N-type field-effect transistor and the source of the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.
15. The storage cell structure of the static random access memory according to claim 14, characterized in that, The drain of the first N-type field-effect transistor and the drain of the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the first transmission transistor.
16. The storage cell structure of the static random access memory according to claim 13, characterized in that, The drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the source of the second N-type field-effect transistor and the source of the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.
17. The storage cell structure of the static random access memory according to claim 16, characterized in that, The drain of the second N-type field-effect transistor and the drain of the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the second transmission transistor.
18. The storage cell structure of the static random access memory according to claim 13, characterized in that, The gate height of the first transmission transistor, the gate height of the first common-gate complementary field-effect transistor, the height of the second common-gate complementary field-effect transistor, and the height of the second transmission transistor are the same. The channel, source, and drain of the first P-type field-effect transistor and the second P-type field-effect transistor are at the same height. The channel, source, and drain of the first N-type field-effect transistor and the second N-type field-effect transistor are at the same height.
19. The storage cell structure of the static random access memory according to claim 18, characterized in that, The height of the channel, source, and drain of the first transmission transistor is the same as the height of the channel, source, and drain of at least one of the first P-type field-effect transistor and the first N-type field-effect transistor.
20. The storage cell structure of the static random access memory according to claim 18, characterized in that, The height of the channel, source, and drain of the second transmission transistor is the same as the height of the channel, source, and drain of at least one of the second P-type field-effect transistor and the second N-type field-effect transistor.
21. The storage cell structure of the static random access memory according to claim 13, characterized in that, The number of channels of the first transmission transistor, the second transmission transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1.
22. The storage cell structure of the static random access memory according to claim 1, characterized in that, Both the first transmission transistor and the second transmission transistor are field-effect transistors.
23. The storage cell structure of the static random access memory according to claim 22, characterized in that, Both the first transmission transistor and the second transmission transistor are N-type field-effect transistors or P-type field-effect transistors.
24. The storage cell structure of the static random access memory according to claim 1, characterized in that, The gate of the first transmission transistor extends to the edge of the memory cell structure of the static random access memory, and the gate of the second transmission transistor extends to the edge of the memory cell structure of the static random access memory.
25. A memory, characterized in that, It includes at least one storage cell structure of a static random access memory as described in any one of claims 1 to 24.
26. The memory according to claim 25, characterized in that, In the third direction, the first transmission transistors of the adjacent memory cell structures of the static random access memory share a common gate, and in the fourth direction, the second transmission transistors of the adjacent memory cell structures of the static random access memory share a common gate. Both the third and fourth directions are perpendicular to the first direction.