Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate and a transistor arranged on one side of the substrate. The transistor comprises an active layer, a gate and a channel region. The active layer comprises a source region and a drain region respectively arranged on both sides of the channel region in a first direction. The gate is arranged on the side of the active layer away from the substrate, and the orthographic projection of the gate on the substrate at least partially overlaps the orthographic projection of the channel region on the substrate. The channel region comprises a first region and a second region arranged on the first region along the first direction. The orthographic projection of the second region and the first region on the substrate overlaps the orthographic projection of the gate on the substrate. The charging capacity of the TFT device can be significantly improved, the screen frame is narrow, and the TFT device can be quickly charged, thereby not affecting the driving capacity of each pixel circuit and meeting the increasing demand for the super-high frequency capacity of the screen.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and liquid crystal display (LCD) are still the focus of current display research field. The driving circuit area accounts for a large proportion in the existing array substrate of OLED and LCD, which is difficult to meet the needs of narrow frame in the field of screen. SUMMARY

[0003] The present application provides an array substrate, a display panel and a display device, which can improve the stability of the gate potential of the driving transistor and improve the display effect.

[0004] In a first aspect, an array substrate is provided, comprising a substrate and a transistor disposed on one side of the substrate, the transistor comprising:

[0005] an active layer comprising a channel region and a source region and a drain region respectively located on both sides of the channel region in a first direction;

[0006] a gate located on a side of the active layer away from the substrate, and a projection of the gate on the substrate at least partially overlaps with a projection of the channel region on the substrate;

[0007] the channel region comprises a first region and a second region disposed on the first region along the first direction, and a projection of the second region and the first region on the substrate overlaps with a projection of the gate on the substrate.

[0008] In a second aspect, based on the same inventive concept, a display panel is provided, comprising the array substrate of the first aspect.

[0009] In a third aspect, based on the same inventive concept, a display device is provided, comprising the display panel of the second aspect.

[0010] According to the array substrate, the display panel and the display device provided by the embodiments of the present application, on the one hand, the channel region and / or the gate of the TFT (Thin Film Transistor) device at the frame of the array substrate is designed in a special shape, so that the coverage area of the gate in the channel region is significantly increased, and in the case of meeting the same charging capacity, the TFT device can be compressed in the extension direction of the gate and the width direction of the channel region, so as to meet the demand of the narrow frame structure; on the other hand, the coverage area of the gate in the channel region is increased, so that the charging capacity of the obtained TFT device is significantly improved, and the TFT device can also be quickly charged under the condition of meeting the small area ratio, so as to not affect the driving effect of each pixel circuit, and meet the increasing demand for the ultra-high frequency capacity of the screen. BRIEF DESCRIPTION OF DRAWINGS

[0011] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-restrictive embodiments, with reference to the attached drawings, in which the same or similar reference signs refer to the same or similar features, and the drawings are not drawn to scale.

[0012] Figure 1 A cross-sectional structure schematic diagram of a transistor provided by an embodiment of the present application is shown;

[0013] Figure 2 A top view structure schematic diagram of a transistor provided by an embodiment of the present application is shown;

[0014] Figure 3 A top view structure schematic diagram of a transistor provided by another embodiment of the present application is shown;

[0015] Figure 4 A top view structure schematic diagram of a second region provided by an embodiment of the present application is shown;

[0016] Figure 5 A top view structure schematic diagram of a second region provided by another embodiment of the present application is shown;

[0017] Figure 6 A top view structure schematic diagram of a second region provided by another embodiment of the present application is shown;

[0018] Figure 7 A top view structure schematic diagram of a second region provided by another embodiment of the present application is shown;

[0019] Figure 8 A top view structure schematic diagram of a transistor provided by another embodiment of the present application is shown;

[0020] Figure 9 A top view structure schematic diagram of a transistor provided by another embodiment of the present application is shown;

[0021] Figure 10 A top view of an array substrate provided by an embodiment of the present application is shown in FIG. 1;

[0022] Figure 11 An enlarged structure diagram of the area A is shown in FIG. 2; Figure 10 An enlarged structure diagram of the area A is shown in FIG. 2;

[0023] Figure 12 A structure diagram of a display panel provided by an embodiment of the present application is shown in FIG. 3;

[0024] Figure 13 A structure diagram of a display device provided by an embodiment of the present application is shown in FIG. 4.

[0025] In the drawings:

[0026] 11, transistor; 12, active layer; 121, source region; 122, drain region; 123, channel region; 1231, first region; 1232, second region; 13, gate; 131, first part; 132, second part; 14, source electrode; 15, drain electrode; 16, substrate;

[0027] 10, array substrate; 101, first region; 102, second region; 104, data line; 105, scan line; 106, first electrode; 107, first control signal line; 108, second control signal line; 3, driving chip;

[0028] 100, display panel; 200, display device. DETAILED DESCRIPTION

[0029] The features and exemplary embodiments of various aspects of the present application will be described below in detail, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application, and are not configured to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0030] It should be noted that in this paper, relational terms such as first and second, and the like are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations.

[0031] It should be understood that when describing the structure of a component, when a layer, a region is referred to as being located "on" or "above" another layer, another region, it can be directly located above the other layer, the other region, or other layers or regions are also included between it and the other layer, the other region. And if the component is turned over, the layer, the region will be located "under" or "below" the other layer, the other region.

[0032] As shown in the example, Figures 2-4 The first direction referred to by the embodiments of the present application is the x-axis direction in the figure, and the second direction referred to by the embodiments of the present application is the y-axis direction in the figure.

[0033] The embodiments of the present application provide an array substrate, a display panel and a display device, which will be described below in conjunction with the accompanying drawings.

[0034] In some embodiments of the present application, optionally, as shown in Figure 1 and Figure 2 As shown in the example, Figure 1 a cross-sectional structure schematic diagram of a transistor 11 provided by an embodiment of the present application is shown, Figure 2 a top view structure schematic diagram of the transistor 11 provided by an embodiment of the present application is shown. The provided array substrate 10 includes a substrate 16 and a transistor 11 disposed on one side of the substrate 16, and the transistor 11 includes an active layer 12 and a gate 13. The active layer 12 includes a channel region 123 and a source region 121 and a drain region 122 respectively located on both sides of the channel region 123 in a first direction. The gate 13 is located on the side of the active layer 12 away from the substrate 16, and the orthogonal projection of the gate 13 on the substrate 16 at least partially overlaps the orthogonal projection of the channel region 123 on the substrate 16. The channel region 123 includes a first region 1231 and a second region 1232 disposed on the first region 1231 in the first direction, and the orthogonal projection of the second region 1232 and the first region 1231 on the substrate 16 overlaps the orthogonal projection of the gate 13 on the substrate 16.

[0035] In the display field, how to improve the screen ratio of the display is a direct means to improve the display ability of the display, and is also a key point in the field that is constantly seeking breakthroughs. With the continuous iteration and upgrading of products, the screen is also pursuing an extreme narrow frame. The existing narrow frame design usually needs to give a larger area to the pixel circuit, so that the transistor 11 device area at the frame is continuously compressed. As an example, in the perpendicular row direction and column direction, the transistor 11 device is severely limited, resulting in insufficient charging capacity of the transistor 11, causing the display effect to decline, and also failing to meet the pursuit of the screen for overclocking ability.

[0036] It can be understood that the transistor 11 can be a thin film transistor 11, an insulated gate field effect transistor 11 mainly composed of a conductive layer and a semiconductor layer, the conductive layer including a gate 13 layer and a source-drain layer, and the semiconductor layer being spaced apart from the gate 13 layer and the gate 13 layer being spaced apart from the source-drain layer by an insulating layer respectively. The semiconductor layer includes an active layer 12, the gate 13 layer includes a gate 13, and the gate 13 is arranged corresponding to a channel region 123 in the active layer 12. The source-drain layer includes a source line and a drain line, the source line is electrically connected with a source region 121, and the drain line is electrically connected with a drain region 122.

[0037] After a voltage is applied to the gate 13, a channel for carrier migration is formed in the active layer 12. Specifically, during the operation of the transistor 11, the gate 13 is applied with a voltage and generates an electric field, the direction of the electric field is from the gate 13 to the surface of the channel region 123 of the active layer 12, and an induced charge is generated at the surface. As the voltage of the gate 13 increases, the surface of the channel region 123 will change from a depletion layer to an electron accumulation layer, forming an inversion layer. When the voltage of the gate 13 reaches a threshold voltage, the voltage applied between the source region 121 and the drain region 122 will cause carriers to pass through the channel region 123.

[0038] It should be noted that, in terms of structure, the transistor 11 provided by the embodiment of the present application can be a back channel etching type thin film transistor 11, or an etching stop type thin film transistor 11. In terms of material, the transistor 11 provided by the embodiment of the present application can be an N-type thin film transistor 11, or a P-type thin film transistor 11. Among them, the N-type thin film transistor 11 refers to that the active layer 12 of the transistor 11 is doped with N-type ions, and the P-type thin film transistor 11 refers to that the active layer 12 of the transistor 11 is doped with P-type ions. In terms of the position of the gate 13, the transistor 11 provided by the embodiment of the present application can be a bottom gate type thin film transistor 11, or a top gate type thin film transistor 11.

[0039] As can be known from the foregoing, the gate 13 forms an electric field by applying a voltage, and then forms an inversion layer in the channel region 123. When the voltage of the gate 13 reaches a threshold voltage, the voltage applied between the source region 121 and the drain region 122 will cause carriers to pass through the channel region 123.

[0040] It can be understood that, according to the driving current formula of the transistor 11, as follows:

[0041]

[0042] Among them, Ids is the driving current of the transistor 11, W is the channel width; L is the distance of the channel region 123 in the second direction; μ is the electron mobility; ε is the dielectric constant of the gate insulating layer; d is the thickness of the gate insulating layer; Vg is the voltage of the gate 13; Vth is the threshold voltage.

[0043] It can be seen that the driving current of the thin film transistor 11 can be changed by changing the aforementioned parameters of the transistor 11, and the charging capacity of the transistor 11 is improved, and the performance of the transistor 11 is improved. However, considering that some of the parameters are the physical and chemical properties of the materials used in the manufacture of the transistor 11 or the prerequisites for the operation of the transistor 11, it is difficult to adjust in actual operation, such as electron mobility, dielectric constant of the gate insulating layer, thickness of the gate insulating layer, gate 13 voltage, threshold voltage. Therefore, in the process of improving the performance of the transistor 11 by changing the driving circuit, the ratio between the channel width W and the distance L of the channel region 123 in the second direction is usually adjusted in actual operation, such as increasing the channel width W to increase the driving current Ids of the transistor 11, or reducing the distance L of the channel region 123 in the second direction to increase the driving current Ids of the transistor 11. However, considering that increasing the channel width W will increase the overall length of the transistor 11, thereby reducing the aperture ratio of the resulting display device, in actual production, the distance L of the channel region 123 in the second direction is often considered to achieve the purpose, but in actual production, reducing the distance L of the channel region 123 in the second direction on the basis of the existing process requires complex structures such as compression spacing, film layer covering, etc. The difficulty of actual operation is high and difficult to implement.

[0044] In the following, the transistor 11 provided by the embodiment of the present application is arranged at the screen frame as an example for specific description. It can be understood that the transistor 11 provided by the present application can also be directly used in the pixel circuit in the screen display area, so that the charging capacity of the pixel circuit is significantly improved under the premise of maintaining the space ratio of the transistor 11 in the existing screen, and the screen overclocking work is facilitated.

[0045] Referring to Figure 2 , Figure 2 A top view structural schematic diagram of the transistor 11 provided by an embodiment of the present application is shown. In the second direction, the source region 121 and the drain region 122 are arranged opposite to each other on both sides of the gate 13, and the gate 13 overlaps the channel region 123 and extends in the first direction. In the first direction, the second region 1232 is additionally arranged in the channel region 123, which changes the proportion of the channel region 123 in the first direction. By fully utilizing the structure of the existing gate 13, the width of the overlapping part of the gate 13 and the channel region 123 can be increased to increase the channel width W, thereby increasing the driving current Ids, and improving the driving capacity of the existing array substrate 10, that is Figure 2As shown in the figure, W1+W>W. And only the channel region 123 is changed in the foregoing structure, and the main structure such as the gate 13, the source region 121 and the drain region 122 is not changed, which can be applied to the transistor 11 main structure which cannot be adjusted. In actual production, the first region 1231 and the second region 1232 can also be formed at the same time by the same process, which does not affect the existing process and is convenient for actual operation.

[0046] It should be noted that the structure of the first region 1231 can adopt the existing structure, which is laid between the source region 121 and the drain region 122 and overlaps with them. The second region 1232 can be formed by continuing to extend the first region 1231 along the first direction, that is, the second region 1232 overlaps with the source region 121 and the drain region 122. Alternatively, the second region 1232 can be formed by partially protruding and extending the first region 1231 along the first direction, that is, the second region 1232 does not overlap with the source region 121 and the drain region 122. The present application does not limit this.

[0047] In some embodiments of the present application, as shown in the figure, Figure 2 Figure 2 The figure shows a top view structural schematic diagram of the transistor 11 provided by an embodiment of the present application. The source region 121 and the drain region 122 overlap with the first region 1231 in the second direction, and the source region 121 and the drain region 122 are staggered with the second region 1232 in the second direction.

[0048] Among them, in the second direction, the source region 121 and the drain region 122 are arranged on the two sides of the gate 13, the first region 1231 is arranged between the source region 121 and the drain region 122 and overlaps with the gate 13, and the second region 1232 is arranged on the two sides of the first region 1231 in the first direction and overlaps with the gate 13 and does not overlap with the source region 121 and the drain region 122. Not limited, the second region 1232 can be integrally formed with the first region 1231, or can be separately arranged.

[0049] Through the arrangement that the second region 1232 is staggered with the source region 121 and the drain region 122 in the second direction, the second region 1232 can be made to avoid overlapping with the source region 121 and the drain region 122 as much as possible, reducing the influence on the transistor 11 architecture and avoiding the generation of additional parasitic capacitance, such as the parasitic capacitance generated between the second region 1232 and the source electrode 14 and the drain electrode 15.

[0050] In some embodiments of the present application, as shown in the figure, Figure 2 Figure 2 The figure shows a top view structural schematic diagram of the transistor 11 provided by an embodiment of the present application. The width of the first region 1231 in the first direction is greater than the width of the second region 1232 in the first direction, that is, W>W1.

[0051] ​​In the second direction, the orthogonal projection of the substrate 16 of the gate 13 overlaps the orthogonal projection of the first region 1231 on the substrate 16, and the second region 1232 fills the part of the substrate 16 where the orthogonal projection of the gate 13 does not overlap the orthogonal projection of the first region 1231 on the substrate 16. Specifically, the width relationship of the first region 1231 and the second region 1232 in the first direction actually reflects the overlapping degree of the gate 13 and the first region 1231 and the second region 1232, that is, the overlapping width of the gate 13 on the first region 1231 is greater than the overlapping width of the gate 13 on the second region 1232.

[0052] By setting the width relationship of the first region 1231 and the second region 1232 in the first direction, the main position of the first region 1231 can be ensured unchanged, the stability of the gate voltage and the threshold voltage of the transistor 11 can be maintained, and the transistor 11 can work normally.

[0053] In some embodiments of the present application, as shown in Figure 2 Figure 2 A top view structural schematic diagram of the transistor 11 provided by an embodiment of the present application is shown. The width of the source region 121 and the drain region 122 in the first direction is equal to the width of the first region 1231 in the first direction.

[0054] In the second direction, the orthogonal projection of the substrate 16 of the gate 13 overlaps the orthogonal projection of the first region 1231 on the substrate 16, and the second region 1232 fills the part of the substrate 16 where the orthogonal projection of the gate 13 does not overlap the orthogonal projection of the first region 1231 on the substrate 16. Specifically, the width relationship of the first region 1231 and the second region 1232 in the first direction actually reflects the overlapping degree of the gate 13 and the first region 1231 and the second region 1232, that is, the overlapping width of the gate 13 on the first region 1231 is greater than the overlapping width of the gate 13 on the second region 1232.

[0055] By maintaining the width relationship of the source region 121 and the drain region 122 and the first region 1231 in the first direction, the stability of the gate voltage and the threshold voltage of the transistor 11 can be maintained, and the transistor 11 can work normally.

[0056] In some embodiments of the present application, as shown in Figure 3 Figure 3 A top view structural schematic diagram of the transistor 11 provided by another embodiment of the present application is shown. At least two second regions 1232 are arranged on both sides of the first region 1231 in the first direction.

[0057] In the second direction, the orthogonal projection of the substrate 16 of the gate 13 overlaps the orthogonal projection of the first region 1231 on the substrate 16, and the second region 1232 fills the part of the substrate 16 where the orthogonal projection of the gate 13 does not overlap the orthogonal projection of the first region 1231 on the substrate 16. Specifically, the width relationship of the first region 1231 and the second region 1232 in the first direction actually reflects the overlapping degree of the gate 13 and the first region 1231 and the second region 1232, that is, the overlapping width of the gate 13 on the first region 1231 is greater than the overlapping width of the gate 13 on the second region 1232. Figure 3

[0058] ​​​By setting the second region 1232 on both sides of the first region 1231, the proportion of the channel region 123 in the first direction can be fully utilized, the width of the overlapping part of the gate 13 and the channel region 123 can be increased, the channel width W can be increased in a way, the driving current Ids can be increased, and the driving capability of the existing array substrate 10 can be improved.

[0059] In some embodiments of the present application, as Figures 4-7 shown, Figure 4 a top view structural schematic diagram of the second region 1232 provided by an embodiment of the present application is shown, Figure 5 a top view structural schematic diagram of the second region 1232 provided by another embodiment of the present application is shown, Figure 6 a top view structural schematic diagram of the second region 1232 provided by still another embodiment of the present application is shown, Figure 7 a top view structural schematic diagram of the second region 1232 provided by yet another embodiment of the present application is shown. The shape of the orthographic projection of the second region 1232 on the substrate 16 includes a rectangle, a square and a trapezoid.

[0060] The second region 1232 is obtained by continuing the first region 1231 in the first direction, and the first region 1231 and the second region 1232 are integrally formed. Without limitation, the shape of the orthographic projection of the second region 1232 on the substrate 16 can also be a trapezoid with curved waist, such as a trapezoid with both waists curved, a trapezoid with one waist curved, etc.

[0061] By setting the shape of the second region 1232 as a rectangle, a square or a trapezoid, the overlapping of the gate 13 and the second region 1232 can be ensured, the proportion of the second region 1232 in the direction other than the extension direction of the gate 13 can be reduced, the overlapping of the gate 13 in other regions and the second region 1232 can be prevented to cause interference capacitance, and the processing difficulty can be significantly reduced.

[0062] In some embodiments of the present application, as Figure 8 shown, Figure 8 a top view structural schematic diagram of the transistor 11 provided by still another embodiment of the present application is shown. The gate 13 includes a first part 131 on one side of the active layer 12 and a second part 132 overlapping the channel region 123, the second part 132 extends in the first direction, the orthographic projection of the second region 1232 on the substrate 16 and the orthographic projection of the first part 131 on the substrate 16 are arranged in a staggered manner, and the orthographic projection of the second region 1232 on the substrate 16 and the orthographic projection of the second part 132 on the substrate 16 are arranged in an overlapping manner.

[0063] The second region 1232 is used to fill the non-overlapping part of the second portion 132 and the first region 1231, and the second region 1232 is connected to the first region 1231. Specifically, one end of the second region 1232 in the first direction is connected to the first region 1231, and the other end extends along the track of the second portion 132.

[0064] The first portion 131 and the second portion 132 are arranged to facilitate the connection of the gate 13 to the signal line scan line 105, and the specific structure of the second region 1232 can be adjusted according to the extension track of the second portion 132, thereby facilitating the application of the transistor 11 to various types.

[0065] In some embodiments of the present application, as shown in Figure 8 Figure 8 A top view structural schematic diagram of the transistor 11 provided by another embodiment of the present application is shown. The second portion 132 is formed in a bending path in the first direction on the substrate 16.

[0066] The second portion 132 is formed in a bending path in the first direction on the substrate 16.

[0067] The special-shaped second portion 132 can significantly increase the relative width of the gate 13 overlapping the channel region 123, which is equivalent to increasing the channel width W, thereby increasing the driving current Ids and improving the driving capability of the existing array substrate 10, as shown in Figure 8 W3+W4>W; and secondly, the bending arrangement of the second portion 132 can ensure the effective overlapping area between the second portion 132 and the channel region 123, that is, the original charging capability can be maintained while the occupied space of the transistor 11 in the first direction is compressed, thereby providing more space for the pixel circuit and compressing the frame width in the first direction.

[0068] In some embodiments of the present application, as shown in Figure 9 Figure 9 A top view structural schematic diagram of the transistor 11 provided by another embodiment of the present application is shown. The channel region 123 is formed in a bending path. The channel region 123 is arranged in a bending shape that is matched with the second portion 132, thereby facilitating the overlapping of the second portion 132 and the channel region 123.

[0069] In some embodiments of the present application, as shown in Figure 9 Figure 9 A top view structural schematic diagram of the transistor 11 provided by another embodiment of the present application is shown. The source region 121 and the drain region 122 are formed in a bending path. The source region 121 and the drain region 122 are arranged in a bending shape that is matched with the second portion 132, thereby facilitating the maintenance of the basic architecture of the existing transistor 11 and improving the off-state capability of the transistor 11. ​​​

[0070] By simultaneously using the bending configuration of the second part 132 and the irregular configuration of the channel region 123, the effective overlap area between the second part 132 and the channel region 123 can be effectively increased. That is, while maintaining the original charging capacity, the space occupied by the transistor 11 in the first and second directions can be reduced, providing more space for the pixel circuit and reducing the width of the bezel in the first and second directions.

[0071] In some embodiments of this application, such as Figure 1 and Figure 9 As shown, Figure 1 This diagram shows a cross-sectional view of a transistor 11 provided in one embodiment of the present application. Figure 9 This diagram shows a top view of a transistor 11 provided in another embodiment of the present application. The array substrate 10 further includes a source electrode 14 and / or a drain electrode 15. The source electrode 14 is located on the side of the active layer 12 opposite to the substrate 16, and includes a source line overlapping with the source region 121, the source line extending along the bending path. The drain electrode 15 is located on the side of the active layer 12 opposite to the substrate 16, and includes a drain line overlapping with the drain region 122, the drain line extending along the bending path. The portions of the source electrode 14 and drain electrode 15 in the source region 121 and drain region 122 within the channel region 123 extend along the bending path.

[0072] The sum of the widths of the first region 1231 and the second region 1232 in the first direction is greater than the width of at least one of the source region 121 and the drain region 122 in the first direction. This ensures that the gate 13 has a larger overlap width in the channel region 123, increases the channel width W, and increases the driving current Ids, thereby improving the driving capability of the existing array substrate 10.

[0073] In some embodiments of this application, such as Figure 10 As shown, Figure 10 This diagram shows a top view of an array substrate 10 according to an embodiment of this application. The array substrate 10 provided in this embodiment includes multiple pixel circuits and multiple border circuits. The multiple pixel circuits can be arranged in an array. The multiple border circuits are disposed around the multiple pixel circuits and electrically connected to the pixel circuits. For example, the multiple pixel circuits can be arranged in an array in two orthogonal directions, such as orthogonal row and column directions.

[0074] In some embodiments of this application, a display panel 100 is provided, including the aforementioned array substrate 10 and display elements located on the array substrate 10. Exemplarily, the display element may be a liquid crystal layer and a color filter (CF) disposed on the array substrate 10, forming an LCD display panel. Exemplarily, the display element may be a light-emitting layer disposed on the array substrate 10. Exemplarily, the light-emitting layer may be an organic light-emitting layer, that is, the display panel 100 may be an organic light-emitting diode (OLED) display panel 100. This display panel 100 can improve the driving capability of transistors 11 in the multiplexer assembly under the requirements of existing narrow bezel technology, avoid insufficient charging of transistors 11 and the resulting display abnormalities, and improve the reliability of the display panel 100.

[0075] Furthermore, embodiments of this application also provide an array substrate 10 and a display panel 100, see reference. Figure 10 and Figure 11 , Figure 10 This diagram shows a top view of the array substrate 10 provided in one embodiment of the present application. Figure 11 Show Figure 10 A magnified structural diagram at point A. This array substrate 10 is similar to the aforementioned array substrate 10, but differs in that it includes a data line 104, a scan line 105, a first electrode 106, a first signal control line 107, a second signal control line 108, and a transistor 11 from any of the aforementioned embodiments, disposed in the first region 101. In the display area, the source electrode 14 of the transistor 11 is electrically connected to the data line 104, the drain electrode 15 of the transistor 11 is electrically connected to the first electrode 106, and the gate electrode 13 is electrically connected to the scan line 105; at the border, the source electrode 14 of the transistor 11 is electrically connected to the first electrode 106, the drain electrode 15 of the transistor 11 is electrically connected to the second signal control line 108, and the gate electrode 13 is electrically connected to the first signal control line 107.

[0076] It can be understood that the first electrode 106 is a pixel electrode, and during a display driving process, the scan line 105 provides a scan signal to the gate electrode 13, and the data line 104 provides a data signal to the source electrode 14. Under the control of the scan signal of the scan line 105, the transistor 11 is switched on and off, so as to realize the import control of the data signal to the first electrode 106. It should be noted that the positions of the source electrode 14 and the drain electrode 15 of the transistor 11 relative to the gate electrode 13 can be replaced according to actual conditions, and the present application does not limit this. It can be understood that the first signal control line 107 and the second signal control line 108 are CKH lines, and are electrically connected with a control component of the screen, such as an IC, for receiving demux signals, source signals and the like output by the IC, and the present application does not limit this.

[0077] In addition, the embodiment of the present application further provides a display panel 100, which refers to Figure 11 and Figure 12 , Figure 12 A structure schematic diagram of a display panel 100 provided by an embodiment of the present application is shown. The array substrate 10 in the display panel 100 is similar to the array substrate 10 described above, but the difference is that the display panel 100 further comprises a driving chip 3 arranged in the second area 102, and the driving chip 3 is electrically connected with the transistor 11. It can be understood that the first area 101 is a display area, and the second area 102 is a frame area.

[0078] In some embodiments of the present application, as Figure 13 shown, Figure 13 A structure schematic diagram of a display device 200 provided by an embodiment of the present application is shown. The embodiment of the present application further provides a display device, and the display device 200 comprises the display panel 100 of any one of the above-mentioned embodiments. It can be understood that the display device 200 provided by the embodiment of the present application can be a computer, a television, a vehicle-mounted display device or other display devices 200 with display functions, and the present application does not specifically limit this. The display device 200 provided by the embodiment of the present application has the beneficial effects of the display panel 100 provided by the embodiment of the present application, and specific descriptions can be referred to the specific descriptions of the display panel 100 in the above-mentioned embodiments, and the present embodiment will not be described here.

[0079] It should be noted that the above-mentioned embodiments can be combined with each other without contradiction.

[0080] In accordance with the embodiments of the application described above, these embodiments are not meant to be all-inclusive or limiting of the scope of the application. It will be apparent to those having skill in the art that many more modifications than those already described are possible. The present specification has been put forth with a full description for the purpose of enabling others skilled in the art to employ this application and modifications made by others skilled in the art based on the teachings herein. The application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized by, The display panel comprises a substrate and a transistor disposed on one side of the substrate, the transistor comprising: an active layer comprising a channel region and a source region and a drain region respectively disposed on two sides of the channel region in a second direction; a gate disposed on a side of the active layer away from the substrate, and a projection of the gate on the substrate at least partially overlaps with a projection of the channel region on the substrate; the channel region comprises a first region and a second region disposed on the first region in a first direction, the second region and the first region are disposed in a staggered manner in the first direction; the gate comprises a first portion disposed on a side of the active layer and a second portion overlapping with the channel region, the second portion extends in the first direction, the second region and the first portion are disposed in a staggered manner in the first direction, and the second region and the second portion are disposed in an overlapping manner in the first direction; the second portion is formed in a bending path in the first direction; the channel region is formed in the bending path; the source region and the drain region are formed in the bending path; the source region and the drain region overlap with the first region in the second direction, and the source region and the drain region are disposed in a staggered manner with the second region in the second direction.

2. The array substrate of claim 1, wherein, The width of the first region in the first direction is greater than the width of the second region in the first direction.

3. The array substrate of claim 1, wherein, The width of the source region and the drain region in the first direction is equal to the width of the first region in the first direction.

4. The array substrate of claim 1, wherein, The shape of the projection of the second region on the substrate comprises a rectangle and a trapezoid.

5. The array substrate of claim 1, wherein, At least two second regions are disposed on both sides of the first region in the first direction.

6. The array substrate of claim 1, wherein, Further comprising: a source electrode disposed on a side of the active layer away from the substrate, the source electrode comprises a source line overlapping with the source region, the source line is formed in the bending path; and / or a drain electrode disposed on a side of the active layer away from the substrate, the drain electrode comprises a drain line overlapping with the drain region, the drain line is formed in the bending path; the part of the source electrode and the drain electrode in the channel region is formed in the bending path.

7. The array substrate of claim 1, wherein, The shape of the bending path comprises a curve and a polyline.

8. The array substrate of claim 1, wherein, The sum of the width of the first region and the second region in the first direction is greater than the width of at least one of the source region and the drain region in the first direction.

9. A display panel, characterized by, The array substrate comprises any one of claims 1-8.

10. A display device, characterized by comprising: The display panel comprises claim 9. The display panel comprises claim 9.

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