A LIGBT device integrated with surface and body anti-parallel diodes

Abstract

The present invention proposes a LIGBT device integrated with surface and body anti-parallel diodes, belonging to the field of power semiconductor technology. The LIGBT device of the present invention integrates surface and body double diodes, wherein the P+ surface layer is the anode, the P-type floating layer is the drift region, the N- isolation region is the drift region, and the N+ surface layer is the cathode, forming a surface diode structure; the P+ surface layer is the anode, the P-top region is the drift region, the N-type drift region and the N- isolation region are the drift regions, and the N+ surface layer is the cathode, forming a body diode structure. When the device conducts forward, holes can be extracted through the body diode, reducing the saturation current density of the device and enhancing the short-circuit safe operating characteristics of the device; when the device conducts reversely, the body and surface diodes bear the reverse current simultaneously; at the turn-off moment, the body diode extracts the stored carriers, reducing the turn-off time and turn-off loss.

Description

Technical Field

[0001] The present invention belongs to the field of power semiconductor devices, and relates to a LIGBT device integrating surface and body anti-parallel diodes. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a bipolar semiconductor power device combining MOSFET and BJT transistors, which has the advantages of low on-state voltage drop, low drive power consumption and high operating frequency. It is widely used in communication technologies, new energy devices and various consumer electronics fields, and is the core device of the electronic power system. Among them, LIGBT (Lateral Insulated Gate Bipolar Transistor) is easy to integrate on a Si substrate and is usually applied in SOI-based power intelligent systems, which is a typical representative of bipolar semiconductor devices.

[0003] However, since the LIGBT does not have reverse conduction ability, a reverse freewheeling diode is usually connected in parallel beside the LIGBT to play a protective role in actual use. At the same time, in order to improve the device integration and reduce the manufacturing cost, people began to try to integrate the protective freewheeling diode inside the LIGBT, replacing the P-Collector of the LIGBT part with N-Collector, and integrating a P-body / N-drift / N-Collector freewheeling diode inside the transistor, becoming LIGBT (Reverse-Conducting Lateral Insulated Gate Bipolar Transistor). This modification not only enables the device to have reverse conduction ability, but also greatly reduces the chip size and can reduce the production cost.

[0004] Traditional LIGBT still has some drawbacks that cannot be ignored in use: for example, in the turn-off stage, there are a large number of carriers in the drift region that need to be extracted. Without a carrier extraction channel, the carriers can only disappear through recombination, resulting in a long turn-off time and a tail current, which affects the use of the device. At present, the structural optimization schemes of LIGBT can be mainly summarized into the following three aspects: 1. Anode optimization, the main purpose is to control the injection efficiency of anode holes; 2. Cathode optimization, the main purpose is to increase the carrier concentration on the cathode side in the on-state; 3. Drift region optimization, the main purpose is to improve the device breakdown voltage and the carrier extraction speed.

[0005] Therefore, in order to better promote the application of LIGBT, it is necessary to further improve the LIGBT to optimize various performances of the LIGBT, thereby enhancing the reliability of the LIGBT device. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a LIGBT device integrating surface and body anti-parallel diodes.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A LIGBT device integrating surface and body anti-parallel diodes is divided into a diode region and a LIGBT region from top to bottom. The diode region is further divided into a surface diode region and a body diode region;

[0009] The LIGBT region includes a P+ emitter 5, an N+ electron emitter 6, an emitter 12, a P-body 7, a gate 13, a silicon dioxide insulating layer 15, an N-type drift region 3, a P-top region 4, an N-type buffer layer 2, a P+ collector 1, a collector 14, and a P-type substrate 16 arranged from left to right; the P+ emitter 5 is located below the emitter 12, its left side is flush with the left side of the device, its right side is closely connected to the left side of the N+ electron emitter 6, and its lower side is connected to the P-body 7; the N+ electron emitter 6 is located below the emitter 12, its right side is connected to the gate 13, and its lower side is the P-body 7; the upper side of the P-body 7 is flush with the upper sides of the P+ emitter 5 and the N+ electron emitter 6, and its lower side is completely covered by the N-type drift region 3; the upper side of the N-type drift region 3 is flush with the upper sides of the P+ emitter 5, the N+ electron emitter 6, the silicon dioxide insulating layer 15, the gate 13, the P-top region 4, the N-type buffer layer 2, and the P+ collector 1, its left side is flush with the left side of the device, its lower side is in contact with the silicon dioxide insulating layer 15, and its right side is flush with the right side of the device; the upper side of the P-top region 4 is flush with the upper side of the N-type drift region 3, its left side is in contact with the silicon dioxide insulating layer 15, and its right side and lower side are completely covered by the N-type drift region 3; the upper side of the N-type buffer layer 2 is flush with the upper sides of the N-type drift region 3 and the P+ collector 1, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type drift region 3; the P+ collector 1 is located below the collector 14, its upper side is flush with the upper sides of the N-type drift region 3 and the N-type buffer layer 2, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type buffer layer 2; the lower side of the silicon dioxide insulating layer 15 is connected to the upper side of the P-type substrate 16, and its left side and right side are flush with the P-type substrate 16;

[0010] The diode region includes a P+ surface layer 11, a P-type floating layer 10, an N- isolation region 9, and an N+ surface layer 8 arranged from left to right; on the left side of the P+ surface layer 11 is an emitter 12, the right side is in close contact with the left side of the P-type floating layer 10, the lower side is in close contact with the upper side of the P-top region 4, and the upper side is flush with the upper sides of the P+ surface layer 11, the N- isolation region 9, and the N+ surface layer 8; the left side of the P-type floating layer 10 is in contact with the P+ surface layer 11, the right side is in close contact with the left side of the N- isolation region 9, the lower side is in close contact with the upper side of the P-top region 4, and the upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8; the left side of the N- isolation region 9 is in contact with the P-type floating layer 10, the right side is in close contact with the left side of the N+ surface layer 8, the lower side is in close contact with the N-type drift region 3 and the silicon dioxide insulating layer 15, and the upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8; the left side of the N+ surface layer 8 is in close contact with the right side of the N- isolation region 9, the right side is the collector 14, and the lower side is the silicon dioxide insulating layer 15;

[0011] In the diode region, the P+ surface layer 11 is the anode of the surface diode, the P-type floating layer 10 is the drift region of the surface diode, the N- isolation region 9 is the drift region of the surface diode, the N+ surface layer 8 is the cathode of the surface diode, forming a surface diode structure; the P+ surface layer 11 is the anode of the body diode, the P-top region 4 is the drift region of the body diode, the N-type drift region 3 and the N- isolation region 9 are the drift regions of the body diode, the N+ surface layer 8 is the cathode of the body diode, forming a body diode structure.

[0012] Furthermore, the LIGBT region further includes an N-type column 17 and a P-type column 18; the right side of the P-top region 4 is in contact with the N-type drift region 3, and the lower side is in close contact with the N-type column 17; the upper side of the N-type column 17 is in close contact with the lower side of the P-top region 4, and the lower side is in close contact with the upper side of the P-type column 18; the upper side of the P-type column 18 is in close contact with the lower side of the N-type column 17, and the lower side is flush with the lower side of the N-type drift region 3; the lower side of the N- isolation region 9 is in close contact with the P-top region 4 and the silicon dioxide insulating layer 15.

[0013] Furthermore, the LIGBT region further includes a hole blocking layer 19, the upper side of the hole blocking layer 19 is in close contact with the P-body 7, the left side is flush with the left side of the device, and the right side is in close contact with the silicon dioxide insulating layer 15.

[0014] Furthermore, the material of the gate 13 includes doped polysilicon or aluminum.

[0015] The beneficial effects of the present invention are as follows:

[0016] (1) In the forward conduction stage, when the collector voltage is relatively large, holes can be extracted through the body diode, reducing the saturation current density of the device and enhancing the short-circuit safe operating characteristics of the device;

[0017] (2) In the reverse conduction stage, due to the introduction of the surface diode and the body diode, the device can conduct reversely;

[0018] (3) At the turn-off moment, holes can be extracted through the body diode, while electrons can be extracted through the N+ surface layer, reducing the turn-off time and turn-off loss;

[0019] (4) In the forward blocking stage, the P-top region and the N-type drift region are depleted of each other and charge compensated, further optimizing the electric field.

[0020] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the examination and research of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the following specification. Brief Description of the Drawings

[0021] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in preferred detail below in conjunction with the drawings, where:

[0022] Figure 1 It is a schematic structural diagram of a LIGBT device integrating surface and body anti-parallel diodes proposed by the present invention and is the structural schematic diagram of Embodiment 1;

[0023] Figure 2 It is the structural schematic diagram of Embodiment 2 of the LIGBT device provided by the present invention;

[0024] Figure 3 It is the structural schematic diagram of Embodiment 3 of the LIGBT device provided by the present invention;

[0025] Figure 4 It is the structural schematic diagram of a traditional LIGBT device;

[0026] Figure 5 It is the equivalent circuit diagram of Embodiment 1 of the LIGBT device provided by the present invention;

[0027] Figure 6 It is the comparison diagram of the forward conduction characteristics of Embodiment 1 and the traditional LIGBT and the equivalent circuit diagram;

[0028] Figure 7 It is the reverse conduction characteristic diagram of Embodiment 1 and the equivalent circuit diagram;

[0029] Figure 8Current density distribution diagram during reverse conduction in Embodiment 1;

[0030] Figure 9 For the blocking characteristics comparison diagram of Embodiment 1 and the traditional LIGBT when the drift region length L D is 20 μm;

[0031] Figure 10 (a) Potential distribution diagram of the traditional LIGBT, (b) Potential distribution diagram of Embodiment 1;

[0032] Figure 11 For the forward conduction characteristics comparison diagram of Embodiment 1 and the traditional LIGBT when the collector voltage is relatively large;

[0033] Figure 12 For the turn-off characteristic curve diagram and equivalent circuit diagram of Embodiment 1 and the traditional LIGBT under the same conduction voltage drop.

[0034] Reference numerals: P+ collector 1, N-type buffer layer 2, N-type drift region 3, P-top region 4, P+ emitter 5, N+ electron emitter 6, P-body 7, N+ surface layer 8, N- isolation region 9, P-type floating layer 10, P+ surface layer 11, emitter 12, gate 13, collector 14, silicon dioxide insulating layer 15, P-type substrate 16, N-type column 17, P-type column 18, hole blocking layer 19. Detailed implementation manners

[0035] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0036] Among them, the drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and cannot be understood as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the drawings will be omitted, enlarged or reduced, and do not represent the dimensions of actual products; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0037] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0038] Embodiment 1:

[0039] As Figure 1 shown, a LIGBT device integrating surface and body anti-parallel diodes proposed by the embodiments of the present invention, the LIGBT device includes a P+ collector 1, an N-type buffer layer 2, an N-type drift region 3, a P-top region 4, a P+ emitter 5, an N+ electron emitter 6, a P-body 7, an N+ surface layer 8, an N- isolation region 9, a P-type floating layer 10, a P+ surface layer 11, an emitter 12, a gate 13, a collector 14, a silicon dioxide insulating layer 15, and a P-type substrate 16.

[0040] The LIGBT device integrating surface and body anti-parallel diodes is divided into a diode region and a LIGBT region from top to bottom. The LIGBT device includes a P+ collector 1, an N-type buffer layer 2, an N-type drift region 3, a P-top region 4, a P+ emitter 5, an N+ electron emitter 6, a P-body 7, an N+ surface layer 8, an N- isolation region 9, a P-type floating layer 10, a P+ surface layer 11, an emitter 12, a gate 13, a collector 14, a silicon dioxide insulating layer 15, and a P-type substrate 16.

[0041] Among them, in the LIGBT region: from left to right, there are respectively arranged a P+ emitter 5, an N+ electron emitter 6, an emitter 12, a P-body 7, a gate 13, a silicon dioxide insulating layer 15, an N-type drift region 3, a P-top region 4, an N-type buffer layer 2, a P+ collector 1, and a collector 14. The P+ emitter 5 is located below the emitter 12, its left side is flush with the left side of the device, its right side is closely connected to the left side of the N+ electron emitter 6, and its lower side is connected to the P-body 7. The N+ electron emitter 6 is located below the emitter 12, its right side is connected to the gate 13, and its lower side is the P-body 7. The upper side of the P-body 7 is flush with the upper sides of the P+ emitter 5 and the N+ electron emitter 6, and its lower side is completely covered by the N-type drift region 3. The upper side of the N-type drift region 3 is flush with the upper sides of the P+ emitter 5, the N+ electron emitter 6, the silicon dioxide insulating layer 15, the gate 13, the P-top region 4, the N-type buffer layer 2, and the P+ collector 1, its left side is flush with the left side of the device, its lower side is in contact with the silicon dioxide insulating layer 15, and its right side is flush with the right side of the device. The upper side of the P-top region 4 is flush with the upper side of the N-type drift region 3, its left side is in contact with the silicon dioxide insulating layer 15, and its right side and lower side are completely covered by the N-type drift region 3. The upper side of the N-type buffer layer 2 is flush with the upper sides of the N-type drift region 3 and the P+ collector 1, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type drift region 3. The P+ collector 1 is located below the collector 14, its upper side is flush with the upper sides of the N-type drift region 3 and the N-type buffer layer 2, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type buffer layer 2.

[0042] PN junction region: from left to right, there are respectively arranged a P+ surface layer 11, a P-type floating layer 10, an N- isolation region 9, and an N+ surface layer 8. The left side of the P+ surface layer 11 is the emitter 12, its right side is closely in contact with the left side of the P-type floating layer 10, its lower side is closely in contact with the upper side of the P-top region 4, and its upper side is flush with the upper sides of the P+ surface layer 11, the N- isolation region 9, and the N+ surface layer 8. The left side of the P-type floating layer 10 is in contact with the P+ surface layer 11, its right side is closely in contact with the left side of the N- isolation region 9, its lower side is closely in contact with the upper side of the P-top region 4, and its upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8. The left side of the N- isolation region 9 is in contact with the P-type floating layer 10, its right side is closely in contact with the left side of the N+ surface layer 8, its lower side is closely in contact with the N-type drift region 3 and the silicon dioxide insulating layer 15, and its upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8. The left side of the N+ surface layer 8 is closely in contact with the right side of the N- isolation region 9, its right side is the collector 14, and its lower side is the silicon dioxide insulating layer 15.

[0043] In the PN junction region of Embodiment 1, the functions of each component are as follows: The P+ surface layer 11 serves as the anode of the surface diode, the P-type floating layer 10 serves as the drift region of the surface diode, the N- isolation region 9 serves as the drift region of the surface diode, and the N+ surface layer 8 serves as the cathode of the surface diode, forming a surface diode structure. The P+ surface layer 11 serves as the anode of the body diode, the P-top region 4 serves as the drift region of the body diode, the drift region 3 and the N- isolation region 9 serve as the drift regions of the body diode, and the N+ surface layer 8 serves as the cathode of the body diode, forming a body diode structure.

[0044] The length of the N-type drift region 3 is 20 μm, the thickness is 4 μm, and the doping concentration is 5×10 15 cm -3 . The length of the P+ collector 1 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the N-type buffer layer 2 is 2 μm, the thickness is 2 μm, and the doping concentration is 5×10 16 cm -3 . The length of the P-top region 4 is 8 μm, the thickness is 2 μm, and the doping concentration is 4×10 15 cm -3 . The length of the P+ emitter 5 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the N+ electron emitter 6 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the P-body 7 is 2 μm, the thickness is 2 μm, and the doping concentration is 8×10 16 cm -3 . The length of the N+ surface layer 8 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the N- isolation region 9 is 7.5 μm, the thickness is 1 μm, and the doping concentration is 1×10 15 cm -3 . The length of the P-type floating layer 10 is 7 μm, the thickness is 1 μm, and the doping concentration is 1×10 15 cm -3 . The length of the P+ surface layer 11 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 .

[0045] When conducting forward, when the collector voltage is relatively large, holes can be extracted through the body diode, reducing the saturation current density of the device and enhancing the short-circuit safety operating characteristics of the device; due to the introduction of the surface diode and the body diode, the device can conduct reversely; at the turn-off moment, holes can be extracted through the body diode, while electrons can be extracted through the N+ surface layer, reducing the turn-off loss. In addition, in the avalanche breakdown state, the P-top region 4 and the N-type drift region 3 deplete each other and compensate for charges, thereby increasing the breakdown voltage.

[0046] Embodiment 2:

[0047] As Figure 2 shown, a LIGBT device integrating surface and body anti-parallel diodes proposed by the present invention embodiment, the LIGBT device includes a P+ collector 1, an N-type buffer layer 2, an N-type drift region 3, a P-top region 4, a P+ emitter 5, an N+ electron emitter 6, a P-body 7, an N+ surface layer 8, an N- isolation region 9, a P-type floating layer 10, a P+ surface layer 11, an emitter 12, a gate 13, a collector 14, a silicon dioxide insulating layer 15, a P-type substrate 16, an N-type column 17, and a P-type column 18.

[0048] The LIGBT device integrating surface and body anti-parallel diodes is divided into a diode region and a LIGBT region from top to bottom. The LIGBT device includes a P+ collector 1, an N-type buffer layer 2, an N-type drift region 3, a P-top region 4, a P+ emitter 5, an N+ electron emitter 6, a P-body 7, an N+ surface layer 8, an N- isolation region 9, a P-type floating layer 10, a P+ surface layer 11, an emitter 12, a gate 13, a collector 14, a silicon dioxide insulating layer 15, a P-type substrate 16, an N-type column 17, and a P-type column 18.

[0049] Among them, in the LIGBT region: from left to right, there are P+ emitter 5, N+ electron emitter 6, emitter 12, P-body 7, gate 13, silicon dioxide insulating layer 15, N-type drift region 3, P-top region 4, N-type column 17, P-type column 18, N-type buffer layer 2, P+ collector 1, and collector 14. The P+ emitter 5 is located below the emitter 12, its left side is flush with the left side of the device, its right side is closely connected to the left side of the N+ electron emitter 6, and its lower side is connected to the P-body 7. The N+ electron emitter 6 is located below the emitter 12, its right side is connected to the gate 13, and its lower side is the P-body 7. The upper side of the P-body 7 is flush with the upper sides of the P+ emitter 5 and the N+ electron emitter 6, and its lower side is completely covered by the N-type drift region 3. The upper side of the N-type drift region 3 is flush with the upper sides of the P+ emitter 5, N+ electron emitter 6, silicon dioxide insulating layer 15, gate 13, P-top region 4, N-type buffer layer 2, and P+ collector 1, its left side is flush with the left side of the device, its lower side is in contact with the silicon dioxide insulating layer 15, and its right side is flush with the right side of the device. The upper side of the P-top region 4 is flush with the upper side of the N-type drift region 3, its left side is in contact with the silicon dioxide insulating layer 15, its right side is in contact with the N-type drift region 3, and its lower side is in close contact with the N-type column 17. The upper side of the N-type buffer layer 2 is flush with the upper side of the P+ collector 1, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type drift region 3. The P+ collector 1 is located below the collector 14, its upper side is flush with the upper sides of the N-type drift region 3 and the N-type buffer layer 2, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type buffer layer 2. The upper side of the N-type column 17 is in close contact with the lower side of the P-top region 4, and its lower side is in close contact with the upper side of the P-type column 18. The upper side of the P-type column 18 is in close contact with the lower side of the N-type column 17, and its lower side is flush with the lower side of the N-type drift region 3.

[0050] PN Junction Region: A P+ surface layer 11, a P-type floating layer 10, an N- isolation region 9, and an N+ surface layer 8 are arranged from left to right. On the left side of the P+ surface layer 11 is the emitter 12. The right side of the P+ surface layer 11 is in close contact with the left side of the P-type floating layer 10, the lower side is in close contact with the upper side of the P-top region 4, and the upper side is flush with the upper sides of the P+ surface layer 11, the N- isolation region 9, and the N+ surface layer 8. The left side of the P-type floating layer 10 is in contact with the P+ surface layer 11, the right side is in close contact with the left side of the N- isolation region 9, the lower side is in close contact with the upper side of the P-top region 4, and the upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8. The left side of the N- isolation region 9 is in contact with the P-type floating layer 10, the right side is in close contact with the left side of the N+ surface layer 8, the lower side is in close contact with the P-top region 4 and the silicon dioxide insulating layer 15, and the upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8. The left side of the N+ surface layer 8 is in close contact with the right side of the N- isolation region 9, the right side is the collector 14, and the lower side is the silicon dioxide insulating layer 15.

[0051] In the PN junction region described in Embodiment 2, the functions of each component are as follows: The P+ surface layer 11 is the anode of the surface diode, the P-type floating layer 10 is the drift region of the surface diode, the N- isolation region 9 is the drift region of the surface diode, the N+ surface layer 8 is the cathode of the surface diode, forming a surface diode structure. The P+ surface layer 11 is the anode of the body diode, the P-top region 4 is the drift region of the body diode, the N-type drift region 3 and the N- isolation region 9 are the drift regions of the body diode, the N+ surface layer 8 is the cathode of the body diode, forming a body diode structure.

[0052] The length of the N-type drift region 3 is 20 μm, the thickness is 4 μm, and the doping concentration is 5×10 15 cm -3 . The length of the P+ collector 1 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the N-type buffer layer 2 is 2 μm, the thickness is 2 μm, and the doping concentration is 5×10 16 cm -3 . The length of the P-top region 4 is 15.5 μm, the thickness is 2 μm, and the doping concentration is 4×10 15 cm -3 . The length of the P+ emitter 5 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the N+ electron emitter 6 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the P-body 7 is 2 μm, the thickness is 2 μm, and the doping concentration is 8×10 16cm -3 The length of the N+ surface layer 8 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of the N- isolation region 9 is 7.5 μm, the thickness is 1 μm, and the doping concentration is 1×10 15 cm -3 The length of the P-type floating layer 10 is 7 μm, the thickness is 1 μm, and the doping concentration is 1×10 15 cm -3 The length of the P+ surface layer 11 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 。

[0053] Due to the introduction of the surface diode and the body diode, the device can conduct in the reverse direction; at the turn-off moment, holes can be extracted through the body diode, and electrons can be extracted through the N+ surface layer 8, reducing the turn-off loss. In addition, due to the introduction of the N-type column 17 and the P-type column 18, in the avalanche breakdown state, the P-top region 4, the N-type column 17, and the P-type column 18 are mutually depleted, charge compensated, the electric field is further optimized, and the breakdown voltage is further increased. The length of the N-type column 17 is 15.5 μm, the thickness is 1 μm, and the doping concentration is 1×10 16 cm -3 The length of the P-type column 18 is 15.5 μm, the thickness is 1 μm, and the doping concentration is 5×10 15 cm -3 。

[0054] Embodiment 3:

[0055] As Figure 3 shown, a LIGBT device integrating surface and body anti-parallel diodes proposed by the present invention, the LIGBT device includes a P+ collector 1, an N-type buffer layer 2, an N-type drift region 3, a P-top region 4, a P+ emitter 5, an N+ electron emitter 6, a P-body 7, an N+ surface layer 8, an N- isolation region 9, a P-type floating layer 10, a P+ surface layer 11, an emitter 12, a gate 13, a collector 14, a silicon dioxide insulating layer 15, a P-type substrate 16, and a hole blocking layer 19.

[0056] The described LIGBT device integrating surface and body anti-parallel diodes is divided into a diode region and an LIGBT region from top to bottom. The LIGBT device includes a P+ collector 1, an N-type buffer layer 2, an N-type drift region 3, a P-top region 4, a P+ emitter 5, an N+ electron emitter 6, a P-body 7, an N+ surface layer 8, an N- isolation region 9, a P-type floating layer 10, a P+ surface layer 11, an emitter 12, a gate 13, a collector 14, a silicon dioxide insulating layer 15, a P-type substrate 16, and a hole blocking layer 19.

[0057] Among them, in the LIGBT region: a P+ emitter 5, an N+ electron emitter 6, an emitter 12, a P-body 7, a hole blocking layer 19, a gate 13, a silicon dioxide insulating layer 15, an N-type drift region 3, a P-top region 4, an N-type buffer layer 2, a P+ collector 1, and a collector 14 are arranged from left to right. The P+ emitter 5 is located below the emitter 12, its left side is flush with the left side of the device, its right side is closely connected to the left side of the N+ electron emitter 6, and its lower side is connected to the P-body 7. The N+ electron emitter 6 is located below the emitter 12, its right side is connected to the gate 13, and its lower side is the P-body 7. The upper side of the P-body 7 is flush with the upper sides of the P+ emitter 5 and the N+ electron emitter 6, and its lower side is completely covered by the hole blocking layer 19. The upper side of the hole blocking layer 19 is in close contact with the P-body 7, its left side is flush with the left side of the device, and its right side is in close contact with the silicon dioxide insulating layer 15. The upper side of the N-type drift region 3 is flush with the upper sides of the P+ emitter 5, the N+ electron emitter 6, the silicon dioxide insulating layer 15, the gate 13, the P-top region 4, the N-type buffer layer 2, and the P+ collector 1, its left side is flush with the left side of the device, its lower side is in contact with the silicon dioxide insulating layer 15, and its right side is flush with the right side of the device. The upper side of the P-top region 4 is flush with the upper side of the N-type drift region 3, its left side is in contact with the silicon dioxide insulating layer 15, and its right side and lower side are completely covered by the N-type drift region 3. The upper side of the N-type buffer layer 2 is flush with the upper sides of the N-type drift region 3 and the P+ collector 1, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type drift region 3. The P+ collector 1 is located below the collector 14, its upper side is flush with the upper sides of the N-type drift region 3 and the N-type buffer layer 2, its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type buffer layer 2.

[0058] PN Junction Region: From left to right, a P+ surface layer 11, a P-type floating layer 10, an N- isolation region 9, and an N+ surface layer 8 are arranged. On the left side of the P+ surface layer 11 is the emitter 12. The right side of the P+ surface layer 11 is in close contact with the left side of the P-type floating layer 10, the lower side is in close contact with the upper side of the P-top region 4, and the upper side is flush with the upper sides of the P+ surface layer 11, the N- isolation region 9, and the N+ surface layer 8. The left side of the P-type floating layer 10 is in contact with the P+ surface layer 11, the right side is in close contact with the left side of the N- isolation region 9, the lower side is in close contact with the upper side of the P-top region 4, and the upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8. The left side of the N- isolation region 9 is in contact with the P-type floating layer 10, the right side is in close contact with the left side of the N+ surface layer 8, the lower side is in close contact with the N-type drift region 3 and the silicon dioxide insulating layer 15, and the upper side is flush with the upper sides of the P-type floating layer 10, the N- isolation region 9, and the N+ surface layer 8. The left side of the N+ surface layer 8 is in close contact with the right side of the N- isolation region 9, the right side is the collector 14, and the lower side is the silicon dioxide insulating layer 15.

[0059] In the PN junction region described in Embodiment 3, the functions of each component are as follows: The P+ surface layer 11 is the anode of the surface diode, the P-type floating layer 10 is the drift region of the surface diode, the N- isolation region 9 is the drift region of the surface diode, and the N+ surface layer 8 is the cathode of the surface diode, forming a surface diode structure. The P+ surface layer 11 is the anode of the body diode, the P-top region 4 is the drift region of the body diode, the N-type drift region 3 and the N- isolation region 9 are the drift regions of the body diode, and the N+ surface layer 8 is the cathode of the body diode, forming a body diode structure.

[0060] The length of the N-type drift region 3 is 20 μm, the thickness is 4 μm, and the doping concentration is 5×10 15 cm -3 . The length of the P+ collector 1 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the N-type buffer layer 2 is 2 μm, the thickness is 2 μm, and the doping concentration is 5×10 16 cm -3 . The length of the P-top region 4 is 8 μm, the thickness is 2 μm, and the doping concentration is 4×10 15 cm -3 . The length of the P+ emitter 5 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the N+ electron emitter 6 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the P-body 7 is 2 μm, the thickness is 2 μm, and the doping concentration is 8×10 16 cm-3 The length of the N+ surface layer 8 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of the N- isolation region 9 is 7.5 μm, the thickness is 1 μm, and the doping concentration is 1×10 15 cm -3 The length of the P-type floating layer 10 is 7 μm, the thickness is 1 μm, and the doping concentration is 1×10 15 cm -3 The length of the P+ surface layer 11 is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 。

[0061] When conducting forwardly, electrons and holes gather in the drift region, and the conductance modulation effect occurs, enhancing the current-carrying ability. The introduction of the hole blocking layer 19 is a potential barrier for holes, preventing holes from flowing to the emitter. A large number of holes remain in the drift region and have a conductance modulation effect with electrons, further enhancing the current-carrying ability of the device and reducing the on-state voltage drop of the device. The length of the hole blocking layer 19 is 2 μm, the thickness is 1 μm, and the doping concentration is 5×10 16 cm -3 。

[0062] Using the SENTAURUS simulation software, perform performance simulation analysis on the structure of the proposed LIGBT device in Embodiment 1 as Figure 1 shown, analyze its mechanism, and conduct electrical simulation. During the simulation process, the various simulation parameters of the device in Embodiment 1 are the same as those of the traditional LIGBT. Among them, the thickness of the N drift region is 4 μm, the carrier lifetime is 10 μs, and the ambient temperature is 300K.

[0063] Figure 4 Shown is the structural schematic diagram of the traditional LIGBT device, which is equivalent to a pnp transistor controlled by nMOS. The N+ electron emitter 6 serves as the source of nMOS, the P-body 7 serves as the P-type substrate, the N-type drift region 3 serves as the drain of nMOS, and the gate 13 controls the turn-on of nMOS. The P+ emitter 5 serves as the collector of the pnp transistor, the N-type drift region 3 serves as the base, the P+ collector 1 serves as the emitter of the pnp transistor, and the base current is provided by nMOS. Therefore, the IGBT combines the characteristics of fast switching speed, small driving power of nMOS and strong current-carrying ability of the pnp transistor. However, since it is a bipolar device, at the turn-off moment, carriers cannot be quickly extracted, resulting in a long turn-off time and a large turn-off loss.

[0064] Figure 5The equivalent circuit diagram of the LIGBT device integrating surface and body anti-parallel diodes in Embodiment 1 is shown. The LIGBT region is equivalent to a pnp transistor controlled by an nMOS. Among them, the N+ electron emitter, P-body, and N-type drift region respectively constitute the source, substrate, and drain of the nMOS; the P-body region, N-type drift region, and P-type collector respectively constitute the collector region, base region, and emitter region of the pnp transistor. The P+ surface layer is the anode of the surface diode, the P-type floating layer is the drift region of the surface diode, the N-isolation region is the drift region of the surface diode, and the N+ surface layer is the cathode of the surface diode, constituting the surface diode structure. The P+ surface layer is the anode of the body diode, the P-top region is the drift region of the body diode, the N-type drift region and the N-isolation region are the drift regions of the body diode, and the N+ surface layer is the cathode of the body diode, constituting the body diode structure. At the turn-off moment, the body diode region provides an additional extraction channel for carriers, reducing the turn-off time of the device and the turn-off loss of the device.

[0065] Figure 6 The forward conduction characteristic comparison diagram and equivalent circuit diagram of Embodiment 1 and the traditional LIGBT are shown. During forward conduction, the emitter is grounded, a positive voltage of 15V is applied to the gate, and a gradually increasing positive voltage is applied to the collector. The equivalent circuit diagram shows the directions of the electron current and the hole current: electrons start from the N+ electron emitter, flow through the channel to the drift region, and finally flow to the collector; holes start from the P+ collector, reach the drift region, and have a conductivity modulation effect with electrons. During the forward conduction stage, the conduction voltage drop of the traditional LIGBT is relatively small, being 1.03V; the conduction voltage drop of Embodiment 1 is 1.26V. During the forward conduction stage, the holes in the drift region of Embodiment 1 can be extracted through the body diode, the conductivity modulation effect in the drift region is weakened, and the conduction voltage drop increases. Therefore, the conduction voltage drop of the device in Embodiment 1 is slightly higher than that of the traditional LIGBT.

[0066] Figure 7 The reverse conduction characteristic comparison diagram and equivalent circuit diagram of Embodiment 1 are shown. The P+ surface layer is the anode of the surface diode, the P-type floating layer is the drift region of the surface diode, the N-isolation region is the drift region of the surface diode, and the N+ surface layer is the cathode of the surface diode, constituting the surface diode structure. The P+ surface layer is the anode of the body diode, the P-top region is the drift region of the body diode, the N-type drift region and the N-isolation region are the drift regions of the body diode, and the N+ surface layer is the cathode of the body diode. During reverse conduction, the collector is grounded, and a gradually increasing positive voltage is applied to the emitter. Thanks to the introduction of the surface diode and the body diode, the device can conduct in the reverse direction. The reverse conduction voltage drop of the device in Embodiment 1 is 0.95V.

[0067] Figure 8It is the current density distribution diagram when reverse conduction occurs in Embodiment 1. The P+ surface layer is the anode of the surface diode, the P-type floating layer is the drift region of the surface diode, the N- isolation region is the drift region of the surface diode, and the N+ surface layer is the cathode of the surface diode, forming a surface diode structure. The P+ surface layer is the anode of the body diode, the P-top region is the drift region of the body diode, the N-type drift region and the N- isolation region are the drift regions of the body diode, and the N+ surface layer is the cathode of the body diode. The current flow direction during reverse conduction can be seen, and mainly the surface diode bears the reverse current.

[0068] Figure 9 For the comparison of the blocking characteristics of Embodiment 1 and the traditional LIGBT in the drift region length L D It is the comparison diagram of the blocking characteristics when it is 20μm. In Embodiment 1, when the drift region concentration is 5×10 15 cm -3 the breakdown voltage is the largest, which is 324V; for the traditional LIGBT, when the drift region concentration is 3×10 15 cm -3 the breakdown voltage is 308V. This is because the traditional LIGBT has no P-top structure, and the P-top region can mutually deplete with the N-type drift region during the blocking stage, perform charge compensation, optimize the electric field distribution, and improve the breakdown voltage of the device.

[0069] Figure 10 It is the potential distribution diagram of Embodiment 1 and the traditional LIGBT under the condition of avalanche breakdown. (a) is the potential distribution diagram of the traditional LIGBT, and (b) is the potential distribution diagram of Embodiment 1. It can be seen from the figure that the potential distribution of the LIGBT device in Embodiment 1 is the densest and most uniform, so the breakdown voltage of the device in Embodiment 1 is larger than that of the traditional LIGBT.

[0070] Figure 11 It is the comparison diagram of the forward conduction characteristics of Embodiment 1 and the traditional LIGBT when the collector voltage is relatively large. During forward conduction, the emitter is grounded, a positive voltage of 15V is applied to the gate, and a gradually increasing positive voltage is applied to the collector. During the forward conduction stage, holes can be extracted through the body diode, reducing the saturation current density of the device and enhancing the short-circuit safe operating characteristics of the device. While the traditional LIGBT device has no redundant extraction channel, therefore, the saturation current density of Embodiment 1 is lower.

[0071] Figure 12For the turn-off characteristics and equivalent circuit diagram of Example 1 and the traditional LIGBT under the same on-state voltage drop, a resistive load is selected for the turn-off circuit. The P+ surface layer is the anode of the surface diode, the P-type floating layer is the drift region of the surface diode, the N- isolation region is the drift region of the surface diode, and the N+ surface layer is the cathode of the surface diode, forming a surface diode structure. The P+ surface layer is the anode of the body diode, the P-top region is the drift region of the body diode, the N-type drift region and the N- isolation region are the drift regions of the body diode, and the N+ surface layer is the cathode of the body diode. The turn-off time refers to the time taken for the collector current to drop from 90% to 10%. The equivalent circuit diagram shows the extra extraction channels of the device in Example 1 compared with the traditional LIGBT device. The turn-off loss of Example 1 is the smallest because at the turn-off moment, the body diode region provides an extraction channel for holes, and the carriers in the drift region of the device are quickly extracted, so the turn-off loss is low.

[0072] In summary, a LIGBT device integrating surface and body anti-parallel diodes proposed by the present invention has the following advantages: (1) In the forward conduction stage, when the collector voltage is small, some holes in the drift region will be extracted by the body diode region, the conductance modulation effect weakens, and the on-state voltage drop of the device increases; when the collector voltage is large, holes can be extracted through the body diode region, reducing the saturation current density of the device and enhancing the short-circuit safe operating characteristics of the device; (2) In the reverse conduction stage, due to the introduction of the surface diode and the body diode, the device can conduct reversely; (3) At the turn-off moment, holes can be extracted through the body diode, and electrons can be extracted through the N+ surface layer, reducing the turn-off time and turn-off loss; (4) In the forward blocking stage, the P-top region and the N-type drift region are depleted of each other and charge compensated, further optimizing the electric field.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. An LIGBT device integrated with surface and body anti-parallel diodes, characterized in that: It is divided into a diode region and an LIGBT region from top to bottom, and the diode region is further divided into a surface diode region and a body diode region; The LIGBT region includes a P+ emitter (5), an N+ electron emitter (6), an emitter (12), a P-body (7), a gate (13), a silicon dioxide insulating layer (15), an N-type drift region (3), a P-top region (4), an N-type buffer layer (2), a P+ collector (1), a collector (14), and a P-type substrate (16) arranged from left to right; the P+ emitter (5) is located below the emitter (12), its left side is flush with the left side of the device, its right side is closely connected to the left side of the N+ electron emitter (6), and its lower side is connected to the P-body (7); the N+ electron emitter (6) is located below the emitter (12), its right side is connected to the gate (13), and its lower side is the P-body (7); the upper side of the P-body (7) is flush with the upper sides of the P+ emitter (5) and the N+ electron emitter (6), and its lower side is completely covered by the N-type drift region (3); the upper side of the N-type drift region (3) is flush with the upper sides of the P+ emitter (5), the N+ electron emitter (6), the silicon dioxide insulating layer (15), the gate (13), the P-top region (4), the N-type buffer layer (2), and the P+ collector (1), its left side is flush with the left side of the device, its lower side is in contact with the silicon dioxide insulating layer (15), and its right side is flush with the right side of the device; the upper side of the P-top region (4) is flush with the upper side of the N-type drift region (3), its left side is in contact with the silicon dioxide insulating layer (15), and its right side and lower side are completely covered by the N-type drift region (3); the upper side of the N-type buffer layer (2) is flush with the upper sides of the N-type drift region (3) and the P+ collector (1), its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type drift region (3); the P+ collector (1) is located below the collector (14), its upper side is flush with the upper sides of the N-type drift region (3) and the N-type buffer layer (2), its right side is flush with the right side of the device, and its left side and lower side are completely covered by the N-type buffer layer (2); the lower side of the silicon dioxide insulating layer (15) is connected to the upper side of the P-type substrate (16), and its left side and right side are flush with the P-type substrate (16); The diode region includes a P+ surface layer (11), a P-type floating layer (10), an N- isolation region (9), and an N+ surface layer (8) arranged from left to right; on the left side of the P+ surface layer (11) is the emitter (12), on the right side it is in close contact with the left side of the P-type floating layer (10), on the lower side it is in close contact with the upper side of the P-top region (4), and on the upper side it is flush with the upper sides of the P+ surface layer (11), the N- isolation region (9), and the N+ surface layer (8); on the left side of the P-type floating layer (10) it is in contact with the P+ surface layer (11), on the right side it is in close contact with the left side of the N- isolation region (9), on the lower side it is in close contact with the upper side of the P-top region (4), and on the upper side it is flush with the upper sides of the P-type floating layer (10), the N- isolation region (9), and the N+ surface layer (8); on the left side of the N- isolation region (9) it is in contact with the P-type floating layer (10), on the right side it is in close contact with the left side of the N+ surface layer (8), on the lower side it is in close contact with the N-type drift region (3) and the silicon dioxide insulating layer (15), and on the upper side it is flush with the upper sides of the P-type floating layer (10), the N- isolation region (9), and the N+ surface layer (8); on the left side of the N+ surface layer (8) it is in close contact with the right side of the N- isolation region (9), on the right side is the collector (14), and on the lower side is the silicon dioxide insulating layer (15); In the diode region, the P+ surface layer (11) is the anode of the surface diode, the P-type floating layer (10) is the drift region of the surface diode, the N- isolation region (9) is the drift region of the surface diode, the N+ surface layer (8) is the cathode of the surface diode, forming a surface diode structure; the P+ surface layer (11) is the anode of the body diode, the P-top region (4) is the drift region of the body diode, the N-type drift region (3) and the N- isolation region (9) are the drift regions of the body diode, the N+ surface layer (8) is the cathode of the body diode, forming a body diode structure.

2. The LIGBT device integrating a surface and a body anti-parallel diode according to claim 1, wherein: The LIGBT region further includes an N-type column (17) and a P-type column (18); on the right side of the P-top region (4) it is in contact with the N-type drift region (3), and on the lower side it is in close contact with the N-type column (17); on the upper side of the N-type column (17) it is in close contact with the lower side of the P-top region (4), and on the lower side it is in close contact with the upper side of the P-type column (18); on the upper side of the P-type column (18) it is in close contact with the lower side of the N-type column (17), and on the lower side it is flush with the lower side of the N-type drift region (3); on the lower side of the N- isolation region (9) it is in close contact with the P-top region (4) and the silicon dioxide insulating layer (15).

3. The LIGBT device integrating a surface and a body anti-parallel diode according to claim 1, characterized in that: The LIGBT region further includes a hole blocking layer (19), the upper side of the hole blocking layer (19) is in close contact with the P-body (7), on the left side it is flush with the left side of the device, and on the right side it is in close contact with the silicon dioxide insulating layer (15).

4. The LIGBT device integrating a surface and a body anti-parallel diode according to any one of claims 1-3, characterized in that: The material of the gate (13) includes doped polysilicon or aluminum.

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