A gate-all-around reconfigurable field effect transistor with asymmetric source and drain

Abstract

The present invention discloses a source-drain asymmetric ring-gate reconfigurable field effect transistor, comprising a vertically arranged nanosheet or nanowire channel, a gate oxide wrapped outside the channel and located below the gate and the gate isolation, a control gate and a polarity gate symmetrically arranged outside the gate oxide, a gate isolation wrapped outside the channel for isolating the control gate from the polarity gate, and side walls arranged at the left and right ends of the channel and wrapped outside the channel, a drain arranged at one end of the channel and a source extending inside the source side wall at the other end of the channel, and a substrate arranged at the bottom. Compared with the existing source-drain symmetrical device, the source extending inside the source side wall increases the contact area between the source end and the channel, increases the probability of carrier line tunneling, and improves the on-state current. When turned off, the drain end structure is the same as the non-overlapping area of ​​the drain structure of the source-drain symmetrical device, and the off-state current remains basically unchanged, so it has a more ideal current switching ratio and a faster logic response.

Description

Technical Field

[0001] The invention belongs to the field of field effect transistors in semiconductor devices, and in particular relates to a ring-gate reconfigurable field effect transistor with asymmetric source and drain. Background Art

[0002] The miniaturization of transistor size has witnessed the development of semiconductor technology. With the continuous advancement of process nodes, the performance degradation of traditional bulk silicon devices has become increasingly important. At the same time, economic constraints and process barriers have also posed huge challenges to the continuation of Moore's Law. In order to meet the needs of the times, many new device structures have been proposed one after another. Among them, the Nanosheet Gate-All-Around Field-Effect Transistor and the Nanowire Gate-All-Around Field-Effect Transistor have become one of the most attractive structures of 5 nanometers and below due to their excellent gate control capabilities and excellent electrostatic integrity. By vertically arranging nanosheets or nanowire channels, a larger saturation current can be obtained on the basis of a certain area, improving device integration and solving the contradiction between power consumption and performance.

[0003] At the same time, reconfigurable field effect transistors (RFETs) have attracted much attention due to their structural advantages and their ability to realize complex logic circuits with a lower number of transistors. By setting two independent gates, the device can flexibly switch between N-type and P-type. The bias of the polarity gate determines the type of carriers that tunnel in the Schottky junctions at both ends, and the control gate affects the on-off of the device. Compared with CMOS-based circuits, its functional selectivity is better. However, the dependence of the tunneling mechanism makes the on-state current density of the device still small, and its application occasions are relatively limited. Summary of the invention

[0004] The purpose of the present invention is to address the problem of small on-state current of existing source-drain symmetrical ring-gate reconfigurable field effect transistors, and to propose a source-drain asymmetrical ring-gate reconfigurable field effect transistor, which increases the probability of carrier line tunneling at the source end, increases the carrier tunneling area, and improves the on-state current of the device, while keeping the off-state current basically unchanged, thereby improving the current switching ratio of the device and reducing the logic response time of the integrated circuit.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A gate-all-around reconfigurable field effect transistor with asymmetric source and drain, characterized in that it comprises:

[0007] Several vertically arranged channels;

[0008] a source disposed at the left end of the plurality of channels and extending toward the interior of the source sidewall;

[0009] A drain located at the right end of several channels;

[0010] A gate oxide wrapped around the outside of each channel and in contact with the control gate and the polarity gate and the gate isolation;

[0011] A control gate and a polarity gate symmetrically arranged and wrapped around the outside of the gate oxide;

[0012] A gate isolation wrapped around the outside of the channel and disposed between the control gate and the polarity gate;

[0013] A source side wall disposed on the left side of the control gate and the right side of the source and wrapped outside the channel;

[0014] A drain side wall disposed on the right side of the polarity gate and the left side of the drain and wrapped outside the channel;

[0015] A substrate disposed at the bottom of the structure;

[0016] The channel is a silicon nanosheet, a germanium nanosheet, a germanium silicon nanosheet, a gallium arsenide nanosheet, a zinc oxide nanosheet or a silicon nanowire, a germanium nanowire, a germanium silicon nanowire, a gallium arsenide nanowire or a zinc oxide nanowire;

[0017] The source and drain extending into the source sidewall are one or a combination of titanium silicide, nickel silicide, cobalt silicide, titanium nitride, and tantalum nitride;

[0018] The gate oxide is silicon dioxide or hafnium dioxide;

[0019] The control gate and polarity gate are aluminum, copper, polysilicon or titanium nitride formed by photolithography and etching;

[0020] The gate isolation is silicon dioxide, silicon nitride, silicon oxynitride, hafnium dioxide, phosphosilicate glass or borophosphosilicate glass deposited outside the channel and between the control gate and the polarity gate;

[0021] The source sidewall and the drain sidewall are made of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borophosphosilicate glass;

[0022] The substrate is bulk silicon, silicon on insulating layer or germanium on insulating layer;

[0023] The length of the source extending into the source sidewall is less than the length of the source sidewall, and the height of the source extension is equal to the height of the source sidewall; the height of the gate isolation is equal to the sum of the height of the control gate and the gate oxide, and equal to the sum of the height of the polarity gate and the gate oxide;

[0024] The gate-all-around reconfigurable field effect transistor with asymmetric source and drain proposed in the present invention has the following advantages compared with the general source-drain symmetric device:

[0025] The off-state current remains unchanged while the on-state current of the device is increased, improving the current switching ratio;

[0026] The switch delay time is reduced, the load driving capability is stronger, and it has stronger logic processing capability;

[0027] It has a wide range of applications and is suitable for fields requiring high current such as high power, radio frequency and microwave. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention taking a nanosheet as an example;

[0029] Figure 2 for Figure 1 Cross-section at AA;

[0030] Figure 3 The middle figures (a), (b), and (c) are Figure 1 Cross-sectional views at BB, CC and DD;

[0031] Figure 4 An energy band diagram for characterizing the N-type and P-type electrical characteristics of existing source-drain symmetric devices along the lateral channel center position of the channel;

[0032] Figure 5 The energy band diagram of the present invention using nanosheets as an example to characterize the N-type and P-type electrical characteristics along the lateral channel center position of the channel;

[0033] Figure 6 The energy band diagram of the channel along the longitudinal position of the channel is characterized by taking the nanosheet as an example of the N-type electrical characteristics of the present invention;

[0034] Figure 7 The present invention uses nanosheets as an example to characterize the energy band diagram of the channel along the longitudinal position of the channel for P-type electrical characteristics;

[0035] Figure 8 The figure is a transfer characteristic curve diagram of the present invention and the existing source-drain symmetrical device;

[0036] Fig. 9 The output characteristic curve diagram of the present invention and the existing source-drain symmetrical device;

[0037] Fig.10 This is a preparation flow chart of the present invention taking nanosheets as an example. DETAILED DESCRIPTION

[0038] The present invention is described in detail below with reference to the accompanying drawings and an embodiment taking nanosheets as an example.

[0039] See also Figure 1-3 The characteristic of the asymmetric source-drain ring-gate reconfigurable field effect transistor is that, at the nanosheet channel near one end of the control gate, the source composed of metal silicide extends a certain length into the source side wall, the extended length is less than the length of the source side wall, and the height of the extended part is equal to the height of the source side wall.

[0040] The gate-all-around reconfigurable field effect transistor with asymmetric source and drain comprises a plurality of vertically arranged channels 1; a source 2 arranged at the left end of the plurality of channels 1 and extending to the inside of a source sidewall 8; a drain 3 arranged at the right end of the plurality of channels 1; a gate oxide 4 wrapped around the outside of each channel 1 and in contact with a control gate 5, a polarity gate 6 and a gate isolation 7; a control gate 5 and a polarity gate 6 symmetrically arranged and wrapped around the outside of the gate oxide 4; a gate isolation 7 wrapped around the outside of the channel 1 and arranged between the control gate 5 and the polarity gate 6; a source sidewall 8 arranged on the left side of the control gate 5 and the right side of the source 2 and wrapped around the outside of the channel 1; a drain sidewall 9 arranged on the right side of the polarity gate 6 and the left side of the drain 3 and wrapped around the outside of the channel 1; and a substrate 10 arranged at the bottom of the above structure.

[0041] The channel 1 is a silicon nanosheet, a germanium nanosheet, a germanium silicon nanosheet, a gallium arsenide nanosheet, a zinc oxide nanosheet or a silicon nanowire, a germanium nanowire, a germanium silicon nanowire, a gallium arsenide nanowire or a zinc oxide nanowire;

[0042] The source 2 and drain 3 extending into the source sidewall 8 are one or a combination of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride;

[0043] The gate oxide 4 is silicon dioxide or hafnium dioxide;

[0044] The control gate 5 and polarity gate 6 are aluminum, copper, polysilicon or titanium nitride formed by photolithography and etching;

[0045] The gate isolation 7 is silicon dioxide, silicon nitride, silicon oxynitride, hafnium dioxide, phosphosilicate glass or borophosphosilicate glass deposited outside the channel 1 and between the control gate 5 and the polarity gate 6;

[0046] The source sidewall 8 and the drain sidewall 9 are made of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borophosphosilicate glass;

[0047] The substrate 10 is bulk silicon, silicon on insulating layer or germanium on insulating layer.

[0048] In source-drain symmetrical devices, carrier tunneling occurs in a direction perpendicular to the gate electric field. This tunneling is point tunneling and only occurs at the gate-source junction, and the on-state current is limited by the contact area. The present invention adopts an asymmetric source-drain structure, and the source structure extending to the inside of the side wall makes it possible for carriers to undergo line tunneling in a direction parallel to the gate electric field. The increase in carrier line tunneling increases the tunneling area of ​​the device, thereby increasing the on-state current density, and the carrier tunneling area can be regulated according to demand. Increasing the proportion of the device line tunneling part can effectively increase the on-state current. Since the asymmetric structure drain end structure is no different from the symmetrical device, the leakage current of the present invention remains basically unchanged when it is turned off, so it has a more ideal current switching ratio. While ensuring that the static power consumption remains unchanged, the operation delay time of the logic gate current is shortened.

[0049] Figure 5 and Figure 4 This shows that the energy band diagram of the present invention is different from that of the existing source-drain symmetrical device in the open state along the lateral position of the channel. The first channel, the second channel and the third channel correspond to Figure 1 There are three nanosheet channels from top to bottom in the structure diagram, among which E C represents the conduction band energy level, E V represents the valence band energy level, E fn represents the electron quasi-Fermi level, E fp represents the quasi-Fermi level of holes, the same below. The figure shows the energy band diagram of channel 1. It can be seen that in the source-drain symmetrical device, the carriers are mainly transported by lateral point tunneling. In comparison, the lateral tunneling barrier height of the present invention remains unchanged, but the barrier width increases, the tunneling probability decreases, and the point tunneling current is only one-third of that. Therefore, the point tunneling of the carriers in the present invention contributes less to the on-state current.

[0050] Figure 6 and Figure 7 The energy band diagrams at the longitudinal position of the channel when the present invention is used as an N-type and P-type device in the open state are respectively given. Along the vertical channel direction, the second channel is affected by the electric field on both the upper and lower surfaces, and the forces acting on the energy band cancel each other out, so the probability of carrier tunneling is low, but it is still higher than the point tunneling probability of the source-drain symmetrical device. Under the action of the vertical electric field, the energy bands of the first channel and the third channel bend to form a steep barrier, and the carriers can undergo vertical line tunneling, crossing from the channel surface to the center, forming a larger on-state current. Therefore, in addition to being formed by carrier point tunneling, the on-state current is also greatly improved by carrier line tunneling, and the latter occupies the main part.

[0051] Figure 8-9 The present invention provides a transfer characteristic curve and an output characteristic curve of a source-drain symmetrical device, V CG Represents the control gate voltage, V PGrepresents the polarity gate voltage. When the device exhibits N-type characteristics, the on-state current of the present invention is 8.93×10 -6 A, the off-state current is 1.53×10 -14 A, the current switching ratio is 5.84×10 8 ; When the device adopts a symmetrical structure, the on-state current is 1.78×10 -6 A, the off-state current is 1.86×10 -14 A, the current switching ratio is 9.57×10 7 When the device exhibits P-type characteristics, the on-state current of the present invention is 2.37×10 -5 A, the off-state current is 1.72×10 -13 A, the current switching ratio is 1.38×10 8 ; When the device adopts a symmetrical structure, the on-state current is 1.34×10 -6 A, the off-state current is 1.47×10 -14 A, the current switching ratio is 9.12×10 7 The switching efficiency of the gate-all-around device with asymmetric source and drain is improved by one order of magnitude compared with the symmetric device.

[0052] See also Fig.10 , the production process of the present invention is as follows:

[0053] (1) Obtaining a silicon substrate 10 by ion implantation and annealing;

[0054] (2) using molecular beam epitaxy technology to sequentially grow germanium silicon, silicon, germanium silicon, silicon, germanium silicon, and silicon stacked thin films on the silicon substrate 10;

[0055] (3) using a self-aligned double patterning technique to carve out a fin-shaped channel on the silicon substrate 10 using the sidewall as a hard mask, and performing a thermal annealing;

[0056] (4) Using chemical vapor deposition technology, polysilicon is deposited and then photolithography is performed to form a virtual control gate and a virtual polarity gate;

[0057] (5) Using chemical vapor deposition technology, depositing source electrical isolation sidewall 8, leakage electrical isolation sidewall 9 and virtual gate isolation;

[0058] (6) Reactive ion etching technology is used to anisotropically etch the source and drain germanium silicon stacked layers, and the etching length is consistent with the length of the drain side wall 9;

[0059] (7) using chemical vapor deposition technology to deposit dielectrics between the nanosheets to form source side walls 8 and drain side walls 9;

[0060] (8) Reactive ion etching technology is used to anisotropically etch the inside of the source side wall 8. The etching length should be less than the length of the source side wall 8, exposing the area where the source 2 extends to the inside of the source side wall 8;

[0061] (9) Using physical vapor deposition technology, prepare metal silicide source 2 and drain 3, fill the internal gap of source sidewall 8, and perform rapid annealing;

[0062] (10) using reactive ion etching technology, anisotropically etching the virtual gate and virtual gate isolation, leaving the silicon-germanium silicon stack layer, and then etching the germanium silicon material to release the nanosheet channel 1;

[0063] (11) Depositing HfO2 into the gap between the nanosheets and etching back using anisotropic etching to form gate oxide 4;

[0064] (12) Using chemical vapor deposition technology, a dielectric is deposited in the gap between the nanosheets and then photolithographically etched to form a gate isolation 7;

[0065] (13) Using atomic layer deposition technology, the control gate 5 and the polarity gate 6 are deposited and etched. After the deposition is completed, a rapid thermal annealing is performed to form Figure 1 The structure shown.

[0066] The control gate 5, polarity gate 6, source 2 and drain 3 are led out through tungsten plugs, and all electrodes are flattened by chemical mechanical polishing technology. The devices of the present invention are connected together through metal wires using CMOS ultra-large-scale circuit back-end Damascus technology.

Claims

1. A gate-all-around reconfigurable field effect transistor with asymmetric source and drain, characterized in that it include: Several vertically arranged channels (1); A source (2) disposed at the left end of the plurality of channels (1) and extending toward the inside of the source side wall (8); A drain (3) provided at the right end of the plurality of channels (1); A gate oxide (4) wrapped around the outside of each channel (1) and in contact with the control gate (5), the polarity gate (6) and the gate isolation (7); A control gate (5) and a polarity gate (6) are symmetrically arranged and wrapped around the outside of the gate oxide (4); A gate isolation (7) wrapped around the outside of the channel (1) and arranged between the control gate (5) and the polarity gate (6); A source side wall (8) disposed on the left side of the control gate (5) and on the right side of the source (2) and wrapped outside the channel (1); A drain side wall (9) disposed on the right side of the polarity gate (6) and on the left side of the drain (3) and wrapped outside the channel (1); A substrate (10) is provided at the bottom of the above structure; wherein: The length of the source (2) extending into the source sidewall (8) is less than the length of the source sidewall (8), and the height of the source (2) extending is equal to the height of the source sidewall (8); the height of the gate isolation (7) is equal to the sum of the heights of the control gate (5) and the gate oxide (4), and is equal to the sum of the heights of the polarity gate (6) and the gate oxide (4).

2. The gate-all-around reconfigurable field effect transistor with asymmetric source and drain according to claim 1, characterized in that: The channel (1) is a silicon nanosheet, a germanium nanosheet, a germanium silicon nanosheet, a gallium arsenide nanosheet, a zinc oxide nanosheet or a silicon nanowire, a germanium nanowire, a germanium silicon nanowire, a gallium arsenide nanowire or a zinc oxide nanowire; The source (2) and drain (3) are one or a combination of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride; The gate oxide (4) is silicon dioxide or hafnium dioxide; The control gate (5) and the polarity gate (6) are made of aluminum, copper, polysilicon or titanium nitride formed by photolithography and etching; The gate isolation (7) is silicon dioxide, silicon nitride, silicon oxynitride, hafnium dioxide, phosphosilicate glass or borophosphosilicate glass deposited outside the channel (1) and between the control gate (5) and the polarity gate (6); The source sidewall (8) and the drain sidewall (9) are made of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borophosphosilicate glass; The substrate (10) is bulk silicon, silicon on an insulating layer, or germanium on an insulating layer.

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