A method for effectively avoiding cracks in the corners of mercury cadmium telluride infrared detector chips

Abstract

The present invention provides a method for effectively preventing cracks in the edges and corners of a mercury cadmium telluride infrared detector chip, comprising the following steps: S1: performing proximity photolithography on the front and / or back of the mercury cadmium telluride chip to produce at least one frame pattern around the front and / or back of the mercury cadmium telluride chip, wherein the frame pattern is located outside the effective imaging area of ​​the chip and is spaced apart from the effective imaging area of ​​the chip; S2: transferring the frame pattern in step S1 to the front and / or back of the mercury cadmium telluride chip after photolithography through a wet etching process, etching the mercury cadmium telluride material located around the effective imaging area of ​​the chip on the front and / or back of the mercury cadmium telluride chip and forming a groove at the position of the frame pattern; S3: after the groove etching is completed, the mercury cadmium telluride chip is cleaned and then subjected to the next chip process. This method can prevent the hidden danger of cracks caused by edge collapse during dicing from being outside the effective imaging area of ​​the mercury cadmium telluride chip, thereby improving the qualified rate of mercury cadmium telluride chip preparation.

Description

Technical Field

[0001] The invention relates to a method for effectively avoiding corner cracks in a mercury cadmium telluride infrared detector chip, and belongs to the technical field of mercury cadmium telluride infrared detector manufacturing. Background Art

[0002] The description in this section merely provides background information related to the disclosure of this specification and does not constitute prior art.

[0003] Mercury cadmium telluride infrared detectors (MCT Infrared Detector) are one of the current mainstream developments in the field of infrared detectors both domestically and internationally, and are widely used in military infrared thermal imaging, aerospace, and satellite infrared remote sensing. The core of a mercury cadmium telluride infrared detector is the detector chip, and chip manufacturing technology directly affects the performance of the detector chip and determines whether the detector can meet the current detector operating standards both domestically and internationally. In existing mercury cadmium telluride infrared detector chips, although the mercury cadmium telluride material is grown as an epitaxial layer on a substrate material, the substrate will eventually be thinned and corroded during the detector manufacturing process, leaving only the mercury cadmium telluride epitaxial layer and the readout circuit to form the detector chip by means of reverse solder connection and filling with glue. The detector chip manufactured in this way needs to withstand various reliability indicators such as temperature and vibration after packaging and cooling operations.

[0004] Currently, in the preparation process of HgCdTe infrared detectors, during the substrate cutting process, due to the dicing knife, a certain degree of edge chipping is unavoidable around the HgCdTe chip. After the substrate is completely removed, an anti-reflection film is coated on the back of the chip and tested by bonding. After the test, the edges of the HgCdTe chip are prone to cracking along the edge chipping caused by cutting, and even extend into the effective imaging area. The crack position is not fixed. This is because the HgCdTe chip undergoes a process of rapid temperature drop from room temperature to low temperature in the liquid nitrogen dewar. This rapid temperature change causes a stress mismatch between the HgCdTe chip and the readout circuit, which directly leads to the formation of cracks at the edge of the substrate and extension to the effective area of ​​the chip. This phenomenon greatly reduces the pass rate of HgCdTe chips. How to effectively improve this phenomenon has become one of the key technologies in the HgCdTe chip preparation process.

[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of this specification and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this specification, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method that can effectively avoid cracks at the edges and corners of mercury cadmium telluride infrared detector chips in response to the shortcomings of the existing technology. This method can block the hidden dangers of cracks caused by edge collapse during dicing outside the effective imaging area of ​​the mercury cadmium telluride chip, thereby effectively blocking cracks caused by edge collapse and greatly improving the qualified rate of mercury cadmium telluride chip preparation.

[0007] This solution is achieved through the following technical measures: A method for effectively avoiding cracks in the corners of mercury cadmium telluride infrared detector chips, which includes the following steps:

[0008] S1: performing proximity photolithography on the front and / or back of the mercury cadmium telluride chip to generate at least one frame pattern around the front and / or back of the mercury cadmium telluride chip, wherein the frame pattern is located outside the effective imaging area of ​​the chip and has a gap between the effective imaging area of ​​the chip;

[0009] S2: transferring the frame pattern in step S1 to the front and / or back of the HgCdTe chip after photolithography by wet etching, etching the HgCdTe material around the effective imaging area of ​​the chip on the front and / or back of the HgCdTe chip to form a groove at the position of the frame pattern;

[0010] S3: After the groove etching is completed, the HgCdTe chip is cleaned and then proceeds to the next chip process.

[0011] Preferably, the width of the groove is 1 μm to 200 μm.

[0012] Preferably, the groove depth on the front side of the mercury cadmium telluride chip is 1 μm to 50 μm.

[0013] Preferably, the groove depth on the front side of the mercury cadmium telluride chip is 20 μm.

[0014] Preferably, the depth of the groove on the back side of the HgCdTe chip is equal to the thickness of the epitaxial layer of the HgCdTe chip.

[0015] Preferably, the frame graphic is rectangular or quasi-rectangular, and correspondingly, the groove is a rectangular groove or a quasi-rectangular groove.

[0016] Preferably, the quasi-rectangular groove has four corners with chamfered outer corners, chamfered inner corners, chamfered right angles or chamfered bevels.

[0017] Preferably, the quasi-rectangular groove is a rectangular groove whose edge is wavy, rectangular gear-shaped or sawtooth-shaped.

[0018] The present invention effectively prevents the extension of edge cracks in HgCdTe chips, significantly reducing the impact of chip edge cracks on the chip's effective imaging area and significantly improving the yield rate of HgCdTe chip production. It also boasts simple process steps, a wide process window, and the ability to operate in large quantities. This demonstrates that the present invention offers outstanding substantive features and significant advancements over existing technologies, and its beneficial effects are readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the front structure of the mercury cadmium telluride chip in the present invention.

[0020] Figure 2 This is a schematic diagram of the partial structure of the back side of the mercury cadmium telluride chip in the present invention.

[0021] Figure 3 It is a structural schematic diagram of the rectangular groove in the present invention.

[0022] In the figure, 1-readout circuit, 2-mercury cadmium telluride chip, 3-effective imaging area of ​​the chip, 4-groove on the back, 5-pin PAD on the readout circuit. DETAILED DESCRIPTION

[0023] In order to clearly illustrate the technical features of this solution, the solution is described below through specific implementation methods and in conjunction with the accompanying drawings.

[0024] Example 1:

[0025] A method for effectively preventing cracks in the corners of a mercury cadmium telluride infrared detector chip comprises the following steps:

[0026] S1: Proximity photolithography is performed on the front surface of the mercury cadmium telluride chip to generate at least one circle of frame pattern around the front surface of the mercury cadmium telluride chip, wherein the frame pattern is located at the periphery of the effective imaging area of ​​the chip and a gap is left between the effective imaging area of ​​the chip; wherein the frame pattern is rectangular or quasi-rectangular, and correspondingly, the groove is a rectangular groove or a quasi-rectangular groove; wherein the quasi-rectangular groove is a rectangular groove with rounded corners (such as Figure 3 (a)), fillet (as shown in Figure 3 (b)), chamfered right angle (as shown in Figure 3 (d)) or chamfered angle (as shown in Figure 3 (f)), the rectangular groove may also be a rectangular groove with a wavy edge (as shown in FIG. Figure 3 (c)), rectangular gear teeth (as shown Figure 3 (e)) or zigzag;

[0027] S2: transferring the frame pattern in step S1 to the front side of the HgCdTe chip through a wet etching process, etching the HgCdTe material around the effective imaging area of ​​the chip on the front side of the HgCdTe chip and forming a groove at the position of the frame pattern; the width of the groove is 1 μm to 200 μm, and a groove width less than 1 μm or greater than 200 μm will make the designed groove processing very difficult; the depth of the groove is 1 μm to 50 μm, preferably the depth of the groove is 20 μm; a groove depth less than 1 μm or greater than 50 μm will make the designed groove processing very difficult;

[0028] S3: After the groove etching is completed, the HgCdTe chip is cleaned and then proceeds to the next chip process.

[0029] In this embodiment, rectangular grooves or quasi-rectangular grooves are formed around the front surface of the HgCdTe chip to prevent cracks at the four corners and other edge anomalies from affecting the chip imaging area, thereby achieving the design requirement of improving the yield of the HgCdTe chip.

[0030] The HgCdTe chip before front grooving has no barrier structure or means, so the chipping or cracks caused by the scribing process and other processes are at risk of spreading to the central imaging area of ​​the HgCdTe chip, seriously affecting the chip imaging effect and the yield of qualified chips. By combining proximity lithography with wet etching, after the front of the HgCdTe chip is grooved, a circle of rectangular grooves or quasi-rectangular grooves is formed on the front of the HgCdTe chip. The groove width is designed to be 15μm. However, since the groove process is wet etching, there is corrosion expansion, and the actual etching width is greater than 15μm. In this embodiment, by isolating the chip's effective imaging area from the chip's chipping (and cracks), the chip's effective imaging area can achieve a shielding effect on the chip's chipping and cracks, greatly reducing adverse effects, thereby improving the yield of qualified chips. Specific data statistics are shown in Table 1.

[0031] category Processing / Module Cracks / modules Crack generation ratio Ungrooved 85 72 84.7％ After grooving 103 5 4.85％

[0032] Table 1: Statistics of slot cracking data in an actual production line of HgCdTe chips using Example 1

[0033] As shown in Table 1, the crack rate after slotting the front side of the HgCdTe chip dropped from 84.7% to 4.85%. This data does not rule out other causes of cracking besides edge and corner cracking (such as photolithography particle capping). This significant reduction in crack rate directly and significantly improves the yield of HgCdTe chips, and thus the yield of HgCdTe detectors.

[0034] Example 2:

[0035] A method for effectively preventing cracks in the corners of a mercury cadmium telluride infrared detector chip comprises the following steps:

[0036] S1: Proximity photolithography is performed on the back side of the HgCdTe chip to generate at least one frame pattern around the back side of the HgCdTe chip, wherein the frame pattern is located at the periphery of the effective imaging area of ​​the chip and a gap is left between the effective imaging area of ​​the chip; wherein the frame pattern is rectangular or quasi-rectangular, and correspondingly, the groove is a rectangular groove or a quasi-rectangular groove; wherein the quasi-rectangular groove is a rectangular groove with rounded corners (such as Figure 3 (a)), fillet (as shown in Figure 3 (b)), chamfered right angle (as shown in Figure 3 (d)) or chamfered angle (as shown in Figure 3 (f)), the rectangular groove may also be a rectangular groove with a wavy edge (as shown in FIG. Figure 3 (c)), rectangular gear teeth (as shown Figure 3 (e)) or zigzag;

[0037] S2: transferring the frame pattern in step S1 to the back side of the HgCdTe chip after photolithography by wet etching, etching the HgCdTe material around the effective imaging area of ​​the chip on the back side of the HgCdTe chip to form a groove at the position of the frame pattern; the width of the groove is 1 μm to 200 μm, and the depth of the groove is the thickness of the epitaxial layer of the HgCdTe chip;

[0038] S3: After the groove etching is completed, the HgCdTe chip is cleaned and then proceeds to the next chip process.

[0039] In this embodiment, rectangular grooves or quasi-rectangular grooves are formed around the back of the HgCdTe chip to prevent corner cracks and other edge anomalies from affecting the chip imaging area, thereby achieving the design requirement of improving the yield of the HgCdTe chip.

[0040] After the back of the HgCdTe chip is grooved and coated with an antireflection film, there is no barrier structure or means between the chip imaging area and the corners. Therefore, the chip ...

[0041] category Processing / Module Cracks / modules Crack generation ratio Ungrooved 85 71 83.5％ After grooving 103 6 5.83％

[0042] Table 2: Statistics of slot cracking data in an actual production line of HgCdTe chips using Example 2

[0043] As shown in Table 2, the crack rate after back-grooving of the HgCdTe chip dropped from 83.5% to 5.83%. This data does not rule out other causes of cracking besides edge and corner cracking (such as photolithography particle capping). This significant reduction in crack rate directly improves the yield of HgCdTe chips, and thus the yield of HgCdTe detectors.

[0044] Example 3:

[0045] A method for effectively preventing cracks in the corners of a mercury cadmium telluride infrared detector chip comprises the following steps:

[0046] S1: Proximity photolithography is performed on the front and back sides of the HgCdTe chip to generate at least one frame pattern around the front and back sides of the HgCdTe chip, wherein the frame pattern is located at the periphery of the effective imaging area of ​​the chip and a gap is left between the effective imaging area of ​​the chip; wherein the frame pattern is rectangular or quasi-rectangular, and correspondingly, the groove is a rectangular groove or a quasi-rectangular groove; wherein the quasi-rectangular groove is a rectangular groove with rounded corners (such as Figure 3 (a)), fillet (as shown in Figure 3 (b)), chamfered right angle (as shown in Figure 3 (d)) or chamfered angle (as shown in Figure 3 (f)), the rectangular groove may also be a rectangular groove with a wavy edge (as shown in FIG. Figure 3 (c)), rectangular gear teeth (as shown Figure 3 (e)) or zigzag;

[0047] S2: transferring the frame pattern in step S1 to the front and back sides of the HgCdTe chip after photolithography by wet etching, etching the HgCdTe material around the effective imaging area of ​​the chip on the front and back sides of the HgCdTe chip to form grooves at the positions of the frame patterns; the width of the grooves is 1 μm to 200 μm, the depth of the grooves on the front side of the HgCdTe chip is 1 μm to 50 μm, preferably the depth of the grooves on the front side of the HgCdTe chip is 20 μm, and the depth of the grooves on the back side of the HgCdTe chip is equal to the thickness of the epitaxial layer of the HgCdTe chip;

[0048] S3: After the groove etching is completed, the HgCdTe chip is cleaned and then proceeds to the next chip process.

[0049] In this embodiment, rectangular grooves or quasi-rectangular grooves are formed around the front and back sides of the HgCdTe chip to prevent corner cracks and other edge anomalies from affecting the chip imaging area, thereby achieving the design requirement of improving the yield of the HgCdTe chip.

[0050] The HgCdTe chip before front grooving has no barrier structures or means. After the HgCdTe chip before back grooving is coated with an antireflection film, its chip imaging area and corners have no barrier structures or means. Therefore, the chip ...

[0051] category Processing / Module Cracks / modules Crack generation ratio Ungrooved 85 75 88.2％ After grooving 103 3 2.91％

[0052] Table 3: Statistics of slot cracking data in an actual production line of HgCdTe chips using Example 3

[0053] As shown in Table 3, after grooving the front and back sides of HgCdTe chips, the crack rate dropped from 88.2% to 2.91%. This data does not rule out other causes of cracking besides edge and corner cracking (such as photolithography particle capping). This significant reduction in crack rate directly improves the yield of HgCdTe chips, and thus the yield of HgCdTe detectors.

[0054] This invention has demonstrated through application that slotting the front and / or back sides of a mercury cadmium telluride chip, with the slots positioned outside the chip's effective imaging area, effectively blocks cracks while having virtually no impact on the chip's effective imaging area. This is because the slots are spaced a certain distance from the chip's effective imaging area and do not directly contact or approach pixels within the chip's effective imaging area. If the slots were placed between pixels within the chip's effective imaging area, there would be a risk of introducing new cracks into the slot walls, defeating the purpose of the slots.

[0055] The present invention can groove the front and / or back sides of HgCdTe chips. Front grooves are located in the front-end process of chip tapeout. After the front grooves are grooved, the chip still has many complex steps to go. Therefore, thorough etching is not used to avoid affecting subsequent steps. The front grooves are only etched to a certain depth, and the groove depth is positively correlated with the thickness of the epitaxial layer and the substrate material. This, to a certain extent, blocks cracks and prevents stray carriers in the epitaxial material outside the grooves from diffusing to the chip's effective imaging area. Back grooves, on the other hand, are located in the back-end process of chip tapeout, when the chip tapeout is about to be completed. This step requires low-temperature Dewar testing, which carries a greater risk of cracking. Therefore, thorough etching is chosen to effectively block cracks.

[0056] In summary, the present invention effectively avoids the extension of edge cracks of the mercury cadmium telluride chip, significantly improves the impact of chip edge cracks on the chip imaging area, greatly improves the qualified rate of mercury cadmium telluride chip preparation, and has the advantages of simple process steps, large process window, and large-scale operation. In addition, when the mercury cadmium telluride chip itself changes, such as changes in type, packaging, size, thickness, etc., it will not affect the effective barrier function of the chip slotting to the chip corner cracks. The method of slotting on the front and / or back of the mercury cadmium telluride chip is also applicable. Therefore, the present invention realizes the versatility of semiconductor chip devices, broadens the scope of application of the method of the present invention, and reduces the cost of manufacturing mercury cadmium telluride detectors.

[0057] Technical features not described in the present invention can be implemented by existing technologies and will not be described in detail here. The present invention is not limited to the above-mentioned specific embodiments. Changes, modifications, additions or substitutions made by ordinary technicians in this field within the scope of the essence of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A method for effectively preventing cracks in the corners of mercury cadmium telluride infrared detector chips, characterized by: It includes the following steps: S1: performing proximity photolithography on the front and / or back of the mercury cadmium telluride chip to generate at least one frame pattern around the front and / or back of the mercury cadmium telluride chip, wherein the frame pattern is located outside the effective imaging area of ​​the chip and has a gap between the effective imaging area of ​​the chip; S2: transferring the frame pattern in step S1 to the front and / or back of the HgCdTe chip after photolithography by wet etching, etching the HgCdTe material around the effective imaging area of ​​the chip on the front and / or back of the HgCdTe chip to form a groove at the position of the frame pattern, wherein the groove depth on the front of the HgCdTe chip is 1 μm to 50 μm, and the groove depth on the back of the HgCdTe chip is equal to the thickness of the epitaxial layer of the HgCdTe chip; The front-side grooving is in the front-end process of chip tape-out. The front-side grooving is only etched to a certain depth, and the depth of the groove is positively correlated with the thickness of the epitaxial layer and the thickness of the substrate material. The back-side grooving is in the back-end process of chip tape-out and is etched thoroughly. S3: After the groove etching is completed, the HgCdTe chip is cleaned and then proceeds to the next chip process.

2. The method for effectively preventing corner cracks in HgCdTe infrared detector chips according to claim 1, characterized in that: The width of the groove is 1 μm to 200 μm.

3. The method for effectively preventing corner cracks in HgCdTe infrared detector chips according to claim 2, characterized in that: The depth of the groove on the front side of the HgCdTe chip is 20 μm.

4. The method for effectively preventing edge cracks in HgCdTe infrared detector chips according to claim 3, wherein: The frame pattern is rectangular or quasi-rectangular, and correspondingly, the groove is a rectangular groove or a quasi-rectangular groove.

5. The method for effectively preventing edge cracks in HgCdTe infrared detector chips according to claim 4, characterized in that: The quasi-rectangular groove has four corners with chamfered outer corners, chamfered inner corners, chamfered right angles or chamfered bevel angles.

6. The method for effectively preventing corner cracks in HgCdTe infrared detector chips according to claim 4, characterized in that: The quasi-rectangular groove is a rectangular groove whose edge is wavy, rectangular gear-shaped or sawtooth-shaped.

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