Biasing arrangement for a linearization transistor having a sense RF signal and providing a bias signal at different terminals

Abstract

The present disclosure relates to biasing arrangements with linearization transistors that sense an RF signal and provide a bias signal at different terminals. Biasing arrangements for an amplifier are disclosed. An exemplary arrangement includes a bias circuit configured to generate a bias signal for the amplifier and a linearization circuit configured to improve linearity of the amplifier by modifying the bias signal based on an RF signal indicative of an RF input signal to be amplified by the amplifier. The linearization circuit includes a bias signal input to receive the bias signal, an RF signal input to receive the RF signal, and an output to provide a modified bias signal. The linearization circuit further includes at least a first linearization transistor having a first terminal, a second terminal, and a third terminal, where each of the bias signal input and the RF signal input of the linearization circuit are coupled to the first terminal of the first linearization transistor, and the output of the linearization circuit is coupled to the third terminal of the first linearization transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to radio frequency (RF) systems, and more particularly to biasing and linearization techniques for amplifiers in RF systems. BACKGROUND

[0002] Radio systems are systems that transmit and receive signals in the form of electromagnetic waves in the RF range of approximately 3 kilohertz (kHz) to 300 gigahertz (GHz). Radio systems are typically used for wireless communication, where cellular / wireless mobile technology is a prominent example, but can also be used for cable communication, such as cable television. In both types of systems, the linearity of the various components plays a crucial role.

[0003] The linearity of an RF component or system is, in theory, easy to understand. That is, linearity generally refers to the ability of a component or system to provide an output signal that is directly proportional to an input signal. In other words, if a component or system is perfectly linear, the relationship of the ratio of the output signal to the input signal is a straight line. Achieving this behavior in real components and systems is much more complex, and many challenges to linearity must be addressed, often at the expense of some other performance parameter (e.g., efficiency).

[0004] Power amplifiers are made of semiconductor materials that are inherently non-linear and need to be operated at relatively high power levels, so they are typically the first components to be analyzed when designing for linearity in an RF system. The power amplifier output with non-linear distortion can result in reduced modulation accuracy (e.g., reduced error vector magnitude (EVM)) and / or out-of-band emissions. As a result, wireless communication systems (e.g., long term evolution (LTE) and fifth generation (5G) systems) and cable communication systems have strict specifications for power amplifier linearity.

[0005] While linearity is also important for small-signal amplifiers such as low-noise amplifiers, the challenge of linearity is particularly pronounced for power amplifiers, because such amplifiers typically need to produce relatively high output power levels, and thus are particularly prone to enter operating conditions where certain non-linear behavior can no longer be ignored. On one hand, when an amplifier operates on signals with high power levels (an operating condition often referred to as “saturation operation”), the non-linear behavior of the semiconductor materials used to form the amplifier tends to worsen, in turn increasing the amount of non-linear distortion in its output signal, which is highly undesirable. On the other hand, amplifiers operating in saturation also typically work at their highest efficiency, which is highly desirable.

[0006] As mentioned above, linearity and efficiency are two performance parameters for which an acceptable trade-off often has to be found, since an improvement in one of these parameters is at the expense of the other parameter not being optimal. For this reason, the term "back-off" is used in the art to describe a measure of how much the input power (i.e. the power of the signal provided to the amplifier for amplification) should be reduced to achieve a desired output linearity (e.g. back-off can be measured as the ratio between the input power at which maximum power is delivered and the input power at which the desired linearity is delivered). For modern communication systems, an amplifier, especially a power amplifier, which is both linear and efficient (i.e. can minimize or eliminate back-off) is indispensable. Therefore, further improvements regarding amplifier design and operation are always needed. SUMMARY

[0007] One aspect of the present application discloses an electronic component comprising: a biasing circuit configured to generate a bias signal for a power amplifier; a coupling circuit configured to receive the bias signal as an input from the biasing circuit and to provide an output signal based on the bias signal to a linearization circuit; a feedback path coupling an output of the coupling circuit to an input of the biasing circuit, thereby forming a bias loop; and a linearization circuit for generating a modified bias signal based on a radio frequency, RF, input signal to be amplified by the power amplifier, wherein the RF input signal is a differential signal comprising a first differential part and a second differential part, and wherein the linearization circuit comprises: a bias signal input for receiving the output signal of the coupling circuit, a first RF signal input for receiving a first RF signal indicative of the first differential part of the RF input signal, a second RF signal input for receiving a second RF signal indicative of the second differential part of the RF input signal, a linearization transistor, each linearization transistor having a first terminal, a second terminal and a third terminal, and an output for providing the modified bias signal, wherein: each of the bias signal input and the first RF signal input is coupled to the first terminal of a first linearization transistor of the linearization transistors, each of the bias signal input and the second RF signal input is coupled to the first terminal of a second linearization transistor of the linearization transistors, the output is coupled to the third terminal of the first linearization transistor and to the third terminal of the second linearization transistor, and the third terminal of the first linearization transistor and the third terminal of the second linearization transistor are grounded via their respective coupling components, respectively.

[0008] Another aspect of the present application discloses an electronic component comprising: a biasing circuit configured to generate a bias signal for a power amplifier; a coupling circuit configured to receive the bias signal as an input from the biasing circuit and to provide an output signal based on the bias signal to a linearization circuit; a feedback path coupling an output of the coupling circuit to an input of the biasing circuit, thereby forming a bias loop; and a linearization circuit for generating a modified bias signal based on the bias signal and further based on a radio frequency, RF, input signal to be amplified by the power amplifier, the linearization circuit comprising: a bias signal input for receiving the output signal of the coupling circuit, a linearization transistor, an RF signal input for receiving an RF signal indicative of the RF input signal to be amplified by the power amplifier, and an output for providing the modified bias signal, wherein: a first terminal of the linearization transistor is coupled to each of the bias signal input and the RF signal input, a second terminal of the linearization transistor is to be coupled to a supply voltage when the linearization transistor is an N-type transistor and to be coupled to a ground voltage when the linearization transistor is a P-type transistor, and a third terminal of the linearization transistor is to be coupled to the output.

[0009] Yet another aspect of the present application discloses an electronic component comprising: a biasing circuit configured to generate a bias signal for a power amplifier; a coupling circuit configured to receive the bias signal as an input from the biasing circuit and to provide an output signal based on the bias signal to a linearization circuit; a feedback path coupling an output of the coupling circuit to an input of the biasing circuit, thereby forming a bias loop; the linearization circuit for generating a modified bias signal based on a radio frequency, RF, input signal to be amplified by the power amplifier, the RF input signal being a differential signal comprising a first differential part and a second differential part, and the linearization circuit comprising: a plurality of linearization transistors, each linearization transistor having a first terminal, a second terminal and a third terminal, a first RF signal input for receiving a first RF signal indicative of the first differential part of the RF input signal, a second RF signal input for receiving a second RF signal indicative of the second differential part of the RF input signal, and an output for outputting the modified bias signal generated based on the RF input signal, wherein: the plurality of linearization transistors comprises a first linearization transistor and a second linearization transistor, the first RF signal input is coupled to the first terminal of the first linearization transistor and to the third terminal of the second linearization transistor, the second RF signal input is coupled to the first terminal of the second linearization transistor and to the third terminal of the first linearization transistor, the output is coupled to the third terminal of the first linearization transistor and to the third terminal of the second linearization transistor, and the third terminal of the first linearization transistor and the third terminal of the second linearization transistor are grounded via their respective coupling components, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0010] For a more complete understanding of the present disclosure, and the features and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like parts, and in which:

[0011] Fig. 1 provides a schematic diagram of a circuit diagram of a biasing arrangement having a single loop for biasing and linearization according to the prior art.

[0012] Figure 2 Block diagrams are provided showing biasing arrangements having separate biasing and linearization circuits coupled by a coupling circuit according to various embodiments of the present disclosure are provided.

[0013] Figures 3 to 7 Schematic diagrams of circuit diagrams of exemplary implementations of biasing arrangements having linearization transistors sensing an RF signal and providing a bias signal at different terminals according to various embodiments of the present disclosure are provided.

[0014] Figure 8Block diagrams are provided showing antenna apparatus having amplifiers that can be biased by biasing arrangements having linearization transistors that sense RF signals and provide bias signals at different terminals, in accordance with some embodiments of the present disclosure.

[0015] Figure 9 Block diagrams are provided showing exemplary data processing systems that can be configured to implement or control at least part of the operation of amplifiers that are biased by biasing arrangements having one or more linearization transistors that sense RF signals and provide bias signals at different terminals, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Overview

[0017] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for the overall inventiveness. The various embodiments of the subject matter described in this specification can be implemented in hardware, software, firmware, or any combination thereof.

[0018] To illustrate the biasing arrangements for amplifiers of wireless and cable communication systems presented herein, it can be useful to first understand the phenomena that can be at play in such systems. The following background information can be considered as a basis that can appropriately explain the present disclosure. Such information is provided for explanatory purposes only and, thus, should not be considered as limiting the broad scope of the present disclosure and its potential applications. While some of the following description can provide examples for which the amplifiers are power amplifiers, embodiments of the present disclosure are equally applicable to other types of amplifiers, such as low noise amplifiers, variable gain amplifiers, etc.

[0019] In the context of a wireless radio system, an antenna is the interface between the radio waves that propagate through space and the electrical currents that move in the metallic conductors used with the transmitter or receiver. During transmission, a radio transmitter can supply an electrical signal that is amplified by a power amplifier, and the amplified version of the signal is provided to the terminals of the antenna. The antenna can then radiate the energy from the signal output by the power amplifier as radio waves. Similarly, in a cable radio system, an electrical signal is first amplified by a power amplifier before being transmitted over a wired cable connection. Thus, linear and efficient power amplifiers are critical for wireless and cable communication systems.

[0020] One approach to improving the linearity of a power amplifier includes careful control of the bias signal provided thereto. For example, adaptive bias circuits have been developed to optimize the linearity of a power amplifier. Such circuits are "adaptive" in that the bias signal provided to the power amplifier is dependent on the signal to be amplified by the power amplifier, which can be advantageous in improving the linearity of the power amplifier. In another example, bias circuits have been developed that include one or more linearization transistors in addition to a mirror transistor. However, the inventors of the present disclosure have recognized that conventional adaptive and linearization bias techniques and circuits can still have drawbacks that can make them suboptimal for use in modern communication systems, such as 5G systems. For example, conventional adaptive and linearization bias techniques and circuits can be sensitive to process, voltage, and temperature (PVT) variations, can have a limited envelope bandwidth, and can not always be suitable for use in power amplifiers that utilize stacked transistors.

[0021] Various embodiments of the present disclosure provide systems and methods that aim to improve one or more of the above-mentioned drawbacks in providing linear and efficient amplifiers, such as but not limited to a power amplifier, a low noise amplifier, or a variable gain amplifier, in RF systems, such as but not limited to a phased antenna array or a cable communication system for 5G cellular technology. In one aspect of the present disclosure, an exemplary bias arrangement for an amplifier includes a bias circuit configured to generate a bias signal for the amplifier and a linearization circuit configured to improve the linearity of the amplifier by modifying the bias signal based on an RF signal indicative of an RF input signal to be amplified by the amplifier. The linearization circuit includes a bias signal input for receiving the bias signal (e.g., a DC signal), at least one RF signal input for receiving / sensing the RF signal (one RF signal input for sensing a single-ended RF input signal and two RF signal inputs for sensing a differential RF input signal), and an output for providing a modified bias signal. The linearization circuit further includes one or more linearization transistors, each linearization transistor having a first terminal, a second terminal, and a third terminal, wherein each of the bias signal input and the RF signal input of the linearization circuit is coupled to the first terminal of a first linearization transistor of the one or more linearization transistors, and wherein the output of the linearization circuit is coupled to the third terminal of the first linearization transistor. As shown in the foregoing example, the RF signal is sensed at the first terminal of the first linearization transistor, while the modified bias signal is output at the third terminal of the first linearization transistor, thus the first linearization transistor is configured to sense the RF signal and output the modified bias signal at a different terminal. Accordingly, such a bias arrangement is referred to herein as a "bias arrangement with a linearization transistor that senses an RF signal and provides a bias signal at a different terminal."

[0022] In another aspect of the disclosure, particularly when the RF input signal is a differential signal, a linearization circuit of another exemplary biasing arrangement can further include a second linearization transistor, where the RF signal provided to the first terminal of the first linearization transistor can also be provided to a third terminal of the second linearization transistor. The third terminal of the second linearization transistor can then be coupled to the node at which the second linearization transistor provides the modified bias signal (e.g., as shown in the embodiment of FIG. 2B), for example, via a resistor. However, in such a biasing arrangement, the first linearization transistor is still configured such that it senses the RF signal and provides the bias signal at a different terminal, and thus, such a biasing arrangement can still be referred to as a “biasing arrangement with a linearization transistor that senses the RF signal and provides the bias signal at a different terminal,” regardless of how the second linearization transistor is configured. Figure 7

[0023] Providing biasing arrangements with linearization transistors that sense the RF signal and provide the bias signal at a different terminal can provide improvements over conventional biasing arrangements, for example, in terms of reducing sensitivity to PVT variations, increasing envelope bandwidth, being suitable for use in amplifiers that utilize stacked transistors, and reducing the die area required to implement these arrangements.

[0024] ​The precise designs of the biasing arrangements for linearized transistors described herein that have a sense RF signal and provide a bias signal at different terminals can be implemented in many different ways, all of which are within the scope of the present disclosure. In one example of a design variation according to various embodiments of the present disclosure, the selection can be made individually for each transistor of a biasing arrangement for one or more linearized transistors that have a sense RF signal and provide a bias signal at different terminals according to any of the embodiments described herein to employ bipolar transistors (e.g., where the various transistors can be NPN or PNP transistors), field effect transistors (FETs), e.g., metal oxide semiconductor (MOS) technology transistors (e.g., where the various transistors can be N-type MOS (NMOS) or P-type MOS (PMOS) transistors), or a combination of one or more FETs with one or more bipolar transistors. In view of this, in the following description, reference is sometimes made to a first terminal, a second terminal, and a third terminal of a transistor. If the transistor is a bipolar transistor, the term "first terminal" (Tl) of the transistor can be used to refer to the base terminal, or if the transistor is a FET, it can be used to refer to the gate terminal, if the transistor is a bipolar transistor, the term "second terminal" (T2) of the transistor can be used to refer to the collector terminal, or if the transistor is a FET, it can be used to refer to the drain terminal, and if the transistor is a bipolar transistor, the term "third terminal" (T3) of the transistor can be used to refer to the emitter terminal, or if the transistor is a FET, it can be used to refer to the source terminal. These terms remain the same regardless of whether the transistor of a given technology is an N-type transistor (e.g., an NPN transistor in the case of a bipolar transistor or an NMOS transistor in the case of a FET) or a P-type transistor (e.g., a PNP transistor in the case of a bipolar transistor or a PMOS transistor in the case of a FET). In another example, in various embodiments, a selection can be made individually for each transistor of any biasing arrangement for linearized transistors as described herein that have a sense RF signal and provide a bias signal at different terminals as to which transistors are implemented as N-type transistors (e.g., NMOS transistors for transistors implemented as FETs, or NPN transistors for transistors implemented as bipolar transistors), and which transistors are implemented as P-type transistors (e.g., PMOS transistors for transistors implemented as FETs, or PNP transistors for transistors implemented as bipolar transistors). In still other examples, in various embodiments, a selection can be made as to which type of transistor architecture to employ.For example, any of the transistors implemented as FETs having a biasing arrangement of linearized transistors that senses an RF input signal and provides a bias signal at different terminals as described herein can be a planar transistor or can be a non-planar transistor (some examples of the latter include a finFET, a nanowire transistor, or a nanoribbon transistor).

[0025] As those skilled in the art will appreciate, aspects of the present disclosure, particularly aspects of biasing arrangements of linearized transistors that senses an RF input signal and provides a bias signal at different terminals as described herein, can be embodied in various ways, for example, as a method, system, computer program product, or computer readable storage medium. Accordingly, aspects of the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects (generally referred to herein as a "circuit," "module" or "system"). At least some of the functionality described in the present disclosure can be implemented as an algorithm executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of any of the methods described herein can be performed by different processing units. Furthermore, aspects of the present disclosure can take the form of a computer program product on one or more computer-readable media preferably non-transitory, having computer-readable program code embodied in the computer-readable media. Such computer program can be, for example, downloaded (updated) to various devices and systems (e.g., various components of RF systems and arrangements of components, and / or controllers thereof, etc.) or stored at the time of manufacture.

[0026] The following detailed description presents various descriptions of certain certain embodiments. However, the innovations described herein can be embodied in a multitude of different ways. For example, the described innovations can be implemented in various ways, as defined and covered within the claims or their equivalents, and / or choices can be made regarding the specific implementation described therein. In the following description, reference is made to the accompanying drawings, in which like reference numerals can refer to similar or like

[0027] This description can use phrases such as “in one embodiment,” or “in multiple embodiments,” each of which can refer to one or more of the same or different embodiments. Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third,” etc. to describe common objects of the description are used merely for distinguishing like from like. Such adjectives do not imply a necessary order or sequence, unless otherwise stated. Moreover, for the purposes of the disclosure, the phrases “A and / or B” or “A / B” mean (A), (B), or (A and B). The phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the notation A / B / C means (A, B, and / or C). When referring to a range of measurements, the term “between” includes the ends of the range of measurements.

[0028] Various aspects of the illustrative embodiments are described using terminology generally employed by those skilled in the art and their everyday equivalents to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical connection between things being connected without any intervening devices / components, while the term “coupled” means a direct electrical connection between things being connected or an indirect connection through one or more passive or active intervening devices / components. In another example, the term “circuit” means one or more passive and / or active components arranged to cooperate with one another to provide a desired function. If used, the terms “substantially,” “approximately,” “about,” and the like can be used to generally refer to being within + / - 20% of a target value, such as within + / - 10% of a target value, based on the context of the particular value as described herein or known in the art.

[0029] Prior art biasing arrangements with a single loop for biasing and linearization

[0030] Figure 1 provides a schematic illustration of a biasing arrangement 100 having a single loop for biasing and linearization according to the prior art. As shown in Figure 1, a biasing signal 102, e.g. a biasing current, can be provided to a biasing circuit transistor 112, which is coupled with a linearization transistor 122 in a loop 118 (shown in Figure 1 with a dashed line outline having arrows). In Figure 1 and in the subsequent figures, various transistors are shown with dashed oval / circular outlines. The inset 104 shown in Figure 1 shows an exemplary transistor, which indicates a first terminal, a second terminal and a third terminal, labeled T1, T2 and T3, respectively, as referred to in the remainder of this description, which applies to all figures presented. If a given transistor described herein is implemented as a FET, as shown for the two transistors of the biasing arrangement 100, then according to conventional nomenclature, the first terminal T1 is the gate terminal, the second terminal T2 is the drain terminal, and the third terminal T3 is the source terminal. The terminals T1-3T are not specifically labeled in the remainder of the biasing arrangement 100 or the figures, in order not to clutter these figures.

[0031] As shown in Figure 1, a first terminal of the linearization transistor 122 can be coupled to the biasing signal 102, e.g. via a node 138. A second terminal of the biasing circuit transistor 112 can also be coupled to the node 138, and thus to the linearization transistor 122. Furthermore, a capacitor 150 can be coupled between the node 138 and a ground potential (labeled "Vgnd" in Figure 1 and in the subsequent figures). A second terminal of the linearization transistor 122 can be coupled to a supply voltage (labeled "Vs" in Figure 1 and in the subsequent figures), while a third terminal of the linearization transistor 122 can be coupled to an output 162. Figure 1 further shows a resistor 164, which can be coupled between the third terminal of the linearization transistor 122 and the output 162. Figure 1 also shows a resistor 174 coupled between the first terminal of the biasing circuit transistor 112 and the output 162, and a resistor 184 coupled between the third terminal of the linearization transistor 122 and the ground potential. In some implementations, the node 162 can be coupled to an RF input signal to be amplified by an amplifier, such that the linearization transistor 122 can sense the RF input signal in order to generate a modified biasing signal.

[0032] The inventors of this disclosure recognized several drawbacks of the bias arrangement 100. The most significant drawback is that the bias circuit transistor 112 shares the same loop 118 with the linearization transistor 122, which may limit the linearization that the linearization transistor 122 can achieve and limit the mirror accuracy that the bias circuit transistor 112 can achieve. Furthermore, sharing the loop 118 in the manner shown in FIG. 1 may impair the stability of the loop 118. This, in turn, may result in a limited envelope bandwidth, as the bandwidth of the linearization circuit loop may be limited by its stability. Moreover, the inventors of this disclosure recognized that, in the case of using stacked transistors in an amplifier, using a single bias circuit transistor 112 can make the design very sensitive to current mirroring.

[0033] Biasing arrangements with separate biasing and linearization circuits coupled by a coupling circuit

[0034] The embodiments of this disclosure, based on the separation of bias circuit transistors and linearization transistors so that they are not coupled in a single loop, can provide insights into improvements over conventional bias arrangements such as those shown in Figure 1.

[0035] Figure 2 A block diagram illustrating a bias arrangement 200 according to some embodiments of the present disclosure is provided, the bias arrangement having separate bias and linearization circuits 210, 220 coupled via a coupling circuit 230. As... Figure 2 As shown, bias circuit 210 can be configured to receive input signal 202 and generate output signal 211. Input signal 202 can be a bias signal, such as a bias current, and bias circuit 210 can be configured to mirror input signal 202 to output, i.e., output signal 211 can be substantially a mirror version of bias signal 202 or a bias voltage. Coupling circuit 230 is configured to receive output signal 211 from bias circuit 210 as input to coupling circuit 230 and provide output signal 231 based on bias signal 211 output by bias circuit 210. Linearization circuit 220 can be configured to receive output signal 231 from coupling circuit 230 and generate output signal 221, which can then be provided to amplifier ( Figure 2 (Amplifier not shown). Specifically, linearization circuit 220 can be configured to improve the linearity of the amplifier by modifying the bias signal 211 generated by bias circuit 210 based on RF signal 225 indicating the RF input signal to be amplified by the amplifier, to produce an output signal 221, which may be referred to as the “modified bias signal” 221 to be provided to the amplifier. In some embodiments, RF signal 225 may be substantially the same as the RF input signal to be amplified by the amplifier, but in other embodiments, the RF signal sensed by linearization circuit 220 may be a slightly different RF signal based on the RF input signal to be amplified by the amplifier.

[0036] likeFigure 2 As shown, coupling circuit 230 is configured to couple bias circuit 210 and linearization circuit 220. Providing separate bias and linearization circuits 210 and 220 coupled to each other via coupling circuit 230 allows for the separation of linearization operation from the bias loop. This helps overcome some drawbacks of prior art bias arrangement 100, providing improvements in PVT variation and achieving better linearization. Specifically, feedback path 240 can be provided to couple the output of coupling circuit 230 to the input of bias circuit 202, thereby forming bias loop 218.

[0037] Compared to the bias loop 118 shown in Figure 1, the bias loop 218 does not include components of the linearization circuit 220. As mentioned above, this allows for the optimization of the components of the linearization circuit 220 without any bias or stability considerations / limitations. Furthermore, the linearization circuit 220 can be designed without any closed loops, which can advantageously reduce or eliminate the limiting envelope bandwidth of the bias arrangement 200.

[0038] It should be noted that, although Figure 2 No additional components are shown in feedback path 240, but various active or passive components may be included therein in various embodiments. For example, in some embodiments, feedback path 240 from the output of coupling circuit 230 to the input of bias circuit 202 may include a voltage level shifter that can help provide a constant current output voltage to one or more transistors of the amplifier, to which a modified bias signal 221 is provided. Thus, in various embodiments, one or more of voltage level shifters, transistors, resistors, capacitors, amplifiers, operational amplifiers (op-amps), etc., may be coupled between the output of coupling circuit 230 and the input of bias circuit 202 in feedback path 240.

[0039] Sensing an RF input signal and outputting a bias signal at different terminals

[0040] Embodiments of this disclosure are further based on the understanding that in bias arrangements where the bias circuit transistor and the linearization transistor are separated so that they are not coupled in a single loop (e.g., in situations such as...). Figure 2 In the bias arrangement shown, one or more linearizing transistors, including those configured to sense the RF signal at the RF input of the indicator amplifier and providing bias signals (i.e., output modified bias signals) at different terminals, can provide further improvements over conventional bias arrangements such as those shown in FIG1. ​​Some exemplary embodiments of bias arrangement 200 are shown in Figures 3 to 7In this bias arrangement, one or more linearization transistors are configured to sense the RF signal at the RF input of the indicator amplifier and provide bias signals at different terminals (i.e., output modified bias signals). However, any embodiment of the bias arrangement 200 described herein is within the scope of this disclosure.

[0041] exist Figures 3 to 7 middle, Figure 2 The reference number used is considered to indicate the relationship with Figure 2 Elements with the same or similar bias arrangements as those shown. For example, Figures 3 to 7 Each of these is shown as bias circuit 210, linearization circuit 220, and coupling circuit 230; however, details of their specific implementations are in […]. Figures 3 to 7 The results may differ in different diagrams.

[0042] Figure 3 A schematic diagram of a bias arrangement 300 according to some embodiments of the present disclosure is provided, which is a first exemplary embodiment of a bias arrangement 200.

[0043] like Figure 3 As shown, in this example, the bias circuit 210 may include a first transistor 312 and a second transistor 314, which may be referred to as a first "bias circuit transistor" and a second "bias circuit transistor" arranged in a common-source, common-gate configuration. As is known in the art, the "common-source, common-gate configuration" of the first and second transistors means that the third terminal of the second transistor is coupled to the second terminal of the first transistor (refer to the notes on the first, second, and third terminals explained in FIG1). In this case, this means that the third terminal of the second transistor 314 (e.g., Figure 3 The source terminal of the FET embodiment of transistor 314 shown can be coupled to the second terminal of the first transistor 312 (e.g., Figure 3 The drain terminal of the FET implementation of transistor 312 shown. The first transistor 312 can be similar to the bias circuit transistor 112 shown in FIG. 1 because it can be used to mirror the bias signal 202 to the output of the bias circuit, which is the first terminal of the first transistor 312 (e.g., Figure 3 The gate terminal of the FET implementation of transistor 312 shown. This is also... Figure 3 The output signal 211 is indicated by showing it located at the first terminal of the first transistor 312. In some embodiments of the bias arrangement 300, the second transistor 314 may be omitted; in this case, the second terminal of transistor 312 will be coupled to the bias signal 202 and ultimately to the supply voltage Vs (for...). Figure 3 The N-type transistor implementation shown above, for example coupled to Vdd (for Figure 3the FET implementation shown). However, embodiments using the second transistor 314 can be advantageous because a biasing circuit 210 having at least 2 transistors in a cascode arrangement can provide better mirroring accuracy when mirroring the bias signal 202 to the output of the biasing circuit 210. When using the second transistor 314, its second terminal can be coupled to the bias signal 202 and further coupled to a supply voltage Vs (for example, Vdd for the N-type transistor implementation shown). Figure 3 the N-type transistor implementation shown), for example, to Vdd (for the FET implementation shown), and the first terminal can be coupled to a reference voltage Vcasl, which can be a fixed DC voltage. In some embodiments, the reference voltage Vcasl can be the same voltage used to bias a cascode amplifier in a main power amplifier (an amplifier not shown in the arrangement 200). Similar to the biasing circuit transistor 112 shown in Figure 1, for the N-type transistor implementation shown, the third terminal of the first transistor 312 can be coupled to a ground potential Vgnd. Figure 3 the N-type transistor implementation shown), for example, to Vdd (for the FET implementation shown), and the first terminal can be coupled to a reference voltage Vcasl, which can be a fixed DC voltage. In some embodiments, the reference voltage Vcasl can be the same voltage used to bias a cascode amplifier in a main power amplifier (an amplifier not shown in the arrangement 200). Similar to the biasing circuit transistor 112 shown in Figure 1, for the N-type transistor implementation shown, the third terminal of the first transistor 312 can be coupled to a ground potential Vgnd. Figure 3 the N-type transistor implementation shown), for example, to Vdd (for the FET implementation shown), and the first terminal can be coupled to a reference voltage Vcasl, which can be a fixed DC voltage. In some embodiments, the reference voltage Vcasl can be the same voltage used to bias a cascode amplifier in a main power amplifier (an amplifier not shown in the arrangement 200). Similar to the biasing circuit transistor 112 shown in Figure 1, for the N-type transistor implementation shown, the third terminal of the first transistor 312 can be coupled to a ground potential Vgnd.

[0044] As Figure 2 shown, the output signal 211 provided at the first terminal of the transistor 312 can be provided from the biasing circuit 210 to the coupling circuit 230. Figure 3 The example shown illustrates the coupling circuit 230 as including a transistor 332, which can be referred to as a "coupling transistor." The output 211 of the biasing circuit 210 can be provided as an input to the coupling circuit 230 by being applied to the third terminal of the coupling transistor 332. For the N-type transistor implementation shown, the third terminal of the coupling transistor 332 can be further coupled to a ground potential Vgnd, for example, via a resistor 336, and the second terminal of the coupling transistor 332 can be coupled to a supply voltage Vs (for example, Vdd for the FET implementation shown). Figure 3 The example shown illustrates the coupling circuit 230 as including a transistor 332, which can be referred to as a "coupling transistor." The output 211 of the biasing circuit 210 can be provided as an input to the coupling circuit 230 by being applied to the third terminal of the coupling transistor 332. For the N-type transistor implementation shown, the third terminal of the coupling transistor 332 can be further coupled to a ground potential Vgnd, for example, via a resistor 336, and the second terminal of the coupling transistor 332 can be coupled to a supply voltage Vs (for example, Vdd for the FET implementation shown). Figure 3 The example shown illustrates the coupling circuit 230 as including a transistor 332, which can be referred to as a "coupling transistor." The output 211 of the biasing circuit 210 can be provided as an input to the coupling circuit 230 by being applied to the third terminal of the coupling transistor 332. For the N-type transistor implementation shown, the third terminal of the coupling transistor 332 can be further coupled to a ground potential Vgnd, for example, via a resistor 336, and the second terminal of the coupling transistor 332 can be coupled to a supply voltage Vs (for example, Vdd for the FET implementation shown). Figure 2 The example shown illustrates the coupling circuit 230 as including a transistor 332, which can be referred to as a "coupling transistor." The output 211 of the biasing circuit 210 can be provided as an input to the coupling circuit 230 by being applied to the third terminal of the coupling transistor 332. For the N-type transistor implementation shown, the third terminal of the coupling transistor 332 can be further coupled to a ground potential Vgnd, for example, via a resistor 336, and the second terminal of the coupling transistor 332 can be coupled to a supply voltage Vs (for example, Vdd for the FET implementation shown). Figure 3 The example shown illustrates a further component 342, which can be included in the feedback path 240 in some embodiments. The further component 342 can be, for example, a voltage level shifter. In other embodiments, the feedback path 240 can not include any intermediate components, and the first terminal of the coupling transistor 332 can be directly connected to the input of the biasing circuit 210. Figure 3A node 338 is shown that can be considered to couple the first terminals of the coupling transistor 332 and the linearization transistor 322 together, and where each of these first terminals is coupled to a node of the feedback path 240.

[0045] Turning to the linearization circuit 220, the linearization circuit 220 is configured to receive a bias signal at its bias signal input. For example, the node 338 can be considered the bias signal input of the linearization circuit 220 at which the linearization circuit 220 can receive an output signal 231 indicative of the bias signal 211 produced by the bias circuit 210. The linearization circuit 220 can further include an RF signal input for receiving or sensing an RF signal (e.g., Figure 2 The RF signal 225 shown) that is indicative of the RF input signal to be amplified by the amplifier. In particular, Figure 3 The embodiment of the linearization circuit 220 shown is one in which the linearization circuit 220 is configured to sense a differential signal version of the RF input signal to be amplified by the amplifier. Thus, Figure 3 The RF signal input of the linearization circuit 220 is shown to include a first RF sense node 360-1 and a second RF sense node 360-2, and thus these nodes can be referred to as a first RF signal input and a second RF signal input, respectively. The first RF sense node 360-1 can be coupled to the positive RF input signal RF+ and configured to receive a first RF signal 225-1 that is indicative of the positive variant of the differential RF input signal, i.e., RF+. The second RF sense node 360-2 can be coupled to the negative RF input signal RF- and configured to receive a second RF signal 225-2 that is indicative of the negative variant of the differential RF input signal, i.e., RF-, where the positive and negative variants are complementary signals indicative of the RF input signal transmitted by a differential signal (i.e., the first RF signal 225-1 and the second RF signal 225-2 are complementary signals).

[0046] Due to the differential signal nature of the sensed RF input signal 225, the linearization circuit 220 includes two branches - a first branch 340-1 can include a first linearization transistor 322-1 and a second branch 340-2 can include a second linearization transistor 322-2. Each linearization transistor 322 has one terminal that can sense the RF signal 225, where the first linearization transistor 322-1 is configured to sense the RF signal 225-1 by having its one terminal (e.g., first terminal) coupled to a first RF sense node 360-1, and the second linearization transistor 322-2 is configured to sense the RF signal 225-2 by having its one terminal (e.g., first terminal) coupled to a second RF sense node 360-2. Further, each linearization transistor 322 has another terminal (e.g., third terminal) coupled to an output node 328 at which the modified bias signal 221 is provided. Thus, each linearization transistor 322 is configured to sense the RF signal and provide a bias signal at a different terminal.

[0047] In some embodiments, the node 328 can also be coupled to a capacitor 350. For example, a first capacitor electrode of the capacitor 350 can be coupled to a ground potential (for N-type transistor implementations of the first and second linearization transistors 322), while a second capacitor electrode of the capacitor 350 can be coupled to the node 328, and thus to the third terminal of each of the first and second linearization transistors 322. In some embodiments, the capacitor 350 can be used to filter at least some of the remaining RF signal and its harmonics, and provide a filtered modified bias signal. Figure 3

[0048] For each of the two linearization transistors 322, in addition to being coupled to a respective RF sense node 360, the first terminal can be coupled to the first terminal of the coupling transistor 332, e.g., via the node 338, and also to the bias signal 202 via the feedback path 240. Thus, for each of the two linearization transistors 322, the bias signal input (e.g., node 338) of the linearization circuit 220 through which the linearization circuit 220 receives the input bias signal (e.g., signal 231) is coupled to the first terminal of the linearization transistor 322. In some embodiments, for each of the two linearization transistors 322, the first terminal of a given linearization transistor 322 can be coupled to the node 338 via a bias signal coupling component 366 configured to couple the bias signal 231 to each linearization transistor 322. In some embodiments, the bias signal coupling component 366 can be implemented as a resistor, as Figure 3 ​As shown, the bias signal input 338 can be coupled to the first terminal of the first linearization transistor 322-1 through the first bias signal coupling component 366-1 and to the first terminal of the first linearization transistor 322-1 through the second terminal of the first bias signal coupling component 366-1. Similarly, for the second linearization transistor 322-2, the bias signal input 338 can be coupled to the first terminal of the second bias signal coupling component 366-2 through the bias signal input 338 and to the first terminal of the second linearization transistor 322-2 through the second terminal of the second bias signal coupling component 366-2.

[0049] In some embodiments, similar coupling components can be included at the RF signal inputs of the linearization circuit 220. As described above, for each of the two linearization transistors 322, the respective RF signal input of the linearization circuit 220 through which the linearization circuit 220 senses the RF input signal (e.g., signal 225) (e.g., node 360-1 for linearization transistor 322-1 or node 360-2 for linearization transistor 322-2) can be coupled to the first terminal of the linearization transistor 322. In some embodiments, for each of the two linearization transistors 322, the first terminal of a given linearization transistor 322 can be coupled to the respective RF signal input 360 via an RF signal coupling component 364 configured to couple the respective RF signal 225-1 or 225-2 to the corresponding linearization transistor 322-1 or 322-2. In some embodiments, the RF signal coupling component 364 can be implemented as a capacitor, as Figure 3The first RF signal input represented by the first RF sense node 360-1 of the linearization circuit 220 can be coupled to the first terminal of the first linearization transistor 322-1, in some embodiments, by coupling to a first terminal of the first RF signal coupling component 364-1 (e.g., a first capacitor electrode of a capacitor used to implement the first RF signal coupling component 364-1) through the first RF sense node 360-1 of the first RF sensing node 360-1, and by coupling to the first terminal of the first linearization transistor 322-1 through a second terminal of the first RF signal coupling component 364-1 (e.g., a second capacitor electrode of the capacitor used to implement the first RF signal coupling component 364-1). Similarly, for the second linearization transistor 322-2, in some embodiments, the second RF signal input represented by the second RF sense node 360-2 of the linearization circuit 220 can be coupled to the first terminal of the second linearization transistor 322-2, by coupling to a first terminal of the second RF signal coupling component 364-2 (e.g., a first capacitor electrode of a capacitor used to implement the second RF signal coupling component 364-2) through the second RF sense node 360-2 of the second RF sensing node 360-2, and by coupling to the first terminal of the second linearization transistor 322-2 through a second terminal of the second RF signal coupling component 364-2 (e.g., a second capacitor electrode of the capacitor used to implement the second RF signal coupling component 364-2).

[0050] Furthermore, for each of the two linearization transistors 322, for Figure 3 For the N-type transistor implementation shown, the second terminal can be coupled to a supply voltage Vs, and the third terminal can be further coupled to a ground potential Vgnd. In some embodiments, the third terminal of the linearization transistor 322 can be coupled to Vgnd via a respective coupling component, e.g., via a resistor 326-1 for the linearization transistor 322-1 and via a resistor 326-2 for the linearization transistor 322-2. The resistors 326-1 and 326-2 can be configured to set a bias current of the linearization transistor 322. In some embodiments, the bias current of the linearization transistor 322 can be set to be substantially equal to the bias current of the coupling transistor 332. Figure 4 One or more of the resistors 326-1, 326-2, and 336 shown can be replaced by a respective current source (not shown in the present figure). In some embodiments, the coupling transistor 332 can be substantially a replica of one of the linearization transistors 322, e.g., the coupling transistor 332 can have substantially the same dimensions as one of the linearization transistors 322, and be formed of substantially the same material. In other embodiments, the coupling transistor 332 can have dimensions that are any multiple of the dimensions of one of the linearization transistors 322.

[0051] Figure 3A schematic of a circuit diagram of a biasing arrangement 400 according to some embodiments of the present disclosure is provided, which is a second exemplary implementation of the biasing arrangement 200. The biasing arrangement 400 includes substantially the same parts as the biasing arrangement 300, except that it further illustrates additional components enclosed within a dashed outline 440. Thus, for the sake of brevity, the description of the elements already described with reference to the biasing arrangement 300 will not be repeated, and only the differences between these figures will be described. The biasing arrangement 400 illustrates that, in some embodiments, a cascode transistor can be added to one or both of the coupling circuit 230 and the linearization circuit 220. For example, in some embodiments, a second coupling transistor 432 can be coupled in a cascode arrangement to the coupling transistor 332. In this case, the second terminal of the coupling transistor 332 can be coupled to the supply voltage Vs via the second coupling transistor 432, by coupling to the third terminal of the second coupling transistor 432, and then the second terminal of the second coupling transistor 432 being coupled to the supply voltage. Figure 4 The biasing arrangement 400 is provided Figure 4 The description of the elements illustrated in the biasing arrangement 400 is provided, and only the differences between these figures will be described. The biasing arrangement 400 illustrates that, in some embodiments, a cascode transistor can be added to one or both of the coupling circuit 230 and the linearization circuit 220. For example, in some embodiments, a second coupling transistor 432 can be coupled in a cascode arrangement to the coupling transistor 332. In this case, the second terminal of the coupling transistor 332 can be coupled to the supply voltage Vs via the second coupling transistor 432, by coupling to the third terminal of the second coupling transistor 432, and then the second terminal of the second coupling transistor 432 being coupled to the supply voltage. Figure 4 Similarly, in some embodiments, a second linearization transistor 422 (illustrated as transistor 422-1 for the first branch 340-1 of the linearization circuit 220, and as transistor 422-2 for the second branch 340-2 of the linearization circuit 220) can be coupled in a cascode arrangement to the respective linearization transistor 322. In this case, the second terminal of the linearization transistor 322-1 can be coupled to the supply voltage Vs via the second linearization transistor 422-1, by coupling to the third terminal of the second linearization transistor 422-1, and then the second terminal of the second linearization transistor 422-1 being coupled to the supply voltage. Furthermore, the second terminal of the linearization transistor 322-2 can be coupled to the supply voltage Vs via the second linearization transistor 422-2, by coupling to the third terminal of the second linearization transistor 422-2, and then the second terminal of the second linearization transistor 422-2 being coupled to the supply voltage. The first terminal of each cascode transistor of the portion 440 can be coupled to a voltage source 442, which can provide a suitable voltage to, for example, match the drain-source voltage (Vds) of the linearization transistors 322-1, 322-2 and / or transistors included in an amplifier to which the modified bias signal 221 is provided. If the amplifier also includes such cascode transistors, then adding the cascode transistors of the portion 440 can be particularly advantageous. Although Figure 4 The cascode transistors of the portion 440 illustrated can be particularly advantageous. Although Figure 5 Although the cascode transistors are illustrated as being added to both the coupling circuit 230 and the linearization circuit 220, in other embodiments of the biasing arrangement 400, such cascode transistors can be added to one of the coupling circuit 230 and the linearization circuit 220, rather than both.

[0052] Figure 3 A schematic of a circuit diagram of a bias arrangement 500 according to some embodiments of the disclosure is provided, which is a third exemplary implementation of the bias arrangement 200. The bias arrangement 500 comprises substantially the same parts as the bias arrangement 300, and thus, for brevity, the description of the elements already described with reference to Figure 5 the bias arrangement 300 is not repeated, and only the differences between these figures are described. Figure 5 The bias arrangement 500 is different from the bias arrangement 300 in that the bias arrangement 500 does not have the linearization circuit 220 as a differential input (i.e., two branches 340-1 and 340-2 and two RF sense nodes 360-1 and 360-2), but instead has a single branch configured to sense the RF signal 225. Thus, Figure 3 one of the two branches of the linearization circuit 220 shown in Figure 3 is not present in the bias arrangement 500 (e.g., the second branch 340-2 with the linearization transistor 322-2). Figure 3 Figure 5 Figure 6

[0053] Figure 5 A schematic of a circuit diagram of a bias arrangement 600 according to some embodiments of the disclosure is provided, which is a fourth exemplary implementation of the bias arrangement 200. The bias arrangement 600 comprises substantially the same parts as the bias arrangement 500, except that it further illustrates additional components enclosed within a dashed outline 640. Thus, for brevity, the description of the elements already described with reference to Figure 6 the bias arrangement 500 is not repeated, and only the differences between these figures are described. Similar to the bias arrangement 400, the bias arrangement 600 illustrates that, in some embodiments, a cascode transistor can be added to one or both of the coupling circuit 230 and the linearization circuit 220. Such a cascode transistor can be the ones described with reference to Figure 4 the bias arrangement 300, and thus, in Figure 6 the same reference numbers as used in Figure 4 the bias arrangement 300 are used. For example, in some embodiments, the second coupling transistor 432 can be coupled to the coupling transistor 332 in a cascode arrangement, as described above. Similarly, in some embodiments, the second linearization transistor 422-1 can be coupled to the linearization transistor 322-1 in a cascode arrangement, also as described above. If the amplifier also comprises such a cascode transistor, it can be particularly advantageous to add Figure 6 the cascode transistor of the part 640 shown. Figure 7

[0054] Figure 3 ​​​​A schematic diagram of a bias arrangement 700 according to some embodiments of the present disclosure is provided, which is a fifth exemplary embodiment of bias arrangement 200. Bias arrangement 700 includes substantially the same portions as bias arrangement 300, except that it further shows RF input signals 225-1 and 225-2 cross-coupled to opposite branch 340. Therefore, for the sake of brevity, references to already discussed... Figure 7 Provided Figure 7 The components shown are described, and only the differences between these figures are described. Bias arrangement 700 shows that, in some embodiments of a bias arrangement configured to sense differential RF input signals, each RF sensing node 360 ​​can be coupled not only to a first terminal of a linearized transistor in one branch (i.e., 340-1 or 340-2), but also to a third terminal of a linearized transistor in another branch (i.e., 340-2 or 340-1, respectively). For example, as... Figure 7 As shown, the first RF sensing node 360-1 can be coupled not only to the first terminal of the first linearization transistor 322-1 included in the first branch 340-1, but also to the third terminal of the second linearization transistor 322-2 included in the second branch 340-2. Similarly, the second RF sensing node 360-2 can be coupled not only to the first terminal of the second linearization transistor 322-2 included in the second branch 340-2, but also to the third terminal of the first linearization transistor 322-1 included in the first branch 340-1. This cross-coupling can advantageously increase the RF linearization range.

[0055] In some embodiments, for each of the two linearization transistors 322, the third terminal of a given linearization transistor 322 of one branch can be coupled via a further RF signal coupling member 764 to an RF sensing node 360 ​​coupled to the first terminal of the linearization transistor 322 of the other branch. This further RF signal coupling member is configured to couple RF signals 225-1 or 225-2 to linearization transistors 322-2 or 322-1, respectively. In some embodiments, the further RF signal coupling member 764 can be implemented as a capacitor, such as... Figure 7As shown. Thus, in some embodiments, the first RF sensing node 360-1 can be coupled to the third terminal of the second linearization transistor 322-2 through a first terminal of the second further RF signal coupling component 764-2 (e.g., a first capacitor electrode of a capacitor used to implement the second further RF signal coupling component 764-2) and through a second terminal of the second further RF signal coupling component 764-2 (e.g., a second capacitor electrode of a capacitor used to implement the second further RF signal coupling component 764-2). Similarly, for the second linearization transistor 322-2, in some embodiments, the second RF sensing node 360-2 can be coupled to the third terminal of the first linearization transistor 322-1 through a first terminal of the first further RF signal coupling component 764-1 (e.g., a first capacitor electrode of a capacitor used to implement the first further RF signal coupling component 764-1) and through a second terminal of the first further RF signal coupling component 764-1 (e.g., a second capacitor electrode of a capacitor used to implement the first further RF signal coupling component 764-1). Implementing further RF signal coupling components 764 can advantageously allow for rejection or reduction of unwanted signals, such as common mode signals and harmonics.

[0056] Figure 7 Further shown, in some embodiments, the biasing arrangement 700 can further include a degeneration component 726. In some embodiments, the degeneration component 726 can be implemented as a resistor, as shown. Figures 3 to 6The output node 328 of the linearization circuit 220 can be coupled to the third terminal of the first linearization transistor 322-1 by a first terminal of the first degeneration component 726-1, and a second terminal of the first degeneration component 726-1 coupled to the third terminal of the first linearization transistor 322-1, in some embodiments. Similarly, the output node 328 can be further coupled to the third terminal of the second linearization transistor 322-2 by a first terminal of the second degeneration component 726-2, and a second terminal of the second degeneration component 726-2 coupled to the third terminal of the second linearization transistor 322-2, in some embodiments. Moreover, the second RF sense node 360-2 can be further coupled to the third terminal of the first linearization transistor 322-1 by a second terminal of the first degeneration component 726-1 coupled to the second RF sense node 360-2, and the first RF sense node 360-1 can be further coupled to the third terminal of the second linearization transistor 322-2 by a second terminal of the second degeneration component coupled to the first RF sense node 360-1, in some embodiments. Implementing the degeneration resistor 726 can advantageously permit improved transistor characteristics for the linearization circuit 220.

[0057] Although not specifically shown in the present figure, in some embodiments, the degeneration resistor 726 can be included in the biasing arrangement 700 as described with reference to Figure 7 Moreover, although not specifically shown in the present figure, in some embodiments, the biasing arrangement 700 can be further modified to include common-gate transistors as described with reference to Figure 4 for example, the transistors enclosed within the dashed outline 440 in Figures 3 to 7

[0058] Figures 3 to 7 Each of FIGS. 6A-6C illustrate embodiments of various transistors used to implement the biasing circuit 210, the linearization circuit 220, and the coupling circuit 230 using NMOS transistors. In Figures 3 to 7 ​In other embodiments of the biasing arrangement shown, one or more NMOS transistors of any of the biasing arrangements 300, 400, 500, 600, and 700 can be replaced with an N-type bipolar transistor, i.e., an NPN transistor. For such embodiments, the description provided above still applies, except that for such bipolar transistors, the "first terminal" described above is the base terminal (i.e., the terminal that is the gate terminal of the FET described above), the "second terminal" is the collector terminal (i.e., the terminal that is the drain terminal of the FET described above), and the "third terminal" is the emitter terminal (i.e., the terminal that is the source terminal of the FET described above). Thus, in various embodiments of the biasing arrangement 200, the transistors used in the biasing circuit 210, the linearization circuit 220, and the coupling circuit 230 can be NMOS transistors, NPN transistors, or a combination of NMOS transistors and NPN transistors.

[0059] Furthermore, although Exemplary RF devices and systems Although each of the biasing arrangements 300, 400, 500, 600, and 700 shown and described above indicate that the biasing arrangement 200 can include various transistors that are N-type transistors (e.g., NMOS or NPN transistors), in further embodiments, any of these transistors can be implemented as P-type transistors (e.g., PMOS or PNP transistors). For such embodiments, the description provided above still applies, except that for P-type transistors, the power supply voltage Vs described above for N-type transistors will be replaced with the ground potential Vgnd, and vice versa.

[0060] Figure 8

[0061] As described herein, biasing arrangements having linearization transistors that sense an RF signal and provide a bias signal at different terminals can be included in various RF devices and systems used in wireless or cable communications. For purposes of illustration only, according to some embodiments of the present disclosure, one exemplary RF device can include one or more biasing arrangements having linearization transistors that sense an RF signal and provide a bias signal at different terminals, the exemplary RF device being a Figure 8 is shown in FIG. 22 and described below.

[0062] Figure 8 is a block diagram of an exemplary RF device 2200 (e.g., an RF transceiver) according to some embodiments of the present disclosure that can include one or more biasing arrangements having linearization transistors that sense an RF signal and provide a bias signal at different terminals.

[0063] In general, RF device 2200 can be any device or system that can support wireless transmission and / or reception of signals in the form of electromagnetic waves in the radio frequency range of about 3 kilohertz (kHz) to about 300 gigahertz (GHz). In some embodiments, RF device 2200 can be used for wireless communication, for example, in a base station (BS) or user equipment (UE) device of any suitable cellular wireless communication technology (e.g., GSM, WCDMA, or LTE). In further examples, RF device 2200 can be used as or in a BS or UE device of millimeter wave wireless technology, for example, fifth generation (5G) wireless (i.e., high frequency / short wavelength spectrum, for example, with frequencies between about 20 GHz and 60 GHz GHz, corresponding to wavelengths between about 5 millimeters and 15 millimeters). In yet another example, RF device 2200 can be used for wireless communication using Wi-Fi technology (e.g., 2.4 GHz frequency band, corresponding to wavelengths of about 12 centimeters, or 5.8 GHz frequency band, corresponding to wavelengths of about 5 centimeters), for example, in a Wi-Fi enabled device, such as a desktop computer, laptop computer, video game console, smart phone, tablet computer, smart television, digital audio player, automobile, printer, etc. In some implementations, the Wi-Fi enabled device can be a node in a smart system configured to communicate data with other nodes (e.g., smart sensors). In still another example, RF device 2200 can be used for wireless communication using Bluetooth technology (e.g., 2.4 to about 2.485 GHz frequency band, corresponding to wavelengths of about 12 centimeters). In other embodiments, RF device 2200 can be used to transmit and / or receive RF signals for purposes other than communication, for example, in an automotive radar system, or in a medical application such as magnetic resonance imaging (MRI).

[0064] In various embodiments, RF device 2200 can include frequency division duplexing (FDD) or time division duplexing (TDD) variants of frequency allocations that can be used in cellular networks. In FDD systems, uplink (i.e., RF signals transmitted from a UE device to a BS) and downlink (i.e., RF signals transmitted from a BS to a UE device) can use separate frequency bands simultaneously. In TDD systems, uplink and downlink can use the same frequency but at different times.

[0065] Several components are in Figure 8The components are shown as included in RF device 2200, but any one or more of these components may be omitted or copied as appropriate for the application. For example, in some embodiments, RF device 2200 may be an RF device (e.g., an RF transceiver) that supports wireless transmission and reception of RF signals, in which case it may include components referred to herein as the transmit (TX) path and components referred herein as the receive (RX) path. However, in other embodiments, RF device 2200 may be an RF device that only supports wireless reception (e.g., an RF receiver), in which case it may include components of the RX path but not components of the TX path; or RF device 2200 may be an RF device that only supports wireless transmission (e.g., an RF transmitter), in which case it may include components of the TX path but not components of the RX path.

[0066] In some embodiments, some or all of the components included in the RF device 2200 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, for example, on a single system-on-a-chip (SOC) die.

[0067] Additionally, in various embodiments, the RF device 2200 may not include... Figure 8 The RF device 2200 may include one or more components, but may include interface circuitry for coupling to those components. For example, the RF device 2200 may not include antenna 2202, but may include antenna interface circuitry (e.g., matching circuitry, connectors, and driver circuitry) to which antenna 2202 can be coupled. In another set of examples, the RF device 2200 may not include digital processing unit 2208 or local oscillator 2206, but may include device interface circuitry (e.g., connectors and support circuitry) to which digital processing unit 2208 or local oscillator 2206 can be coupled.

[0068] like Figure 8 As shown, the RF device 2200 may include an antenna 2202, a duplexer 2204 (e.g., if the RF device 2200 is an FDD RF device; otherwise, the duplexer 2204 may be omitted), a local oscillator 2206, and a digital processing unit 2208. Similarly, as... Figure 8 As shown, the RF device 2200 may include an RX path, which may include an RX path amplifier 2212, an RX path premix filter 2214, an RX path mixer 2216, an RX path postmix filter 2218, and an analog-to-digital converter (ADC) 2220. Figure 8Further, the RF device 2200 may include a TX path, which may include a TX path amplifier 2222, a TX path post-mixing filter 2224, a TX path mixer 2226, a TX path pre-mixing filter 2228, and a digital-to-analog converter (DAC) 2230. Furthermore, the RF device 2200 may further include an impedance tuner 2232, an RF switch 2234, and control logic 2236. In various embodiments, the RF device 2200 may include... Figure 8 Examples of any of the components shown. In some embodiments, RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form, or be part of, the RF front end (FE) of RF device 2200. In some embodiments, RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form, or be part of, the RF front end of RF device 2200. In some embodiments, RX path mixer 2216 and TX path mixer 2226 (possibly having...) Figure 8 The associated premixing and postmixing filters shown can be considered as forming an RF transceiver of RF device 2200 (or, if RF device 2200 includes only RX path components or TX path components respectively, an RF receiver or an RF transmitter), or a part thereof. In some embodiments, RF device 2200 may further include one or more control logic elements / circuits, in Figure 8 This is shown as control logic 2236, such as an RF FE control interface. In some embodiments, control logic 2236 may be configured to control operation of at least a portion of a bias arrangement of any linearized transistor having a sensing RF signal and providing a bias signal at different terminals, as described herein, for example, a bias arrangement configured to provide a bias signal to the TX path amplifier 2222 of the RF device 2200. In some embodiments, control logic 2236 may be used to perform other functional controls within the RF device 2200, such as enhancing control of complex RF system environments, supporting implementations of envelope tracking techniques, reducing power dissipation, etc.

[0069] The antenna 2202 can be configured to wirelessly transmit and / or receive RF signals in accordance with any wireless standard or protocol, such as Wi-Fi, LTE, or GSM, and any other wireless protocol designated as 3G, 4G, 5G, and beyond. If the RF device 2200 is an FDD transceiver, the antenna 2202 can be configured for simultaneous reception and transmission of communication signals in separate (i.e., non-overlapping and non-contiguous) frequency bands, such as in frequency bands that are separated from each other by, for example, 20 MHz. If the RF device 2200 is a TDD transceiver, the antenna 2202 can be configured for sequential reception and transmission of communication signals in a frequency band in which the TX and RX paths can be the same or overlapping. In some embodiments, the RF device 2200 can be a multi-band RF device, in which case the antenna 2202 can be configured for simultaneous reception of signals having multiple RF components in separate frequency bands and / or configured for simultaneous transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna 2202 can be a single wideband antenna or a plurality of specific band antennas (i.e., a plurality of antennas each configured to receive and / or transmit signals in a particular frequency band). In various embodiments, the antenna 2202 can include a plurality of antenna elements, such as a plurality of antenna elements forming a phased antenna array (i.e., a communication system or antenna array in which a plurality of antenna elements and phase shifts can be used to transmit and receive RF signals). Phased antenna arrays can provide advantages such as increased gain, steering capability, and simultaneous communication, as compared to single antenna systems. In some embodiments, the RF device 2200 can include more than one antenna 2202 to implement antenna diversity. In some such embodiments, the RF switch 2234 can be deployed to switch between different antennas.

[0070] The output of the antenna 2202 can be coupled to an input of a duplexer 2204. The duplexer 2204 can be any suitable component configured to filter a plurality of signals to permit bidirectional communication over a single path between the duplexer 2204 and the antenna 2202. The duplexer 2204 can be configured to provide RX signals to the RX path of the RF device 2200 and to receive TX signals from the TX path of the RF device 2200.

[0071] The RF device 2200 can include one or more local oscillators 2206 configured to provide local oscillator signals that can be used to downconvert RF signals received by the antenna 2202 and / or upconvert signals to be transmitted by the antenna 2202.

[0072] The RF device 2200 can include a digital processing unit 2208, which can include one or more processing devices. The digital processing unit 2208 can be configured to perform various functions related to digital processing of RX and / or TX signals. Examples of such functions include, but are not limited to, decimation / downsampling, error correction, digital downconversion or upconversion, DC offset cancellation, automatic gain control, etc. Although not shown in FIG. 22, in some embodiments, the RF device 2200 can further include a memory device configured to cooperate with the digital processing unit 2208. Figure 8

[0073] Turning to details of the RX path, which can be included in the RF device 2200, the RX path amplifier 2212 can include a low noise amplifier (LNA). An input of the RX path amplifier 2212 can be coupled to an antenna port (not shown) of the antenna 2202, e.g., via the duplexer 2204. The RX path amplifier 2212 can amplify RF signals received by the antenna 2202.

[0074] An output of the RX path amplifier 2212 can be coupled to an input of an RX path pre-mix filter 2214, which can be a harmonic or bandpass (e.g., lowpass) filter configured to filter the received RF signals that have been amplified by the RX path amplifier 2212.

[0075] ​The output of the RX path pre-mix filter 2214 can be coupled to an input of an RX path mixer 2216 (also referred to as a down-converter). The RX path mixer 2216 can include two inputs and one output. A first input can be configured to receive RX signals indicative of signals received by the antenna 2202, which can be current signals (e.g., the first input can receive the output of the RX path pre-mix filter 2214). A second input can be configured to receive a local oscillator signal from one of the local oscillators 2206. The RX path mixer 2216 can then mix the signals received at its two inputs to produce a down-converted RX signal provided at the output of the RX path mixer 2216. As used herein, down-conversion refers to the process of mixing a received RF signal with a local oscillator signal to produce a lower frequency signal. In particular, the TX path mixer (e.g., down-converter) 2216 can be configured to produce sum and / or difference frequencies at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device 2200 can implement a direct-conversion receiver (DCR), also known as a homodyne, synchrodyne, or zero-IF receiver, in which case the RX path mixer 2216 can be configured to demodulate an incoming radio signal using a local oscillator signal whose frequency is equal to or very close to the carrier frequency of the radio signal. In other embodiments, the RF device 2200 can utilize down-conversion to an intermediate frequency (IF). The IF can be used in a superheterodyne radio receiver, in which the received RF signal is shifted to an IF before final detection of the information in the received signal is completed. Converting to an IF can be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes these filters easier to construct and tune. In some embodiments, the RX path mixer 2216 can include several such IF conversion stages.

[0076] Although in Figure 8A single RX path mixer 2216 is shown in the RX path, but in some embodiments, the RX path mixer 2216 can be implemented as a quadrature downconverter, in which case it would include a first RX path mixer and a second RX path mixer. The first RX path mixer can be configured to perform downconversion to produce an in-phase (I) downconverted RX signal by mixing an RX signal received by the antenna 2202 with an in-phase component of a local oscillator signal provided by the local oscillator 2206. The second RX path mixer can be configured to perform downconversion to produce a quadrature (Q) downconverted RX signal by mixing the RX signal received by the antenna 2202 with a quadrature component of the local oscillator signal (the quadrature component being a component that is offset in phase by 90 degrees from the in-phase component of the local oscillator signal). The output of the first RX path mixer can be provided to an I signal path, and the output of the second RX path mixer can be provided to a Q signal path, which can be offset in phase from the I signal path by substantially 90 degrees.

[0077] Optionally, the output of the RX path mixer 2216 can be coupled to an RX path post-mixing filter 2218, which can be a low pass filter. In the case where the RX path mixer 2216 is a quadrature mixer that implements first and second mixers as described above, the in-phase and quadrature components provided at the output of the first and second mixers, respectively, can be coupled to respective separate first and second RX path post-mixing filters included in the filter 2218.

[0078] The ADC 2220 can be configured to convert the mixed RX signal from the RX path mixer 2216 from the analog domain to the digital domain. The ADC 2220 can be a quadrature ADC that, like the RX path quadrature mixer 2216, can include two ADCs configured to digitize the downconverted RX path signals separated in in-phase and quadrature components. The output of the ADC 2220 can be provided to the digital processing unit 2208, which is configured to perform various functions related to the digital processing of the RX signal so that information encoded in the RX signal can be extracted.

[0079] Turning to the details of the TX path that can be included in the RF device 2200, the digital signal (TX signal) to be transmitted later by the antenna 2202 can be provided from the digital processing unit 2208 to a DAC 2230. Like the ADC 2220, the DAC 2230 can include two DACs configured to convert digital I and Q path TX signal components, respectively, to analog form.

[0080] Optionally, the output of the DAC 2230 can be coupled to a TX path pre-mix filter 2228, which can be a bandpass (e.g., lowpass) filter (or a pair of bandpass (e.g., lowpass) filters in the case of quadrature processing), configured to filter out signal components outside of the desired frequency band from the analog TX signal output by the DAC 2230. The digital TX signal can then be provided to a TX path mixer 2226, which can also be referred to as an up-converter. As with the RX path mixer 2216, the TX path mixer 2226 can include a pair of TX path mixers for in-phase and quadrature components. As with the first RX path mixer and the second RX path mixer that can be included in the RX path, each TX path mixer of the TX path mixer 2226 can include two inputs and one output. The first input can receive the TX signal components converted to analog form by the corresponding DAC 2230, which are to be up-converted to produce the RF signal to be transmitted. The first TX path mixer can produce an in-phase (I) up-converted signal by mixing the TX signal components converted to analog form by the DAC 2230 with an in-phase component of a TX path local oscillator signal provided from a local oscillator 2206 (which, in various embodiments, can include a plurality of different local oscillators, or be configured to provide different local oscillator frequencies to the mixers 2216 in the RX path and the mixers 2226 in the TX path). The second TX path mixer can produce a quadrature-phase (Q) up-converted signal by mixing the TX signal components converted to analog form by the DAC 2230 with a quadrature component of the TX path local oscillator signal. The output of the second TX path mixer can be summed with the output of the first TX path mixer to produce the real RF signal. The second input of each TX path mixer can be coupled to the local oscillator 2206.

[0081] Optionally, the RF device 2200 can include a TX path post-mix filter 2224 configured to filter the output of the TX path mixer 2226.

[0082] The TX path amplifier 2222 can include any of the embodiments of biasing arrangements for linearization transistors that sense the RF signal and provide a bias signal at a different terminal, as described herein.

[0083] In various embodiments, any of the RX path pre-mix filters 2214, the RX path post-mix filters 2218, the TX post-mix filters 2224, and the TX pre-mix filters 2228 can be implemented as RF filters. In some embodiments, the RF filters can be implemented as multiple RF filters or filter banks. A filter bank can include multiple RF filters that can be coupled to a switch, such as the RF switch 2234, configured to selectively turn on and off any of the RF filters (e.g., activate any of the RF filters) in order to achieve the desired filtering characteristics of the filter bank (i.e., in order to program the filter bank). For example, when the RF device 2200 is or is included in a BS or UE device, such a filter bank can be used to switch between different RF frequency ranges. In another example, such a filter bank can be programmable to suppress TX leakage over different duplex distances.

[0084] The impedance tuner 2232 can include any suitable circuitry configured to match the input and output impedances of different RF circuitry to minimize signal loss in the RF device 2200. For example, the impedance tuner 2232 can include an antenna impedance tuner. It can be particularly advantageous to be able to tune the impedance of the antenna 2202 because the impedance of the antenna is a function of the environment in which the RF device 2200 is placed, e.g., the impedance of the antenna varies depending on whether the antenna is held in a hand, placed on a rooftop, etc.

[0085] As described above, the RF switch 2234 can be a device configured to route high frequency signals through a transmission path, e.g., in order to achieve the desired behavior and characteristics of the RF device 2200. Exemplary data processing systems between any one of the components shown, e.g., to achieve the desired behavior and characteristics of the RF device 2200. For example, in some embodiments, the RF switch can be used to switch between different antennas 2202. In other embodiments, the radio frequency switch can be used to switch between multiple RF filters of the RF device 2200 (e.g., by selectively turning on and off the RF filters). Typically, an RF system will include multiple such RF switches.

[0086] The RF device 2200 provides a simplified version, and in further embodiments, can include Figure 9other components not specifically shown. For example, the RX path of RF device 2200 can include a current-to-voltage amplifier between the RX path mixer 2216 and the ADC 2220, which can be configured to amplify and convert the downconverted signal to a voltage signal. In another example, the RX path of RF device 2200 can include a balun for generating a balanced signal. In yet another example, RF device 2200 can further include a clock generator, which may, for example, include a suitable phase-locked loop (PLL) configured to receive a reference clock signal and use it to generate different clock signals that can then be used to time the operation of the ADC 2220, the DAC 2230, and / or can also be used by the local oscillator 2206 to generate a local oscillator signal to be used in the RX path or TX path.

[0087] Figures 3 to 7

[0088] Figure 8 A block diagram showing an exemplary data processing system 2300 according to some embodiments of the present disclosure is provided, which can be configured to control the operation of one or more biasing arrangements having a linearization transistor that senses an RF signal and provides a bias signal at different terminals, as described herein. For example, the data processing system 2300 can be configured to implement or control the portion of the biasing arrangement shown in Figure 9 , or any further embodiments of a biasing arrangement having a linearization transistor that senses an RF signal and provides a bias signal at different terminals, as described herein. In another example, the data processing system 2300 can be configured to implement Figures 2 to 9 at least a portion of the control logic 2236 shown in

[0089] As shown in Figure 9 , the data processing system 2300 can include at least one processor 2302, such as a hardware processor 2302, coupled to memory elements 2304 through a system bus 2306. As such, the data processing system can store program code within memory elements 2304. Further, the processor 2302 can execute the program code accessed from the memory elements 2304 via system bus 2306. In one aspect, the data processing system can be implemented as a computer that is suitable for storing and / or executing program code. It should be appreciated, however, that the data processing system 2300 can be implemented in the form of any system including a processor and a memory that is capable of

[0090] In some embodiments, the processor 2302 can execute software or an algorithm to perform the activities discussed in this disclosure, particularly those related to operating a biasing arrangement having a linearization transistor that senses an RF signal and provides a bias signal at different terminals, as described herein. The processor 2302 can include any combination of hardware, software, or firmware that provides programmable logic, including, by way of non-limiting example, a microprocessor, a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA), an application-specific integrated circuit (IC) (ASIC), or a virtual machine processor. The processor 2302 can be communicatively coupled to the memory element 2304 (e.g., in a direct memory access (DMA) configuration) such that the processor 2302 can read from or write to the memory element 2304.

[0091] In general, the memory element 2304 can include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any memory element discussed herein should be interpreted as encompassing the broad term “memory.” Any information measured, processed, tracked, or transmitted to or from the data processing system 2300 can be provided in any database, register, control list, cache, or storage structure, all of which can be referenced at any suitable time frame. Any such storage option can be included in the broad term “memory” as used herein. Similarly, any potential processing elements, modules, and machines described herein should be interpreted as encompassed in the broad term “processor.” As Figure 9 As shown, each element shown in the figure, such as any element showing a biasing arrangement having a linearization transistor that senses an RF signal and provides a bias signal at different terminals, can also include an interface that is adapted to receive, transmit and / or otherwise communicate data or information in a network environment, such that it can be in communication with, for example, the data processing system 2300.

[0092] In certain example embodiments, mechanisms for implementing or operating a biasing arrangement having a linearization transistor that senses an RF signal and provides a bias signal at different terminals, as outlined herein, can be implemented by logic encoded in one or more tangible media (e.g., a non-transitory medium), which can include DSP instructions, software (potentially including object code and source code) to be executed by a processor, or other similar machines, e.g., an embedded logic of an ASIC. In some of these instances, a memory element, such as the memory element 2304, can store program instructions to be executed by the processor 2302, and a processing element, such as the processor 2302, can execute the instructions to implement or operate a biasing arrangement having a linearization transistor that senses an RF signal and provides a bias signal at different terminals, as outlined herein. Figure 9The memory element 2304 shown can store data or information used for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor can execute any type of instructions associated with data or information to implement the operations detailed herein. In one example, a processor, for example... Figure 9 The processor 2302 shown can transform an element or item (e.g., data) from one state or thing to another. In another instance, the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0093] Memory element 2304 may include one or more physical memory devices, such as local memory 2308 and one or more mass storage devices 2310. Local memory may refer to RAM or other non-persistent memory devices that are typically used during the actual execution of the program code. Mass storage devices may be implemented as hard disk drives or other persistent data storage devices. Processing system 2300 may also include one or more cache memories (not shown) that provide temporary storage for at least some program code to reduce the number of times program code must be retrieved from mass storage device 2310 during execution.

[0094] like Figure 9 As shown, memory element 2304 can store application 2318. In various embodiments, application 2318 can be stored in local memory 2308, one or more mass storage devices 2310, or separately from local memory and mass storage devices. It should be understood that data processing system 2300 can further execute an operating system (…). Selection examples (Not shown in the image), the operating system can facilitate the execution of application 2318. Application 2318, implemented as executable program code, can be executed by data processing system 2300, for example, by processor 2302. In response to executing the application, data processing system 2300 can be configured to perform one or more operational or method steps described herein.

[0095] Input / output (I / O) devices described as input device 2312 and output device 2314 optionally can be coupled to the data processing system. Examples of input devices can include, but are not limited to, a keyboard, a pointing device such as a mouse, or the like. Examples of output devices can include, but are not limited to, a monitor or display, speakers, or the like. In some embodiments, output device 2314 can be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some implementations, the system can include a driver (not shown) for output device 2314. Input and / or output device 2312, 2314 can be coupled to the data processing system either directly or through intervening I / O controllers.

[0096] In one embodiment, input and output devices can be implemented as a combined input / output device (shown in FIG. 23 with dashed line enclosing input device 2312 and output device 2314). An example of such a combined device is a touch-sensitive display, sometimes also referred to as a "touchscreen display" or simply "touchscreen." In such embodiments, input to the device can be provided by moving a physical object (such as a stylus or a user's finger) on or near the touchscreen display. Variations and embodiments

[0097] Optionally, network adapter 2316 can also be coupled to data processing system to enable it to become coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter can comprise a data receiver for receiving data that is transmitted by the systems, devices and / or networks to data processing system 2300, and a data transmitter for transmitting data from data processing system 2300 to the systems, devices and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapter that can be used with data processing system 2300.

[0098] Figures 2 to 9

[0099] The following paragraphs provide various examples of embodiments disclosed herein.

[0100] ​Example 1 provides a biasing arrangement for an amplifier, where the amplifier can be one of a power amplifier (e.g., a Doherty amplifier, a Class-A amplifier, a Class-B amplifier, a Class-AB amplifier, or a Class-C amplifier), a linear amplifier, an LNA, or a variable gain amplifier. The biasing arrangement includes a linearization circuit configured to produce a modified bias signal based on an RF signal indicative of an RF input signal to be amplified by the power amplifier, the linearization circuit including a bias signal input to receive a bias signal (e.g., a DC signal), an RF signal input to receive the RF signal, one or more linearization transistors (each linearization transistor having a first terminal (e.g., a gate terminal of a transistor implemented as a FET or a base terminal of a transistor implemented as a BJT), a second terminal (e.g., a drain terminal of a transistor implemented as a FET or a collector terminal of a transistor implemented as a BJT), and a third terminal (e.g., a source terminal of a transistor implemented as a FET or an emitter terminal of a transistor implemented as a BJT)), and an output to provide the modified bias signal. Each of the bias signal input and the RF signal input of the linearization circuit is coupled to the first terminal of a first linearization transistor of the one or more linearization transistors, and the output of the linearization circuit is coupled to the third terminal of the first linearization transistor.

[0101] Example 2 provides the biasing arrangement of Example 1, where the linearization circuit further includes an RF signal coupling component (e.g., a coupling capacitor) having a first terminal and a second terminal, and the RF signal input of the linearization circuit is coupled to the first terminal of the RF signal coupling component, and the second terminal of the RF signal coupling component is coupled to the first terminal of the first linearization transistor.

[0102] Example 3 provides the biasing arrangement of Example 2, where the RF signal coupling component is a capacitor, the first terminal of the RF signal coupling component is a first capacitor electrode of the capacitor, and the second terminal of the RF signal coupling component is a second capacitor electrode of the capacitor.

[0103] Example 4 provides the biasing arrangement of any of the preceding claims, where the linearization circuit further includes a bias signal coupling component (e.g., a coupling resistor) having a first terminal and a second terminal, and the bias signal input of the linearization circuit is coupled to the first terminal of the bias signal coupling component, and the second terminal of the bias signal coupling component is coupled to the first terminal of the first linearization transistor.

[0104] Example 5 provides the biasing arrangement of Example 4, where the bias signal coupling component is a resistor.

[0105] Example 6 provides the biasing arrangement of any of the preceding claims, wherein the second terminal of the first linearization transistor is coupled to a supply voltage if each of the one or more linearization transistors is an N-type transistor, and the second terminal of the first linearization transistor is coupled to a ground voltage if each of the one or more linearization transistors is a P-type transistor.

[0106] Example 7 provides the biasing arrangement of any of the preceding claims, wherein the one or more linearization transistors further comprise a cascode linearization transistor, the second terminal of the first linearization transistor is coupled to a third terminal of the cascode linearization transistor.

[0107] Example 8 provides the biasing arrangement of Example 7, wherein the second terminal of the cascode linearization transistor is coupled to a supply voltage if each of the one or more linearization transistors is an N-type transistor, and the second terminal of the cascode linearization transistor is coupled to a ground voltage if each of the one or more linearization transistors is a P-type transistor.

[0108] Example 9 provides the biasing arrangement of claim 7 or 8, wherein the first terminal of the cascode linearization transistor is coupled to a voltage source.

[0109] Example 10 provides the biasing arrangement of any of the preceding claims, wherein the RF input signal is a differential signal comprising a first differential part and a second differential part, the RF signal is a first differential RF signal indicative of the first differential part of the RF input signal, the RF signal input is a first RF signal input, the linearization circuit further comprises a second RF signal input for receiving a second differential RF signal indicative of the second differential part of the RF input signal, the one or more linearization transistors further comprise a second linearization transistor, each of the bias signal input of the linearization circuit and the second RF signal input is coupled to a first terminal of the second linearization transistor, and the output of the linearization circuit is further coupled to a third terminal of the second linearization transistor.

[0110] Example 11 provides the biasing arrangement of Example 10, wherein the linearization circuit further comprises a second RF signal coupling component (e.g., a coupling capacitor) having a first terminal and a second terminal, and the second RF signal input of the linearization circuit is coupled to the first terminal of the second RF signal coupling component, and the second terminal of the second RF signal coupling component is coupled to the first terminal of the second linearization transistor, the second RF signal input of the linearization circuit is coupled to the first terminal of the second linearization transistor.

[0111] Example 12 provides the bias arrangement of Example 11, wherein the second RF signal coupling component is a capacitor, the first terminal of the second RF signal coupling component is a first capacitor electrode of the capacitor, and the third terminal of the second RF signal coupling component is a second capacitor electrode of the capacitor.

[0112] Example 13 provides the bias arrangement of any one of claims 10 to 12, wherein the one or more linearization transistors further comprise a first cascode linearization transistor and a second cascode linearization transistor, the second terminal of the first linearization transistor is coupled to a third terminal of the first cascode linearization transistor, the second terminal of the second linearization transistor is coupled to a third terminal of the second cascode linearization transistor, and a first terminal of the first cascode linearization transistor is coupled to a first terminal of the second cascode linearization transistor.

[0113] Example 14 provides the bias arrangement of any one of claims 10 to 13, wherein the second RF signal input of the linearization circuit is further coupled to the third terminal of the first linearization transistor, and the first RF signal input of the linearization circuit is further coupled to the third terminal of the second linearization transistor.

[0114] Example 15 provides the bias arrangement of any one of the preceding claims, wherein the linearization circuit further comprises a first degeneration component (e.g., a first degeneration resistor) and a second degeneration component (e.g., a second degeneration resistor), each degeneration component having a first terminal and a second terminal, the first terminal of the first degeneration component is coupled to the output of the linearization circuit through, and the second terminal of the first degeneration component is coupled to the third terminal of the first linearization transistor, the output of the linearization circuit is coupled to the third terminal of the first linearization transistor, and the output of the linearization circuit is coupled to the third terminal of the second linearization transistor through the first terminal of the second degeneration component, and the second terminal of the second degeneration component is coupled to the third terminal of the second linearization transistor.

[0115] Example 16 provides the bias arrangement of Example 15, wherein the second terminal of the first degeneration component is coupled to the second RF signal input of the linearization circuit, the second RF signal input of the linearization circuit is further coupled to the third terminal of the first linearization transistor, and the second terminal of the second degeneration component is coupled to the first RF signal input of the linearization circuit through, and the first RF signal input of the linearization circuit is further coupled to the third terminal of the second linearization transistor.

[0116] Example 17 provides a biasing arrangement for a power amplifier. The biasing arrangement includes a linearization circuit configured to generate a modified bias signal based on an RF input signal to be amplified by the power amplifier, the linearization circuit including one or more linearization transistors each having a first terminal (e.g., a gate terminal for a transistor implemented as an FET or a base terminal for a transistor implemented as a BJT), a second terminal (e.g., a drain terminal for a transistor implemented as an FET or a collector terminal for a transistor implemented as a BJT), and a third terminal (e.g., a source terminal for a transistor implemented as an FET or an emitter terminal for a transistor implemented as a BJT), and an RF signal input for receiving an RF signal indicative of the RF input signal to be amplified by the power amplifier. The biasing arrangement further includes an output for outputting the modified bias signal generated based on the RF signal, wherein the RF signal input and the output of the linearization circuit are coupled to different terminals of a first linearization transistor of the one or more linearization transistors.

[0117] Example 18 provides the biasing arrangement of Example 17, wherein the biasing arrangement further includes a bias circuit having an output configured to output a bias signal for the power amplifier, the biasing arrangement further including a coupling circuit having an input coupled to the output of the bias circuit, and an output coupled to an input of the bias circuit, the linearization circuit further including a bias signal input for receiving a signal indicative of the bias signal output by the bias circuit, the bias signal input of the linearization circuit being coupled to the output of the coupling circuit, and the RF signal input and the bias signal input of the linearization circuit being coupled to a single (i.e., same) terminal of the first linearization transistor.

[0118] Example 19 provides a biasing arrangement for a power amplifier, the biasing arrangement comprising a linearization circuit configured to generate a modified bias signal based on an RF input signal to be amplified by the power amplifier, the RF input signal being a differential signal comprising a first differential portion and a second differential portion. The linearization circuit comprises a plurality of linearization transistors, each linearization transistor having a first terminal (e.g., a gate terminal of a transistor implemented as a FET or a base terminal of a transistor implemented as a BJT), a second terminal (e.g., a drain terminal of a transistor implemented as a FET or a collector terminal of a transistor implemented as a BJT), and a third terminal (e.g., a source terminal of a transistor implemented as a FET or an emitter terminal of a transistor implemented as a BJT). Each linearization transistor further comprises a first RF signal input to receive a first differential RF signal indicative of the first differential portion of the RF input signal, a second RF signal input to receive a second differential RF signal indicative of the second differential portion of the RF input signal, and an output to output the modified bias signal generated based on the RF input signal. The plurality of linearization transistors comprises a first linearization transistor and a second linearization transistor, wherein the first RF signal input is coupled to the first terminal of the first linearization transistor and the third terminal of the second linearization transistor, the second RF signal input is coupled to the first terminal of the second linearization transistor and the third terminal of the first linearization transistor, and the output is coupled to the third terminal of the first linearization transistor and the third terminal of the second linearization transistor.

[0119] Example 20 provides the biasing arrangement of Example 19, wherein the first RF signal input is coupled to the first terminal of the first linearization transistor via a first coupling component (e.g., capacitor 364-1), the second RF signal input is coupled to the third terminal of the first linearization transistor via a second coupling component (e.g., capacitor 764-1), the first RF signal input is coupled to the third terminal of the second linearization transistor via a first further coupling component (e.g., capacitor 764-2), and the second RF signal input is coupled to the first terminal of the second linearization transistor via a second further coupling component (e.g., capacitor 364-2).

[0120] Example 21 provides an RF system, the RF system comprising an amplifier configured to receive an input signal and generate an output signal based on the input signal; and a biasing arrangement configured to provide a bias signal to the amplifier, wherein the biasing arrangement is in accordance with any of the preceding examples.

[0121] Example 22 provides the RF system of Example 21, further comprising an antenna element configured to wirelessly transmit an RF signal based on the output signal generated by the amplifier.

[0122] Example 23 provides an RF system according to Example 21 or 22, further including a beamforming element configured to receive a first signal and generate a second signal phase-shifted relative to the first signal, wherein the input signal of the amplifier is based on the second signal generated by the beamforming element.

[0123] Example 24 provides an RF system according to any one of Examples 21 to 23, wherein the amplifier is one of a power amplifier (e.g., a Dougherty amplifier, a Class A amplifier, a Class B amplifier, a Class AB amplifier, or a Class C amplifier), a linear amplifier, an LNA, or a variable gain amplifier.

[0124] Example 25 provides an RF system according to any one of Examples 21 to 24, wherein the RF system is a mobile device (e.g., a UE of a wireless cellular network).

[0125] Example 26 provides an RF system according to any one of Examples 21 to 24, wherein the RF system is a base station of a wireless cellular network or a transmitter of a cable communication network.

[0126] Figures 2 to 9

[0127] Despite the above reference ​ The exemplary embodiments shown describe embodiments of this disclosure; however, those skilled in the art will recognize that the various teachings described above can be applied to a variety of other embodiments. For example, the description provided herein is applicable not only to 5G systems providing examples of wireless communication systems, but also to other wireless communication systems, such as, but not limited to, Wi-Fi or Bluetooth technologies. In yet another example, the description provided herein is applicable not only to wireless communication systems, but also to any other system that may use amplifiers, such as radar systems, automotive radar, and cable communication systems (e.g., cable television systems, etc.).

[0128] In certain contexts, the features discussed in this paper can be applied to automotive systems, medical systems, scientific instruments, wireless and wired communications, radio, radar, and digital processing-based systems.

[0129] In the discussion of the above embodiments, system components, such as phase shifters, mixers, transistors, resistors, capacitors, amplifiers, and / or other components, can be readily replaced, superseded, or otherwise modified to suit the needs of a particular circuit system. Furthermore, it should be noted that the use of complementary electronics, hardware, software, etc., provides an equally viable alternative to implementing the teachings of this disclosure, which pertain to the bias arrangement of linearized transistors that sense RF signals and provide bias signals at different terminals, as described herein.

[0130] Aspects for implementing various systems for biasing arrangements having a linearized transistor that senses an RF signal and provides a bias signal at different terminals can include electronic circuitry that performs the functions described herein, as presented herein. In some cases, one or more parts of the system can be provided by a processor specifically configured to perform the functions described herein. For example, the processor can include one or more application-specific components, or can include programmable logic gates configured to perform the functions described herein. The circuitry can operate in the analog domain, the digital domain, or the mixed-signal domain. In some cases, the processor can be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0131] In one example embodiment, any number of the circuits of the present figures can be implemented on a board of an associated electronic device. The board can be a general purpose circuit board or a dedicated purpose board, which can hold various components of the internal electronic system of the device and further provide connectors to allow access to the internal components by other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (including DSPs, microprocessors, supporting chipsets and the like), computer readable non-transitory memory elements, or the like, can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, or the like. Other components such as external storage, additional sensors, controllers and peripherals for audio / video displays, or the like, can be attached to the board as plug-in cards via appropriate cable connections or integrated into the board itself in various embodiments. The functions described herein can be implemented in emulation form as software or firmware running in one or more configurable (e.g., programmable) elements in structures arranged to support the functionality of these elements. The software or firmware providing the emulation can be provided on non-transitory computer readable storage medium including instructions that, when executed by a processor, result in the performance of these functions.

[0132] In another example embodiment, the circuits of the present invention can be implemented as a standalone module (e.g., a device having the relevant components and circuitry configured to perform particular applications or functions) or as a plug-in module in application-specific hardware of an electronic device. Note that particular embodiments of the present disclosure can be readily included in a SOC package, among other possibilities. A SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It can contain digital, analog, mixed-signal, and often RF functions: all of which can be provided on a single chip substrate. Other embodiments can include a multi-chip-module (MCM), in which multiple separate ICs are located on a single module and configured to interact closely with each other through the electronic module.

[0133] It must also be noted that all specifications, dimensions and relationships herein outlined (e.g., the ​The number of components shown in the system of FIG. 1 is provided for purposes of example and teaching only. Such information can vary considerably without departing from the spirit of the present disclosure or the scope of the appended claims. It will be appreciated that the system can be integrated in any suitable manner. Along similar design alternatives, any of the circuits, components, modules, and elements shown in the present figures can be combined in various possible configurations, all of which are clearly within the broad scope of the present specification. In the foregoing description, exemplary embodiments have been described with reference to particular processor and / or component arrangements. Various modifications and changes can be made to such embodiments without departing from the scope of the appended claims. The description and figures are, therefore, to be considered in all respects only as illustrative and not restrictive.

[0134] It is also important to note that the functions relating to implementing biasing arrangements with linearization transistors that sense RF signals and provide bias signals at different terminals described herein show only some possible functions that can be performed by or within an RF system. Some of these operations can be deleted or removed where appropriate, or these operations can be modified or changed considerably without departing from the scope of the present disclosure. Considerable flexibility is provided by the embodiments described herein, as any suitable arrangements, schedules, configurations, and timing mechanisms can be provided without departing from the teachings of the present disclosure.

Claims

1. An electronic component, comprising: a biasing circuit configured to generate a bias signal for a power amplifier; a coupling circuit configured to receive the bias signal as input from the biasing circuit and to provide an output signal based on the bias signal to a linearization circuit; a feedback path coupling an output of the coupling circuit to an input of the biasing circuit, thereby forming a bias loop; and a linearization circuit for generating a modified bias signal based on a radio frequency, RF, input signal to be amplified by the power amplifier, wherein the RF input signal is a differential signal comprising a first differential part and a second differential part, and wherein the linearization circuit comprises: a bias signal input for receiving the output signal of the coupling circuit, a first RF signal input for receiving a first RF signal indicative of the first differential part of the RF input signal, a second RF signal input for receiving a second RF signal indicative of the second differential part of the RF input signal, linearization transistors each having a first terminal, a second terminal, and a third terminal, and an output for providing the modified bias signal, wherein: each of the bias signal input and the first RF signal input is coupled to the first terminal of a first one of the linearization transistors, each of the bias signal input and the second RF signal input is coupled to the first terminal of a second one of the linearization transistors, the output is coupled to the third terminal of the first linearization transistor and to the third terminal of the second linearization transistor, and the third terminal of the first linearization transistor and the third terminal of the second linearization transistor are each grounded via their respective coupling components.

2. The electronic component of claim 1, wherein: the linearization circuit further comprises an RF signal coupling component having a first terminal and a second terminal, and the first terminal of the RF signal coupling component is coupled to the first RF signal input, and the second terminal of the RF signal coupling component is coupled to the first terminal of the first linearization transistor, the first RF signal input being coupled to the first terminal of the first linearization transistor.

3. The electronic component of claim 2, wherein the RF signal coupling component is a capacitor, the first terminal of the RF signal coupling component is a first capacitor electrode of the capacitor, and the second terminal of the RF signal coupling component is a second capacitor electrode of the capacitor.

4. The electronic component of claim 1, wherein: the linearization circuit further comprises a bias signal coupling component having a first terminal and a second terminal, and the first terminal of the bias signal coupling component is coupled to the bias signal input, and the second terminal of the bias signal coupling component is coupled to the first terminal of the first linearization transistor, the bias signal input being coupled to the first terminal of the first linearization transistor.

5. The electronic component of claim 4, wherein the bias signal coupling component is a resistor. ​ 6. The electronic component of claim 1, wherein: when the first linearization transistor is an N-type transistor, the second terminal of the first linearization transistor is to be coupled to a power supply, and when the first linearization transistor is a P-type transistor, the second terminal of the first linearization transistor is to be coupled to a ground voltage.

7. The electronic component of claim 1, wherein: the linearization transistor further comprises a cascode linearization transistor, and the second terminal of the first linearization transistor is coupled to a third terminal of the cascode linearization transistor.

8. The electronic component of claim 7, wherein: when the cascode linearization transistor is an N-type transistor, the second terminal of the cascode linearization transistor is to be coupled to a power supply voltage, and when the cascode linearization transistor is a P-type transistor, the second terminal of the cascode linearization transistor is to be coupled to a ground voltage.

9. The electronic component of claim 7, wherein a first terminal of the cascode linearization transistor is to be coupled to a voltage source.

10. The electronic component of claim 1, further comprising a power amplifier.

11. The electronic component of claim 1, wherein the electronic component is an RF transceiver.

12. The electronic component of claim 1, wherein: the linearization circuit further comprises a second RF signal coupling component having a first terminal and a second terminal, and the second RF signal input is coupled to the first terminal of the second RF signal coupling component, and the second terminal of the second RF signal coupling component is coupled to the first terminal of the second linearization transistor.

13. The electronic component of claim 12, wherein the second RF signal coupling component is a capacitor, the first terminal of the second RF signal coupling component is a first capacitor electrode of the capacitor, and the second terminal of the second RF signal coupling component is a second capacitor electrode of the capacitor.

14. The electronic component of claim 1, wherein: the linearization transistor further comprises a first cascode linearization transistor and a second cascode linearization transistor, the second terminal of the first linearization transistor is coupled to a third terminal of the first cascode linearization transistor, the second terminal of the second linearization transistor is coupled to a third terminal of the second cascode linearization transistor, and a first terminal of the first cascode linearization transistor is coupled to a first terminal of the second cascode linearization transistor.

15. The electronic component of claim 1, wherein: the second RF signal input is further coupled to a third terminal of the first linearization transistor, and the first RF signal input is further coupled to a third terminal of the second linearization transistor.

16. The electronic component of claim 15, wherein: the linearization circuit further comprises a first degeneration component and a second degeneration component, each degeneration component having a first terminal and a second terminal, the first terminal of the first degeneration component is coupled to the third terminal of the first linearization transistor, and the first terminal of the second degeneration component is coupled to the third terminal of the second linearization transistor. through a first terminal of the first degeneration component and a second terminal of the first degeneration component is coupled to a third terminal of the first linearization transistor, the output is coupled to the third terminal of the first linearization transistor, and through a first terminal of the second degeneration component and a second terminal of the second degeneration component is coupled to a third terminal of the second linearization transistor, the output is further coupled to the third terminal of the second linearization transistor.

17. The electronic component of claim 16, wherein: through the second RF signal input is coupled to a second terminal of the first degeneration component, the second RF signal input is further coupled to a third terminal of the first linearization transistor, and through the first RF signal input is coupled to a second terminal of the second degeneration component, the first RF signal input is further coupled to a third terminal of the second linearization transistor.

18. An electronic component, comprising: a biasing circuit configured to generate a bias signal for a power amplifier; a coupling circuit configured to receive the bias signal as an input from the biasing circuit and to provide an output signal based on the bias signal to a linearization circuit; a feedback path coupling an output of the coupling circuit to an input of the biasing circuit, thereby forming a bias loop; and the linearization circuit for generating a modified bias signal based on the bias signal and further based on a radio frequency, RF, input signal to be amplified by the power amplifier, the linearization circuit comprising: a bias signal input for receiving the output signal of the coupling circuit, a linearization transistor, an RF signal input for receiving an RF signal indicative of the RF input signal to be amplified by the power amplifier, and an output for providing the modified bias signal, wherein: a first terminal of the linearization transistor is coupled to each of the bias signal input and the RF signal input, a second terminal of the linearization transistor is to be coupled to a supply voltage when the linearization transistor is an N-type transistor and to be coupled to a ground voltage when the linearization transistor is a P-type transistor, a third terminal of the linearization transistor is to be coupled to the output.

19. The electronic component of claim 18, wherein, the linearization circuit further comprises a bias signal coupling component coupled between the bias signal input and the first terminal of the linearization transistor.

20. The electronic component of claim 19, wherein, through a first terminal of the bias signal coupling component and a second terminal of the bias signal coupling component is coupled to the first terminal of the linearization transistor, the first terminal of the linearization transistor is coupled to the bias signal input.

21. The electronic component of claim 19, wherein, the bias signal coupling component is a resistor.

22. The electronic component of claim 18, wherein: when the linearization transistor is a bipolar transistor, a first terminal of the linearization transistor is a base terminal, a second terminal of the linearization transistor is a collector terminal, and a third terminal of the linearization transistor is an emitter terminal, and when the linearization transistor is a field effect transistor, a first terminal of the linearization transistor is a source terminal, a second terminal of the linearization transistor is a drain terminal, and a third terminal of the linearization transistor is a gate terminal. When the linearization transistor is a field effect transistor, the first terminal of the linearization transistor is a gate terminal, the second terminal of the linearization transistor is a drain terminal, and the third terminal of the linearization transistor is a source terminal.

23. The electronic component of claim 18, further comprising the power amplifier.

24. The electronic component of claim 18, further comprising an antenna element for wirelessly transmitting an RF signal based on an output signal generated by the power amplifier based on an RF input signal.

25. The electronic component of claim 18, further comprising a beamforming element for receiving a first signal and generating a second signal that is phase shifted relative to the first signal, wherein the RF input signal to be amplified by the power amplifier is based on the second signal generated by the beamforming element.

26. The electronic component of claim 18, wherein, The electronic component is an RF transceiver.

27. An electronic component, comprising: a biasing circuit configured to generate a bias signal for a power amplifier; a coupling circuit configured to receive the bias signal as an input from the biasing circuit and to provide an output signal based on the bias signal to a linearization circuit; a feedback path coupling an output of the coupling circuit to an input of the biasing circuit, thereby forming a bias loop; a linearization circuit for generating a modified bias signal based on a radio frequency, RF, input signal to be amplified by the power amplifier, the RF input signal being a differential signal comprising a first differential part and a second differential part, and the linearization circuit comprising: a plurality of linearization transistors, each linearization transistor having a first terminal, a second terminal, and a third terminal, a first RF signal input for receiving a first RF signal indicative of the first differential part of the RF input signal, a second RF signal input for receiving a second RF signal indicative of the second differential part of the RF input signal, and an output for outputting the modified bias signal generated based on the RF input signal, wherein: the plurality of linearization transistors comprises a first linearization transistor and a second linearization transistor, the first RF signal input is coupled to the first terminal of the first linearization transistor and to the third terminal of the second linearization transistor, the second RF signal input is coupled to the first terminal of the second linearization transistor and to the third terminal of the first linearization transistor, the output is coupled to the third terminal of the first linearization transistor and to the third terminal of the second linearization transistor, and the third terminal of the first linearization transistor and the third terminal of the second linearization transistor are grounded via their respective coupling components.

28. The electronic component of claim 27, wherein: the first RF signal input is coupled to the first terminal of the first linearization transistor via a first coupling component, the second RF signal input is coupled to the third terminal of the first linearization transistor via a second coupling component, the first RF signal input is coupled to the third terminal of the second linearization transistor via a first further coupling component, and the second RF signal input is coupled to the third terminal of the first linearization transistor via a second further coupling component. The second RF signal input is coupled to a first terminal of the second linearization transistor via a second further coupling component.

29. The electronic component of claim 27, wherein: when a single linearization transistor of the plurality of linearization transistors is a bipolar transistor, a first terminal of the single linearization transistor is a base terminal, a second terminal of the single linearization transistor is a collector terminal, and a third terminal of the single linearization transistor is an emitter terminal, and when a single linearization transistor of the plurality of linearization transistors is a field effect transistor, a first terminal of the single linearization transistor is a gate terminal, a second terminal of the single linearization transistor is a drain terminal, and a third terminal of the single linearization transistor is a source terminal.

30. The electronic component of claim 27, further comprising the power amplifier.

31. The electronic component of claim 27, further comprising an antenna element for wirelessly transmitting an RF signal based on an output signal generated by the power amplifier based on an RF input signal.

32. The electronic component of claim 27, further comprising a beamforming element for receiving a first signal and generating a second signal that is phase shifted relative to the first signal, wherein the RF input signal to be amplified by the power amplifier is based on the second signal generated by the beamforming element.

33. The electronic component of claim 27, wherein, The electronic component is an RF transceiver.

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