A sigma-delta analog-to-digital converter

Abstract

The application discloses a Sigma-Delta analog-digital converter, which comprises a loop filter module, a first feedback circuit, a second feedback circuit and a quantizer; the loop filter module comprises summation nodes connected in a cascade mode; the first feedback circuit is connected between the input end of the summation node corresponding to the first-stage integrator and the output end of the quantizer, and is used for performing first time extension processing on the quantization output signal output by the quantizer and converting a first feedback signal; the second feedback circuit is connected between the summation node corresponding to the last-stage integrator and the output end of the quantizer, and is used for performing second time extension processing on the quantization output signal output by the quantizer and converting a second feedback signal, and then transmitting the second feedback signal to the summation node corresponding to the last-stage integrator.

Description

Technical Field

[0001] This invention belongs to the technical field of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and particularly relates to a Sigma-Delta analog-to-digital converter. Background Technology

[0002] A Sigma-Delta analog-to-digital converter (ADC), also known as a delta-sigma analog-to-digital converter, primarily employs oversampling and noise shaping techniques for high-precision audio signal processing. The basic structure of a Sigma-Delta ADC includes a ring filter, a quantizer, and a feedback DAC, which together form a feedback loop. Generally, a Sigma-Delta ADC operates at a rate significantly higher than the bandwidth of the analog input signal to provide oversampling. The analog input is differentially compared with the feedback signal (error signal), and the resulting difference is fed into the ring filter. The Sigma-Delta ADC then uses feedback to bring this difference towards zero.

[0003] The quantizer used in Sigma-Delta analog-to-digital converters can be a multi-bit quantizer. After the result of the quantizer is encoded, it is directly output in multiple bits simultaneously. Using a multi-bit quantizer can increase the signal-to-noise ratio, making the Sigma-Delta ADC easier to stabilize and generating fewer harmonic components. However, multi-bit quantizers increase the complexity of the Sigma-Delta ADC and require the multi-bit DAC used for feedback to have sufficient accuracy to ensure the accuracy and linearity of the final quantization by the quantizer.

[0004] Multi-bit quantization requires a multi-bit feedback DAC. Mismatch in the unit structure of different feedback DACs can cause nonlinearity in the feedback DAC. The component matching index and accuracy requirements of the feedback DAC will increase with the increase of the number of bits of the feedback DAC, which increases the design complexity of the Sigma-Delta analog-to-digital converter. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention discloses a Sigma-Delta analog-to-digital converter (ADC), specifically a Sigma-Delta ADC capable of achieving time-stretching effects. This reduces the design complexity of the DAC in the feedback loop, further lowers matching requirements, and simultaneously ensures the linearity of the DAC. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its purpose is to present some concepts in a simple form as an outline for the detailed description that follows.

[0006] A Sigma-Delta analog-to-digital converter (ADC) includes a loop filter module, a first feedback circuit, and a quantizer. The loop filter module includes a summing node and an integrator. The integrators are cascaded within the loop filter module, with the input of each integrator connected to a corresponding summing node, forming a single integrator corresponding to a single summing node. The first feedback circuit is connected between the input of the summing node corresponding to the first-stage integrator and the output of the quantizer. The first feedback circuit performs a first time-delay processing on the quantized output signal from the quantizer and converts it into a first feedback signal, which is then transmitted to the input of the summing node corresponding to the first-stage integrator.

[0007] Furthermore, the Sigma-Delta analog-to-digital converter also includes a second feedback circuit; the second feedback circuit is connected between the summing node corresponding to the last stage integrator and the output terminal of the quantizer, and the second feedback circuit is used to perform a second time-delay processing on the quantized output signal output by the quantizer and convert it into a second feedback signal, and then transmit the second feedback signal to the summing node corresponding to the last stage integrator; wherein, the second time-delay processing performed by the second feedback circuit is used to compensate for the first time-delay processing performed by the first feedback circuit.

[0008] Furthermore, the quantizer, the first feedback circuit, and the loop filter module are cascaded to form a feedback loop and constitute a first loop filter function; wherein, the first loop filter function is obtained by modifying the original transfer function by the first feedback circuit, and is the transfer function of the Sigma-Delta analog-to-digital converter; the quantizer, the second feedback circuit, and the loop filter module are cascaded to form a compensation loop and constitute a second loop filter function, wherein, the second loop filter function is used to compensate the first loop filter function to adjust the transfer function of the Sigma-Delta analog-to-digital converter back to the original transfer function.

[0009] Further, the first feedback circuit includes a first feedback DAC and a first filter; the input terminal of the first filter is connected to the output terminal of the quantizer, the input terminal of the first feedback DAC is connected to the output terminal of the first filter, and the output terminal of the first feedback DAC is connected to the input terminal of the summing node corresponding to the first-stage integrator; the first filter is used to perform a delay processing on the quantized output signal output by the quantizer for a number of times equal to a first preset number of taps, wherein the delay processing performed by the first filter for a number of times equal to the first preset number of taps is the first time stretching processing, so that the accuracy of the quantized output signal filtered by the first filter is higher than that of the quantized output signal; the first preset number of taps is the number of taps of the first filter; the first feedback DAC is used to convert the quantized output signal filtered by the first filter into a first feedback signal in real time, and then transmit the first feedback signal to the input terminal of the summing node corresponding to the first-stage integrator, so as to change the original transfer function.

[0010] Furthermore, except for the summing node corresponding to the first-stage integrator, the input terminal of the summing node corresponding to each stage integrator is connected to the output terminal of the first feedback DAC.

[0011] Further, the second feedback circuit includes a second feedback DAC and a second filter; the number of taps of the second filter is equal to the second preset number of taps; the input of the second filter is connected to the output of the quantizer, the input of the second feedback DAC is connected to the output of the second filter, and the output of the second feedback DAC is connected to the input of the summing node corresponding to the last integrator; the second filter is used to perform a delay processing on the quantized output signal output by the quantizer for the number of times the second preset number of taps is performed, wherein the delay processing performed by the second filter for the number of times the second preset number of taps is the second time extension processing, to compensate the first filter, and also to make the accuracy of the quantized output signal filtered by the second filter higher than that of the quantized output signal; the second feedback DAC is used to convert the quantized output signal filtered by the second filter into a second feedback signal, and then transmit the second feedback signal to the input of the summing node corresponding to the last integrator, so that the quantized output signal is extended into an analog signal with a delay compensation effect, thereby adjusting the transfer function of the Sigma-Delta analog-to-digital converter to the original transfer function.

[0012] Furthermore, the first filter internally has first filter coefficients, and correspondingly, the first filter introduces a first filter transfer function into the first feedback circuit; wherein, the first filter coefficients are parameters belonging to the first filter transfer function; the second filter internally has second filter coefficients, and correspondingly, the second filter introduces a second filter transfer function into the second feedback circuit; wherein, the second filter coefficients are parameters belonging to the second filter transfer function; wherein, the first filter coefficients and the second filter coefficients cooperate with each other, so that the signal changes induced by the first filter transfer function in the Sigma-Delta analog-to-digital converter and the signals induced by the second filter transfer function in the Sigma-Delta analog-to-digital converter cancel each other out, thereby controlling the delay state of the transfer function of the Sigma-Delta analog-to-digital converter to remain the same as the delay state of the original transfer function.

[0013] Furthermore, the filter coefficients set inside the first filter and the filter coefficients set inside the second filter are not exactly the same. The number of filter coefficients set inside the first filter and the number of filter coefficients set inside the second filter are both equal to the preset number of taps. The implementation structure of the first filter and the implementation structure of the second filter belong to the same preset filter structure.

[0014] Furthermore, the preset filter structure includes m delay units, a coefficient matching module, and an accumulator; the m delay units are connected in series to generate m digital input signals representing different delays; where m is a positive integer; the coefficient matching module is used to provide a matching filter coefficient for each digital input signal, multiply each digital input signal by its matching filter coefficient, and then output the corresponding product; the accumulator is used to add each product output by the coefficient matching module to obtain the filtered quantized output signal.

[0015] Furthermore, the loop filtering module includes N-stage summing nodes, N-stage integrators, and a final operational amplifier; the output of the final integrator is connected to the input of the final operational amplifier, the output of the final operational amplifier is connected to the input of the quantizer, and the output of the final operational amplifier is used to output a pre-feedback analog signal; each summing node has a first input, a second input, and an output; the first input of the i-th stage summing node is connected to the output of the (i-1)-th stage integrator, and the first input of the i-th stage summing node is used to receive the (i-1)-th stage integrated analog signal output by the (i-1)-th stage integrator; the second input of the i-th stage summing node is connected to the output of the final operational amplifier, and the second input of the i-th stage summing node... The terminal is used to receive the pre-feedback analog signal output by the final operational amplifier; the output terminal of the i-th stage summing node is connected to the input terminal of the i-th stage integrator, and the output terminal of the i-th stage summing node is used to output the i-th stage summing analog signal to the input terminal of the i-th stage integrator, wherein the i-th stage summing analog signal is the sum of the (i-1)-th stage integrated analog signal and the pre-feedback analog signal output by the final operational amplifier; the i-th stage integrator is used to integrate the i-th stage summing analog signal and then output the i-th stage integrated analog signal; the (i-1)-th stage integrator is used to integrate the output signal of the (i-1)-th stage summing node to obtain the (i-1)-th stage integrated analog signal; wherein, N is a positive integer; i is an integer greater than 1 and i is an integer less than or equal to N-1.

[0016] Further, the first input terminal of the first-stage summing node is used to receive an analog input signal, and the second input terminal of the first-stage summing node is used to receive a first feedback signal output by the first feedback circuit; the output terminal of the first-stage summing node is used to output a first-stage summing analog signal to the first-stage integrator; wherein, the first-stage summing node is used to sum the analog signal and the first feedback signal provided by the first feedback circuit, and configure the sum value as the first-stage summing analog signal; wherein, the first-stage integrator is used to receive the integration of the first-stage summing analog signal to obtain a first-stage integrated analog signal.

[0017] Furthermore, the first input terminal of the Nth-stage summing node is connected to the output terminal of the (N-1)th-stage integrator, and the first input terminal of the Nth-stage summing node is used to receive the (N-1)th-stage integral analog signal output by the (N-1)th-stage integrator; the second input terminal of the i-th-stage summing node is connected to the output terminal of the second feedback circuit, and the second input terminal of the i-th-stage summing node is used to receive the second feedback signal output by the second feedback circuit; the output terminal of the Nth-stage summing node is used to output the Nth-stage summing analog signal to the Nth-stage integrator.

[0018] Furthermore, in addition to the first and second input terminals, the Nth-level summing node also has N-1 preset input terminals; in the first to N-1th-level summing nodes, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the Nth-level summing node; wherein, the Nth-level summing node is used to sum the N-1th-level integral analog signal, the second feedback signal, and the signal input to each preset input terminal, and configures the sum value as the Nth-level summing analog signal; wherein, the Nth-level integrator is used to receive the integration of the Nth-level summing analog signal to obtain the Nth-level integral analog signal.

[0019] Furthermore, each integrator stage is a continuous-time structure used to integrate the input signal. Each integrator stage internally includes branch resistors and pre-configured operational amplifiers. The output of the branch resistor is connected to the input of the pre-configured operational amplifier, and the input of the branch resistor is configured as the input of the corresponding summation node. The output of the branch resistor is configured as the output of the corresponding summation node. The pre-configured operational amplifier's input is the input of its respective integrator. The first input of each summation node is the input of one branch resistor within the corresponding integrator, and the second input of each summation node is the input of another branch resistor within the corresponding integrator. Each preset input of the final summation node is the input of the corresponding branch resistor within the final integrator.

[0020] Furthermore, N is a value of 3; when the quantization bit number of the quantizer is set to a value of 1, the quantizer is used to quantize the signal output by the loop filter module into a 1-bit digital signal to reduce the nonlinearity of the feedback DAC; both the first feedback circuit and the second feedback circuit are used to convert the 1-bit digital signal output by the quantizer into an analog signal for feedback.

[0021] Compared with the prior art, the present invention connects a first feedback circuit between the loop filter module and the quantizer. The first feedback circuit processes the quantized output signal output by the quantizer in a time-delayed manner. In fact, it uses a first loop filter function composed of the cascaded first feedback circuit, the loop filter module and the quantizer to process the input analog signal, especially to extend the quantized output signal in the associated time domain. This enables multiple feedback processing of the same quantized output signal and real-time feedback back to the loop filter module. Compared with the quantized output signal, the first feedback circuit can obtain a more accurate extension processing result while reducing the conversion time.

[0022] This invention also connects a second feedback circuit between the loop filter module and the quantizer. The second feedback circuit is a compensation feedback path that constitutes the first feedback circuit, overcoming the change introduced by the first feedback circuit to the original transfer function. This causes the transfer function of the Sigma-Delta analog-to-digital converter to change from the original transfer function to the first loop filter function. The second feedback circuit processes the quantized output signal from the quantizer in a time-delayed manner. In fact, it uses the second loop filter function, which is composed of the cascaded second feedback circuit, the loop filter module, and the quantizer, to process the input analog signal. In particular, it performs time delay processing on the quantized output signal in the associated time domain, performs multiple feedback processing on the same quantized output signal, and promptly feeds it back to the loop filter module to compensate for the change of the original transfer function by the first loop filter function in real time. This allows the transfer function of the Sigma-Delta analog-to-digital converter to adjust back to the original transfer function, and allows the accuracy of the digital signal converted by the Sigma-Delta analog-to-digital converter to converge quickly, achieving the balance between component matching indicators and accuracy required for the feedback DAC.

[0023] In summary, this invention improves the device matching effect of the feedback ADC in the first and second feedback circuits, reduces the complexity of the DAC, and further lowers the matching requirements; it also improves the linear output of the feedback DAC, thereby improving the linearity of the entire ADC system. If this invention uses a higher-order Sigma-Delta analog-to-digital converter, it reduces the problems of increased device load and signal processing complexity. Furthermore, the cascaded combination of a one-bit quantizer and a one-bit DAC can achieve the effect of a multi-bit DAC through time-delay, ensuring the accuracy of the final quantization. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the framework of a Sigma-Delta analog-to-digital converter disclosed in an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the framework of a third-order Sigma-Delta analog-to-digital converter disclosed in another embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of an implementation structure shared by the first filter or the second filter disclosed in another embodiment of the present invention. Detailed Implementation

[0027] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Some portions and features of some embodiments may be included in or replace portions and features of other embodiments. The scope of embodiments of the invention includes the entire scope of the claims and all available equivalents thereof. In this document, these embodiments of the invention may be referred to individually or collectively with the term "invention," which is merely for convenience and is not intended to automatically limit the scope of the application to any single invention or inventive concept if more than one invention is disclosed.

[0028] As one embodiment, this invention discloses a Sigma-Delta analog-to-digital converter (ADC), which includes a loop filter module, a first feedback circuit, and a quantizer. The loop filter module includes a summing node and an integrator. The integrators are cascaded within the loop filter module, with the input of each integrator stage connected to a corresponding summing node, forming a one-to-one correspondence between each integrator stage and a unique summing node. Each summing node corresponds to an integrator of the same stage. Figure 1 The "+" sign enclosed in a circle; for example, a loop filter module includes at least two stages of summing nodes and at least two stages of integrators, specifically... Figure 1The diagram shows a first-stage integrator, a second-stage integrator, a third-stage integrator, ..., a (N-1)th-stage integrator, and an Nth-stage integrator (i.e., the last stage integrator). Correspondingly, the input of the first-stage integrator is connected to the first-stage summing node, the input of the second-stage integrator is connected to the second-stage summing node, the input of the third-stage integrator is connected to the third-stage summing node, ..., the input of the (N-1)th-stage integrator is connected to the (N-1)th-stage summing node, and the input of the Nth-stage integrator is connected to the Nth-stage summing node. A first feedback circuit is connected between the input of the summing node corresponding to the first-stage integrator and the output of the quantizer, forming a feedback loop. It should be noted that in this embodiment, a feedback path must be ensured between the input of the summing node corresponding to the first-stage integrator and the output of the quantizer. For the remaining stages of integrators and the output of the quantizer, a feedback path may not be designed, or a feedback path may be designed between the corresponding first-stage integrator and the quantizer according to the actual signal processing requirements. The first feedback circuit is used to perform a first time-delay processing on the quantized output signal output by the quantizer and convert it into a first feedback signal. This first feedback signal is then transmitted to the input of the summing node corresponding to the first-stage integrator. Specifically, the first feedback circuit extends the quantized output signal in the discrete-time domain, which is mathematically equivalent to processing the quantized output signal according to the relevant Z-function. This is essentially a delay processing. Each time the first feedback circuit performs a first time-delay processing, it performs multiple delay processing operations. The first feedback circuit converts the digital signal generated by each delay processing into an analog signal in real time, i.e., the first feedback signal. Whenever the first feedback signal is input to the summing node corresponding to the first-stage integrator (i.e., the first-stage summing node), it is determined that the Sigma-Delta analog-to-digital converter has completed one feedback processing operation, which is a feedback processing operation on the input analog signal. At this time, the first feedback circuit continues to perform the first time-delay processing on the quantized output signal. Specifically, when the quantization bit count of the quantizer is 1, whenever a delay processing operation is performed on a 1-bit quantized output signal, the first feedback circuit feeds back an analog signal to the first-stage summing node.

[0029] It should be noted that the signal input to the loop filter module is an analog signal. After processing by the cascaded integrator and the feedback processing of the first feedback circuit, it is equivalent to filtering the analog signal at each summing node of the input. Furthermore, the quantizer quantizes the output signal of the loop filter module, outputting a bit stream with a value of +1 or -1, corresponding to a high or low level, converting it into a digital code stream represented using "1 / 0". Therefore, the quantized output signal is a digital signal. Quantizers can be divided into one-bit quantizers and multi-bit quantizers. Using a multi-bit quantizer can increase the signal-to-noise ratio, making the Sigma-Delta analog-to-digital converter easier to stabilize, generating fewer harmonic components, and ensuring sufficient accuracy of the first feedback circuit to guarantee the accuracy of the final fed-out analog signal. Using a one-bit quantizer, because only one bit of digital signal is input to the first feedback circuit, there is no nonlinearity problem.

[0030] Compared with existing technologies, this invention connects a first feedback circuit between the loop filter module and the quantizer. The first feedback circuit processes the quantized output signal from the quantizer in a time-extended manner. In fact, it utilizes a first loop filter function composed of the cascaded first feedback circuit, the loop filter module, and the quantizer to process the input analog signal, especially extending the quantized output signal in the associated time domain. This enables multiple feedback processing of the same quantized output signal and real-time feedback back to the loop filter module, reducing the design complexity of the DAC in the first feedback circuit. Moreover, compared with the quantized output signal, the first feedback circuit can obtain a more accurate extended processing result while reducing the conversion time.

[0031] As one embodiment, the Sigma-Delta analog-to-digital converter further includes a second feedback circuit. The second feedback circuit is connected between the summing node corresponding to the last integrator and the output of the quantizer. The second feedback circuit is used to perform a second time-delay processing on the quantized output signal output by the quantizer and convert it into a second feedback signal. The second feedback signal is then transmitted to the summing node corresponding to the last integrator (i.e., the last-stage summing node). Specifically, the second feedback circuit extends the quantized output signal output by the quantizer in the discrete-time domain. Mathematically, this is equivalent to processing the quantized output signal according to the relevant Z function, which is actually a kind of delay processing to cancel the noise signal newly introduced by the first feedback circuit. Each time the second feedback circuit performs the first time-delay processing, it performs multiple delay processing. The second feedback circuit converts the digital signal generated by each delay processing into an analog signal in real time, i.e., the second feedback signal. The node of the second feedback signal fed back to the loop filter module is different from the node of the first feedback signal. Whenever the second feedback signal is input to the summing node corresponding to the last integrator (i.e., the last summing node), it is determined that the Sigma-Delta analog-to-digital converter has completed one feedback processing, which is a feedback processing of the input analog signal. At this time, the second feedback circuit continues to perform a second time-delay processing on the quantized output signal. The second time-delay processing performed by the second feedback circuit is used to compensate for the first time-delay processing performed by the first feedback circuit. Optionally, the second time-delay processing will cancel the delay effect introduced by the first time-delay processing, and will also cancel the same type of parameters generated by the first time-delay processing from the dimensions of filter coefficients and / or amplitude values ​​at the corresponding time nodes, so that the delay state of the transfer function of the Sigma-Delta analog-to-digital converter is dynamically adjusted back to the original transfer function. Specifically, when the number of quantization bits of the quantizer is 1, the second feedback circuit feeds back an analog signal to the last summing node whenever it performs a delay processing on a 1-bit quantized output signal. This reduces the design complexity of the DAC in the second feedback circuit. The second feedback circuit can assist the first feedback circuit in obtaining more accurate extended processing results while reducing conversion time. Consequently, the accuracy of the digital signal converted by the Sigma-Delta analog-to-digital converter converges faster, improving the linearity of the analog signals output by the second and first feedback circuits. It also achieves a balance between the component matching indicators and accuracy required for the feedback DAC.

[0032] Based on the above embodiments, the quantizer, the first feedback circuit, and the loop filter module are cascaded to form a feedback loop and constitute a first loop filter function. The first feedback circuit processes the input analog signal according to the first loop filter function, so that the original transfer function is changed by the first feedback circuit. That is, the original transfer function is changed by the device introduced by the first feedback circuit. The first loop filter function is regarded as the ratio of the analog signal output by the output terminal of the loop filter module to the external analog signal input to the Sigma-Delta analog-to-digital converter in the z-domain. Specifically, within the feedback loop, the transfer function of the Sigma-Delta analog-to-digital converter is changed from the original transfer function to the first loop filter function.

[0033] Therefore, by introducing the second feedback circuit at different points in the feedback loop into the Sigma-Delta analog-to-digital converter (ADC), the quantizer, the second feedback circuit, and the loop filter module are cascaded to form a compensation loop and constitute a second loop filter function. The second feedback circuit processes the input analog signal according to the second loop filter function. The second loop filter function is considered to be the ratio in the z-domain between the analog signal output from the loop filter module and the external analog signal input to the Sigma-Delta ADC, without the first feedback circuit. The Sigma-Delta ADC controls the second loop filter function to compensate the first loop filter function, restoring the transfer function of the Sigma-Delta ADC from the first loop filter function back to the original transfer function. It should be noted that the original transfer function is the initial design transfer function of the Sigma-Delta ADC, and also the transfer function formed when no filter structure is introduced in the feedback loop of the Sigma-Delta ADC. It can be considered as the original transfer function possessed by the loop filter module. Ensure the accuracy of the digital signal output by the quantizer of the Sigma-Delta analog-to-digital converter.

[0034] In summary, this invention connects a second feedback circuit between the loop filter module and the quantizer. This second feedback circuit forms a compensation feedback path for the first feedback circuit, overcoming the change introduced by the first feedback circuit to the original transfer function. This causes the transfer function of the Sigma-Delta analog-to-digital converter to change from the original transfer function to the first loop filter function. The second feedback circuit processes the quantized output signal from the quantizer in a time-delayed manner. In effect, it utilizes the second loop filter function, composed of the cascaded second feedback circuit, the loop filter module, and the quantizer, to process the input analog signal. Specifically, it delays the quantized output signal within the associated time domain, performing multiple feedback processes on the same quantized output signal and promptly feeding it back to the loop filter module. This compensates in real-time for the change in the original transfer function caused by the first loop filter function, allowing the Sigma-Delta analog-to-digital converter's transfer function to adjust back to the original transfer function. This also allows the accuracy of the digital signal converted by the Sigma-Delta analog-to-digital converter to converge quickly, achieving the balance between component matching and accuracy required for a feedback DAC.

[0035] As one embodiment, the first feedback circuit includes a first feedback DAC and a first filter; such as Figure 1 As shown, the input of the first filter is connected to the output of the quantizer, the input of the first feedback DAC is connected to the output of the first filter, and the output of the first feedback DAC is connected to the input of the summing node corresponding to the first-stage integrator. That is, the output of the first feedback DAC is connected to the input of the first-stage summing node. Figure 1The leftmost circled "+" input terminal is connected; the line segment connecting the output terminal of the first feedback DAC to the input terminal of the first stage summing node is marked with "-", indicating that the output terminal of the first feedback DAC transmits a signal that acts as negative feedback; the first filter is used to perform a delay processing on the quantized output signal output by the quantizer for a number of times equal to a first preset number of taps, wherein the delay processing performed by the first filter for a number of times equal to the first preset number of taps is the first time extension processing, so that the accuracy of the quantized output signal filtered by the first filter is higher than that of the quantized output signal; the accuracy of the quantized output signal filtered by the first filter is close to the accuracy of the level adjustment of the first preset number of taps level, the level adjustment of the first preset number of taps level is specifically performed by the first filter, and the first preset number of taps is the number of taps of the first filter. The first feedback DAC is used to convert the quantized output signal filtered by the first filter into a first feedback signal in real time, and then transmit the first feedback signal to the input of the summing node corresponding to the first-stage integrator. During the delay process under the first time extension processing of the first filter, the first feedback DAC converts the quantized output signal filtered by the first filter into a first feedback signal in real time, and then transmits the newly converted first feedback signal to the first-stage summing node. It should be noted that the first filter internally has first filter coefficients, and correspondingly, the first filter introduces a first filter transfer function in the first feedback circuit. In this embodiment, the first filter coefficients are parameters belonging to the first filter transfer function. The first filter transfer function is configured to perform a delay processing on the quantized output signal output by the quantizer for a number of times equal to a first preset number of taps. That is, the digital code stream output by the quantizer is filtered according to the first filter transfer function to achieve time extension of the quantized output signal before it is handed over to the first feedback DAC for digital-to-analog conversion. Even if a one-bit quantizer is used, the first time extension processing of the first feedback circuit can achieve the effect of synchronous DAC conversion of multi-bit digital signals, reducing the complexity of the data converted by the first feedback DAC and also reducing the matching index and accuracy requirements of the first feedback DAC.

[0036] Optionally, except for the summation node corresponding to the first integrator, the input terminal of the summation node corresponding to each integrator stage is connected to the output terminal of the first feedback DAC. Therefore, in the Sigma-Delta analog-to-digital converter, the input terminal of each summation node is connected to the output terminal of the first feedback DAC. The first feedback DAC is used to transmit the first feedback signal obtained from the latest conversion to each summation node, so as to introduce the time-stretched analog signal into each integrator stage, comprehensively enhance the overall delay effect of the loop filter module, and improve the accuracy of the signal processing of the Sigma-Delta analog-to-digital converter, specifically improving the accuracy of the digital-to-analog conversion of the first feedback circuit and the analog-to-digital conversion of the quantizer.

[0037] As one embodiment, the second feedback circuit includes a second feedback DAC and a second filter; the number of taps in the second filter is equal to a second preset number of taps; such as Figure 1 As shown, the input of the second filter is connected to the output of the quantizer, the input of the second feedback DAC is connected to the output of the second filter, and the output of the second feedback DAC is connected to the input of the summing node corresponding to the last stage integrator. That is, the output of the second feedback DAC is connected to the input of the summing node of the last stage. Figure 1 The rightmost circled "+" input is connected; the line segment connecting the output of the second feedback DAC to the input of the last stage summing node is marked with "-", indicating that the output of the second feedback DAC transmits a signal that acts as negative feedback; the second filter is used to delay the quantized output signal of the quantizer by a number of times equal to the second preset number of taps. The delay processing performed by the second filter by the second preset number of taps is the second time stretching process, which compensates for the second filter and makes the accuracy of the quantized output signal filtered by the second filter higher than that of the quantized output signal; the accuracy of the quantized output signal filtered by the second filter is close to the accuracy of the level adjustment of the second preset number of taps level. The level adjustment of the second preset number of taps level is specifically performed by the second filter, and the second preset number of taps is the number of taps of the second filter. The second feedback DAC is used to convert the quantized output signal filtered by the second filter into a second feedback signal, and then transmit the second feedback signal to the input of the summing node corresponding to the last stage integrator. During the delay process of the second filter performing the second time extension processing, the second feedback DAC converts the quantized output signal filtered by the second filter into a second feedback signal in real time, and then transmits the newly converted second feedback signal to the last stage summing node.

[0038] It should be noted that the second filter internally has second filter coefficients, and correspondingly, the second filter introduces a second filter transfer function into the second feedback circuit. In this embodiment, the second filter coefficients are parameters belonging to the second filter transfer function. The second filter transfer function is configured to perform a delay processing on the quantized output signal output by the quantizer for a number of times equal to a second preset number of taps. That is, the digital code stream output by the quantizer is filtered according to the second filter transfer function to achieve time extension of the quantized output signal. Then, after being converted and output to the loop filter module by the second feedback DAC, the quantized output signal is extended into an analog signal with a delay compensation effect, thereby offsetting the effect of the first time extension processing performed by the first feedback circuit on the change of the original transfer function. Specifically, the first filter transfer function is the transfer function introduced by the loop filter module, such that the quantizer, the first feedback circuit, and the loop filter module are cascaded to form the first loop filter function, that is, the transfer function of the Sigma-Delta analog-to-digital converter is transformed into the first loop filter function; the second filter transfer function is the transfer function introduced by the loop filter module, such that the quantizer, the second feedback circuit, and the loop filter module are cascaded to form the second loop filter function, that is, the transfer function of the Sigma-Delta analog-to-digital converter is transformed into the second loop filter function; then, the effects of the second filter transfer function introduced by the loop filter module and the first filter transfer function introduced by the loop filter module cancel each other out, thereby canceling the effect of the first time extension processing performed by the first feedback circuit on the change of the original transfer function.

[0039] Meanwhile, even using a single-bit quantizer, the Sigma-Delta analog-to-digital converter can achieve synchronous DAC conversion of multi-bit digital signals through the second time-delay processing of the second feedback circuit. This reduces the complexity of the data converted by the second feedback DAC and lowers the matching index and accuracy requirements of the second feedback DAC. The second filter transfer function can more completely compensate for the first filter transfer function introduced by the first filter, canceling the noise effect introduced by the first filter, and thus adjusting the transfer function of the Sigma-Delta analog-to-digital converter to the original transfer function. In this way, through the complementary effect of the two feedback circuits, a better device matching effect for each feedback DAC can be achieved through delay, improving the linear output of the feedback DAC and thus improving the linearity of the Sigma-Delta analog-to-digital converter.

[0040] Based on the above embodiments, the first filter coefficients and the second filter coefficients cooperate to ensure that the signal changes induced by the first filter transfer function in the Sigma-Delta analog-to-digital converter (ADC) and the signals induced by the second filter transfer function in the Sigma-Delta ADC cancel each other out, thereby controlling the delay state of the Sigma-Delta ADC's transfer function to remain the same as the delay state of the original transfer function. Specifically, the filter coefficients set inside the first filter and the filter coefficients set inside the second filter are not completely identical. The number of filter coefficients set inside the first filter and the number of filter coefficients set inside the second filter are both equal to the preset number of taps, that is, the first preset number of taps equals the second preset number of taps. The implementation structures of the first filter and the second filter belong to the same preset filter structure, but the filter coefficients are not completely identical. This filter structure can be a direct implementation of a finite impulse response (FIR) filter, making the expressions of the first filter transfer function and the second filter transfer function consistent in form, only the filter coefficients are different. Therefore, the second filter transfer function can cancel out the signal influence introduced by the first filter transfer function in the loop filtering module from the perspective of the filter coefficients, accelerating the convergence speed of the conversion accuracy of the Sigma-Delta ADC.

[0041] In some embodiments, the expression for the first filter transfer function is: In the first filter transfer function, each filter coefficient is one-twelfth; correspondingly, the expression for the second filter transfer function is Fc(z) = 0.9 + 0.3z. -1 +0.3z -2 +0.3z -3 +0.3z -4 +0.2z -5 +0.2z -6 +0.2z -7 +0.2z -8 +0.12z -9 +0.08z -10 +0.03z -11 The filter coefficients in the second filter transfer function are arranged from low to high according to the power of the denominator polynomial, namely 0.9, 0.3, 0.3, 0.3, 0.3, 0.2, 0.2, 0.2, 0.2, 0.12, 0.08 and 0.03.

[0042] In the first filter transfer function, the highest power of the denominator polynomial represents the order of the first filter, and the highest power of the denominator polynomial in the second filter transfer function represents the order of the second filter.

[0043] As one embodiment, the preset filter structure includes m delay units, a coefficient matching module, and an accumulator, where m is equal to the number of taps of the first filter or the number of taps of the second filter. It is understood that when the number of taps of the first filter is not equal to the number of taps of the second filter, the number of delay units used by the first filter is not equal to the number of delay units used by the second filter. Figure 3 The embodiment shown uses m to represent the number of taps in the first filter or the number of taps in the second filter. For example, m can be divided into m1 and m2, where m1 represents the number of taps in the first filter and m2 represents the number of taps in the second filter.

[0044] like Figure 3 As shown, m delay units are connected in series to generate m digital input signals representing different delays. These m digital input signals serve as either the input signal to the first filter or the input signal to the second filter, forming one path of the digital differential signal; where m is a positive integer; the input terminal of the first filter or the input terminal of the second filter is... Figure 3 The input terminal of the leftmost delay unit shown is denoted as the input terminal of the first-stage delay unit. Optionally, the input terminal of the first-stage delay unit is also connected to a modulator. The input terminal of the first-stage delay unit receives the quantized output signal through the modulator. The quantized output signal output by the modulator is input to the modulator, preferably a Sigma-Delta structure, which outputs a digital code stream to the first-stage delay unit. When the modulator outputs a 1-bit digital code stream, the 1-bit digital code stream is buffered by m cascaded delay units to output an m-bit digital code stream. The m-bit digital code stream represents 1-bit digital signals with different delays, such as... Figure 3 As shown, from left to right, the m 1-bit digital signals are D0, D1, D2, ..., Dm-1. These m signals are buffered in their corresponding registers. Except for the first 1-bit digital signal D0, the inputs of the remaining m-1 registers are connected to the outputs of their corresponding delay units. These m delay units can be delay units connected in series within an m-bit serial shift register. The coefficient matching module provides a matching filter coefficient for each digital input signal, multiplies each digital input signal by its matching filter coefficient, and outputs the corresponding product. The accumulator adds each product output by the coefficient matching module to obtain the filtered quantized output signal, which is a digital differential output signal. Therefore, this embodiment can improve the linearity of the digital-to-analog conversion signal and reduce the complexity of the filter circuit implementation.

[0045] In some embodiments, the coefficient matching module is equivalent to... Figure 3The filter coefficients a(0), a(1), a(2), ..., a(m-1) shown are multiplied by m unit current sources, and the multiplication results are then input into the accumulator for summation. Both the first and second filter implementations are preferably direct implementations of finite impulse response (FIR) filters. The FIR filter mainly consists of a current source array, a coefficient matching module, and an accumulator. The filter coefficients need to be determined based on the required filtering characteristics. The filter coefficients are implemented using current sources; alternatively, the current source array can be directly connected to a node to perform the current summation function. Specifically, in the current source array, the length of the transistor is represented by L, and the width is represented by W. The magnitude of the current is determined by W / L. Changing the length or the width can change the magnitude of the current. For example, if the size of the transistor in a unit current source is 4 / 4, then a transistor size of 4 / 1 or 16 / 4 can both obtain a current of 4 times the size of the unit current source. Therefore, in one embodiment of the present invention, different coefficients can be achieved by changing the length and width of the transistor. Compared with the conventional method of only changing the width of the transistor to achieve different coefficients, the scale of the current source array is reduced.

[0046] As one example, combined with Figure 1 It is understood that the loop filtering module includes N-stage summing nodes, N-stage integrators, and a final operational amplifier. The output of the final integrator is connected to the input of the final operational amplifier, and the output of the final operational amplifier is connected to the input of the quantizer. The output of the final operational amplifier is used to output a pre-feedback analog signal, which serves as the analog signal output by the loop filtering module. The pre-feedback analog signal is the result of integrating the externally input analog signal to the loop filtering module using the N-stage integrators, and then time-extending it using the first and second feedback circuits. Each summing node has a first input, a second input, and an output.

[0047] In this embodiment, the first input terminal of the i-th stage summing node is connected to the output terminal of the (i-1)-th stage integrator. Preferably, the first input terminal of the i-th stage summing node can be connected to the output terminal of the (i-1)-th stage integrator through a buffer or operational amplifier to convert the current signal into a voltage signal. The first input terminal of the i-th stage summing node is used to receive the (i-1)-th stage integrated analog signal output by the (i-1)-th stage integrator, wherein the (i-1)-th stage integrator is used to integrate the output signal of the (i-1)-th stage summing node to obtain the (i-1)-th stage integrated analog signal. The second input of the i-th stage summing node is connected to the output of the final operational amplifier. This second input receives the pre-feedback analog signal from the final operational amplifier. The output of the i-th stage summing node is connected to the input of the i-th stage integrator. This output outputs the i-th stage summing analog signal to the input of the i-th stage integrator. The i-th stage summing analog signal is the sum of the (i-1)-th stage integrated analog signal and the pre-feedback analog signal from the final operational amplifier. This makes the pre-feedback analog signal the analog feedback signal for each integrator stage except the first and last stages, which helps overcome the offset problem within the integrator and ensures signal linearity. The i-th stage integrator integrates the i-th stage summing analog signal and outputs the i-th stage integrated analog signal. Here, N is a positive integer; i is an integer greater than 1 and less than or equal to N-1. Correspondingly, when i equals 2, the (i-1)-th stage integrator is... Figure 1 The first-stage integrator shown is the i-th-stage integrator. Figure 1 The second-stage integrator is shown; when i equals 3, the i-th-stage integrator is Figure 1 The third-stage integrator is shown. In summary, the analog signal output by the loop filter module can be used in the feedback loop, and it also ensures the accuracy of the digital signal quantized by the quantizer.

[0048] It should be noted that the number of integrators in the Sigma-Delta analog-to-digital converter determines the order of the Sigma-Delta converter. Generally, a higher order results in better amplitude-frequency characteristics, more severe attenuation in the low-frequency band, better high-frequency throughput, and a larger effective number of bits. However, the delay will also be significant, reducing the swing of the input signal. In addition, excessive noise amplitude at high frequencies can reduce the stability of the entire system. Therefore, the value of N must be set to consider the amplitude of the analog signal that needs to be converted into a digital signal in the loop filter module, in order to meet the matching and accuracy requirements of the DACs in the first and second feedback circuits.

[0049] like Figure 1As shown, the first input terminal of the first-stage summing node is used to receive an analog input signal, which can be one path of the analog differential signal output by the first feedback circuit. Preferably, the first input terminal of the first-stage summing node is connected to an operational amplifier, so that the first-stage summing node receives the analog input signal from outside the Sigma-Delta analog-to-digital converter through the operational amplifier, thereby improving the driving capability of the analog signal. The second input terminal of the first-stage summing node is used to receive the first feedback signal output by the first feedback circuit; the output terminal of the first-stage summing node is used to output the first-stage summing analog signal to the first-stage integrator; wherein, the first-stage summing node is used to sum the analog signal and the first feedback signal provided by the first feedback circuit, and configure the sum value as the first-stage summing analog signal; preferably, the first-stage summing node can be implemented using an adder. The first-stage integrator is used to receive the integration of the first-stage summing analog signal to obtain the first-stage integrated analog signal. In this embodiment, the series structure composed of the first-stage summing node and the first-stage integrator provides a channel for the first feedback signal to enter the loop filtering module.

[0050] like Figure 1 As shown, the first input terminal of the Nth-stage summing node is connected to the output terminal of the (N-1)th-stage integrator. Preferably, the first input terminal of the Nth-stage summing node is connected to an operational amplifier, so that the Nth-stage summing node receives the analog signal output by the (N-1)th-stage integrator through the operational amplifier to improve the driving capability of the analog signal. Specifically, the first input terminal of the Nth-stage summing node is used to receive the N-1th-stage integrated analog signal output by the (N-1)th-stage integrator. The second input terminal of the Nth-stage summing node is connected to the output terminal of the second feedback circuit, and the second input terminal of the Nth-stage summing node is used to receive the second feedback signal output by the second feedback circuit, thereby providing a channel for the second feedback signal to enter the loop filtering module.

[0051] exist Figure 1 In the above, the Nth-level summation node, in addition to having the first and second input terminals, also has N-1 preset input terminals. The Nth-level summation node is... Figure 1The rightmost circled "+" sign; in the first to N-1th level summing nodes, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the Nth level summing node; the output terminal of the Nth level summing node is used to output the Nth level summing analog signal to the Nth level integrator, wherein the Nth level summing node is used to sum the N-1th level integrated analog signal, the second feedback signal, and the signal input to each preset input terminal, and configure the sum value as the Nth level summing analog signal; the Nth level integrator is used to receive and integrate the Nth level summing analog signal to obtain the Nth level integrated analog signal. This samples a relatively stable analog signal for the quantizer. In summary, the Nth level integrator in the Sigma-Delta analog-to-digital converter has lower performance requirements for the operational amplifier and can achieve a higher sampling rate.

[0052] Optionally, the number of feedback DACs in the first feedback circuit corresponds to the number of operational amplifiers in the loop filter module, and the input terminal of each feedback DAC in the first feedback circuit is connected to the output terminal of the quantizer. The output terminal of each feedback DAC in the first feedback circuit is connected to the input terminal of the corresponding operational amplifier in the loop filter module (specifically, the input terminal of the operational amplifier set inside the integrator), or the output terminal of each feedback DAC in the first feedback circuit is connected to the input terminal of the corresponding first-stage summing node. This improves the conversion accuracy of the Sigma-Delta analog-to-digital converter.

[0053] In the foregoing embodiments, each integrator stage is a continuous-time structure used to integrate the input signal. Therefore, the Sigma-Delta analog-to-digital converter (ADC) is configured as a continuous-time Sigma-Delta ADC. Compared to traditional discrete Sigma-Delta ADCs, the continuous-time Sigma-Delta ADC disclosed in this embodiment has a built-in loop filter module. This loop filter module has lower performance requirements for its built-in operational amplifier, allowing for a higher sampling rate, and lower sensitivity requirements for its internal capacitors. It should be noted that a continuous-time Sigma-Delta ADC refers to a ADC where sampling occurs after the integrator, where the integrator consists of an operational amplifier, resistors, and capacitors, unlike a discrete Sigma-Delta ADC where the integrator consists of switches, capacitors, and operational amplifiers.

[0054] In the foregoing embodiments, the Sigma-Delta analog-to-digital converter is a differential circuit, supporting differential input and differential output. Each integrator stage includes branch resistors and pre-configured operational amplifiers. The output of the branch resistor is connected to the input of the pre-configured operational amplifier. The input of the branch resistor is configured as the input of the corresponding first-stage summation node, and the output of the branch resistor is configured as the output of the corresponding first-stage summation node. In this embodiment, the input of the pre-configured operational amplifier is the input of its respective integrator. The first input of each summation node is the input of one branch resistor within the corresponding first-stage integrator, and the second input of each summation node is the input of another branch resistor within the corresponding first-stage integrator. The stage number of the corresponding first-stage integrator in the loop filter module is equal to the stage number of the summation node in the same loop filter module. Furthermore, each preset input of the last summation node is the input of the corresponding branch resistor within the last stage integrator. Therefore, the more inputs of the pre-configured operational amplifiers, the more input branches are provided for summation. This minimizes the nonlinearity introduced by the mismatch of the current source inside the loop filter module.

[0055] Each integrator stage also includes an integrating capacitor, and the aforementioned branch resistor can be an integrating resistor. The pre-configured operational amplifier is an operational amplifier used for integration, and the integrating capacitor is connected in parallel with the pre-configured operational amplifier. The integrating capacitor is connected between the input terminal and the output terminal of the pre-configured operational amplifier. The proportional accuracy of the integrating capacitor can be well controlled, thereby effectively compensating for the noise signal introduced by the feedback loop and the signal changes caused by the related transfer function.

[0056] Specifically, the branch resistance can be divided into a first preset resistor and a second preset resistor. The input terminal of the first preset resistor in the first-stage integrator is configured as the first input terminal of the first-stage summing node. The output terminal of the first preset resistor in the first-stage integrator is connected to the input terminal of a pre-configured operational amplifier in the first-stage integrator. The input terminal of the second preset resistor in the first-stage integrator is configured as the second input terminal of the first-stage summing node. The output terminal of the second preset resistor in the first-stage integrator is connected to the input terminal of a pre-configured operational amplifier in the first-stage integrator. Both the output terminals of the first and second preset resistors in the first-stage integrator are connected to the same input terminal of the pre-configured operational amplifier in the first-stage integrator, including the positive input terminal of the operational amplifier. Or a negative input terminal; similarly, the input terminal of the first preset resistor in the last stage integrator is configured as the first input terminal of the last stage summing node, the output terminal of the first preset resistor in the last stage integrator is connected to the input terminal of the pre-configured operational amplifier in the last stage integrator, the input terminal of the second preset resistor in the last stage integrator is configured as the second input terminal of the last stage summing node, and the output terminal of the second preset resistor in the last stage integrator is connected to the input terminal of the pre-configured operational amplifier in the last stage integrator, wherein the output terminals of the first preset resistor and the second preset resistor in the last stage integrator are both input terminals with the same electrode attribute as the pre-configured operational amplifier in the last stage integrator, including the positive or negative input terminal of the operational amplifier.

[0057] In summary, for each stage of the summing node of each analog signal in the input analog differential signal, each input terminal of each stage of the summing node is connected to a branch resistor. The input terminal of the branch resistor is configured as an input terminal of the summing node, and the output terminal of the branch resistor is connected to the same input terminal of the pre-configured operational amplifier. The output terminal of the branch resistor is configured as the output terminal of the summing node.

[0058] As one embodiment, when N is 3, a third-order Sigma-Delta analog-to-digital converter is formed. The first feedback circuit includes a first feedback DAC and a first filter connected in series. The second feedback circuit includes a second feedback DAC and a second filter connected in series. The signal flow and effect of the first and second feedback circuits in the Sigma-Delta analog-to-digital converter are as described in the previous embodiment and will not be repeated here. Figure 2As shown, the loop filter module includes a three-stage summing node, a three-stage integrator, and an operational amplifier. The output of the third-stage integrator is connected to the input of the operational amplifier, and the output of the operational amplifier is connected to the input of the quantizer. The output of the operational amplifier is used to output a pre-feedback analog signal, which serves as the analog signal output by the loop filter module. The pre-feedback analog signal is the result of integrating the externally input analog signal to the loop filter module using the three-stage integrator, followed by time-delay processing by the first and second feedback circuits. It should be noted that each summing node (circled "+") has a first input, a second input, and an output.

[0059] In this embodiment, the first input terminal of the second-stage summing node is connected to the output terminal of the first-stage integrator. Preferably, the first input terminal of the second-stage summing node can be connected to the output terminal of the first-stage integrator through a buffer or operational amplifier to convert the current signal into a voltage signal. The first input terminal of the second-stage summing node is used to receive the first-stage integrated analog signal output by the first-stage integrator, wherein the first-stage integrator is used to integrate the output signal of the first-stage summing node to obtain the first-stage integrated analog signal. The second input terminal of the second-stage summing node is connected to... Figure 2 The output of the operational amplifier shown is connected, and the second input of the second-stage summing node is used to receive... Figure 2 The operational amplifier output shown is a pre-feedback analog signal; the output of the second-stage summing node is connected to the input of the second-stage integrator. The output of the second-stage summing node is used to output the second-stage summing analog signal to the input of the second-stage integrator. The second-stage summing analog signal is the sum of the first-stage integration analog signal and the input of the second-stage integrator. Figure 2 The sum of the pre-feedback analog signals output by the operational amplifier shown; the second-stage integrator is used to integrate the second-stage summed analog signal and then output the second-stage integrated analog signal.

[0060] like Figure 2As shown, the first input terminal of the first-stage summing node is used to receive an analog input signal, which can be one path of the analog differential signal output by the first feedback circuit. Preferably, the first input terminal of the first-stage summing node is connected to an operational amplifier, so that the first-stage summing node receives the analog input signal from outside the Sigma-Delta analog-to-digital converter through the operational amplifier, thereby improving the driving capability of the analog signal. The second input terminal of the first-stage summing node is used to receive the first feedback signal output by the first feedback circuit; the output terminal of the first-stage summing node is used to output the first-stage summing analog signal to the first-stage integrator; wherein, the first-stage summing node is used to sum the analog signal and the first feedback signal provided by the first feedback circuit, and configure the sum value as the first-stage summing analog signal; preferably, the first-stage summing node can be implemented using an adder. The first-stage integrator is used to receive the integration of the first-stage summing analog signal to obtain the first-stage integrated analog signal. In this embodiment, the series structure composed of the first-stage summing node and the first-stage integrator provides a channel for the first feedback signal to enter the loop filtering module.

[0061] like Figure 2 As shown, the first input terminal of the third-stage summing node is connected to the output terminal of the second-stage integrator. Preferably, the first input terminal of the second-stage summing node is connected to... Figure 2 The operational amplifier shown has a third-stage summing node that... Figure 2 The operational amplifier shown receives the analog signal output from the second-stage integrator to improve its driving capability for analog signals. Specifically, the first input of the third-stage summing node receives the second-stage integrated analog signal output from the second-stage integrator; the second input of the third-stage summing node is connected to the output of the second feedback circuit, and the second input of the third-stage summing node receives the second feedback signal output from the second feedback circuit, thereby providing a channel for the second feedback signal to enter the loop filter module. Figure 2 In the process, the third-level summation node, in addition to having the first and second input terminals, also has two preset input terminals. The third-level summation node is... Figure 2The rightmost circled "+" sign; in the first to second stage summing nodes, the signal input to the first input terminal of each stage summing node is also configured to be input to the corresponding preset input terminal in the third stage summing node; the output terminal of the third stage summing node is used to output the third stage summing analog signal to the third stage integrator, wherein the third stage summing node is used to sum the second stage integral analog signal, the second feedback signal, and the signal input to each preset input terminal, and configure the sum value as the third stage summing analog signal; the third stage integrator is used to receive the integration of the third stage summing analog signal to obtain the third stage integral analog signal. This allows the quantizer to sample a relatively stable analog signal. In summary, the three-stage integrator in the Sigma-Delta analog-to-digital converter has lower performance requirements for the operational amplifier and can achieve a higher sampling rate.

[0062] Preferably, the quantizer has a quantization bit count of 1. The quantizer is used to quantize the signal output by the loop filter module into a 1-bit digital signal, reducing the device load, reducing the complexity of signal processing, and reducing the nonlinearity of the feedback DAC. Both the first feedback circuit and the second feedback circuit are used to convert the 1-bit digital signal output by the quantizer into an analog signal for feedback.

[0063] In summary, the analog signal output by the loop filtering module is usable in the feedback loop and ensures the accuracy of the digital signal quantized by the quantizer, thereby achieving high-precision output while reducing the conversion time of the Sigma-Delta analog-to-digital converter. In this embodiment, the 1-bit quantizer features high linearity, low complexity, and low precision. Therefore, this invention improves the device matching effect of the feedback ADC in the first and second feedback circuits, reduces the complexity of the DAC, and further lowers the matching requirements; it also improves the linear output of the feedback DAC, thereby improving the linearity of the entire ADC system.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A Sigma-Delta analog-to-digital converter, characterized in that, The Sigma-Delta analog-to-digital converter includes a loop filter module, a first feedback circuit, and a quantizer; The loop filtering module includes summing nodes and integrators; the integrators exist in the loop filtering module in a cascaded manner, with the input of each integrator connected to the corresponding summing node, so that one integrator corresponds to one summing node. The first feedback circuit is connected between the input terminal of the summing node corresponding to the first-stage integrator and the output terminal of the quantizer. The first feedback circuit is used to perform first time extension processing on the quantized output signal output by the quantizer and convert it into a first feedback signal, and then transmit the first feedback signal to the input terminal of the summing node corresponding to the first-stage integrator. The Sigma-Delta analog-to-digital converter also includes a second feedback circuit; The second feedback circuit is connected between the summing node corresponding to the last integrator and the output of the quantizer. The second feedback circuit is used to perform a second time-delay processing on the quantized output signal output by the quantizer and convert it into a second feedback signal, and then transmit the second feedback signal to the summing node corresponding to the last integrator. The second time-delay processing performed by the second feedback circuit is used to compensate for the first time-delay processing performed by the first feedback circuit.

2. The Sigma-Delta analog-to-digital converter according to claim 1, characterized in that, The quantizer, the first feedback circuit, and the loop filter module are cascaded to form a feedback loop and constitute the first loop filter function; wherein, the first loop filter function is obtained by changing the original transfer function by the first feedback circuit, and is the transfer function of the Sigma-Delta analog-to-digital converter; The quantizer, the second feedback circuit, and the loop filter module are cascaded to form a compensation loop and constitute a second loop filter function. The second loop filter function is used to compensate the first loop filter function to adjust the transfer function of the Sigma-Delta analog-to-digital converter to the original transfer function.

3. The Sigma-Delta analog-to-digital converter according to claim 2, characterized in that, The first feedback circuit includes a first feedback DAC and a first filter; The input of the first filter is connected to the output of the quantizer, the input of the first feedback DAC is connected to the output of the first filter, and the output of the first feedback DAC is connected to the input of the summing node corresponding to the first-stage integrator. The first filter is used to perform a delay processing on the quantized output signal output by the quantizer for a number of times equal to a first preset number of taps. The delay processing performed by the first filter for a number of times equal to the first preset number of taps is the first time stretching processing, so that the accuracy of the quantized output signal filtered by the first filter is higher than that of the quantized output signal. The first preset number of taps is the number of taps of the first filter. The first feedback DAC is used to convert the quantized output signal filtered by the first filter into a first feedback signal in real time, and then transmit the first feedback signal to the input of the summing node corresponding to the first-stage integrator to change the original transfer function.

4. The Sigma-Delta analog-to-digital converter according to claim 3, characterized in that, Except for the summing node corresponding to the first-stage integrator, the input of the summing node corresponding to each stage integrator is connected to the output of the first feedback DAC.

5. The Sigma-Delta analog-to-digital converter according to claim 3, characterized in that, The second feedback circuit includes a second feedback DAC and a second filter; the number of taps in the second filter is equal to the number of second preset taps. The input of the second filter is connected to the output of the quantizer, the input of the second feedback DAC is connected to the output of the second filter, and the output of the second feedback DAC is connected to the input of the summing node corresponding to the last integrator. The second filter is used to perform a delay processing on the quantized output signal output by the quantizer for a number of times equal to a second preset number of taps. The delay processing performed by the second filter for a number of times equal to the second preset number of taps is the second time stretching processing, which compensates for the first filter and also makes the accuracy of the quantized output signal filtered by the second filter higher than that of the quantized output signal. The second feedback DAC is used to convert the quantized output signal filtered by the second filter into a second feedback signal, and then transmit the second feedback signal to the input of the summing node corresponding to the last stage integrator, so that the quantized output signal is extended into an analog signal with delay compensation effect, thereby adjusting the transfer function of the Sigma-Delta analog-to-digital converter to the original transfer function.

6. The Sigma-Delta analog-to-digital converter according to claim 5, characterized in that, The first filter has internally configured first filter coefficients, and correspondingly, the first filter introduces a first filter transfer function into the first feedback circuit; wherein, the first filter coefficients are parameters belonging to the first filter transfer function; The second filter has internally configured second filter coefficients, and correspondingly, the second filter introduces a second filter transfer function into the second feedback circuit; wherein, the second filter coefficients are parameters belonging to the second filter transfer function; The first filter coefficient and the second filter coefficient work together to make the signal changes caused by the first filter transfer function in the Sigma-Delta analog-to-digital converter cancel each other out, so as to control the delay state of the transfer function of the Sigma-Delta analog-to-digital converter to remain the same as the delay state of the original transfer function.

7. The Sigma-Delta analog-to-digital converter according to claim 5, characterized in that, The filter coefficients set inside the first filter and the filter coefficients set inside the second filter are not exactly the same. The number of filter coefficients set inside the first filter and the number of filter coefficients set inside the second filter are both equal to the preset number of taps. The implementation structures of the first filter and the second filter both belong to the same preset filter structure.

8. The Sigma-Delta analog-to-digital converter according to claim 7, characterized in that, The preset filter structure includes m delay units, a coefficient matching module, and an accumulator; m delay units are connected in series to generate m digital input signals representing different delays; where m is a positive integer. The coefficient matching module is used to provide a matching filter coefficient for each of the digital input signals, multiply each of the digital input signals by its matching filter coefficient, and then output the corresponding product; The accumulator is used to add up each product output by the coefficient matching module to obtain a filtered quantized output signal.

9. The Sigma-Delta analog-to-digital converter according to any one of claims 1 to 8, characterized in that, The loop filtering module includes N-stage summing nodes, N-stage integrators, and a final operational amplifier. The output of the final integrator is connected to the input of the final operational amplifier, and the output of the final operational amplifier is connected to the input of the quantizer. The output of the final operational amplifier is used to output the pre-feedback analog signal. Each level of summation node has a first input, a second input, and an output. The first input of the i-th stage summing node is connected to the output of the (i-1)-th stage integrator, and is used to receive the (i-1)-th stage integrated analog signal output by the (i-1)-th stage integrator. The second input of the i-th stage summing node is connected to the output of the final stage operational amplifier, and is used to receive the pre-feedback analog signal output by the final stage operational amplifier. The output of the i-th stage summing node is connected to the input of the i-th stage integrator, and is used to output the i-th stage summing analog signal to the input of the i-th stage integrator. The i-th stage summing analog signal is the sum of the (i-1)-th stage integrated analog signal and the pre-feedback analog signal output by the final stage operational amplifier. The i-th stage integrator is used to integrate the i-th stage summation analog signal and then output the i-th stage integrated analog signal; the (i-1)-th stage integrator is used to integrate the output signal of the (i-1)-th stage summation node to obtain the (i-1)-th stage integrated analog signal. Where N is a positive integer; i is an integer greater than 1, and i is an integer less than or equal to N-1.

10. The Sigma-Delta analog-to-digital converter according to claim 9, characterized in that, The first input terminal of the first-stage summing node is used to receive the analog input signal, and the second input terminal of the first-stage summing node is used to receive the first feedback signal output by the first feedback circuit. The output of the first-stage summing node is used to output the first-stage summing analog signal to the first-stage integrator. The first-level summing node is used to sum the analog signal and the first feedback signal provided by the first feedback circuit, and configure the sum value as the first-level summing analog signal; The first-stage integrator is used to receive and integrate the first-stage summed analog signal to obtain the first-stage integrated analog signal.

11. The Sigma-Delta analog-to-digital converter according to claim 10, characterized in that, The first input terminal of the Nth stage summing node is connected to the output terminal of the (N-1)th stage integrator, and the first input terminal of the Nth stage summing node is used to receive the N-1th stage integrated analog signal output by the (N-1)th stage integrator; the second input terminal of the i-th stage summing node is connected to the output terminal of the second feedback circuit, and the second input terminal of the i-th stage summing node is used to receive the second feedback signal output by the second feedback circuit. The output of the Nth-level summation node is used to output the Nth-level summation analog signal to the Nth-level integrator.

12. The Sigma-Delta analog-to-digital converter according to claim 11, characterized in that, In addition to the first and second input terminals, the Nth level summation node also has N-1 preset input terminals; In the first-level summing node to the (N-1)th-level summing node, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the Nth-level summing node; The Nth level summation node is used to sum the N-1th level integral analog signal, the second feedback signal, and the signal input from each preset input terminal, and configure the sum value as the Nth level summation analog signal; The Nth-stage integrator is used to receive and integrate the Nth-stage summed analog signal to obtain the Nth-stage integrated analog signal.

13. The Sigma-Delta analog-to-digital converter according to claim 12, characterized in that, Each stage of the integrator is a continuous-time structure used to integrate the input signal through a continuous-time structure. Each integrator stage includes branch resistors and pre-configured operational amplifiers. The output of the branch resistor is connected to the input of the pre-configured operational amplifier, and the input of the branch resistor is configured as the input of the corresponding summation node. The output of the branch resistor is configured as the output of the corresponding summation node. The input terminal of the pre-configured operational amplifier is the input terminal of the corresponding integrator; In this system, the first input terminal of each summing node is the input terminal of a branch resistor inside the corresponding first-stage integrator, and the second input terminal of each summing node is the input terminal of another branch resistor inside the corresponding first-stage integrator. In this system, each preset input terminal of the last stage summing node is the input terminal of the corresponding branch resistor inside the last stage integrator.

14. The Sigma-Delta analog-to-digital converter according to claim 12, characterized in that, N is the value 3; When the quantization bit count of the quantizer is set to 1, the quantizer is used to quantize the signal output by the loop filter module into a 1-bit digital signal to reduce the nonlinearity of the feedback DAC. Both the first feedback circuit and the second feedback circuit are used to convert the 1-bit digital signal output by the quantizer into an analog signal for feedback.

Images