High-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals

Abstract

The present invention discloses a high-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals, which includes the following FPGA sub-modules: (1) a beam control module for controlling the working states of other sub-modules; (2) a vector (matrix) multiplier module capable of setting the working modes of fixed-point multipliers and adders; (3) a channel data storage module serving as a circular buffer to store sampled data; (4) an addressing storage module for configuring a beamforming delay table; and (5) a coefficient storage module for configuring a beamforming vector table. The present invention realizes beamforming under high-precision and continuous real-time sampling through the combination of partial resources of an FPGA chip and the instantiation of modules, and provides multi-beam signals with low signal-to-noise ratio in real time for target estimation and detection.

Description

Technical Field

[0001] The present invention relates to the implementation of a high-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals, belonging to the technical field of sonar signal processing. Background Art

[0002] The so-called Digital Beam Forming (DBF) technology is a new technology developed on the basis of array antennas and signal processing, and has been widely used in the fields of sonar and radar technology. On the one hand, by performing beamforming processing in a certain direction, the signal can obtain the maximum output in this direction. On the other hand, the beamforming processing technology can effectively suppress spatial interference and improve the signal-to-noise ratio of the signal. The basic idea of DBF is to perform weighted processing on the data received by the array elements to control the direction function of the antenna array, so that the antenna array pattern generates a high-gain narrow beam in the direction of the desired signal and a deeper null in the direction of the interference signal, achieving the purpose of spatial domain filtering. Therefore, the beamforming system is the core component of modern sonar and is the basis for sonar to have good tactical and technical performance. Underwater acoustic signals can achieve anti-interference underwater, enhance angular resolution, enhance signal-to-noise ratio, etc. by using digital beamforming technology. At the same time, the characteristics of the beam are controlled by the steering vector of the beam, which is convenient for implementing maneuvering processing, so that the sonar array has better adaptive correction and low sidelobe performance.

[0003] At present, there are mainly two ways to implement beamforming: one is the beamformer with frequency-domain phase shift weighting; the other is the beamformer with time-domain delay. For narrowband signals, frequency-domain weighting has good results, but the frequency offset of underwater acoustic signals is relatively large, and the underwater signal bandwidth is relatively wide, so it is more reasonable to use time-delay beamforming. However, the sampling rate of the signal is limited, which results in the time delay not always being accurate. To obtain high-precision fractional time delay results, a large amount of computing power is required for interpolation fitting, and the power consumption will increase accordingly. Therefore, how to simply and accurately complete time-delay beamforming is a problem worthy of in-depth study.

[0004] At present, there are mainly two ways to implement beamforming algorithms: one is to use ARM and DSP chips; the other is to use FPGA chips. Since the former has a small number of CPU cores and the device can only execute programs sequentially, it is difficult for such chips to achieve the expected results when the real-time requirement is relatively high. Therefore, people usually use FPGA chips to complete the system design. However, the processing speed of the beamforming algorithm is often the bottleneck of the FPGA system performance. In the case of real-time processing of multiple beam directions, the system has relatively high requirements for both data throughput rate and computing volume, which poses very high requirements for hardware implementation. At present, in known high-speed signal processing systems, high-speed differential interfaces are used for data transmission, and increasingly high-end FPGAs are used for complex signal processing. It is often necessary to form multiple beams simultaneously, which leads to a multiple increase in the number of multipliers inside the FPGA. The number of multipliers increases from dozens at the beginning to hundreds, and then to thousands now. The number of array elements and beams is increasing, and the overall hardware scale is getting larger and larger. Summary of the Invention

[0005] Object of the Invention: Aiming at the problems of slow processing speed, low beam resolution, high power consumption, and failure to meet real-time requirements in the implementation of underwater acoustic signal beamforming by serial programming calculation in existing embedded systems, the present invention discloses a high-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals. The invention will utilize the ram resources and basic arithmetic unit resources in the FPGA chip, and by building a beam control module, a sampled data storage module, an address fetch storage module, a coefficient storage module, and a vector multiplication module, and presetting the parameters of the beam control module and the initial values of the address fetch and coefficient storage modules, through real-time sampling and beam calculation, a high-precision, strong real-time, and low-power FPGA beamformer is realized.

[0006] Technical Solution: A high-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals, which fully utilizes the internal resources of the FPGA, has high precision, strong real-time performance, and low power consumption. The specific implementation includes the following functional modules:

[0007] (1) Beam control module, used to set beamforming-related parameters;

[0008] (2) Vector (matrix) multiplier module, used to set the working modes of fixed-point multipliers and adders;

[0009] (3) Channel data storage module, used as a circular buffer to store sampled data;

[0010] (4) Address fetch storage module, used to configure the beamforming delay table;

[0011] (5) Coefficient storage module, used to configure the beamforming vector table.

[0012] In the beam control module, the following design is used to control the working status of other modules:

[0013] The finite state machine is used to control the beam number, array element number, delay unit, various memories, operation enable of the arithmetic unit, memory address control line, read / write control line, etc. calculated under the current clock. A total of 5 states are set, and the state name, function and jump condition are as follows:

[0014]

[0015] When the state machine is in the BEAM state and the LAST_BEAM state, the beam number and the delay unit number are cyclically incremented, and the read memory enable and the operator calculation enable are set to 1. At the same time, the current beam number, delay unit number, read enable, calculation enable and other signals are transmitted from the beam control module to the vector (matrix) multiplier module, the address storage module and the coefficient storage module.

[0016] In the vector (matrix) multiplier module, the following design is used to complete fractional delay filtering and weighted beamforming:

[0017] Using M multipliers and M-1 adders, the multipliers and adders are connected in a tree structure. The leaf layer consists of M multipliers. The outputs of every two multipliers are connected to the input of an adder, and the outputs of every two multipliers are connected to the input of an adder. The output of the last adder is the output of the root node of the tree structure. The multipliers and adders work in parallel and simultaneously to complete the vector inner product operation. One vector inner product can be completed per clock, and the calculation can be shared across multiple clocks to complete a matrix multiplication.

[0018] In the channel data storage module, the following method is used to buffer the sampled data to meet the delay requirement:

[0019] A RAM is allocated for sampling data from a particular channel. When writing data, data reading is disabled. The write address wraddr_base starts at 0 and counts up to a maximum before wrapping around to 0 to continue writing data. When reading data, writing is disabled. The read address is the sum of the current write address (base address wraddr_base) and the read address offset rdaddr_offset output by the addressing storage module. It can be shown that, with the current write address as the end of the ring buffer, the older the data is, the earlier it is.

[0020] In order to save resources, you can choose to divide the dual-port RAM space into two parts by setting the highest bit of the address line to 0 or 1, and store the sampling data of the two channels respectively.

[0021] In the addressing and storage module, the following method is adopted to extract and store the integer delay parameter to achieve fractional filtering:

[0022] Now assume that for the i-th array element, the analog delay amount required for the j-th beam is τ ij , and the sampling rate is f s . Then the digital delay Nτ after sampling ij should be

[0023] Nτ ij = τ ij f s

[0024] Round it to the nearest integer

[0025] P ij = round(Nτ ij )

[0026] where P ij is the integer delay part. For all i and j, P ij has a minimum value P less than 0 min

[0027] [[ID=#39]]

[0028] To prevent the read address of the channel data memory under all beams in the same sampling from overwriting the current write address, a bias process must be performed on the integer delay

[0029] P ij = P ij - P min

[0030] The obtained P ij are all positive integers, and they are stored in the corresponding positions of the corresponding memory.

[0031] In the coefficient storage module, the following method is adopted to store the fractional filtering fir coefficient and the weighted beamforming coefficient:

[0032] As described in the addressing and storage module, Nτ ij is the digital delay amount that the i-th array element should perform for the j-th beam. To obtain the sampling value of the i-th array element here, the FIR filtering method is adopted, and the formula is

[0033]

[0034] where round(x) is the rounding function, and sinc(x) is the sinc function:

[0035]

[0036] For the convenience of calculation, k ranges from -l to +l, that is, a 2l+1 order fractional delay filter is performed. The value of x[round(Nτ ij +k)] is output by the channel data storage module, and the value of sinc[(Nτ ij +k)-round(Nτ ij +k)] is denoted as h(i,j,k);

[0037] On the other hand, sometimes there are special requirements for the performance indicators of the beam. In this case, it may be necessary to perform different weightings on the array elements. For example, the chebyshev weighting method, and the weight coefficient is denoted as W(i,j);

[0038] Then, the two product factors are calculated in advance, F(i,j,k) = h(j,j,k)*W(i,j);

[0039] Since the range of F(i,j,k) is (-1,+1), and fixed-point numbers are used in the FPGA for calculation. Then, F(j,i,k) is amplified to a fixed-point number with M bits wide for easy storage and calculation in the FPGA. After multiplying F(i,j,k) by 2 to the power of M and taking the integer part:

[0040] D(i,j,k) = round(F(i,j,k)*2 M )

[0041] Finally, the value of D(i,j,k) is stored in the corresponding position of the corresponding memory.

[0042] Beneficial effects: The high-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals provided by the present invention has the following advantages compared with the traditional beamforming method with a serial programming structure: (1) Adopting a pipeline processing and fully parallel structure, it has low delay and fast processing speed, and can perform multi-beam calculation of continuous signals in real time; (2) Having the ability of high-order fractional delay filtering and beam weighting, it has good beam directivity and high precision; (3) All are implemented using the internal resources of the FPGA, with a simple structure, small volume and low power consumption. Description of the Drawings

[0043] Figure 1 It is a schematic diagram of the overall framework of the embodiment of the present invention;

[0044] Figure 2 It is an implementation block diagram of the vector (matrix) multiplier module;

[0045] Figure 3 It is a time-domain waveform diagram of the receiving array element;

[0046] Figure 4 It is a time-domain waveform diagram of the beam in the maximum direction;

[0047] Figure 5 It is a beam energy diagram of theoretical calculation;

[0048] Figure 6 It is the beam energy diagram of the actual output. Specific implementation manner

[0049] The following further clarifies the present invention in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. After reading the present invention, various equivalent modifications of the present invention by those skilled in the art fall within the scope defined by the appended claims of this application.

[0050] A high-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals disclosed in this embodiment utilizes the ram resources and basic arithmetic unit resources in the FPGA chip. By building a beam control module, a sampling data storage module, an addressing storage module, a coefficient storage module, and a vector multiplication module, and presetting the parameters of the beam control module and the initial values of the addressing and coefficient storage modules, high-precision, real-time, and continuous beamforming output is achieved through real-time sampling and beam calculation.

[0051] As Figure 1 shown, the beam control module is driven by the sampling storage completion signal of the channel data storage module to operate the state machine in this module, and is also used to provide working parameters and enable control signals to other modules; the vector (matrix) multiplier module receives the channel data of the channel data storage module and the product coefficients of the coefficient storage module, and completes a vector inner product every clock. The result of the vector inner product is the beam result to be output; the channel data storage module stores the sampling data as a circular buffer, provides a single-sampling completion pulse signal to the beam control module, and at the same time gives the channel data to be output to the vector (matrix) multiplication module; the addressing storage module initializes and configures the beamforming delay table, is driven by the beam control module, and outputs the address offset of the channel data to the channel data storage module; the coefficient storage module initializes and configures the beamforming vector table, is driven by the beam control module, and outputs the beam delay filtering and weighting coefficients to the vector (matrix) multiplication module.

[0052] The present invention realizes beamforming under high-precision and continuous real-time sampling through the combination of partial resources of the FPGA chip and the use of module instantiation, and provides real-time multi-beam signals with low signal-to-noise ratio for target estimation and detection.

[0053] The present invention discloses a high-precision, continuous-delay, FPGA-based real-time beamformer for underwater acoustic signals. This system operates based on the received signals from a 32-element uniform linear array. The system transmits a single-frequency continuous signal. The speed of sound in water is c = 1500 m / s. The target scatterer is located at a distance of approximately 10 m, at a distance of -1.5° from the normal to the linear array. The echo signal is sampled at a sampling rate of fs = 476 kHz. The sampling results are sent to the beamforming module (i.e., the present invention) for beamforming processing. The specific module configuration of the method is as follows:

[0054] In the beam control module, the following design is used to control the working status of other modules:

[0055] The finite state machine is used to control the beam number, array element number, delay unit, various memories, operation enable of the arithmetic unit, memory address control line, read / write control line, etc. calculated under the current clock. A total of 5 states are set, and the state name, function and jump condition are as follows:

[0056]

[0057] When the state machine is in the BEAM state and the LAST_BEAM state, the beam number and the delay unit number are cyclically incremented, and the read memory enable and the operator calculation enable are set to 1. At the same time, the current beam number, delay unit number, read enable, calculation enable and other signals are transmitted from the beam control module to the vector (matrix) multiplier module, the address storage module and the coefficient storage module.

[0058] In the beam control module, the number of array elements is 32 and the number of beams is 81. The beamforming state machine is started in the IDLE state and waits for the beamforming calculation start request from the channel data storage module.

[0059] In the beam control module, 32 multipliers and 31 adders are called according to Figure 2 The method is used to arm the connection and wait for the beam calculation enable signal from the beam control module, the channel data from the channel data storage module and the coefficients from the coefficient storage module, and then starts to calculate the output beam.

[0060] The channel data storage module uses 16 dual-port RAMs, each with a 16-bit width and a depth of 1024. This means that the address lines are 10, the address range of RAM port A is 0-511, and the address range of RAM port B is 512 to 1023. This splits the dual-port RAM into two single-port RAMs. The sampled data for 32 array elements is stored in each of these 32 memory spaces. When a sample is stored, the channel data storage module initiates a beam calculation start request to the beam control module. It then waits for the read channel memory enable and address signals from the vector (matrix) multiplier module to output the channel sampled data required for beam calculation.

[0061] In the address fetching and storage module, calculate the integer time delays of each array element under each beam. The uniform linear array pitch is d, which is half of the wavelength of the transmitted signal. The signal frequency is fc, the sampling rate fs > 5fc, the underwater sound speed v is taken as 1500 m / s, the beam opening angle is taken as ±60° relative to the normal of the linear array method, the beam interval is 1.5°, and the beams are numbered from 0 to 81 starting from -60. Taking the 0th array element as the reference, for the i-th array element, the acoustic path difference τ relative to the reference array element on the j-th beam ij is

[0062]

[0063] The digital time delay amount after sampling is

[0064] Nτ ij = τ ij fs

[0065] Round Nτ ij to the nearest integer

[0066] P ij = round(Nτ ij )

[0067] For all i and j, P ij has a minimum value less than 0, P min

[0068]

[0069] In this example, P min = -162. In order to prevent the read addresses of the channel data memories under all beams in the same sampling from overwriting the current write address, a bias processing must be performed on the integer delay

[0070] P ij = P ij + 162

[0071] Finally, store the result of P ij into the address fetching and storage module

[0072] After initialization is completed, wait for the read address memory enable signal and read address signal of the beam control module, and then start working

[0073] In the coefficient storage module, calculate the filtering and weighting coefficients of each array element under each beam. In this example, perform seventh-order fractional delay filtering and Dolph-Chebyshev weighting. The fractional delay result for the i-th array element and the j-th beam under seventh-order filtering should be

[0074]

[0075] Among them, corresponding to the sampling point P ij The filtering coefficient at +k is

[0076] h(i, j, k) = sinc[Nτ ij +k - P ij )]

[0077] On the other hand, 32 array elements are DC weighted, and the sidelobe level is taken as -30 dB, and the weighting vector obtained is

[0078] W = [0.44, 0.24, 0.30, 0.36, 0.43, 0.50, 0.57, 0.64, 0.71, 0.78, 0.83, 0.89, 0.93, 0.96, 0.98, 1, 1, 0.98, 0.96, 0.93, 0.89, 0.83, 0.78, 0.71, 0.64, 0.57, 0.50, 0.43, 0.36, 0.30, 0.24, 0.44]

[0079] Multiply the two coefficients in advance

[0080] F(i, j, k) = h(i, j, k) * W(i)

[0081] Scale F(I, j, k) to a fixed-point number of M = 16 bits for easy storage and calculation in the FPGA

[0082] D(i, j, k) = round(F(i, j, k) * 2 15 )

[0083] Finally, store the value of D(i, j, k) in the coefficient storage module

[0084] After initialization, wait for the read coefficient memory enable signal and read address signal of the beam control module to start working

[0085] As the sampling continues, the beamformer on the FPGA also outputs high-precision continuous beam results in real time. By comprehensively analyzing the sampling signal and the beam results, the time-domain waveform of part of the sampling signal is obtained Figure 3 and the time-domain waveform of the beam at the direction with the maximum beam energy Figure 4 , and it can be seen that the signal-to-noise ratio has been significantly improved Figure 5 is the beam energy diagram under matlab simulation Figure 6 is the high-precision beam energy diagram output by the FPGA. The graphs are basically the same, the beam pointing is accurate, and the error does not exceed ±0.5°

Claims

1. A high-precision continuous delay type FPGA real-time beamformer for underwater acoustic signals, characterized in that, Fully utilize the internal resources of FPGA. The specific implementation includes the following functional modules: (1) Beam control module, used to set beamforming related parameters; (2) Vector-matrix multiplier module, used to set the working mode of fixed-point multipliers and adders; (3) Channel data storage module, which acts as a ring buffer to store sampled data; (4) Addressing the storage module and configuring the beamforming delay table; (5) Coefficient storage module, configuring the beamforming vector table; In the address storage module, the following method is used to extract and store integer delay parameters to implement decimal filtering: Now, assume that for the i-th array element, the required analog delay for the j-th beam is τ ij , and the sampling rate is f s ; then the digital delay Nτ ij after sampling should be Nτ ij = τ ij f s , and round it to the integer part P ij = round(Nτ ij ), where P ij is the integer delay part. For all i and j, P ij has a minimum value P min less than 0, round(x) is the rounding function; In order to prevent the read addresses of the channel data memories under all beams in the same sampling from overwriting the current write address, a bias process must be performed on the integer delay, P ij = P ij - P min At this time, the obtained P ij are all positive integers, which are stored in the corresponding positions of the corresponding memories.

2. The high-precision continuous delay type FPGA real-time beamformer for acoustic signals according to claim 1, wherein In the beam control module, the following design is used to control the working status of other modules: The finite state machine is used to control the beam number, array element number, delay unit, various memories, the operation enable of the arithmetic unit, the address control line of the memory, and the read / write control line of the memory under the current clock. A total of five states are set: State name: IDLE; Function: Idle state; Jump condition: One sampling, after the signals of all channels are stored in the channel data memory, jump to READY; Status name: READY; Function: ready state; jump condition: jump to BEAM after one clock; State name: BEAM; Function: beam calculation state; jump condition: jump to LAST_BEAM after the required number of beams minus one clock; State name: LAST_BEAM; Function: Beam completion state; Jump condition: Jump to END after one clock; State name: END; Function: End state; Jump condition: Jump to IDLE after one clock; When the state machine is in the BEAM state and the LAST_BEAM state, the beam number and the delay unit number are cyclically incremented, and the read memory enable and the operator calculation enable are set to 1. At the same time, the current beam number, delay unit number, read enable, calculation enable and other signals are transmitted from the beam control module to the vector matrix multiplier module, the address storage module and the coefficient storage module.

3. The high-precision continuous-delay type FPGA real-time beamformer for acoustic signals according to claim 1, characterized in that In the vector matrix multiplier module, the following design is used to complete fractional delay filtering and weighted beamforming: A multipliers and A-1 adders are used. The connection between the multipliers and adders is a tree structure. The leaf layer is A multipliers. The outputs of every two multipliers are connected to the input of an adder at the same time. The outputs of every two multipliers are connected to the input of an adder in common. The output of the last adder is the output of the root node of the tree structure. The multipliers and adders work in parallel and simultaneously to complete the vector inner product operation. One vector inner product can be completed per clock, and time-sharing calculations are performed under multiple clocks to complete one matrix multiplication in a coordinated manner.

4. The high-precision continuous delay type FPGA real-time beamformer for acoustic signals according to claim 1, characterized in that In the channel data storage module, the following method is used to buffer the sampled data to meet the delay requirement: For the sampling data of a certain channel, a RAM is allocated; when writing data, reading data is prohibited, and the write address wraddr_base starts from 0 and counts to the maximum, then returns to 0 to continue writing data; when reading data, writing data is prohibited, and the read address is the sum of the current write address as the base address wraddr_base plus the read address offset rdaddr_offset output by the addressing storage module.

5. The high-precision continuous delay type FPGA real-time beamformer for acoustic signals according to claim 4, wherein Select to divide the space of the dual-port RAM into two parts according to whether the most significant bit of the address line is 0 or 1, and store the sampling data of the two channels separately.

6. The high-precision continuous delay type FPGA real-time beamformer for acoustic signals according to claim 1, characterized in that In the coefficient storage module, the following method is used for storing the fractional filter FIR coefficients and the weighted beamforming coefficients: Nτ ij is the digital time delay that the i-th array element should perform for the j-th beam. To obtain the sampling value x(Nτ ij ) of the i-th array element at this location, the FIR filtering method is adopted, and the formula is x[round(Nτ ij +k)] is the output of the channel data storage module, and the value of sinc[(Nτ ij +k)-round(Nτ ij +k)] is denoted as h(i,j,k); where round(x) is the rounding function and sinc(x) is the sinc function, and f s is the sampling rate. Select the weighted method Chebyshev, and denote the weight coefficient as W(i, j); Then calculate the two product factors in advance, F(i, j, k) = h(i, j, k) * W(i, j); Scale F(i, j, k) to M-bit fixed-point numbers for easy storage and calculation in the FPGA. D(i,j,k) = round(F(i,j,k) * 2 M ) Finally, store the value of D(i, j, k) in the corresponding position of the corresponding memory.

Images